1129198Scognet/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37139735Simp/*- 38129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 39129198Scognet * Copyright (c) 1994 Brini. 40129198Scognet * All rights reserved. 41129198Scognet * 42129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 43129198Scognet * 44129198Scognet * Redistribution and use in source and binary forms, with or without 45129198Scognet * modification, are permitted provided that the following conditions 46129198Scognet * are met: 47129198Scognet * 1. Redistributions of source code must retain the above copyright 48129198Scognet * notice, this list of conditions and the following disclaimer. 49129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 50129198Scognet * notice, this list of conditions and the following disclaimer in the 51129198Scognet * documentation and/or other materials provided with the distribution. 52129198Scognet * 3. All advertising materials mentioning features or use of this software 53129198Scognet * must display the following acknowledgement: 54129198Scognet * This product includes software developed by Brini. 55129198Scognet * 4. The name of the company nor the name of the author may be used to 56129198Scognet * endorse or promote products derived from this software without specific 57129198Scognet * prior written permission. 58129198Scognet * 59129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69129198Scognet * SUCH DAMAGE. 70129198Scognet * 71129198Scognet * RiscBSD kernel project 72129198Scognet * 73129198Scognet * cpuswitch.S 74129198Scognet * 75129198Scognet * cpu switching functions 76129198Scognet * 77129198Scognet * Created : 15/10/94 78129198Scognet * 79129198Scognet */ 80129198Scognet 81137274Scognet#include "assym.s" 82245477Scognet#include "opt_sched.h" 83137274Scognet 84129198Scognet#include <machine/asm.h> 85129198Scognet#include <machine/asmacros.h> 86129198Scognet#include <machine/armreg.h> 87266277Sian#include <machine/vfp.h> 88266277Sian 89129198Scognet__FBSDID("$FreeBSD$"); 90129198Scognet 91129198Scognet#define DOMAIN_CLIENT 0x01 92129198Scognet 93266159Sian#if defined(_ARM_ARCH_6) && defined(SMP) 94266159Sian#define GET_PCPU(tmp, tmp2) \ 95266159Sian mrc p15, 0, tmp, c0, c0, 5; \ 96266159Sian and tmp, tmp, #0xf; \ 97266159Sian ldr tmp2, .Lcurpcpu+4; \ 98266159Sian mul tmp, tmp, tmp2; \ 99266159Sian ldr tmp2, .Lcurpcpu; \ 100266159Sian add tmp, tmp, tmp2; 101239268Sgonzo#else 102129198Scognet 103266159Sian#define GET_PCPU(tmp, tmp2) \ 104239268Sgonzo ldr tmp, .Lcurpcpu 105239268Sgonzo#endif 106129198Scognet 107266277Sian#ifdef VFP 108266277Sian .fpu vfp /* allow VFP instructions */ 109266277Sian#endif 110266277Sian 111266159Sian.Lcurpcpu: 112266159Sian .word _C_LABEL(__pcpu) 113266159Sian .word PCPU_SIZE 114129198Scognet.Lcpufuncs: 115129198Scognet .word _C_LABEL(cpufuncs) 116171780Scognet.Lblocked_lock: 117171780Scognet .word _C_LABEL(blocked_lock) 118239268Sgonzo 119135655ScognetENTRY(cpu_throw) 120135655Scognet mov r5, r1 121129198Scognet 122135655Scognet /* 123239268Sgonzo * r0 = oldtd 124137274Scognet * r5 = newtd 125135655Scognet */ 126129198Scognet 127266277Sian#ifdef VFP /* This thread is dying, disable */ 128266277Sian bl _C_LABEL(vfp_discard) /* VFP without preserving state. */ 129266277Sian#endif 130266277Sian 131266159Sian GET_PCPU(r7, r9) 132137274Scognet ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */ 133239268Sgonzo 134135655Scognet /* Switch to lwp0 context */ 135135655Scognet 136135655Scognet ldr r9, .Lcpufuncs 137266058Sian#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT) 138135655Scognet mov lr, pc 139135655Scognet ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] 140239268Sgonzo#endif 141135655Scognet ldr r0, [r7, #(PCB_PL1VEC)] 142135655Scognet ldr r1, [r7, #(PCB_DACR)] 143135655Scognet /* 144135655Scognet * r0 = Pointer to L1 slot for vector_page (or NULL) 145135655Scognet * r1 = lwp0's DACR 146135655Scognet * r5 = lwp0 147135655Scognet * r6 = exit func 148135655Scognet * r7 = lwp0's PCB 149135655Scognet * r9 = cpufuncs 150135655Scognet */ 151135655Scognet 152135655Scognet /* 153135655Scognet * Ensure the vector table is accessible by fixing up lwp0's L1 154135655Scognet */ 155135655Scognet cmp r0, #0 /* No need to fixup vector table? */ 156135655Scognet ldrne r3, [r0] /* But if yes, fetch current value */ 157135655Scognet ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */ 158135655Scognet mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 159135655Scognet cmpne r3, r2 /* Stuffing the same value? */ 160135655Scognet strne r2, [r0] /* Store if not. */ 161135655Scognet 162135655Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 163135655Scognet /* 164135655Scognet * Need to sync the cache to make sure that last store is 165135655Scognet * visible to the MMU. 166135655Scognet */ 167135655Scognet movne r1, #4 168135655Scognet movne lr, pc 169135655Scognet ldrne pc, [r9, #CF_DCACHE_WB_RANGE] 170135655Scognet#endif /* PMAP_INCLUDE_PTE_SYNC */ 171135655Scognet 172135655Scognet /* 173135655Scognet * Note: We don't do the same optimisation as cpu_switch() with 174135655Scognet * respect to avoiding flushing the TLB if we're switching to 175135655Scognet * the same L1 since this process' VM space may be about to go 176135655Scognet * away, so we don't want *any* turds left in the TLB. 177135655Scognet */ 178135655Scognet 179135655Scognet /* Switch the memory to the new process */ 180135655Scognet ldr r0, [r7, #(PCB_PAGEDIR)] 181135655Scognet mov lr, pc 182135655Scognet ldr pc, [r9, #CF_CONTEXT_SWITCH] 183135655Scognet 184135655Scognet /* Restore all the save registers */ 185172614Scognet#ifndef _ARM_ARCH_5E 186135655Scognet add r1, r7, #PCB_R8 187135655Scognet ldmia r1, {r8-r13} 188135655Scognet#else 189135655Scognet ldr r8, [r7, #(PCB_R8)] 190135655Scognet ldr r9, [r7, #(PCB_R9)] 191135655Scognet ldr r10, [r7, #(PCB_R10)] 192135655Scognet ldr r11, [r7, #(PCB_R11)] 193135655Scognet ldr r12, [r7, #(PCB_R12)] 194135655Scognet ldr r13, [r7, #(PCB_SP)] 195135655Scognet#endif 196135655Scognet 197266159Sian GET_PCPU(r6, r4) 198266159Sian /* Hook in a new pcb */ 199266159Sian str r7, [r6, #PC_CURPCB] 200138751Scognet /* We have a new curthread now so make a note it */ 201266159Sian add r6, r6, #PC_CURTHREAD 202138751Scognet str r5, [r6] 203266159Sian#ifndef ARM_TP_ADDRESS 204266159Sian mcr p15, 0, r5, c13, c0, 4 205266159Sian#endif 206142570Scognet /* Set the new tp */ 207142955Scognet ldr r6, [r5, #(TD_MD + MD_TP)] 208239268Sgonzo#ifdef ARM_TP_ADDRESS 209188540Scognet ldr r4, =ARM_TP_ADDRESS 210188540Scognet str r6, [r4] 211188540Scognet ldr r6, [r5, #(TD_MD + MD_RAS_START)] 212188540Scognet str r6, [r4, #4] /* ARM_RAS_START */ 213188540Scognet ldr r6, [r5, #(TD_MD + MD_RAS_END)] 214188581Scognet str r6, [r4, #8] /* ARM_RAS_END */ 215239268Sgonzo#else 216239268Sgonzo mcr p15, 0, r6, c13, c0, 3 217239268Sgonzo#endif 218138751Scognet 219247864Sandrew add sp, sp, #4; 220138856Scognet ldmfd sp!, {r4-r7, pc} 221248361SandrewEND(cpu_throw) 222138751Scognet 223129198ScognetENTRY(cpu_switch) 224129198Scognet stmfd sp!, {r4-r7, lr} 225247864Sandrew sub sp, sp, #4; 226254847Sandrew#ifdef __ARM_EABI__ 227254847Sandrew .save {r4-r7, lr} 228254847Sandrew .pad #4 229254847Sandrew#endif 230254847Sandrew 231171780Scognet mov r6, r2 /* Save the mutex */ 232129198Scognet 233135655Scognet.Lswitch_resume: 234137274Scognet /* rem: r0 = old lwp */ 235129198Scognet /* rem: interrupts are disabled */ 236129198Scognet 237129198Scognet /* Process is now on a processor. */ 238135655Scognet /* We have a new curthread now so make a note it */ 239266159Sian GET_PCPU(r7, r2) 240266159Sian str r1, [r7, #PC_CURTHREAD] 241266159Sian#ifndef ARM_TP_ADDRESS 242266159Sian mcr p15, 0, r1, c13, c0, 4 243266159Sian#endif 244129198Scognet 245129198Scognet /* Hook in a new pcb */ 246137274Scognet ldr r2, [r1, #TD_PCB] 247239268Sgonzo str r2, [r7, #PC_CURPCB] 248129198Scognet 249137274Scognet /* rem: r1 = new process */ 250129198Scognet /* rem: interrupts are enabled */ 251129198Scognet 252129198Scognet /* Stage two : Save old context */ 253129198Scognet 254171780Scognet /* Get the user structure for the old thread. */ 255137274Scognet ldr r2, [r0, #(TD_PCB)] 256171780Scognet mov r4, r0 /* Save the old thread. */ 257129198Scognet 258171780Scognet /* Save all the registers in the old thread's pcb */ 259172614Scognet#ifndef _ARM_ARCH_5E 260137274Scognet add r7, r2, #(PCB_R8) 261129198Scognet stmia r7, {r8-r13} 262129198Scognet#else 263137274Scognet strd r8, [r2, #(PCB_R8)] 264137274Scognet strd r10, [r2, #(PCB_R10)] 265137274Scognet strd r12, [r2, #(PCB_R12)] 266129198Scognet#endif 267181144Scognet str pc, [r2, #(PCB_PC)] 268236991Simp 269129198Scognet /* 270129198Scognet * NOTE: We can now use r8-r13 until it is time to restore 271129198Scognet * them for the new process. 272129198Scognet */ 273239268Sgonzo#ifdef ARM_TP_ADDRESS 274142570Scognet /* Store the old tp */ 275175982Sraj ldr r3, =ARM_TP_ADDRESS 276188540Scognet ldr r9, [r3] 277142570Scognet str r9, [r0, #(TD_MD + MD_TP)] 278188540Scognet ldr r9, [r3, #4] 279188540Scognet str r9, [r0, #(TD_MD + MD_RAS_START)] 280188540Scognet ldr r9, [r3, #8] 281188540Scognet str r9, [r0, #(TD_MD + MD_RAS_END)] 282129198Scognet 283142570Scognet /* Set the new tp */ 284142570Scognet ldr r9, [r1, #(TD_MD + MD_TP)] 285188540Scognet str r9, [r3] 286188540Scognet ldr r9, [r1, #(TD_MD + MD_RAS_START)] 287188540Scognet str r9, [r3, #4] 288188540Scognet ldr r9, [r1, #(TD_MD + MD_RAS_END)] 289188540Scognet str r9, [r3, #8] 290239268Sgonzo#else 291239268Sgonzo /* Store the old tp */ 292239268Sgonzo mrc p15, 0, r9, c13, c0, 3 293239268Sgonzo str r9, [r0, #(TD_MD + MD_TP)] 294129198Scognet 295239268Sgonzo /* Set the new tp */ 296239268Sgonzo ldr r9, [r1, #(TD_MD + MD_TP)] 297239268Sgonzo mcr p15, 0, r9, c13, c0, 3 298239268Sgonzo#endif 299239268Sgonzo 300129198Scognet /* Get the user structure for the new process in r9 */ 301137274Scognet ldr r9, [r1, #(TD_PCB)] 302129198Scognet 303239268Sgonzo /* rem: r2 = old PCB */ 304129198Scognet /* rem: r9 = new PCB */ 305129198Scognet /* rem: interrupts are enabled */ 306129198Scognet 307254461Sandrew#ifdef VFP 308266277Sian fmrx r0, fpexc /* If the VFP is enabled */ 309266277Sian tst r0, #(VFPEXC_EN) /* the current thread has */ 310266277Sian movne r1, #1 /* used it, so go save */ 311266277Sian addne r0, r2, #(PCB_VFPSTATE) /* the state into the PCB */ 312266277Sian blne _C_LABEL(vfp_store) /* and disable the VFP. */ 313239268Sgonzo#endif 314129198Scognet 315266277Sian /* r0-r3 now free! */ 316239268Sgonzo 317129198Scognet /* Third phase : restore saved context */ 318129198Scognet 319239268Sgonzo /* rem: r2 = old PCB */ 320129198Scognet /* rem: r9 = new PCB */ 321129198Scognet /* rem: interrupts are enabled */ 322129198Scognet 323138414Scognet ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */ 324138414Scognet mov r2, #DOMAIN_CLIENT 325138414Scognet cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */ 326138414Scognet beq .Lcs_context_switched /* Yup. Don't flush cache */ 327138414Scognet mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */ 328129198Scognet /* 329129198Scognet * Get the new L1 table pointer into r11. If we're switching to 330129198Scognet * an LWP with the same address space as the outgoing one, we can 331129198Scognet * skip the cache purge and the TTB load. 332129198Scognet * 333129198Scognet * To avoid data dep stalls that would happen anyway, we try 334129198Scognet * and get some useful work done in the mean time. 335129198Scognet */ 336138414Scognet mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */ 337129198Scognet ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */ 338129198Scognet 339129198Scognet 340129198Scognet teq r10, r11 /* Same L1? */ 341137274Scognet cmpeq r0, r5 /* Same DACR? */ 342129198Scognet beq .Lcs_context_switched /* yes! */ 343129198Scognet 344266058Sian#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT) 345129198Scognet /* 346129198Scognet * Definately need to flush the cache. 347129198Scognet */ 348129198Scognet 349129198Scognet ldr r1, .Lcpufuncs 350129198Scognet mov lr, pc 351129198Scognet ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 352239268Sgonzo#endif 353129198Scognet.Lcs_cache_purge_skipped: 354171780Scognet /* rem: r6 = lock */ 355129198Scognet /* rem: r9 = new PCB */ 356129198Scognet /* rem: r10 = old L1 */ 357129198Scognet /* rem: r11 = new L1 */ 358129198Scognet 359129198Scognet mov r2, #0x00000000 360129198Scognet ldr r7, [r9, #(PCB_PL1VEC)] 361129198Scognet 362129198Scognet /* 363129198Scognet * Ensure the vector table is accessible by fixing up the L1 364129198Scognet */ 365129198Scognet cmp r7, #0 /* No need to fixup vector table? */ 366129198Scognet ldrne r2, [r7] /* But if yes, fetch current value */ 367129198Scognet ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ 368137274Scognet mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */ 369129198Scognet cmpne r2, r0 /* Stuffing the same value? */ 370135655Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 371129198Scognet strne r0, [r7] /* Nope, update it */ 372129198Scognet#else 373129198Scognet beq .Lcs_same_vector 374129198Scognet str r0, [r7] /* Otherwise, update it */ 375129198Scognet 376129198Scognet /* 377129198Scognet * Need to sync the cache to make sure that last store is 378129198Scognet * visible to the MMU. 379129198Scognet */ 380129198Scognet ldr r2, .Lcpufuncs 381129198Scognet mov r0, r7 382129198Scognet mov r1, #4 383129198Scognet mov lr, pc 384129198Scognet ldr pc, [r2, #CF_DCACHE_WB_RANGE] 385129198Scognet 386129198Scognet.Lcs_same_vector: 387129198Scognet#endif /* PMAP_INCLUDE_PTE_SYNC */ 388129198Scognet 389129198Scognet cmp r10, r11 /* Switching to the same L1? */ 390129198Scognet ldr r10, .Lcpufuncs 391129198Scognet beq .Lcs_same_l1 /* Yup. */ 392129198Scognet /* 393129198Scognet * Do a full context switch, including full TLB flush. 394129198Scognet */ 395129198Scognet mov r0, r11 396129198Scognet mov lr, pc 397129198Scognet ldr pc, [r10, #CF_CONTEXT_SWITCH] 398129198Scognet 399129198Scognet b .Lcs_context_switched 400129198Scognet 401129198Scognet /* 402129198Scognet * We're switching to a different process in the same L1. 403129198Scognet * In this situation, we only need to flush the TLB for the 404129198Scognet * vector_page mapping, and even then only if r7 is non-NULL. 405129198Scognet */ 406129198Scognet.Lcs_same_l1: 407129198Scognet cmp r7, #0 408129198Scognet movne r0, #0 /* We *know* vector_page's VA is 0x0 */ 409129198Scognet movne lr, pc 410129198Scognet ldrne pc, [r10, #CF_TLB_FLUSHID_SE] 411129198Scognet 412129198Scognet.Lcs_context_switched: 413129198Scognet 414171780Scognet /* Release the old thread */ 415171780Scognet str r6, [r4, #TD_LOCK] 416245477Scognet#if defined(SCHED_ULE) && defined(SMP) 417171780Scognet ldr r6, .Lblocked_lock 418239268Sgonzo GET_CURTHREAD_PTR(r3) 419171780Scognet1: 420171780Scognet ldr r4, [r3, #TD_LOCK] 421171780Scognet cmp r4, r6 422171780Scognet beq 1b 423245477Scognet#endif 424171780Scognet 425129198Scognet /* XXXSCW: Safe to re-enable FIQs here */ 426129198Scognet 427129198Scognet /* rem: r9 = new PCB */ 428129198Scognet 429129198Scognet /* Restore all the save registers */ 430172614Scognet#ifndef _ARM_ARCH_5E 431129198Scognet add r7, r9, #PCB_R8 432129198Scognet ldmia r7, {r8-r13} 433129198Scognet sub r7, r7, #PCB_R8 /* restore PCB pointer */ 434129198Scognet#else 435129198Scognet mov r7, r9 436129198Scognet ldr r8, [r7, #(PCB_R8)] 437129198Scognet ldr r9, [r7, #(PCB_R9)] 438129198Scognet ldr r10, [r7, #(PCB_R10)] 439129198Scognet ldr r11, [r7, #(PCB_R11)] 440129198Scognet ldr r12, [r7, #(PCB_R12)] 441129198Scognet ldr r13, [r7, #(PCB_SP)] 442129198Scognet#endif 443129198Scognet 444129198Scognet /* rem: r5 = new lwp's proc */ 445171780Scognet /* rem: r6 = lock */ 446129198Scognet /* rem: r7 = new PCB */ 447129198Scognet 448129198Scognet.Lswitch_return: 449129198Scognet 450129198Scognet /* 451129198Scognet * Pull the registers that got pushed when either savectx() or 452129198Scognet * cpu_switch() was called and return. 453129198Scognet */ 454247864Sandrew add sp, sp, #4; 455129198Scognet ldmfd sp!, {r4-r7, pc} 456129198Scognet#ifdef DIAGNOSTIC 457129198Scognet.Lswitch_bogons: 458129198Scognet adr r0, .Lswitch_panic_str 459129198Scognet bl _C_LABEL(panic) 460129198Scognet1: nop 461129198Scognet b 1b 462129198Scognet 463129198Scognet.Lswitch_panic_str: 464129198Scognet .asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n" 465129198Scognet#endif 466248361SandrewEND(cpu_switch) 467248361Sandrew 468129198ScognetENTRY(savectx) 469150856Scognet stmfd sp!, {r4-r7, lr} 470247864Sandrew sub sp, sp, #4 471150856Scognet /* 472150856Scognet * r0 = pcb 473150856Scognet */ 474150856Scognet /* Store all the registers in the process's pcb */ 475150856Scognet add r2, r0, #(PCB_R8) 476150856Scognet stmia r2, {r8-r13} 477254461Sandrew#ifdef VFP 478266277Sian fmrx r2, fpexc /* If the VFP is enabled */ 479266277Sian tst r2, #(VFPEXC_EN) /* the current thread has */ 480266277Sian movne r1, #1 /* used it, so go save */ 481266277Sian addne r0, r0, #(PCB_VFPSTATE) /* the state into the PCB */ 482266277Sian blne _C_LABEL(vfp_store) /* and disable the VFP. */ 483239268Sgonzo#endif 484247864Sandrew add sp, sp, #4; 485150856Scognet ldmfd sp!, {r4-r7, pc} 486248361SandrewEND(savectx) 487150856Scognet 488129198ScognetENTRY(fork_trampoline) 489266311Sian STOP_UNWINDING /* EABI: Don't unwind beyond the thread enty point. */ 490266311Sian mov fp, #0 /* OABI: Stack traceback via fp stops here. */ 491266311Sian mov r2, sp 492129198Scognet mov r1, r5 493129198Scognet mov r0, r4 494266311Sian ldr lr, =swi_exit /* Go finish forking, then return */ 495266311Sian b _C_LABEL(fork_exit) /* to userland via swi_exit code. */ 496248361SandrewEND(fork_trampoline) 497248361Sandrew 498