fpu_emu.h revision 92991
1/* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 43 * $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ 44 * $FreeBSD: head/lib/libc/sparc64/fpu/fpu_emu.h 92991 2002-03-22 23:42:05Z obrien $ 45 */ 46 47/* 48 * Floating point emulator (tailored for SPARC, but structurally 49 * machine-independent). 50 * 51 * Floating point numbers are carried around internally in an `expanded' 52 * or `unpacked' form consisting of: 53 * - sign 54 * - unbiased exponent 55 * - mantissa (`1.' + 112-bit fraction + guard + round) 56 * - sticky bit 57 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 58 * always nonzero. Additional low-order `guard' and `round' bits are 59 * scrunched in, making the entire mantissa 115 bits long. This is divided 60 * into four 32-bit words, with `spare' bits left over in the upper part 61 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 62 * number is thus kept within the half-open interval [1.0,2.0) (but see 63 * the `number classes' below). This holds even for denormalized numbers: 64 * when we explode an external denorm, we normalize it, introducing low-order 65 * zero bits, so that the rest of the code always sees normalized values. 66 * 67 * Note that a number of our algorithms use the `spare' bits at the top. 68 * The most demanding algorithm---the one for sqrt---depends on two such 69 * bits, so that it can represent values up to (but not including) 8.0, 70 * and then it needs a carry on top of that, so that we need three `spares'. 71 * 72 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 73 * whole words from the mantissa into it. 74 * 75 * All operations are done in this internal extended precision. According 76 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 77 * it is OK to do a+b in extended precision and then round the result to 78 * single precision---provided single, double, and extended precisions are 79 * `far enough apart' (they always are), but we will try to avoid any such 80 * extra work where possible. 81 */ 82 83#ifndef _SPARC64_FPU_FPU_EMU_H_ 84#define _SPARC64_FPU_FPU_EMU_H_ 85 86#include "fpu_reg.h" 87 88struct fpn { 89 int fp_class; /* see below */ 90 int fp_sign; /* 0 => positive, 1 => negative */ 91 int fp_exp; /* exponent (unbiased) */ 92 int fp_sticky; /* nonzero bits lost at right end */ 93 u_int fp_mant[4]; /* 115-bit mantissa */ 94}; 95 96#define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 97#define FP_NG 2 /* number of low-order guard bits */ 98#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 99#define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 100#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 101#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 102#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 103 104/* 105 * Number classes. Since zero, Inf, and NaN cannot be represented using 106 * the above layout, we distinguish these from other numbers via a class. 107 * In addition, to make computation easier and to follow Appendix N of 108 * the SPARC Version 8 standard, we give each kind of NaN a separate class. 109 */ 110#define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 111#define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 112#define FPC_ZERO 0 /* zero (sign matters) */ 113#define FPC_NUM 1 /* number (sign matters) */ 114#define FPC_INF 2 /* infinity (sign matters) */ 115 116#define ISNAN(fp) ((fp)->fp_class < 0) 117#define ISZERO(fp) ((fp)->fp_class == 0) 118#define ISINF(fp) ((fp)->fp_class == FPC_INF) 119 120/* 121 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 122 * to the `more significant' operand for our purposes. Appendix N says that 123 * the result of a computation involving two numbers are: 124 * 125 * If both are SNaN: operand 2, converted to Quiet 126 * If only one is SNaN: the SNaN operand, converted to Quiet 127 * If both are QNaN: operand 2 128 * If only one is QNaN: the QNaN operand 129 * 130 * In addition, in operations with an Inf operand, the result is usually 131 * Inf. The class numbers are carefully arranged so that if 132 * (unsigned)class(op1) > (unsigned)class(op2) 133 * then op1 is the one we want; otherwise op2 is the one we want. 134 */ 135#define ORDER(x, y) { \ 136 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 137 SWAP(x, y); \ 138} 139#define SWAP(x, y) { \ 140 register struct fpn *swap; \ 141 swap = (x), (x) = (y), (y) = swap; \ 142} 143 144/* 145 * Floating point operand types. FTYPE_LNG is syntethic (it does not occur in 146 * instructions). 147 */ 148#define FTYPE_INT INSFP_i 149#define FTYPE_SNG INSFP_s 150#define FTYPE_DBL INSFP_d 151#define FTYPE_EXT INSFP_q 152#define FTYPE_LNG -1 153 154/* 155 * Emulator state. 156 */ 157struct fpemu { 158 u_long fe_fsr; /* fsr copy (modified during op) */ 159 int fe_cx; /* exceptions */ 160 struct fpn fe_f1; /* operand 1 */ 161 struct fpn fe_f2; /* operand 2, if required */ 162 struct fpn fe_f3; /* available storage for result */ 163}; 164 165/* 166 * Arithmetic functions. 167 * Each of these may modify its inputs (f1,f2) and/or the temporary. 168 * Each returns a pointer to the result and/or sets exceptions. 169 */ 170#define __fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, __fpu_add(fe)) 171 172#ifdef FPU_DEBUG 173#define FPE_INSN 0x1 174#define FPE_REG 0x2 175extern int __fpe_debug; 176void __fpu_dumpfpn(struct fpn *); 177#define DPRINTF(x, y) if (__fpe_debug & (x)) printf y 178#define DUMPFPN(x, f) if (__fpe_debug & (x)) __fpu_dumpfpn((f)) 179#else 180#define DPRINTF(x, y) 181#define DUMPFPN(x, f) 182#endif 183 184#endif /* !_SPARC64_FPU_FPU_EXTERN_H_ */ 185