fpu_emu.h revision 91174
1/* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * from: @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 43 * from: NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh 44 * 45 * $FreeBSD: head/lib/libc/sparc64/fpu/fpu_emu.h 91174 2002-02-23 21:37:18Z tmm $ 46 */ 47 48/* 49 * Floating point emulator (tailored for SPARC, but structurally 50 * machine-independent). 51 * 52 * Floating point numbers are carried around internally in an `expanded' 53 * or `unpacked' form consisting of: 54 * - sign 55 * - unbiased exponent 56 * - mantissa (`1.' + 112-bit fraction + guard + round) 57 * - sticky bit 58 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 59 * always nonzero. Additional low-order `guard' and `round' bits are 60 * scrunched in, making the entire mantissa 115 bits long. This is divided 61 * into four 32-bit words, with `spare' bits left over in the upper part 62 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 63 * number is thus kept within the half-open interval [1.0,2.0) (but see 64 * the `number classes' below). This holds even for denormalized numbers: 65 * when we explode an external denorm, we normalize it, introducing low-order 66 * zero bits, so that the rest of the code always sees normalized values. 67 * 68 * Note that a number of our algorithms use the `spare' bits at the top. 69 * The most demanding algorithm---the one for sqrt---depends on two such 70 * bits, so that it can represent values up to (but not including) 8.0, 71 * and then it needs a carry on top of that, so that we need three `spares'. 72 * 73 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 74 * whole words from the mantissa into it. 75 * 76 * All operations are done in this internal extended precision. According 77 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 78 * it is OK to do a+b in extended precision and then round the result to 79 * single precision---provided single, double, and extended precisions are 80 * `far enough apart' (they always are), but we will try to avoid any such 81 * extra work where possible. 82 */ 83 84#ifndef _SPARC64_FPU_FPU_EMU_H_ 85#define _SPARC64_FPU_FPU_EMU_H_ 86 87#include "fpu_reg.h" 88 89struct fpn { 90 int fp_class; /* see below */ 91 int fp_sign; /* 0 => positive, 1 => negative */ 92 int fp_exp; /* exponent (unbiased) */ 93 int fp_sticky; /* nonzero bits lost at right end */ 94 u_int fp_mant[4]; /* 115-bit mantissa */ 95}; 96 97#define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 98#define FP_NG 2 /* number of low-order guard bits */ 99#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 100#define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 101#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 102#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 103#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 104 105/* 106 * Number classes. Since zero, Inf, and NaN cannot be represented using 107 * the above layout, we distinguish these from other numbers via a class. 108 * In addition, to make computation easier and to follow Appendix N of 109 * the SPARC Version 8 standard, we give each kind of NaN a separate class. 110 */ 111#define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 112#define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 113#define FPC_ZERO 0 /* zero (sign matters) */ 114#define FPC_NUM 1 /* number (sign matters) */ 115#define FPC_INF 2 /* infinity (sign matters) */ 116 117#define ISNAN(fp) ((fp)->fp_class < 0) 118#define ISZERO(fp) ((fp)->fp_class == 0) 119#define ISINF(fp) ((fp)->fp_class == FPC_INF) 120 121/* 122 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 123 * to the `more significant' operand for our purposes. Appendix N says that 124 * the result of a computation involving two numbers are: 125 * 126 * If both are SNaN: operand 2, converted to Quiet 127 * If only one is SNaN: the SNaN operand, converted to Quiet 128 * If both are QNaN: operand 2 129 * If only one is QNaN: the QNaN operand 130 * 131 * In addition, in operations with an Inf operand, the result is usually 132 * Inf. The class numbers are carefully arranged so that if 133 * (unsigned)class(op1) > (unsigned)class(op2) 134 * then op1 is the one we want; otherwise op2 is the one we want. 135 */ 136#define ORDER(x, y) { \ 137 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 138 SWAP(x, y); \ 139} 140#define SWAP(x, y) { \ 141 register struct fpn *swap; \ 142 swap = (x), (x) = (y), (y) = swap; \ 143} 144 145/* 146 * Floating point operand types. FTYPE_LNG is syntethic (it does not occur in 147 * instructions). 148 */ 149#define FTYPE_INT INSFP_i 150#define FTYPE_SNG INSFP_s 151#define FTYPE_DBL INSFP_d 152#define FTYPE_EXT INSFP_q 153#define FTYPE_LNG -1 154 155/* 156 * Emulator state. 157 */ 158struct fpemu { 159 int fe_fsr; /* fsr copy (modified during op) */ 160 int fe_cx; /* exceptions */ 161 struct fpn fe_f1; /* operand 1 */ 162 struct fpn fe_f2; /* operand 2, if required */ 163 struct fpn fe_f3; /* available storage for result */ 164}; 165 166/* 167 * Arithmetic functions. 168 * Each of these may modify its inputs (f1,f2) and/or the temporary. 169 * Each returns a pointer to the result and/or sets exceptions. 170 */ 171#define __fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, __fpu_add(fe)) 172 173#ifdef FPU_DEBUG 174#define FPE_INSN 0x1 175#define FPE_REG 0x2 176extern int __fpe_debug; 177void __fpu_dumpfpn(struct fpn *); 178#define DPRINTF(x, y) if (__fpe_debug & (x)) printf y 179#define DUMPFPN(x, f) if (__fpe_debug & (x)) __fpu_dumpfpn((f)) 180#else 181#define DPRINTF(x, y) 182#define DUMPFPN(x, f) 183#endif 184 185#endif /* !_SPARC64_FPU_FPU_EXTERN_H_ */ 186