fpu_emu.h revision 204974
1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 1992, 1993 3316485Sdavidcs * The Regents of the University of California. All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * This software was developed by the Computer Systems Engineering group 6316485Sdavidcs * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7316485Sdavidcs * contributed to Berkeley. 8316485Sdavidcs * 9316485Sdavidcs * Redistribution and use in source and binary forms, with or without 10316485Sdavidcs * modification, are permitted provided that the following conditions 11316485Sdavidcs * are met: 12316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 13316485Sdavidcs * notice, this list of conditions and the following disclaimer. 14316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 15316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 16316485Sdavidcs * documentation and/or other materials provided with the distribution. 17316485Sdavidcs * 4. Neither the name of the University nor the names of its contributors 18316485Sdavidcs * may be used to endorse or promote products derived from this software 19316485Sdavidcs * without specific prior written permission. 20316485Sdavidcs * 21316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22316485Sdavidcs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25316485Sdavidcs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26316485Sdavidcs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27316485Sdavidcs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28316485Sdavidcs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29316485Sdavidcs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30316485Sdavidcs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31320164Sdavidcs * SUCH DAMAGE. 32316485Sdavidcs * 33316485Sdavidcs * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 34316485Sdavidcs * $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ 35316485Sdavidcs * $FreeBSD: head/lib/libc/sparc64/fpu/fpu_emu.h 204974 2010-03-10 19:55:48Z marius $ 36316485Sdavidcs */ 37316485Sdavidcs 38316485Sdavidcs/* 39316485Sdavidcs * Floating point emulator (tailored for SPARC, but structurally 40316485Sdavidcs * machine-independent). 41316485Sdavidcs * 42316485Sdavidcs * Floating point numbers are carried around internally in an `expanded' 43316485Sdavidcs * or `unpacked' form consisting of: 44337517Sdavidcs * - sign 45337517Sdavidcs * - unbiased exponent 46316485Sdavidcs * - mantissa (`1.' + 112-bit fraction + guard + round) 47316485Sdavidcs * - sticky bit 48316485Sdavidcs * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 49316485Sdavidcs * always nonzero. Additional low-order `guard' and `round' bits are 50316485Sdavidcs * scrunched in, making the entire mantissa 115 bits long. This is divided 51316485Sdavidcs * into four 32-bit words, with `spare' bits left over in the upper part 52316485Sdavidcs * of the top word (the high bits of fp_mant[0]). An internal `exploded' 53316485Sdavidcs * number is thus kept within the half-open interval [1.0,2.0) (but see 54316485Sdavidcs * the `number classes' below). This holds even for denormalized numbers: 55316485Sdavidcs * when we explode an external denorm, we normalize it, introducing low-order 56316485Sdavidcs * zero bits, so that the rest of the code always sees normalized values. 57316485Sdavidcs * 58316485Sdavidcs * Note that a number of our algorithms use the `spare' bits at the top. 59316485Sdavidcs * The most demanding algorithm---the one for sqrt---depends on two such 60316485Sdavidcs * bits, so that it can represent values up to (but not including) 8.0, 61316485Sdavidcs * and then it needs a carry on top of that, so that we need three `spares'. 62316485Sdavidcs * 63316485Sdavidcs * The sticky-word is 32 bits so that we can use `OR' operators to goosh 64316485Sdavidcs * whole words from the mantissa into it. 65316485Sdavidcs * 66316485Sdavidcs * All operations are done in this internal extended precision. According 67316485Sdavidcs * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 68316485Sdavidcs * it is OK to do a+b in extended precision and then round the result to 69316485Sdavidcs * single precision---provided single, double, and extended precisions are 70316485Sdavidcs * `far enough apart' (they always are), but we will try to avoid any such 71316485Sdavidcs * extra work where possible. 72316485Sdavidcs */ 73316485Sdavidcs 74316485Sdavidcs#ifndef _SPARC64_FPU_FPU_EMU_H_ 75316485Sdavidcs#define _SPARC64_FPU_FPU_EMU_H_ 76316485Sdavidcs 77316485Sdavidcs#include "fpu_reg.h" 78316485Sdavidcs 79316485Sdavidcsstruct fpn { 80316485Sdavidcs int fp_class; /* see below */ 81316485Sdavidcs int fp_sign; /* 0 => positive, 1 => negative */ 82316485Sdavidcs int fp_exp; /* exponent (unbiased) */ 83316485Sdavidcs int fp_sticky; /* nonzero bits lost at right end */ 84316485Sdavidcs u_int fp_mant[4]; /* 115-bit mantissa */ 85316485Sdavidcs}; 86316485Sdavidcs 87316485Sdavidcs#define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 88316485Sdavidcs#define FP_NG 2 /* number of low-order guard bits */ 89316485Sdavidcs#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 90316485Sdavidcs#define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 91316485Sdavidcs#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 92316485Sdavidcs#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 93316485Sdavidcs#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 94316485Sdavidcs 95316485Sdavidcs/* 96316485Sdavidcs * Number classes. Since zero, Inf, and NaN cannot be represented using 97316485Sdavidcs * the above layout, we distinguish these from other numbers via a class. 98316485Sdavidcs * In addition, to make computation easier and to follow Appendix N of 99316485Sdavidcs * the SPARC Version 8 standard, we give each kind of NaN a separate class. 100316485Sdavidcs */ 101316485Sdavidcs#define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 102316485Sdavidcs#define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 103316485Sdavidcs#define FPC_ZERO 0 /* zero (sign matters) */ 104316485Sdavidcs#define FPC_NUM 1 /* number (sign matters) */ 105316485Sdavidcs#define FPC_INF 2 /* infinity (sign matters) */ 106316485Sdavidcs 107316485Sdavidcs#define ISNAN(fp) ((fp)->fp_class < 0) 108316485Sdavidcs#define ISZERO(fp) ((fp)->fp_class == 0) 109316485Sdavidcs#define ISINF(fp) ((fp)->fp_class == FPC_INF) 110316485Sdavidcs 111316485Sdavidcs/* 112316485Sdavidcs * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 113316485Sdavidcs * to the `more significant' operand for our purposes. Appendix N says that 114337517Sdavidcs * the result of a computation involving two numbers are: 115337517Sdavidcs * 116337517Sdavidcs * If both are SNaN: operand 2, converted to Quiet 117337517Sdavidcs * If only one is SNaN: the SNaN operand, converted to Quiet 118337517Sdavidcs * If both are QNaN: operand 2 119337517Sdavidcs * If only one is QNaN: the QNaN operand 120316485Sdavidcs * 121316485Sdavidcs * In addition, in operations with an Inf operand, the result is usually 122316485Sdavidcs * Inf. The class numbers are carefully arranged so that if 123316485Sdavidcs * (unsigned)class(op1) > (unsigned)class(op2) 124316485Sdavidcs * then op1 is the one we want; otherwise op2 is the one we want. 125316485Sdavidcs */ 126316485Sdavidcs#define ORDER(x, y) { \ 127316485Sdavidcs if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 128316485Sdavidcs SWAP(x, y); \ 129316485Sdavidcs} 130316485Sdavidcs#define SWAP(x, y) { \ 131316485Sdavidcs register struct fpn *swap; \ 132316485Sdavidcs swap = (x), (x) = (y), (y) = swap; \ 133316485Sdavidcs} 134316485Sdavidcs 135316485Sdavidcs/* 136316485Sdavidcs * Floating point operand types. FTYPE_LNG is syntethic (it does not occur in 137316485Sdavidcs * instructions). 138316485Sdavidcs */ 139316485Sdavidcs#define FTYPE_INT INSFP_i 140316485Sdavidcs#define FTYPE_SNG INSFP_s 141316485Sdavidcs#define FTYPE_DBL INSFP_d 142316485Sdavidcs#define FTYPE_EXT INSFP_q 143316485Sdavidcs#define FTYPE_LNG 5 144316485Sdavidcs 145316485Sdavidcs/* 146316485Sdavidcs * Emulator state. 147316485Sdavidcs */ 148316485Sdavidcsstruct fpemu { 149316485Sdavidcs u_long fe_fsr; /* fsr copy (modified during op) */ 150316485Sdavidcs int fe_cx; /* exceptions */ 151316485Sdavidcs int pad; /* align access to following fields */ 152316485Sdavidcs struct fpn fe_f1; /* operand 1 */ 153316485Sdavidcs struct fpn fe_f2; /* operand 2, if required */ 154316485Sdavidcs struct fpn fe_f3; /* available storage for result */ 155316485Sdavidcs}; 156316485Sdavidcs 157316485Sdavidcs/* 158316485Sdavidcs * Arithmetic functions. 159316485Sdavidcs * Each of these may modify its inputs (f1,f2) and/or the temporary. 160316485Sdavidcs * Each returns a pointer to the result and/or sets exceptions. 161316485Sdavidcs */ 162316485Sdavidcs#define __fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, __fpu_add(fe)) 163316485Sdavidcs 164316485Sdavidcs#ifdef FPU_DEBUG 165337517Sdavidcs#define FPE_INSN 0x1 166337517Sdavidcs#define FPE_REG 0x2 167337517Sdavidcsextern int __fpe_debug; 168337517Sdavidcsvoid __fpu_dumpfpn(struct fpn *); 169337517Sdavidcs#define DPRINTF(x, y) if (__fpe_debug & (x)) printf y 170337517Sdavidcs#define DUMPFPN(x, f) if (__fpe_debug & (x)) __fpu_dumpfpn((f)) 171337517Sdavidcs#else 172316485Sdavidcs#define DPRINTF(x, y) 173316485Sdavidcs#define DUMPFPN(x, f) 174316485Sdavidcs#endif 175316485Sdavidcs 176316485Sdavidcs#endif /* !_SPARC64_FPU_FPU_EXTERN_H_ */ 177316485Sdavidcs