fpu_emu.h revision 205002
1116759Ssam/* 2190425Ssam * Copyright (c) 1992, 1993 3116759Ssam * The Regents of the University of California. All rights reserved. 4116759Ssam * 5116759Ssam * This software was developed by the Computer Systems Engineering group 6116759Ssam * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7116759Ssam * contributed to Berkeley. 8116759Ssam * 9116759Ssam * Redistribution and use in source and binary forms, with or without 10116759Ssam * modification, are permitted provided that the following conditions 11116759Ssam * are met: 12116759Ssam * 1. Redistributions of source code must retain the above copyright 13116759Ssam * notice, this list of conditions and the following disclaimer. 14116759Ssam * 2. Redistributions in binary form must reproduce the above copyright 15116759Ssam * notice, this list of conditions and the following disclaimer in the 16116759Ssam * documentation and/or other materials provided with the distribution. 17116759Ssam * 4. Neither the name of the University nor the names of its contributors 18116759Ssam * may be used to endorse or promote products derived from this software 19116759Ssam * without specific prior written permission. 20116759Ssam * 21116759Ssam * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22116759Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23116759Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24116759Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25116759Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26116759Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27116759Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28116759Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29116759Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30116759Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31253551Spluknet * SUCH DAMAGE. 32116759Ssam * 33116759Ssam * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 34116759Ssam * $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ 35116759Ssam * $FreeBSD: head/lib/libc/sparc64/fpu/fpu_emu.h 205002 2010-03-11 07:46:17Z marius $ 36116759Ssam */ 37116759Ssam 38116759Ssam/* 39185522Ssam * Floating point emulator (tailored for SPARC, but structurally 40185522Ssam * machine-independent). 41185522Ssam * 42185522Ssam * Floating point numbers are carried around internally in an `expanded' 43185522Ssam * or `unpacked' form consisting of: 44185522Ssam * - sign 45185522Ssam * - unbiased exponent 46185522Ssam * - mantissa (`1.' + 112-bit fraction + guard + round) 47185522Ssam * - sticky bit 48185522Ssam * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 49185522Ssam * always nonzero. Additional low-order `guard' and `round' bits are 50185522Ssam * scrunched in, making the entire mantissa 115 bits long. This is divided 51185522Ssam * into four 32-bit words, with `spare' bits left over in the upper part 52185522Ssam * of the top word (the high bits of fp_mant[0]). An internal `exploded' 53185522Ssam * number is thus kept within the half-open interval [1.0,2.0) (but see 54222489Sadrian * the `number classes' below). This holds even for denormalized numbers: 55185522Ssam * when we explode an external denorm, we normalize it, introducing low-order 56190425Ssam * zero bits, so that the rest of the code always sees normalized values. 57222489Sadrian * 58222489Sadrian * Note that a number of our algorithms use the `spare' bits at the top. 59253551Spluknet * The most demanding algorithm---the one for sqrt---depends on two such 60185522Ssam * bits, so that it can represent values up to (but not including) 8.0, 61116759Ssam * and then it needs a carry on top of that, so that we need three `spares'. 62185522Ssam * 63190425Ssam * The sticky-word is 32 bits so that we can use `OR' operators to goosh 64253551Spluknet * whole words from the mantissa into it. 65253551Spluknet * 66222489Sadrian * All operations are done in this internal extended precision. According 67185522Ssam * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 68185522Ssam * it is OK to do a+b in extended precision and then round the result to 69185522Ssam * single precision---provided single, double, and extended precisions are 70185522Ssam * `far enough apart' (they always are), but we will try to avoid any such 71185522Ssam * extra work where possible. 72116759Ssam */ 73185522Ssam 74222489Sadrian#ifndef _SPARC64_FPU_FPU_EMU_H_ 75222489Sadrian#define _SPARC64_FPU_FPU_EMU_H_ 76185522Ssam 77185522Ssam#include "fpu_reg.h" 78185522Ssam 79116759Ssamstruct fpn { 80220019Sadrian int fp_class; /* see below */ 81222489Sadrian int fp_sign; /* 0 => positive, 1 => negative */ 82222489Sadrian int fp_exp; /* exponent (unbiased) */ 83185522Ssam int fp_sticky; /* nonzero bits lost at right end */ 84185522Ssam u_int fp_mant[4]; /* 115-bit mantissa */ 85185522Ssam}; 86185522Ssam 87185522Ssam#define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 88134322Ssimon#define FP_NG 2 /* number of low-order guard bits */ 89116759Ssam#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 90116759Ssam#define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 91116759Ssam#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 92116759Ssam#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 93122086Ssam#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 94134322Ssimon 95140297Sru/* 96140297Sru * Number classes. Since zero, Inf, and NaN cannot be represented using 97140297Sru * the above layout, we distinguish these from other numbers via a class. 98140297Sru * In addition, to make computation easier and to follow Appendix N of 99140297Sru * the SPARC Version 8 standard, we give each kind of NaN a separate class. 100140297Sru */ 101140297Sru#define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 102140297Sru#define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 103140297Sru#define FPC_ZERO 0 /* zero (sign matters) */ 104140297Sru#define FPC_NUM 1 /* number (sign matters) */ 105140297Sru#define FPC_INF 2 /* infinity (sign matters) */ 106140297Sru 107140297Sru#define ISNAN(fp) ((fp)->fp_class < 0) 108140297Sru#define ISZERO(fp) ((fp)->fp_class == 0) 109140297Sru#define ISINF(fp) ((fp)->fp_class == FPC_INF) 110140297Sru 111140297Sru/* 112140297Sru * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 113140297Sru * to the `more significant' operand for our purposes. Appendix N says that 114140297Sru * the result of a computation involving two numbers are: 115140297Sru * 116140297Sru * If both are SNaN: operand 2, converted to Quiet 117140297Sru * If only one is SNaN: the SNaN operand, converted to Quiet 118140297Sru * If both are QNaN: operand 2 119218523Sjpaetzel * If only one is QNaN: the QNaN operand 120218523Sjpaetzel * 121218523Sjpaetzel * In addition, in operations with an Inf operand, the result is usually 122140297Sru * Inf. The class numbers are carefully arranged so that if 123140297Sru * (unsigned)class(op1) > (unsigned)class(op2) 124140297Sru * then op1 is the one we want; otherwise op2 is the one we want. 125140297Sru */ 126140297Sru#define ORDER(x, y) { \ 127140297Sru if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 128140297Sru SWAP(x, y); \ 129140297Sru} 130140297Sru#define SWAP(x, y) { \ 131140297Sru register struct fpn *swap; \ 132140297Sru swap = (x), (x) = (y), (y) = swap; \ 133253552Spluknet} 134116759Ssam 135116759Ssam/* 136117727Shmp * Floating point operand types. FTYPE_LNG is syntethic (it does not occur in 137116759Ssam * instructions). 138116759Ssam */ 139116759Ssam#define FTYPE_INT INSFP_i 140116759Ssam#define FTYPE_SNG INSFP_s 141116759Ssam#define FTYPE_DBL INSFP_d 142116759Ssam#define FTYPE_EXT INSFP_q 143116759Ssam#define FTYPE_LNG 4 144116759Ssam 145116759Ssam/* 146 * Emulator state. 147 */ 148struct fpemu { 149 u_long fe_fsr; /* fsr copy (modified during op) */ 150 int fe_cx; /* exceptions */ 151 int pad; /* align access to following fields */ 152 struct fpn fe_f1; /* operand 1 */ 153 struct fpn fe_f2; /* operand 2, if required */ 154 struct fpn fe_f3; /* available storage for result */ 155}; 156 157/* 158 * Arithmetic functions. 159 * Each of these may modify its inputs (f1,f2) and/or the temporary. 160 * Each returns a pointer to the result and/or sets exceptions. 161 */ 162#define __fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, __fpu_add(fe)) 163 164#ifdef FPU_DEBUG 165#define FPE_INSN 0x1 166#define FPE_REG 0x2 167extern int __fpe_debug; 168void __fpu_dumpfpn(struct fpn *); 169#define DPRINTF(x, y) if (__fpe_debug & (x)) printf y 170#define DUMPFPN(x, f) if (__fpe_debug & (x)) __fpu_dumpfpn((f)) 171#else 172#define DPRINTF(x, y) 173#define DUMPFPN(x, f) 174#endif 175 176#endif /* !_SPARC64_FPU_FPU_EXTERN_H_ */ 177