1249259Sdim//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief This is the parent TargetLowering class for hardware code gen 12249259Sdim/// targets. 13249259Sdim// 14249259Sdim//===----------------------------------------------------------------------===// 15249259Sdim 16249259Sdim#include "AMDGPUISelLowering.h" 17263508Sdim#include "AMDGPU.h" 18263508Sdim#include "AMDGPUFrameLowering.h" 19249259Sdim#include "AMDGPURegisterInfo.h" 20263508Sdim#include "AMDGPUSubtarget.h" 21249259Sdim#include "AMDILIntrinsicInfo.h" 22263508Sdim#include "R600MachineFunctionInfo.h" 23263508Sdim#include "SIMachineFunctionInfo.h" 24249259Sdim#include "llvm/CodeGen/CallingConvLower.h" 25249259Sdim#include "llvm/CodeGen/MachineFunction.h" 26249259Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 27249259Sdim#include "llvm/CodeGen/SelectionDAG.h" 28249259Sdim#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29263508Sdim#include "llvm/IR/DataLayout.h" 30249259Sdim 31249259Sdimusing namespace llvm; 32263508Sdimstatic bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT, 33263508Sdim CCValAssign::LocInfo LocInfo, 34263508Sdim ISD::ArgFlagsTy ArgFlags, CCState &State) { 35263508Sdim unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() / 8, ArgFlags.getOrigAlign()); 36263508Sdim State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 37249259Sdim 38263508Sdim return true; 39263508Sdim} 40263508Sdim 41249259Sdim#include "AMDGPUGenCallingConv.inc" 42249259Sdim 43249259SdimAMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : 44249259Sdim TargetLowering(TM, new TargetLoweringObjectFileELF()) { 45249259Sdim 46249259Sdim // Initialize target lowering borrowed from AMDIL 47249259Sdim InitAMDILLowering(); 48249259Sdim 49249259Sdim // We need to custom lower some of the intrinsics 50249259Sdim setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 51249259Sdim 52249259Sdim // Library functions. These default to Expand, but we have instructions 53249259Sdim // for them. 54249259Sdim setOperationAction(ISD::FCEIL, MVT::f32, Legal); 55249259Sdim setOperationAction(ISD::FEXP2, MVT::f32, Legal); 56249259Sdim setOperationAction(ISD::FPOW, MVT::f32, Legal); 57249259Sdim setOperationAction(ISD::FLOG2, MVT::f32, Legal); 58249259Sdim setOperationAction(ISD::FABS, MVT::f32, Legal); 59249259Sdim setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 60249259Sdim setOperationAction(ISD::FRINT, MVT::f32, Legal); 61263508Sdim setOperationAction(ISD::FROUND, MVT::f32, Legal); 62249259Sdim 63263508Sdim // The hardware supports ROTR, but not ROTL 64263508Sdim setOperationAction(ISD::ROTL, MVT::i32, Expand); 65263508Sdim 66249259Sdim // Lower floating point store/load to integer store/load to reduce the number 67249259Sdim // of patterns in tablegen. 68249259Sdim setOperationAction(ISD::STORE, MVT::f32, Promote); 69249259Sdim AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); 70249259Sdim 71263508Sdim setOperationAction(ISD::STORE, MVT::v2f32, Promote); 72263508Sdim AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); 73263508Sdim 74249259Sdim setOperationAction(ISD::STORE, MVT::v4f32, Promote); 75249259Sdim AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); 76249259Sdim 77263508Sdim setOperationAction(ISD::STORE, MVT::v8f32, Promote); 78263508Sdim AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); 79263508Sdim 80263508Sdim setOperationAction(ISD::STORE, MVT::v16f32, Promote); 81263508Sdim AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); 82263508Sdim 83263508Sdim setOperationAction(ISD::STORE, MVT::f64, Promote); 84263508Sdim AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64); 85263508Sdim 86263508Sdim // Custom lowering of vector stores is required for local address space 87263508Sdim // stores. 88263508Sdim setOperationAction(ISD::STORE, MVT::v4i32, Custom); 89263508Sdim // XXX: Native v2i32 local address space stores are possible, but not 90263508Sdim // currently implemented. 91263508Sdim setOperationAction(ISD::STORE, MVT::v2i32, Custom); 92263508Sdim 93263508Sdim setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); 94263508Sdim setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); 95263508Sdim setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); 96263508Sdim // XXX: This can be change to Custom, once ExpandVectorStores can 97263508Sdim // handle 64-bit stores. 98263508Sdim setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand); 99263508Sdim 100249259Sdim setOperationAction(ISD::LOAD, MVT::f32, Promote); 101249259Sdim AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); 102249259Sdim 103263508Sdim setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 104263508Sdim AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); 105263508Sdim 106249259Sdim setOperationAction(ISD::LOAD, MVT::v4f32, Promote); 107249259Sdim AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); 108249259Sdim 109263508Sdim setOperationAction(ISD::LOAD, MVT::v8f32, Promote); 110263508Sdim AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); 111263508Sdim 112263508Sdim setOperationAction(ISD::LOAD, MVT::v16f32, Promote); 113263508Sdim AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); 114263508Sdim 115263508Sdim setOperationAction(ISD::LOAD, MVT::f64, Promote); 116263508Sdim AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64); 117263508Sdim 118263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 119263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); 120263508Sdim setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); 121263508Sdim setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); 122263508Sdim 123263508Sdim setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand); 124263508Sdim setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand); 125263508Sdim setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand); 126263508Sdim setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand); 127263508Sdim setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand); 128263508Sdim setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand); 129263508Sdim setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand); 130263508Sdim setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand); 131263508Sdim setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand); 132263508Sdim setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand); 133263508Sdim setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand); 134263508Sdim setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand); 135263508Sdim 136266715Sdim setOperationAction(ISD::BR_CC, MVT::i1, Expand); 137266715Sdim 138263508Sdim setOperationAction(ISD::FNEG, MVT::v2f32, Expand); 139263508Sdim setOperationAction(ISD::FNEG, MVT::v4f32, Expand); 140263508Sdim 141263508Sdim setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 142263508Sdim 143249259Sdim setOperationAction(ISD::MUL, MVT::i64, Expand); 144249259Sdim 145249259Sdim setOperationAction(ISD::UDIV, MVT::i32, Expand); 146249259Sdim setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 147249259Sdim setOperationAction(ISD::UREM, MVT::i32, Expand); 148263508Sdim setOperationAction(ISD::VSELECT, MVT::v2f32, Expand); 149263508Sdim setOperationAction(ISD::VSELECT, MVT::v4f32, Expand); 150263508Sdim 151263508Sdim static const MVT::SimpleValueType IntTypes[] = { 152263508Sdim MVT::v2i32, MVT::v4i32 153263508Sdim }; 154263508Sdim const size_t NumIntTypes = array_lengthof(IntTypes); 155263508Sdim 156263508Sdim for (unsigned int x = 0; x < NumIntTypes; ++x) { 157263508Sdim MVT::SimpleValueType VT = IntTypes[x]; 158263508Sdim //Expand the following operations for the current type by default 159263508Sdim setOperationAction(ISD::ADD, VT, Expand); 160263508Sdim setOperationAction(ISD::AND, VT, Expand); 161263508Sdim setOperationAction(ISD::FP_TO_SINT, VT, Expand); 162263508Sdim setOperationAction(ISD::FP_TO_UINT, VT, Expand); 163263508Sdim setOperationAction(ISD::MUL, VT, Expand); 164263508Sdim setOperationAction(ISD::OR, VT, Expand); 165263508Sdim setOperationAction(ISD::SHL, VT, Expand); 166263508Sdim setOperationAction(ISD::SINT_TO_FP, VT, Expand); 167263508Sdim setOperationAction(ISD::SRL, VT, Expand); 168263508Sdim setOperationAction(ISD::SRA, VT, Expand); 169263508Sdim setOperationAction(ISD::SUB, VT, Expand); 170263508Sdim setOperationAction(ISD::UDIV, VT, Expand); 171263508Sdim setOperationAction(ISD::UINT_TO_FP, VT, Expand); 172263508Sdim setOperationAction(ISD::UREM, VT, Expand); 173263508Sdim setOperationAction(ISD::VSELECT, VT, Expand); 174263508Sdim setOperationAction(ISD::XOR, VT, Expand); 175263508Sdim } 176263508Sdim 177263508Sdim static const MVT::SimpleValueType FloatTypes[] = { 178263508Sdim MVT::v2f32, MVT::v4f32 179263508Sdim }; 180263508Sdim const size_t NumFloatTypes = array_lengthof(FloatTypes); 181263508Sdim 182263508Sdim for (unsigned int x = 0; x < NumFloatTypes; ++x) { 183263508Sdim MVT::SimpleValueType VT = FloatTypes[x]; 184263508Sdim setOperationAction(ISD::FABS, VT, Expand); 185263508Sdim setOperationAction(ISD::FADD, VT, Expand); 186263508Sdim setOperationAction(ISD::FDIV, VT, Expand); 187263508Sdim setOperationAction(ISD::FFLOOR, VT, Expand); 188263508Sdim setOperationAction(ISD::FMUL, VT, Expand); 189263508Sdim setOperationAction(ISD::FRINT, VT, Expand); 190263508Sdim setOperationAction(ISD::FSQRT, VT, Expand); 191263508Sdim setOperationAction(ISD::FSUB, VT, Expand); 192263508Sdim } 193249259Sdim} 194249259Sdim 195263508Sdim//===----------------------------------------------------------------------===// 196263508Sdim// Target Information 197263508Sdim//===----------------------------------------------------------------------===// 198263508Sdim 199263508SdimMVT AMDGPUTargetLowering::getVectorIdxTy() const { 200263508Sdim return MVT::i32; 201263508Sdim} 202263508Sdim 203263508Sdimbool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, 204263508Sdim EVT CastTy) const { 205263508Sdim if (LoadTy.getSizeInBits() != CastTy.getSizeInBits()) 206263508Sdim return true; 207263508Sdim 208263508Sdim unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits(); 209263508Sdim unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits(); 210263508Sdim 211263508Sdim return ((LScalarSize <= CastScalarSize) || 212263508Sdim (CastScalarSize >= 32) || 213263508Sdim (LScalarSize < 32)); 214263508Sdim} 215263508Sdim 216249259Sdim//===---------------------------------------------------------------------===// 217263508Sdim// Target Properties 218263508Sdim//===---------------------------------------------------------------------===// 219263508Sdim 220263508Sdimbool AMDGPUTargetLowering::isFAbsFree(EVT VT) const { 221263508Sdim assert(VT.isFloatingPoint()); 222263508Sdim return VT == MVT::f32; 223263508Sdim} 224263508Sdim 225263508Sdimbool AMDGPUTargetLowering::isFNegFree(EVT VT) const { 226263508Sdim assert(VT.isFloatingPoint()); 227263508Sdim return VT == MVT::f32; 228263508Sdim} 229263508Sdim 230263508Sdim//===---------------------------------------------------------------------===// 231249259Sdim// TargetLowering Callbacks 232249259Sdim//===---------------------------------------------------------------------===// 233249259Sdim 234249259Sdimvoid AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State, 235249259Sdim const SmallVectorImpl<ISD::InputArg> &Ins) const { 236249259Sdim 237249259Sdim State.AnalyzeFormalArguments(Ins, CC_AMDGPU); 238249259Sdim} 239249259Sdim 240249259SdimSDValue AMDGPUTargetLowering::LowerReturn( 241249259Sdim SDValue Chain, 242249259Sdim CallingConv::ID CallConv, 243249259Sdim bool isVarArg, 244249259Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 245249259Sdim const SmallVectorImpl<SDValue> &OutVals, 246263508Sdim SDLoc DL, SelectionDAG &DAG) const { 247249259Sdim return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); 248249259Sdim} 249249259Sdim 250249259Sdim//===---------------------------------------------------------------------===// 251249259Sdim// Target specific lowering 252249259Sdim//===---------------------------------------------------------------------===// 253249259Sdim 254249259SdimSDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 255249259Sdim const { 256249259Sdim switch (Op.getOpcode()) { 257249259Sdim default: 258249259Sdim Op.getNode()->dump(); 259249259Sdim assert(0 && "Custom lowering code for this" 260249259Sdim "instruction is not implemented yet!"); 261249259Sdim break; 262249259Sdim // AMDIL DAG lowering 263249259Sdim case ISD::SDIV: return LowerSDIV(Op, DAG); 264249259Sdim case ISD::SREM: return LowerSREM(Op, DAG); 265249259Sdim case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 266249259Sdim case ISD::BRCOND: return LowerBRCOND(Op, DAG); 267249259Sdim // AMDGPU DAG lowering 268263508Sdim case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 269263508Sdim case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 270263508Sdim case ISD::FrameIndex: return LowerFrameIndex(Op, DAG); 271249259Sdim case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 272249259Sdim case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); 273263508Sdim case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 274249259Sdim } 275249259Sdim return Op; 276249259Sdim} 277249259Sdim 278263508SdimSDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI, 279263508Sdim SDValue Op, 280263508Sdim SelectionDAG &DAG) const { 281263508Sdim 282263508Sdim const DataLayout *TD = getTargetMachine().getDataLayout(); 283263508Sdim GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op); 284263508Sdim 285263508Sdim assert(G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS); 286263508Sdim // XXX: What does the value of G->getOffset() mean? 287263508Sdim assert(G->getOffset() == 0 && 288263508Sdim "Do not know what to do with an non-zero offset"); 289263508Sdim 290263508Sdim const GlobalValue *GV = G->getGlobal(); 291263508Sdim 292263508Sdim unsigned Offset; 293263508Sdim if (MFI->LocalMemoryObjects.count(GV) == 0) { 294263508Sdim uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType()); 295263508Sdim Offset = MFI->LDSSize; 296263508Sdim MFI->LocalMemoryObjects[GV] = Offset; 297263508Sdim // XXX: Account for alignment? 298263508Sdim MFI->LDSSize += Size; 299263508Sdim } else { 300263508Sdim Offset = MFI->LocalMemoryObjects[GV]; 301263508Sdim } 302263508Sdim 303263508Sdim return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace())); 304263508Sdim} 305263508Sdim 306263508Sdimvoid AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG, 307263508Sdim SmallVectorImpl<SDValue> &Args, 308263508Sdim unsigned Start, 309263508Sdim unsigned Count) const { 310263508Sdim EVT VT = Op.getValueType(); 311263508Sdim for (unsigned i = Start, e = Start + Count; i != e; ++i) { 312263508Sdim Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), 313263508Sdim VT.getVectorElementType(), 314263508Sdim Op, DAG.getConstant(i, MVT::i32))); 315263508Sdim } 316263508Sdim} 317263508Sdim 318263508SdimSDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op, 319263508Sdim SelectionDAG &DAG) const { 320263508Sdim SmallVector<SDValue, 8> Args; 321263508Sdim SDValue A = Op.getOperand(0); 322263508Sdim SDValue B = Op.getOperand(1); 323263508Sdim 324263508Sdim ExtractVectorElements(A, DAG, Args, 0, 325263508Sdim A.getValueType().getVectorNumElements()); 326263508Sdim ExtractVectorElements(B, DAG, Args, 0, 327263508Sdim B.getValueType().getVectorNumElements()); 328263508Sdim 329263508Sdim return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), 330263508Sdim &Args[0], Args.size()); 331263508Sdim} 332263508Sdim 333263508SdimSDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, 334263508Sdim SelectionDAG &DAG) const { 335263508Sdim 336263508Sdim SmallVector<SDValue, 8> Args; 337263508Sdim EVT VT = Op.getValueType(); 338263508Sdim unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 339263508Sdim ExtractVectorElements(Op.getOperand(0), DAG, Args, Start, 340263508Sdim VT.getVectorNumElements()); 341263508Sdim 342263508Sdim return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), 343263508Sdim &Args[0], Args.size()); 344263508Sdim} 345263508Sdim 346263508SdimSDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op, 347263508Sdim SelectionDAG &DAG) const { 348263508Sdim 349263508Sdim MachineFunction &MF = DAG.getMachineFunction(); 350263508Sdim const AMDGPUFrameLowering *TFL = 351263508Sdim static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering()); 352263508Sdim 353263508Sdim FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op); 354263508Sdim assert(FIN); 355263508Sdim 356263508Sdim unsigned FrameIndex = FIN->getIndex(); 357263508Sdim unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex); 358263508Sdim return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), 359263508Sdim Op.getValueType()); 360263508Sdim} 361263508Sdim 362249259SdimSDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 363249259Sdim SelectionDAG &DAG) const { 364249259Sdim unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 365263508Sdim SDLoc DL(Op); 366249259Sdim EVT VT = Op.getValueType(); 367249259Sdim 368249259Sdim switch (IntrinsicID) { 369249259Sdim default: return Op; 370249259Sdim case AMDGPUIntrinsic::AMDIL_abs: 371249259Sdim return LowerIntrinsicIABS(Op, DAG); 372249259Sdim case AMDGPUIntrinsic::AMDIL_exp: 373249259Sdim return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); 374249259Sdim case AMDGPUIntrinsic::AMDGPU_lrp: 375249259Sdim return LowerIntrinsicLRP(Op, DAG); 376249259Sdim case AMDGPUIntrinsic::AMDIL_fraction: 377249259Sdim return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); 378249259Sdim case AMDGPUIntrinsic::AMDIL_max: 379249259Sdim return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), 380249259Sdim Op.getOperand(2)); 381249259Sdim case AMDGPUIntrinsic::AMDGPU_imax: 382249259Sdim return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), 383249259Sdim Op.getOperand(2)); 384249259Sdim case AMDGPUIntrinsic::AMDGPU_umax: 385249259Sdim return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), 386249259Sdim Op.getOperand(2)); 387249259Sdim case AMDGPUIntrinsic::AMDIL_min: 388249259Sdim return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), 389249259Sdim Op.getOperand(2)); 390249259Sdim case AMDGPUIntrinsic::AMDGPU_imin: 391249259Sdim return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1), 392249259Sdim Op.getOperand(2)); 393249259Sdim case AMDGPUIntrinsic::AMDGPU_umin: 394249259Sdim return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1), 395249259Sdim Op.getOperand(2)); 396249259Sdim case AMDGPUIntrinsic::AMDIL_round_nearest: 397249259Sdim return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); 398249259Sdim } 399249259Sdim} 400249259Sdim 401249259Sdim///IABS(a) = SMAX(sub(0, a), a) 402249259SdimSDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op, 403249259Sdim SelectionDAG &DAG) const { 404249259Sdim 405263508Sdim SDLoc DL(Op); 406249259Sdim EVT VT = Op.getValueType(); 407249259Sdim SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), 408249259Sdim Op.getOperand(1)); 409249259Sdim 410249259Sdim return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1)); 411249259Sdim} 412249259Sdim 413249259Sdim/// Linear Interpolation 414249259Sdim/// LRP(a, b, c) = muladd(a, b, (1 - a) * c) 415249259SdimSDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, 416249259Sdim SelectionDAG &DAG) const { 417263508Sdim SDLoc DL(Op); 418249259Sdim EVT VT = Op.getValueType(); 419249259Sdim SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, 420249259Sdim DAG.getConstantFP(1.0f, MVT::f32), 421249259Sdim Op.getOperand(1)); 422249259Sdim SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, 423249259Sdim Op.getOperand(3)); 424249259Sdim return DAG.getNode(ISD::FADD, DL, VT, 425249259Sdim DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)), 426249259Sdim OneSubAC); 427249259Sdim} 428249259Sdim 429249259Sdim/// \brief Generate Min/Max node 430249259SdimSDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op, 431249259Sdim SelectionDAG &DAG) const { 432263508Sdim SDLoc DL(Op); 433249259Sdim EVT VT = Op.getValueType(); 434249259Sdim 435249259Sdim SDValue LHS = Op.getOperand(0); 436249259Sdim SDValue RHS = Op.getOperand(1); 437249259Sdim SDValue True = Op.getOperand(2); 438249259Sdim SDValue False = Op.getOperand(3); 439249259Sdim SDValue CC = Op.getOperand(4); 440249259Sdim 441249259Sdim if (VT != MVT::f32 || 442249259Sdim !((LHS == True && RHS == False) || (LHS == False && RHS == True))) { 443249259Sdim return SDValue(); 444249259Sdim } 445249259Sdim 446249259Sdim ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); 447249259Sdim switch (CCOpcode) { 448249259Sdim case ISD::SETOEQ: 449249259Sdim case ISD::SETONE: 450249259Sdim case ISD::SETUNE: 451249259Sdim case ISD::SETNE: 452249259Sdim case ISD::SETUEQ: 453249259Sdim case ISD::SETEQ: 454249259Sdim case ISD::SETFALSE: 455249259Sdim case ISD::SETFALSE2: 456249259Sdim case ISD::SETTRUE: 457249259Sdim case ISD::SETTRUE2: 458249259Sdim case ISD::SETUO: 459249259Sdim case ISD::SETO: 460249259Sdim assert(0 && "Operation should already be optimised !"); 461249259Sdim case ISD::SETULE: 462249259Sdim case ISD::SETULT: 463249259Sdim case ISD::SETOLE: 464249259Sdim case ISD::SETOLT: 465249259Sdim case ISD::SETLE: 466249259Sdim case ISD::SETLT: { 467249259Sdim if (LHS == True) 468249259Sdim return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS); 469249259Sdim else 470249259Sdim return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS); 471249259Sdim } 472249259Sdim case ISD::SETGT: 473249259Sdim case ISD::SETGE: 474249259Sdim case ISD::SETUGE: 475249259Sdim case ISD::SETOGE: 476249259Sdim case ISD::SETUGT: 477249259Sdim case ISD::SETOGT: { 478249259Sdim if (LHS == True) 479249259Sdim return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS); 480249259Sdim else 481249259Sdim return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS); 482249259Sdim } 483249259Sdim case ISD::SETCC_INVALID: 484249259Sdim assert(0 && "Invalid setcc condcode !"); 485249259Sdim } 486249259Sdim return Op; 487249259Sdim} 488249259Sdim 489263508SdimSDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op, 490263508Sdim SelectionDAG &DAG) const { 491263508Sdim LoadSDNode *Load = dyn_cast<LoadSDNode>(Op); 492263508Sdim EVT MemEltVT = Load->getMemoryVT().getVectorElementType(); 493263508Sdim EVT EltVT = Op.getValueType().getVectorElementType(); 494263508Sdim EVT PtrVT = Load->getBasePtr().getValueType(); 495263508Sdim unsigned NumElts = Load->getMemoryVT().getVectorNumElements(); 496263508Sdim SmallVector<SDValue, 8> Loads; 497263508Sdim SDLoc SL(Op); 498249259Sdim 499263508Sdim for (unsigned i = 0, e = NumElts; i != e; ++i) { 500263508Sdim SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(), 501263508Sdim DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT)); 502263508Sdim Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT, 503263508Sdim Load->getChain(), Ptr, 504263508Sdim MachinePointerInfo(Load->getMemOperand()->getValue()), 505263508Sdim MemEltVT, Load->isVolatile(), Load->isNonTemporal(), 506263508Sdim Load->getAlignment())); 507263508Sdim } 508263508Sdim return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), &Loads[0], 509263508Sdim Loads.size()); 510263508Sdim} 511249259Sdim 512263508SdimSDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op, 513263508Sdim SelectionDAG &DAG) const { 514263508Sdim StoreSDNode *Store = dyn_cast<StoreSDNode>(Op); 515263508Sdim EVT MemVT = Store->getMemoryVT(); 516263508Sdim unsigned MemBits = MemVT.getSizeInBits(); 517263508Sdim 518263508Sdim // Byte stores are really expensive, so if possible, try to pack 519263508Sdim // 32-bit vector truncatating store into an i32 store. 520263508Sdim // XXX: We could also handle optimize other vector bitwidths 521263508Sdim if (!MemVT.isVector() || MemBits > 32) { 522263508Sdim return SDValue(); 523263508Sdim } 524263508Sdim 525263508Sdim SDLoc DL(Op); 526263508Sdim const SDValue &Value = Store->getValue(); 527263508Sdim EVT VT = Value.getValueType(); 528263508Sdim const SDValue &Ptr = Store->getBasePtr(); 529263508Sdim EVT MemEltVT = MemVT.getVectorElementType(); 530263508Sdim unsigned MemEltBits = MemEltVT.getSizeInBits(); 531263508Sdim unsigned MemNumElements = MemVT.getVectorNumElements(); 532263508Sdim EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); 533263508Sdim SDValue Mask; 534263508Sdim switch(MemEltBits) { 535263508Sdim case 8: 536263508Sdim Mask = DAG.getConstant(0xFF, PackedVT); 537263508Sdim break; 538263508Sdim case 16: 539263508Sdim Mask = DAG.getConstant(0xFFFF, PackedVT); 540263508Sdim break; 541263508Sdim default: 542263508Sdim llvm_unreachable("Cannot lower this vector store"); 543263508Sdim } 544263508Sdim SDValue PackedValue; 545263508Sdim for (unsigned i = 0; i < MemNumElements; ++i) { 546263508Sdim EVT ElemVT = VT.getVectorElementType(); 547263508Sdim SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value, 548263508Sdim DAG.getConstant(i, MVT::i32)); 549263508Sdim Elt = DAG.getZExtOrTrunc(Elt, DL, PackedVT); 550263508Sdim Elt = DAG.getNode(ISD::AND, DL, PackedVT, Elt, Mask); 551263508Sdim SDValue Shift = DAG.getConstant(MemEltBits * i, PackedVT); 552263508Sdim Elt = DAG.getNode(ISD::SHL, DL, PackedVT, Elt, Shift); 553263508Sdim if (i == 0) { 554263508Sdim PackedValue = Elt; 555263508Sdim } else { 556263508Sdim PackedValue = DAG.getNode(ISD::OR, DL, PackedVT, PackedValue, Elt); 557263508Sdim } 558263508Sdim } 559263508Sdim return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr, 560263508Sdim MachinePointerInfo(Store->getMemOperand()->getValue()), 561263508Sdim Store->isVolatile(), Store->isNonTemporal(), 562263508Sdim Store->getAlignment()); 563263508Sdim} 564263508Sdim 565263508SdimSDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op, 566263508Sdim SelectionDAG &DAG) const { 567263508Sdim StoreSDNode *Store = cast<StoreSDNode>(Op); 568263508Sdim EVT MemEltVT = Store->getMemoryVT().getVectorElementType(); 569263508Sdim EVT EltVT = Store->getValue().getValueType().getVectorElementType(); 570263508Sdim EVT PtrVT = Store->getBasePtr().getValueType(); 571263508Sdim unsigned NumElts = Store->getMemoryVT().getVectorNumElements(); 572263508Sdim SDLoc SL(Op); 573263508Sdim 574263508Sdim SmallVector<SDValue, 8> Chains; 575263508Sdim 576263508Sdim for (unsigned i = 0, e = NumElts; i != e; ++i) { 577263508Sdim SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, 578263508Sdim Store->getValue(), DAG.getConstant(i, MVT::i32)); 579263508Sdim SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, 580263508Sdim Store->getBasePtr(), 581263508Sdim DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), 582263508Sdim PtrVT)); 583263508Sdim Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr, 584263508Sdim MachinePointerInfo(Store->getMemOperand()->getValue()), 585263508Sdim MemEltVT, Store->isVolatile(), Store->isNonTemporal(), 586263508Sdim Store->getAlignment())); 587263508Sdim } 588263508Sdim return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, &Chains[0], NumElts); 589263508Sdim} 590263508Sdim 591263508SdimSDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 592263508Sdim SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG); 593263508Sdim if (Result.getNode()) { 594263508Sdim return Result; 595263508Sdim } 596263508Sdim 597263508Sdim StoreSDNode *Store = cast<StoreSDNode>(Op); 598263508Sdim if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS || 599263508Sdim Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) && 600263508Sdim Store->getValue().getValueType().isVector()) { 601263508Sdim return SplitVectorStore(Op, DAG); 602263508Sdim } 603263508Sdim return SDValue(); 604263508Sdim} 605263508Sdim 606249259SdimSDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op, 607249259Sdim SelectionDAG &DAG) const { 608263508Sdim SDLoc DL(Op); 609249259Sdim EVT VT = Op.getValueType(); 610249259Sdim 611249259Sdim SDValue Num = Op.getOperand(0); 612249259Sdim SDValue Den = Op.getOperand(1); 613249259Sdim 614249259Sdim SmallVector<SDValue, 8> Results; 615249259Sdim 616249259Sdim // RCP = URECIP(Den) = 2^32 / Den + e 617249259Sdim // e is rounding error. 618249259Sdim SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den); 619249259Sdim 620249259Sdim // RCP_LO = umulo(RCP, Den) */ 621249259Sdim SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den); 622249259Sdim 623249259Sdim // RCP_HI = mulhu (RCP, Den) */ 624249259Sdim SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); 625249259Sdim 626249259Sdim // NEG_RCP_LO = -RCP_LO 627249259Sdim SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), 628249259Sdim RCP_LO); 629249259Sdim 630249259Sdim // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO) 631249259Sdim SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT), 632249259Sdim NEG_RCP_LO, RCP_LO, 633249259Sdim ISD::SETEQ); 634249259Sdim // Calculate the rounding error from the URECIP instruction 635249259Sdim // E = mulhu(ABS_RCP_LO, RCP) 636249259Sdim SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); 637249259Sdim 638249259Sdim // RCP_A_E = RCP + E 639249259Sdim SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E); 640249259Sdim 641249259Sdim // RCP_S_E = RCP - E 642249259Sdim SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E); 643249259Sdim 644249259Sdim // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E) 645249259Sdim SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT), 646249259Sdim RCP_A_E, RCP_S_E, 647249259Sdim ISD::SETEQ); 648249259Sdim // Quotient = mulhu(Tmp0, Num) 649249259Sdim SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); 650249259Sdim 651249259Sdim // Num_S_Remainder = Quotient * Den 652249259Sdim SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den); 653249259Sdim 654249259Sdim // Remainder = Num - Num_S_Remainder 655249259Sdim SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder); 656249259Sdim 657249259Sdim // Remainder_GE_Den = (Remainder >= Den ? -1 : 0) 658249259Sdim SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den, 659249259Sdim DAG.getConstant(-1, VT), 660249259Sdim DAG.getConstant(0, VT), 661263508Sdim ISD::SETUGE); 662263508Sdim // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0) 663263508Sdim SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num, 664263508Sdim Num_S_Remainder, 665249259Sdim DAG.getConstant(-1, VT), 666249259Sdim DAG.getConstant(0, VT), 667263508Sdim ISD::SETUGE); 668249259Sdim // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero 669249259Sdim SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, 670249259Sdim Remainder_GE_Zero); 671249259Sdim 672249259Sdim // Calculate Division result: 673249259Sdim 674249259Sdim // Quotient_A_One = Quotient + 1 675249259Sdim SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient, 676249259Sdim DAG.getConstant(1, VT)); 677249259Sdim 678249259Sdim // Quotient_S_One = Quotient - 1 679249259Sdim SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient, 680249259Sdim DAG.getConstant(1, VT)); 681249259Sdim 682249259Sdim // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One) 683249259Sdim SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT), 684249259Sdim Quotient, Quotient_A_One, ISD::SETEQ); 685249259Sdim 686249259Sdim // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div) 687249259Sdim Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT), 688249259Sdim Quotient_S_One, Div, ISD::SETEQ); 689249259Sdim 690249259Sdim // Calculate Rem result: 691249259Sdim 692249259Sdim // Remainder_S_Den = Remainder - Den 693249259Sdim SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den); 694249259Sdim 695249259Sdim // Remainder_A_Den = Remainder + Den 696249259Sdim SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den); 697249259Sdim 698249259Sdim // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den) 699249259Sdim SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT), 700249259Sdim Remainder, Remainder_S_Den, ISD::SETEQ); 701249259Sdim 702249259Sdim // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem) 703249259Sdim Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT), 704249259Sdim Remainder_A_Den, Rem, ISD::SETEQ); 705249259Sdim SDValue Ops[2]; 706249259Sdim Ops[0] = Div; 707249259Sdim Ops[1] = Rem; 708249259Sdim return DAG.getMergeValues(Ops, 2, DL); 709249259Sdim} 710249259Sdim 711263508SdimSDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op, 712263508Sdim SelectionDAG &DAG) const { 713263508Sdim SDValue S0 = Op.getOperand(0); 714263508Sdim SDLoc DL(Op); 715263508Sdim if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64) 716263508Sdim return SDValue(); 717263508Sdim 718263508Sdim // f32 uint_to_fp i64 719263508Sdim SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0, 720263508Sdim DAG.getConstant(0, MVT::i32)); 721263508Sdim SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo); 722263508Sdim SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0, 723263508Sdim DAG.getConstant(1, MVT::i32)); 724263508Sdim SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi); 725263508Sdim FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi, 726263508Sdim DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32 727263508Sdim return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi); 728263508Sdim 729263508Sdim} 730263508Sdim 731249259Sdim//===----------------------------------------------------------------------===// 732249259Sdim// Helper functions 733249259Sdim//===----------------------------------------------------------------------===// 734249259Sdim 735263508Sdimvoid AMDGPUTargetLowering::getOriginalFunctionArgs( 736263508Sdim SelectionDAG &DAG, 737263508Sdim const Function *F, 738263508Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 739263508Sdim SmallVectorImpl<ISD::InputArg> &OrigIns) const { 740263508Sdim 741263508Sdim for (unsigned i = 0, e = Ins.size(); i < e; ++i) { 742263508Sdim if (Ins[i].ArgVT == Ins[i].VT) { 743263508Sdim OrigIns.push_back(Ins[i]); 744263508Sdim continue; 745263508Sdim } 746263508Sdim 747263508Sdim EVT VT; 748263508Sdim if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) { 749263508Sdim // Vector has been split into scalars. 750263508Sdim VT = Ins[i].ArgVT.getVectorElementType(); 751263508Sdim } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() && 752263508Sdim Ins[i].ArgVT.getVectorElementType() != 753263508Sdim Ins[i].VT.getVectorElementType()) { 754263508Sdim // Vector elements have been promoted 755263508Sdim VT = Ins[i].ArgVT; 756263508Sdim } else { 757263508Sdim // Vector has been spilt into smaller vectors. 758263508Sdim VT = Ins[i].VT; 759263508Sdim } 760263508Sdim 761263508Sdim ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used, 762263508Sdim Ins[i].OrigArgIndex, Ins[i].PartOffset); 763263508Sdim OrigIns.push_back(Arg); 764263508Sdim } 765263508Sdim} 766263508Sdim 767249259Sdimbool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const { 768249259Sdim if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) { 769249259Sdim return CFP->isExactlyValue(1.0); 770249259Sdim } 771249259Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 772249259Sdim return C->isAllOnesValue(); 773249259Sdim } 774249259Sdim return false; 775249259Sdim} 776249259Sdim 777249259Sdimbool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const { 778249259Sdim if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) { 779249259Sdim return CFP->getValueAPF().isZero(); 780249259Sdim } 781249259Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 782249259Sdim return C->isNullValue(); 783249259Sdim } 784249259Sdim return false; 785249259Sdim} 786249259Sdim 787249259SdimSDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG, 788249259Sdim const TargetRegisterClass *RC, 789249259Sdim unsigned Reg, EVT VT) const { 790249259Sdim MachineFunction &MF = DAG.getMachineFunction(); 791249259Sdim MachineRegisterInfo &MRI = MF.getRegInfo(); 792249259Sdim unsigned VirtualRegister; 793249259Sdim if (!MRI.isLiveIn(Reg)) { 794249259Sdim VirtualRegister = MRI.createVirtualRegister(RC); 795249259Sdim MRI.addLiveIn(Reg, VirtualRegister); 796249259Sdim } else { 797249259Sdim VirtualRegister = MRI.getLiveInVirtReg(Reg); 798249259Sdim } 799249259Sdim return DAG.getRegister(VirtualRegister, VT); 800249259Sdim} 801249259Sdim 802249259Sdim#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node; 803249259Sdim 804249259Sdimconst char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { 805249259Sdim switch (Opcode) { 806249259Sdim default: return 0; 807249259Sdim // AMDIL DAG nodes 808249259Sdim NODE_NAME_CASE(CALL); 809249259Sdim NODE_NAME_CASE(UMUL); 810249259Sdim NODE_NAME_CASE(DIV_INF); 811249259Sdim NODE_NAME_CASE(RET_FLAG); 812249259Sdim NODE_NAME_CASE(BRANCH_COND); 813249259Sdim 814249259Sdim // AMDGPU DAG nodes 815249259Sdim NODE_NAME_CASE(DWORDADDR) 816249259Sdim NODE_NAME_CASE(FRACT) 817249259Sdim NODE_NAME_CASE(FMAX) 818249259Sdim NODE_NAME_CASE(SMAX) 819249259Sdim NODE_NAME_CASE(UMAX) 820249259Sdim NODE_NAME_CASE(FMIN) 821249259Sdim NODE_NAME_CASE(SMIN) 822249259Sdim NODE_NAME_CASE(UMIN) 823249259Sdim NODE_NAME_CASE(URECIP) 824249259Sdim NODE_NAME_CASE(EXPORT) 825249259Sdim NODE_NAME_CASE(CONST_ADDRESS) 826249259Sdim NODE_NAME_CASE(REGISTER_LOAD) 827249259Sdim NODE_NAME_CASE(REGISTER_STORE) 828263508Sdim NODE_NAME_CASE(LOAD_CONSTANT) 829263508Sdim NODE_NAME_CASE(LOAD_INPUT) 830263508Sdim NODE_NAME_CASE(SAMPLE) 831263508Sdim NODE_NAME_CASE(SAMPLEB) 832263508Sdim NODE_NAME_CASE(SAMPLED) 833263508Sdim NODE_NAME_CASE(SAMPLEL) 834263508Sdim NODE_NAME_CASE(STORE_MSKOR) 835263508Sdim NODE_NAME_CASE(TBUFFER_STORE_FORMAT) 836249259Sdim } 837249259Sdim} 838