1239310Sdim//===- TargetItinerary.td - Target Itinierary Description --*- tablegen -*-===// 2239310Sdim// 3239310Sdim// The LLVM Compiler Infrastructure 4239310Sdim// 5239310Sdim// This file is distributed under the University of Illinois Open Source 6239310Sdim// License. See LICENSE.TXT for details. 7239310Sdim// 8239310Sdim//===----------------------------------------------------------------------===// 9239310Sdim// 10239310Sdim// This file defines the target-independent scheduling interfaces 11239310Sdim// which should be implemented by each target that uses instruction 12239310Sdim// itineraries for scheduling. Itineraries are details reservation 13239310Sdim// tables for each instruction class. They are most appropriate for 14239310Sdim// in-order machine with complicated scheduling or bundling constraints. 15239310Sdim// 16239310Sdim//===----------------------------------------------------------------------===// 17239310Sdim 18239310Sdim//===----------------------------------------------------------------------===// 19239310Sdim// Processor functional unit - These values represent the function units 20239310Sdim// available across all chip sets for the target. Eg., IntUnit, FPUnit, ... 21239310Sdim// These may be independent values for each chip set or may be shared across 22239310Sdim// all chip sets of the target. Each functional unit is treated as a resource 23239310Sdim// during scheduling and has an affect instruction order based on availability 24239310Sdim// during a time interval. 25239310Sdim// 26239310Sdimclass FuncUnit; 27239310Sdim 28239310Sdim//===----------------------------------------------------------------------===// 29239310Sdim// Pipeline bypass / forwarding - These values specifies the symbolic names of 30239310Sdim// pipeline bypasses which can be used to forward results of instructions 31239310Sdim// that are forwarded to uses. 32239310Sdimclass Bypass; 33239310Sdimdef NoBypass : Bypass; 34239310Sdim 35239310Sdimclass ReservationKind<bits<1> val> { 36239310Sdim int Value = val; 37239310Sdim} 38239310Sdim 39239310Sdimdef Required : ReservationKind<0>; 40239310Sdimdef Reserved : ReservationKind<1>; 41239310Sdim 42239310Sdim//===----------------------------------------------------------------------===// 43239310Sdim// Instruction stage - These values represent a non-pipelined step in 44239310Sdim// the execution of an instruction. Cycles represents the number of 45239310Sdim// discrete time slots needed to complete the stage. Units represent 46239310Sdim// the choice of functional units that can be used to complete the 47239310Sdim// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many 48239310Sdim// cycles should elapse from the start of this stage to the start of 49239310Sdim// the next stage in the itinerary. For example: 50239310Sdim// 51239310Sdim// A stage is specified in one of two ways: 52239310Sdim// 53239310Sdim// InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles 54239310Sdim// InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit 55239310Sdim// 56239310Sdim 57239310Sdimclass InstrStage<int cycles, list<FuncUnit> units, 58239310Sdim int timeinc = -1, 59239310Sdim ReservationKind kind = Required> { 60239310Sdim int Cycles = cycles; // length of stage in machine cycles 61239310Sdim list<FuncUnit> Units = units; // choice of functional units 62239310Sdim int TimeInc = timeinc; // cycles till start of next stage 63239310Sdim int Kind = kind.Value; // kind of FU reservation 64239310Sdim} 65239310Sdim 66239310Sdim//===----------------------------------------------------------------------===// 67239310Sdim// Instruction itinerary - An itinerary represents a sequential series of steps 68239310Sdim// required to complete an instruction. Itineraries are represented as lists of 69239310Sdim// instruction stages. 70239310Sdim// 71239310Sdim 72239310Sdim//===----------------------------------------------------------------------===// 73239310Sdim// Instruction itinerary classes - These values represent 'named' instruction 74239310Sdim// itinerary. Using named itineraries simplifies managing groups of 75239310Sdim// instructions across chip sets. An instruction uses the same itinerary class 76239310Sdim// across all chip sets. Thus a new chip set can be added without modifying 77239310Sdim// instruction information. 78239310Sdim// 79239310Sdimclass InstrItinClass; 80239310Sdimdef NoItinerary : InstrItinClass; 81239310Sdim 82239310Sdim//===----------------------------------------------------------------------===// 83239310Sdim// Instruction itinerary data - These values provide a runtime map of an 84239310Sdim// instruction itinerary class (name) to its itinerary data. 85239310Sdim// 86239310Sdim// NumMicroOps represents the number of micro-operations that each instruction 87239310Sdim// in the class are decoded to. If the number is zero, then it means the 88239310Sdim// instruction can decode into variable number of micro-ops and it must be 89239310Sdim// determined dynamically. This directly relates to the itineraries 90239310Sdim// global IssueWidth property, which constrains the number of microops 91239310Sdim// that can issue per cycle. 92239310Sdim// 93239310Sdim// OperandCycles are optional "cycle counts". They specify the cycle after 94239310Sdim// instruction issue the values which correspond to specific operand indices 95239310Sdim// are defined or read. Bypasses are optional "pipeline forwarding pathes", if 96239310Sdim// a def by an instruction is available on a specific bypass and the use can 97239310Sdim// read from the same bypass, then the operand use latency is reduced by one. 98239310Sdim// 99239310Sdim// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>, 100239310Sdim// InstrStage<1, [A9_AGU]>], 101239310Sdim// [3, 1], [A9_LdBypass]>, 102239310Sdim// InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], 103239310Sdim// [1, 1], [NoBypass, A9_LdBypass]>, 104239310Sdim// 105239310Sdim// In this example, the instruction of IIC_iLoadi reads its input on cycle 1 106239310Sdim// (after issue) and the result of the load is available on cycle 3. The result 107239310Sdim// is available via forwarding path A9_LdBypass. If it's used by the first 108239310Sdim// source operand of instructions of IIC_iMVNr class, then the operand latency 109239310Sdim// is reduced by 1. 110239310Sdimclass InstrItinData<InstrItinClass Class, list<InstrStage> stages, 111239310Sdim list<int> operandcycles = [], 112239310Sdim list<Bypass> bypasses = [], int uops = 1> { 113239310Sdim InstrItinClass TheClass = Class; 114239310Sdim int NumMicroOps = uops; 115239310Sdim list<InstrStage> Stages = stages; 116239310Sdim list<int> OperandCycles = operandcycles; 117239310Sdim list<Bypass> Bypasses = bypasses; 118239310Sdim} 119239310Sdim 120239310Sdim//===----------------------------------------------------------------------===// 121239310Sdim// Processor itineraries - These values represent the set of all itinerary 122239310Sdim// classes for a given chip set. 123239310Sdim// 124239310Sdim// Set property values to -1 to use the default. 125239310Sdim// See InstrItineraryProps for comments and defaults. 126239310Sdimclass ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp, 127239310Sdim list<InstrItinData> iid> { 128239310Sdim list<FuncUnit> FU = fu; 129239310Sdim list<Bypass> BP = bp; 130239310Sdim list<InstrItinData> IID = iid; 131239310Sdim} 132239310Sdim 133239310Sdim// NoItineraries - A marker that can be used by processors without schedule 134239310Sdim// info. Subtargets using NoItineraries can bypass the scheduler's 135239310Sdim// expensive HazardRecognizer because no reservation table is needed. 136239310Sdimdef NoItineraries : ProcessorItineraries<[], [], []>; 137