1224133Sdim//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim// 10224133Sdim// This file describes an abstract interface used to get information about a 11224133Sdim// target machines register file. This information is used for a variety of 12224133Sdim// purposed, especially register allocation. 13224133Sdim// 14224133Sdim//===----------------------------------------------------------------------===// 15224133Sdim 16224133Sdim#ifndef LLVM_MC_MCREGISTERINFO_H 17224133Sdim#define LLVM_MC_MCREGISTERINFO_H 18224133Sdim 19226633Sdim#include "llvm/ADT/DenseMap.h" 20234353Sdim#include "llvm/Support/ErrorHandling.h" 21224133Sdim#include <cassert> 22224133Sdim 23224133Sdimnamespace llvm { 24224133Sdim 25249423Sdim/// An unsigned integer type large enough to represent all physical registers, 26249423Sdim/// but not necessarily virtual registers. 27249423Sdimtypedef uint16_t MCPhysReg; 28249423Sdim 29226633Sdim/// MCRegisterClass - Base class of TargetRegisterClass. 30226633Sdimclass MCRegisterClass { 31226633Sdimpublic: 32249423Sdim typedef const MCPhysReg* iterator; 33249423Sdim typedef const MCPhysReg* const_iterator; 34234353Sdim 35226633Sdim const char *Name; 36234353Sdim const iterator RegsBegin; 37234353Sdim const uint8_t *const RegSet; 38234353Sdim const uint16_t RegsSize; 39234353Sdim const uint16_t RegSetSize; 40234353Sdim const uint16_t ID; 41234353Sdim const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes 42234353Sdim const int8_t CopyCost; 43226633Sdim const bool Allocatable; 44226633Sdim 45226633Sdim /// getID() - Return the register class ID number. 46226633Sdim /// 47226633Sdim unsigned getID() const { return ID; } 48226633Sdim 49226633Sdim /// getName() - Return the register class name for debugging. 50226633Sdim /// 51226633Sdim const char *getName() const { return Name; } 52226633Sdim 53226633Sdim /// begin/end - Return all of the registers in this class. 54226633Sdim /// 55226633Sdim iterator begin() const { return RegsBegin; } 56234353Sdim iterator end() const { return RegsBegin + RegsSize; } 57226633Sdim 58226633Sdim /// getNumRegs - Return the number of registers in this class. 59226633Sdim /// 60234353Sdim unsigned getNumRegs() const { return RegsSize; } 61226633Sdim 62226633Sdim /// getRegister - Return the specified register in the class. 63226633Sdim /// 64226633Sdim unsigned getRegister(unsigned i) const { 65226633Sdim assert(i < getNumRegs() && "Register number out of range!"); 66226633Sdim return RegsBegin[i]; 67226633Sdim } 68226633Sdim 69226633Sdim /// contains - Return true if the specified register is included in this 70226633Sdim /// register class. This does not include virtual registers. 71226633Sdim bool contains(unsigned Reg) const { 72226633Sdim unsigned InByte = Reg % 8; 73226633Sdim unsigned Byte = Reg / 8; 74226633Sdim if (Byte >= RegSetSize) 75226633Sdim return false; 76226633Sdim return (RegSet[Byte] & (1 << InByte)) != 0; 77226633Sdim } 78226633Sdim 79226633Sdim /// contains - Return true if both registers are in this class. 80226633Sdim bool contains(unsigned Reg1, unsigned Reg2) const { 81226633Sdim return contains(Reg1) && contains(Reg2); 82226633Sdim } 83226633Sdim 84226633Sdim /// getSize - Return the size of the register in bytes, which is also the size 85226633Sdim /// of a stack slot allocated to hold a spilled copy of this register. 86226633Sdim unsigned getSize() const { return RegSize; } 87226633Sdim 88226633Sdim /// getAlignment - Return the minimum required alignment for a register of 89226633Sdim /// this class. 90226633Sdim unsigned getAlignment() const { return Alignment; } 91226633Sdim 92226633Sdim /// getCopyCost - Return the cost of copying a value between two registers in 93226633Sdim /// this class. A negative number means the register class is very expensive 94226633Sdim /// to copy e.g. status flag register classes. 95226633Sdim int getCopyCost() const { return CopyCost; } 96226633Sdim 97226633Sdim /// isAllocatable - Return true if this register class may be used to create 98226633Sdim /// virtual registers. 99226633Sdim bool isAllocatable() const { return Allocatable; } 100226633Sdim}; 101226633Sdim 102263508Sdim/// MCRegisterDesc - This record contains information about a particular 103263508Sdim/// register. The SubRegs field is a zero terminated array of registers that 104263508Sdim/// are sub-registers of the specific register, e.g. AL, AH are sub-registers 105263508Sdim/// of AX. The SuperRegs field is a zero terminated array of registers that are 106263508Sdim/// super-registers of the specific register, e.g. RAX, EAX, are 107263508Sdim/// super-registers of AX. 108224133Sdim/// 109224133Sdimstruct MCRegisterDesc { 110239462Sdim uint32_t Name; // Printable name for the reg (for debugging) 111239462Sdim uint32_t SubRegs; // Sub-register set, described above 112239462Sdim uint32_t SuperRegs; // Super-register set, described above 113239462Sdim 114239462Sdim // Offset into MCRI::SubRegIndices of a list of sub-register indices for each 115239462Sdim // sub-register in SubRegs. 116239462Sdim uint32_t SubRegIndices; 117239462Sdim 118239462Sdim // RegUnits - Points to the list of register units. The low 4 bits holds the 119239462Sdim // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 120239462Sdim uint32_t RegUnits; 121224133Sdim}; 122224133Sdim 123224133Sdim/// MCRegisterInfo base class - We assume that the target defines a static 124224133Sdim/// array of MCRegisterDesc objects that represent all of the machine 125224133Sdim/// registers that the target has. As such, we simply have to track a pointer 126224133Sdim/// to this array so that we can turn register number into a register 127224133Sdim/// descriptor. 128224133Sdim/// 129224133Sdim/// Note this class is designed to be a base class of TargetRegisterInfo, which 130224133Sdim/// is the interface used by codegen. However, specific targets *should never* 131224133Sdim/// specialize this class. MCRegisterInfo should only contain getters to access 132224133Sdim/// TableGen generated physical register data. It must not be extended with 133224133Sdim/// virtual methods. 134224133Sdim/// 135224133Sdimclass MCRegisterInfo { 136226633Sdimpublic: 137226633Sdim typedef const MCRegisterClass *regclass_iterator; 138234353Sdim 139234353Sdim /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 140234353Sdim /// performed with a binary search. 141234353Sdim struct DwarfLLVMRegPair { 142234353Sdim unsigned FromReg; 143234353Sdim unsigned ToReg; 144234353Sdim 145234353Sdim bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 146234353Sdim }; 147263508Sdim 148263508Sdim /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg 149263508Sdim /// index, -1 in any being invalid. 150263508Sdim struct SubRegCoveredBits { 151263508Sdim uint16_t Offset; 152263508Sdim uint16_t Size; 153263508Sdim }; 154224133Sdimprivate: 155226633Sdim const MCRegisterDesc *Desc; // Pointer to the descriptor array 156226633Sdim unsigned NumRegs; // Number of entries in the array 157226633Sdim unsigned RAReg; // Return address register 158249423Sdim unsigned PCReg; // Program counter register 159226633Sdim const MCRegisterClass *Classes; // Pointer to the regclass array 160226633Sdim unsigned NumClasses; // Number of entries in the array 161239462Sdim unsigned NumRegUnits; // Number of regunits. 162239462Sdim const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table. 163249423Sdim const MCPhysReg *DiffLists; // Pointer to the difflists array 164239462Sdim const char *RegStrings; // Pointer to the string table. 165234353Sdim const uint16_t *SubRegIndices; // Pointer to the subreg lookup 166234353Sdim // array. 167263508Sdim const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered 168263508Sdim // bit ranges array. 169234353Sdim unsigned NumSubRegIndices; // Number of subreg indices. 170239462Sdim const uint16_t *RegEncodingTable; // Pointer to array of register 171239462Sdim // encodings. 172234353Sdim 173234353Sdim unsigned L2DwarfRegsSize; 174234353Sdim unsigned EHL2DwarfRegsSize; 175234353Sdim unsigned Dwarf2LRegsSize; 176234353Sdim unsigned EHDwarf2LRegsSize; 177234353Sdim const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 178234353Sdim const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 179234353Sdim const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 180234353Sdim const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 181226633Sdim DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 182224133Sdim 183224133Sdimpublic: 184239462Sdim /// DiffListIterator - Base iterator class that can traverse the 185239462Sdim /// differentially encoded register and regunit lists in DiffLists. 186239462Sdim /// Don't use this class directly, use one of the specialized sub-classes 187239462Sdim /// defined below. 188239462Sdim class DiffListIterator { 189239462Sdim uint16_t Val; 190249423Sdim const MCPhysReg *List; 191239462Sdim 192239462Sdim protected: 193239462Sdim /// Create an invalid iterator. Call init() to point to something useful. 194239462Sdim DiffListIterator() : Val(0), List(0) {} 195239462Sdim 196239462Sdim /// init - Point the iterator to InitVal, decoding subsequent values from 197239462Sdim /// DiffList. The iterator will initially point to InitVal, sub-classes are 198239462Sdim /// responsible for skipping the seed value if it is not part of the list. 199249423Sdim void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { 200239462Sdim Val = InitVal; 201239462Sdim List = DiffList; 202239462Sdim } 203239462Sdim 204239462Sdim /// advance - Move to the next list position, return the applied 205239462Sdim /// differential. This function does not detect the end of the list, that 206239462Sdim /// is the caller's responsibility (by checking for a 0 return value). 207239462Sdim unsigned advance() { 208239462Sdim assert(isValid() && "Cannot move off the end of the list."); 209249423Sdim MCPhysReg D = *List++; 210239462Sdim Val += D; 211239462Sdim return D; 212239462Sdim } 213239462Sdim 214239462Sdim public: 215239462Sdim 216239462Sdim /// isValid - returns true if this iterator is not yet at the end. 217239462Sdim bool isValid() const { return List; } 218239462Sdim 219239462Sdim /// Dereference the iterator to get the value at the current position. 220239462Sdim unsigned operator*() const { return Val; } 221239462Sdim 222239462Sdim /// Pre-increment to move to the next position. 223239462Sdim void operator++() { 224239462Sdim // The end of the list is encoded as a 0 differential. 225239462Sdim if (!advance()) 226239462Sdim List = 0; 227239462Sdim } 228239462Sdim }; 229239462Sdim 230239462Sdim // These iterators are allowed to sub-class DiffListIterator and access 231239462Sdim // internal list pointers. 232239462Sdim friend class MCSubRegIterator; 233239462Sdim friend class MCSuperRegIterator; 234239462Sdim friend class MCRegUnitIterator; 235239462Sdim friend class MCRegUnitRootIterator; 236239462Sdim 237249423Sdim /// \brief Initialize MCRegisterInfo, called by TableGen 238224133Sdim /// auto-generated routines. *DO NOT USE*. 239226633Sdim void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 240249423Sdim unsigned PC, 241234353Sdim const MCRegisterClass *C, unsigned NC, 242239462Sdim const uint16_t (*RURoots)[2], 243239462Sdim unsigned NRU, 244249423Sdim const MCPhysReg *DL, 245239462Sdim const char *Strings, 246234353Sdim const uint16_t *SubIndices, 247239462Sdim unsigned NumIndices, 248263508Sdim const SubRegCoveredBits *SubIdxRanges, 249239462Sdim const uint16_t *RET) { 250224133Sdim Desc = D; 251224133Sdim NumRegs = NR; 252226633Sdim RAReg = RA; 253249423Sdim PCReg = PC; 254226633Sdim Classes = C; 255239462Sdim DiffLists = DL; 256239462Sdim RegStrings = Strings; 257226633Sdim NumClasses = NC; 258239462Sdim RegUnitRoots = RURoots; 259239462Sdim NumRegUnits = NRU; 260234353Sdim SubRegIndices = SubIndices; 261234353Sdim NumSubRegIndices = NumIndices; 262263508Sdim SubRegIdxRanges = SubIdxRanges; 263239462Sdim RegEncodingTable = RET; 264224133Sdim } 265226633Sdim 266249423Sdim /// \brief Used to initialize LLVM register to Dwarf 267226633Sdim /// register number mapping. Called by TableGen auto-generated routines. 268226633Sdim /// *DO NOT USE*. 269234353Sdim void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 270234353Sdim bool isEH) { 271234353Sdim if (isEH) { 272234353Sdim EHL2DwarfRegs = Map; 273234353Sdim EHL2DwarfRegsSize = Size; 274234353Sdim } else { 275234353Sdim L2DwarfRegs = Map; 276234353Sdim L2DwarfRegsSize = Size; 277234353Sdim } 278226633Sdim } 279234353Sdim 280249423Sdim /// \brief Used to initialize Dwarf register to LLVM 281226633Sdim /// register number mapping. Called by TableGen auto-generated routines. 282226633Sdim /// *DO NOT USE*. 283234353Sdim void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 284234353Sdim bool isEH) { 285234353Sdim if (isEH) { 286234353Sdim EHDwarf2LRegs = Map; 287234353Sdim EHDwarf2LRegsSize = Size; 288234353Sdim } else { 289234353Sdim Dwarf2LRegs = Map; 290234353Sdim Dwarf2LRegsSize = Size; 291234353Sdim } 292226633Sdim } 293234353Sdim 294226633Sdim /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 295226633Sdim /// number mapping. By default the SEH register number is just the same 296226633Sdim /// as the LLVM register number. 297226633Sdim /// FIXME: TableGen these numbers. Currently this requires target specific 298226633Sdim /// initialization code. 299226633Sdim void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 300226633Sdim L2SEHRegs[LLVMReg] = SEHReg; 301226633Sdim } 302226633Sdim 303249423Sdim /// \brief This method should return the register where the return 304226633Sdim /// address can be found. 305226633Sdim unsigned getRARegister() const { 306226633Sdim return RAReg; 307226633Sdim } 308226633Sdim 309249423Sdim /// Return the register which is the program counter. 310249423Sdim unsigned getProgramCounter() const { 311249423Sdim return PCReg; 312249423Sdim } 313249423Sdim 314224133Sdim const MCRegisterDesc &operator[](unsigned RegNo) const { 315224133Sdim assert(RegNo < NumRegs && 316224133Sdim "Attempting to access record for invalid register number!"); 317224133Sdim return Desc[RegNo]; 318224133Sdim } 319224133Sdim 320249423Sdim /// \brief Provide a get method, equivalent to [], but more useful with a 321224133Sdim /// pointer to this object. 322224133Sdim const MCRegisterDesc &get(unsigned RegNo) const { 323224133Sdim return operator[](RegNo); 324224133Sdim } 325224133Sdim 326249423Sdim /// \brief Returns the physical register number of sub-register "Index" 327234353Sdim /// for physical register RegNo. Return zero if the sub-register does not 328234353Sdim /// exist. 329239462Sdim unsigned getSubReg(unsigned Reg, unsigned Idx) const; 330234353Sdim 331249423Sdim /// \brief Return a super-register of the specified register 332234353Sdim /// Reg so its sub-register of index SubIdx is Reg. 333234353Sdim unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 334239462Sdim const MCRegisterClass *RC) const; 335234353Sdim 336249423Sdim /// \brief For a given register pair, return the sub-register index 337234353Sdim /// if the second register is a sub-register of the first. Return zero 338234353Sdim /// otherwise. 339239462Sdim unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; 340234353Sdim 341263508Sdim /// \brief Get the size of the bit range covered by a sub-register index. 342263508Sdim /// If the index isn't continuous, return the sum of the sizes of its parts. 343263508Sdim /// If the index is used to access subregisters of different sizes, return -1. 344263508Sdim unsigned getSubRegIdxSize(unsigned Idx) const; 345263508Sdim 346263508Sdim /// \brief Get the offset of the bit range covered by a sub-register index. 347263508Sdim /// If an Offset doesn't make sense (the index isn't continuous, or is used to 348263508Sdim /// access sub-registers at different offsets), return -1. 349263508Sdim unsigned getSubRegIdxOffset(unsigned Idx) const; 350263508Sdim 351249423Sdim /// \brief Return the human-readable symbolic target-specific name for the 352224133Sdim /// specified physical register. 353224133Sdim const char *getName(unsigned RegNo) const { 354239462Sdim return RegStrings + get(RegNo).Name; 355224133Sdim } 356224133Sdim 357249423Sdim /// \brief Return the number of registers this target has (useful for 358224133Sdim /// sizing arrays holding per register information) 359224133Sdim unsigned getNumRegs() const { 360224133Sdim return NumRegs; 361224133Sdim } 362226633Sdim 363249423Sdim /// \brief Return the number of sub-register indices 364243830Sdim /// understood by the target. Index 0 is reserved for the no-op sub-register, 365243830Sdim /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. 366243830Sdim unsigned getNumSubRegIndices() const { 367243830Sdim return NumSubRegIndices; 368243830Sdim } 369243830Sdim 370249423Sdim /// \brief Return the number of (native) register units in the 371239462Sdim /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 372239462Sdim /// can be accessed through MCRegUnitIterator defined below. 373239462Sdim unsigned getNumRegUnits() const { 374239462Sdim return NumRegUnits; 375239462Sdim } 376239462Sdim 377249423Sdim /// \brief Map a target register to an equivalent dwarf register 378226633Sdim /// number. Returns -1 if there is no equivalent value. The second 379226633Sdim /// parameter allows targets to use different numberings for EH info and 380226633Sdim /// debugging info. 381239462Sdim int getDwarfRegNum(unsigned RegNum, bool isEH) const; 382234353Sdim 383249423Sdim /// \brief Map a dwarf register back to a target register. 384239462Sdim int getLLVMRegNum(unsigned RegNum, bool isEH) const; 385234353Sdim 386249423Sdim /// \brief Map a target register to an equivalent SEH register 387226633Sdim /// number. Returns LLVM register number if there is no equivalent value. 388239462Sdim int getSEHRegNum(unsigned RegNum) const; 389226633Sdim 390226633Sdim regclass_iterator regclass_begin() const { return Classes; } 391226633Sdim regclass_iterator regclass_end() const { return Classes+NumClasses; } 392226633Sdim 393226633Sdim unsigned getNumRegClasses() const { 394226633Sdim return (unsigned)(regclass_end()-regclass_begin()); 395226633Sdim } 396226633Sdim 397249423Sdim /// \brief Returns the register class associated with the enumeration 398226633Sdim /// value. See class MCOperandInfo. 399243830Sdim const MCRegisterClass& getRegClass(unsigned i) const { 400226633Sdim assert(i < getNumRegClasses() && "Register Class ID out of range"); 401226633Sdim return Classes[i]; 402226633Sdim } 403239462Sdim 404249423Sdim /// \brief Returns the encoding for RegNo 405239462Sdim uint16_t getEncodingValue(unsigned RegNo) const { 406239462Sdim assert(RegNo < NumRegs && 407239462Sdim "Attempting to get encoding for invalid register number!"); 408239462Sdim return RegEncodingTable[RegNo]; 409239462Sdim } 410239462Sdim 411249423Sdim /// \brief Returns true if RegB is a sub-register of RegA. 412249423Sdim bool isSubRegister(unsigned RegA, unsigned RegB) const { 413249423Sdim return isSuperRegister(RegB, RegA); 414249423Sdim } 415249423Sdim 416249423Sdim /// \brief Returns true if RegB is a super-register of RegA. 417249423Sdim bool isSuperRegister(unsigned RegA, unsigned RegB) const; 418249423Sdim 419249423Sdim /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA. 420249423Sdim bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { 421249423Sdim return isSuperRegisterEq(RegB, RegA); 422249423Sdim } 423249423Sdim 424249423Sdim /// \brief Returns true if RegB is a super-register of RegA or if 425249423Sdim /// RegB == RegA. 426249423Sdim bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { 427249423Sdim return RegA == RegB || isSuperRegister(RegA, RegB); 428249423Sdim } 429249423Sdim 430224133Sdim}; 431234353Sdim 432239462Sdim//===----------------------------------------------------------------------===// 433239462Sdim// Register List Iterators 434239462Sdim//===----------------------------------------------------------------------===// 435239462Sdim 436239462Sdim// MCRegisterInfo provides lists of super-registers, sub-registers, and 437239462Sdim// aliasing registers. Use these iterator classes to traverse the lists. 438239462Sdim 439239462Sdim/// MCSubRegIterator enumerates all sub-registers of Reg. 440263508Sdim/// If IncludeSelf is set, Reg itself is included in the list. 441239462Sdimclass MCSubRegIterator : public MCRegisterInfo::DiffListIterator { 442239462Sdimpublic: 443263508Sdim MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, 444263508Sdim bool IncludeSelf = false) { 445239462Sdim init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); 446263508Sdim // Initially, the iterator points to Reg itself. 447263508Sdim if (!IncludeSelf) 448263508Sdim ++*this; 449239462Sdim } 450239462Sdim}; 451239462Sdim 452239462Sdim/// MCSuperRegIterator enumerates all super-registers of Reg. 453263508Sdim/// If IncludeSelf is set, Reg itself is included in the list. 454239462Sdimclass MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { 455239462Sdimpublic: 456263508Sdim MCSuperRegIterator() {} 457263508Sdim MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, 458263508Sdim bool IncludeSelf = false) { 459239462Sdim init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 460239462Sdim // Initially, the iterator points to Reg itself. 461239462Sdim if (!IncludeSelf) 462239462Sdim ++*this; 463239462Sdim } 464239462Sdim}; 465239462Sdim 466249423Sdim// Definition for isSuperRegister. Put it down here since it needs the 467249423Sdim// iterator defined above in addition to the MCRegisterInfo class itself. 468249423Sdiminline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ 469249423Sdim for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I) 470249423Sdim if (*I == RegB) 471249423Sdim return true; 472249423Sdim return false; 473249423Sdim} 474249423Sdim 475239462Sdim//===----------------------------------------------------------------------===// 476239462Sdim// Register Units 477239462Sdim//===----------------------------------------------------------------------===// 478239462Sdim 479239462Sdim// Register units are used to compute register aliasing. Every register has at 480239462Sdim// least one register unit, but it can have more. Two registers overlap if and 481239462Sdim// only if they have a common register unit. 482239462Sdim// 483239462Sdim// A target with a complicated sub-register structure will typically have many 484239462Sdim// fewer register units than actual registers. MCRI::getNumRegUnits() returns 485239462Sdim// the number of register units in the target. 486239462Sdim 487239462Sdim// MCRegUnitIterator enumerates a list of register units for Reg. The list is 488239462Sdim// in ascending numerical order. 489239462Sdimclass MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 490239462Sdimpublic: 491239462Sdim /// MCRegUnitIterator - Create an iterator that traverses the register units 492239462Sdim /// in Reg. 493263508Sdim MCRegUnitIterator() {} 494239462Sdim MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 495249423Sdim assert(Reg && "Null register has no regunits"); 496239462Sdim // Decode the RegUnits MCRegisterDesc field. 497239462Sdim unsigned RU = MCRI->get(Reg).RegUnits; 498239462Sdim unsigned Scale = RU & 15; 499239462Sdim unsigned Offset = RU >> 4; 500239462Sdim 501239462Sdim // Initialize the iterator to Reg * Scale, and the List pointer to 502239462Sdim // DiffLists + Offset. 503239462Sdim init(Reg * Scale, MCRI->DiffLists + Offset); 504239462Sdim 505239462Sdim // That may not be a valid unit, we need to advance by one to get the real 506239462Sdim // unit number. The first differential can be 0 which would normally 507239462Sdim // terminate the list, but since we know every register has at least one 508239462Sdim // unit, we can allow a 0 differential here. 509239462Sdim advance(); 510239462Sdim } 511239462Sdim}; 512239462Sdim 513239462Sdim// Each register unit has one or two root registers. The complete set of 514239462Sdim// registers containing a register unit is the union of the roots and their 515239462Sdim// super-registers. All registers aliasing Unit can be visited like this: 516239462Sdim// 517239462Sdim// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 518263508Sdim// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) 519239462Sdim// visit(*SI); 520239462Sdim// } 521239462Sdim 522239462Sdim/// MCRegUnitRootIterator enumerates the root registers of a register unit. 523239462Sdimclass MCRegUnitRootIterator { 524239462Sdim uint16_t Reg0; 525239462Sdim uint16_t Reg1; 526239462Sdimpublic: 527263508Sdim MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} 528239462Sdim MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { 529239462Sdim assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); 530239462Sdim Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 531239462Sdim Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 532239462Sdim } 533239462Sdim 534249423Sdim /// \brief Dereference to get the current root register. 535239462Sdim unsigned operator*() const { 536239462Sdim return Reg0; 537239462Sdim } 538239462Sdim 539249423Sdim /// \brief Check if the iterator is at the end of the list. 540239462Sdim bool isValid() const { 541239462Sdim return Reg0; 542239462Sdim } 543239462Sdim 544249423Sdim /// \brief Preincrement to move to the next root register. 545239462Sdim void operator++() { 546239462Sdim assert(isValid() && "Cannot move off the end of the list."); 547239462Sdim Reg0 = Reg1; 548239462Sdim Reg1 = 0; 549239462Sdim } 550239462Sdim}; 551239462Sdim 552263508Sdim/// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is 553263508Sdim/// set, Reg itself is included in the list. This iterator does not guarantee 554263508Sdim/// any ordering or that entries are unique. 555263508Sdimclass MCRegAliasIterator { 556263508Sdimprivate: 557263508Sdim unsigned Reg; 558263508Sdim const MCRegisterInfo *MCRI; 559263508Sdim bool IncludeSelf; 560263508Sdim 561263508Sdim MCRegUnitIterator RI; 562263508Sdim MCRegUnitRootIterator RRI; 563263508Sdim MCSuperRegIterator SI; 564263508Sdimpublic: 565263508Sdim MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, 566263508Sdim bool IncludeSelf) 567263508Sdim : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { 568263508Sdim 569263508Sdim // Initialize the iterators. 570263508Sdim for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) { 571263508Sdim for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) { 572263508Sdim for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) { 573263508Sdim if (!(!IncludeSelf && Reg == *SI)) 574263508Sdim return; 575263508Sdim } 576263508Sdim } 577263508Sdim } 578263508Sdim } 579263508Sdim 580263508Sdim bool isValid() const { 581263508Sdim return RI.isValid(); 582263508Sdim } 583263508Sdim 584263508Sdim unsigned operator*() const { 585263508Sdim assert (SI.isValid() && "Cannot dereference an invalid iterator."); 586263508Sdim return *SI; 587263508Sdim } 588263508Sdim 589263508Sdim void advance() { 590263508Sdim // Assuming SI is valid. 591263508Sdim ++SI; 592263508Sdim if (SI.isValid()) return; 593263508Sdim 594263508Sdim ++RRI; 595263508Sdim if (RRI.isValid()) { 596263508Sdim SI = MCSuperRegIterator(*RRI, MCRI, true); 597263508Sdim return; 598263508Sdim } 599263508Sdim 600263508Sdim ++RI; 601263508Sdim if (RI.isValid()) { 602263508Sdim RRI = MCRegUnitRootIterator(*RI, MCRI); 603263508Sdim SI = MCSuperRegIterator(*RRI, MCRI, true); 604263508Sdim } 605263508Sdim } 606263508Sdim 607263508Sdim void operator++() { 608263508Sdim assert(isValid() && "Cannot move off the end of the list."); 609263508Sdim do advance(); 610263508Sdim while (!IncludeSelf && isValid() && *SI == Reg); 611263508Sdim } 612263508Sdim}; 613263508Sdim 614224133Sdim} // End llvm namespace 615224133Sdim 616224133Sdim#endif 617