1115013Smarcel/* Target-dependent code for AMD64. 2160157Smarcel 3121642Smarcel Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4121642Smarcel Contributed by Jiri Smid, SuSE Labs. 5121642Smarcel 6121642Smarcel This file is part of GDB. 7121642Smarcel 8121642Smarcel This program is free software; you can redistribute it and/or modify 9121642Smarcel it under the terms of the GNU General Public License as published by 10121642Smarcel the Free Software Foundation; either version 2 of the License, or 11115013Smarcel (at your option) any later version. 12121642Smarcel 13121642Smarcel This program is distributed in the hope that it will be useful, 14121642Smarcel but WITHOUT ANY WARRANTY; without even the implied warranty of 15121642Smarcel MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16121642Smarcel GNU General Public License for more details. 17121642Smarcel 18121642Smarcel You should have received a copy of the GNU General Public License 19121642Smarcel along with this program; if not, write to the Free Software 20121642Smarcel Foundation, Inc., 59 Temple Place - Suite 330, 21121642Smarcel Boston, MA 02111-1307, USA. */ 22121642Smarcel 23121642Smarcel#include "defs.h" 24121642Smarcel#include "arch-utils.h" 25115013Smarcel#include "block.h" 26115013Smarcel#include "dummy-frame.h" 27115013Smarcel#include "frame.h" 28115013Smarcel#include "frame-base.h" 29115013Smarcel#include "frame-unwind.h" 30115013Smarcel#include "inferior.h" 31115013Smarcel#include "gdbcmd.h" 32115013Smarcel#include "gdbcore.h" 33115013Smarcel#include "objfiles.h" 34115013Smarcel#include "regcache.h" 35115013Smarcel#include "regset.h" 36115013Smarcel#include "symfile.h" 37115013Smarcel 38115013Smarcel#include "gdb_assert.h" 39115013Smarcel 40115013Smarcel#include "amd64-tdep.h" 41115013Smarcel#include "i387-tdep.h" 42115013Smarcel 43115013Smarcel/* Note that the AMD64 architecture was previously known as x86-64. 44115013Smarcel The latter is (forever) engraved into the canonical system name as 45129059Smarcel returned by config.guess, and used as the name for the AMD64 port 46115013Smarcel of GNU/Linux. The BSD's have renamed their ports to amd64; they 47115013Smarcel don't like to shout. For GDB we prefer the amd64_-prefix over the 48115013Smarcel x86_64_-prefix since it's so much easier to type. */ 49115013Smarcel 50115013Smarcel/* Register information. */ 51115013Smarcel 52115013Smarcelstruct amd64_register_info 53129059Smarcel{ 54115013Smarcel char *name; 55115013Smarcel struct type **type; 56115013Smarcel}; 57115013Smarcel 58115013Smarcelstatic struct amd64_register_info amd64_register_info[] = 59115013Smarcel{ 60115013Smarcel { "rax", &builtin_type_int64 }, 61115013Smarcel { "rbx", &builtin_type_int64 }, 62115013Smarcel { "rcx", &builtin_type_int64 }, 63115013Smarcel { "rdx", &builtin_type_int64 }, 64129059Smarcel { "rsi", &builtin_type_int64 }, 65115013Smarcel { "rdi", &builtin_type_int64 }, 66115013Smarcel { "rbp", &builtin_type_void_data_ptr }, 67115013Smarcel { "rsp", &builtin_type_void_data_ptr }, 68129059Smarcel 69115013Smarcel /* %r8 is indeed register number 8. */ 70129059Smarcel { "r8", &builtin_type_int64 }, 71129059Smarcel { "r9", &builtin_type_int64 }, 72115013Smarcel { "r10", &builtin_type_int64 }, 73115013Smarcel { "r11", &builtin_type_int64 }, 74115013Smarcel { "r12", &builtin_type_int64 }, 75115013Smarcel { "r13", &builtin_type_int64 }, 76115013Smarcel { "r14", &builtin_type_int64 }, 77115013Smarcel { "r15", &builtin_type_int64 }, 78115013Smarcel { "rip", &builtin_type_void_func_ptr }, 79160163Smarcel { "eflags", &builtin_type_int32 }, 80115013Smarcel { "cs", &builtin_type_int32 }, 81160163Smarcel { "ss", &builtin_type_int32 }, 82160163Smarcel { "ds", &builtin_type_int32 }, 83115013Smarcel { "es", &builtin_type_int32 }, 84115013Smarcel { "fs", &builtin_type_int32 }, 85115013Smarcel { "gs", &builtin_type_int32 }, 86115013Smarcel 87160157Smarcel /* %st0 is register number 24. */ 88115013Smarcel { "st0", &builtin_type_i387_ext }, 89115013Smarcel { "st1", &builtin_type_i387_ext }, 90115013Smarcel { "st2", &builtin_type_i387_ext }, 91115013Smarcel { "st3", &builtin_type_i387_ext }, 92115013Smarcel { "st4", &builtin_type_i387_ext }, 93115013Smarcel { "st5", &builtin_type_i387_ext }, 94115013Smarcel { "st6", &builtin_type_i387_ext }, 95115013Smarcel { "st7", &builtin_type_i387_ext }, 96115013Smarcel { "fctrl", &builtin_type_int32 }, 97115013Smarcel { "fstat", &builtin_type_int32 }, 98115013Smarcel { "ftag", &builtin_type_int32 }, 99115013Smarcel { "fiseg", &builtin_type_int32 }, 100160157Smarcel { "fioff", &builtin_type_int32 }, 101160157Smarcel { "foseg", &builtin_type_int32 }, 102160157Smarcel { "fooff", &builtin_type_int32 }, 103115013Smarcel { "fop", &builtin_type_int32 }, 104115013Smarcel 105115013Smarcel /* %xmm0 is register number 40. */ 106115013Smarcel { "xmm0", &builtin_type_v4sf }, 107115013Smarcel { "xmm1", &builtin_type_v4sf }, 108115013Smarcel { "xmm2", &builtin_type_v4sf }, 109115013Smarcel { "xmm3", &builtin_type_v4sf }, 110115013Smarcel { "xmm4", &builtin_type_v4sf }, 111115013Smarcel { "xmm5", &builtin_type_v4sf }, 112115013Smarcel { "xmm6", &builtin_type_v4sf }, 113115013Smarcel { "xmm7", &builtin_type_v4sf }, 114115013Smarcel { "xmm8", &builtin_type_v4sf }, 115115013Smarcel { "xmm9", &builtin_type_v4sf }, 116115013Smarcel { "xmm10", &builtin_type_v4sf }, 117115013Smarcel { "xmm11", &builtin_type_v4sf }, 118115013Smarcel { "xmm12", &builtin_type_v4sf }, 119129059Smarcel { "xmm13", &builtin_type_v4sf }, 120115013Smarcel { "xmm14", &builtin_type_v4sf }, 121115013Smarcel { "xmm15", &builtin_type_v4sf }, 122115013Smarcel { "mxcsr", &builtin_type_int32 } 123115013Smarcel}; 124115013Smarcel 125115013Smarcel/* Total number of registers. */ 126129059Smarcel#define AMD64_NUM_REGS \ 127115013Smarcel (sizeof (amd64_register_info) / sizeof (amd64_register_info[0])) 128115013Smarcel 129115013Smarcel/* Return the name of register REGNUM. */ 130115013Smarcel 131115013Smarcelstatic const char * 132115013Smarcelamd64_register_name (int regnum) 133115013Smarcel{ 134115013Smarcel if (regnum >= 0 && regnum < AMD64_NUM_REGS) 135115013Smarcel return amd64_register_info[regnum].name; 136115013Smarcel 137115013Smarcel return NULL; 138115013Smarcel} 139115013Smarcel 140160157Smarcel/* Return the GDB type object for the "standard" data type of data in 141160157Smarcel register REGNUM. */ 142115013Smarcel 143115013Smarcelstatic struct type * 144129059Smarcelamd64_register_type (struct gdbarch *gdbarch, int regnum) 145115013Smarcel{ 146115013Smarcel gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS); 147115013Smarcel 148115013Smarcel return *amd64_register_info[regnum].type; 149115013Smarcel} 150115013Smarcel 151115013Smarcel/* DWARF Register Number Mapping as defined in the System V psABI, 152129059Smarcel section 3.6. */ 153115013Smarcel 154115013Smarcelstatic int amd64_dwarf_regmap[] = 155115013Smarcel{ 156115013Smarcel /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ 157115013Smarcel AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, 158115013Smarcel AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, 159115013Smarcel AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 160115013Smarcel 161129059Smarcel /* Frame Pointer Register RBP. */ 162115013Smarcel AMD64_RBP_REGNUM, 163115013Smarcel 164115013Smarcel /* Stack Pointer Register RSP. */ 165115013Smarcel AMD64_RSP_REGNUM, 166115013Smarcel 167115013Smarcel /* Extended Integer Registers 8 - 15. */ 168115013Smarcel 8, 9, 10, 11, 12, 13, 14, 15, 169115013Smarcel 170160163Smarcel /* Return Address RA. Mapped to RIP. */ 171115013Smarcel AMD64_RIP_REGNUM, 172115013Smarcel 173160163Smarcel /* SSE Registers 0 - 7. */ 174160163Smarcel AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 175115013Smarcel AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 176160163Smarcel AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 177115013Smarcel AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 178115013Smarcel 179115013Smarcel /* Extended SSE Registers 8 - 15. */ 180115013Smarcel AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, 181115013Smarcel AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, 182115013Smarcel AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, 183115013Smarcel AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, 184115013Smarcel 185115013Smarcel /* Floating Point Registers 0-7. */ 186115013Smarcel AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, 187115013Smarcel AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, 188115013Smarcel AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, 189115013Smarcel AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7 190115013Smarcel}; 191115013Smarcel 192115013Smarcelstatic const int amd64_dwarf_regmap_len = 193115013Smarcel (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); 194160163Smarcel 195115013Smarcel/* Convert DWARF register number REG to the appropriate register 196115013Smarcel number used by GDB. */ 197115013Smarcel 198115013Smarcelstatic int 199160157Smarcelamd64_dwarf_reg_to_regnum (int reg) 200160157Smarcel{ 201160157Smarcel int regnum = -1; 202160157Smarcel 203115013Smarcel if (reg >= 0 || reg < amd64_dwarf_regmap_len) 204115013Smarcel regnum = amd64_dwarf_regmap[reg]; 205115013Smarcel 206115013Smarcel if (regnum == -1) 207115013Smarcel warning ("Unmapped DWARF Register #%d encountered\n", reg); 208115013Smarcel 209115013Smarcel return regnum; 210115013Smarcel} 211160157Smarcel 212115013Smarcel/* Return nonzero if a value of type TYPE stored in register REGNUM 213160157Smarcel needs any special handling. */ 214115013Smarcel 215115013Smarcelstatic int 216115013Smarcelamd64_convert_register_p (int regnum, struct type *type) 217129059Smarcel{ 218115013Smarcel return i386_fp_regnum_p (regnum); 219115013Smarcel} 220115013Smarcel 221115013Smarcel 222115013Smarcel/* Register classes as defined in the psABI. */ 223115013Smarcel 224115013Smarcelenum amd64_reg_class 225129059Smarcel{ 226115013Smarcel AMD64_INTEGER, 227115013Smarcel AMD64_SSE, 228115013Smarcel AMD64_SSEUP, 229115013Smarcel AMD64_X87, 230115013Smarcel AMD64_X87UP, 231115013Smarcel AMD64_COMPLEX_X87, 232115013Smarcel AMD64_NO_CLASS, 233115013Smarcel AMD64_MEMORY 234129059Smarcel}; 235115013Smarcel 236115013Smarcel/* Return the union class of CLASS1 and CLASS2. See the psABI for 237115013Smarcel details. */ 238115013Smarcel 239115013Smarcelstatic enum amd64_reg_class 240115013Smarcelamd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) 241160163Smarcel{ 242115013Smarcel /* Rule (a): If both classes are equal, this is the resulting class. */ 243115013Smarcel if (class1 == class2) 244115013Smarcel return class1; 245115013Smarcel 246115013Smarcel /* Rule (b): If one of the classes is NO_CLASS, the resulting class 247115013Smarcel is the other class. */ 248115013Smarcel if (class1 == AMD64_NO_CLASS) 249115013Smarcel return class2; 250115013Smarcel if (class2 == AMD64_NO_CLASS) 251115013Smarcel return class1; 252115013Smarcel 253115013Smarcel /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ 254115013Smarcel if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) 255115013Smarcel return AMD64_MEMORY; 256115013Smarcel 257115013Smarcel /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ 258115013Smarcel if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) 259115013Smarcel return AMD64_INTEGER; 260115013Smarcel 261115013Smarcel /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, 262115013Smarcel MEMORY is used as class. */ 263115013Smarcel if (class1 == AMD64_X87 || class1 == AMD64_X87UP 264115013Smarcel || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 265115013Smarcel || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) 266115013Smarcel return AMD64_MEMORY; 267115013Smarcel 268160157Smarcel /* Rule (f): Otherwise class SSE is used. */ 269115013Smarcel return AMD64_SSE; 270115013Smarcel} 271115013Smarcel 272115013Smarcelstatic void amd64_classify (struct type *type, enum amd64_reg_class class[2]); 273115013Smarcel 274/* Return non-zero if TYPE is a non-POD structure or union type. */ 275 276static int 277amd64_non_pod_p (struct type *type) 278{ 279 /* ??? A class with a base class certainly isn't POD, but does this 280 catch all non-POD structure types? */ 281 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) 282 return 1; 283 284 return 0; 285} 286 287/* Classify TYPE according to the rules for aggregate (structures and 288 arrays) and union types, and store the result in CLASS. */ 289 290static void 291amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) 292{ 293 int len = TYPE_LENGTH (type); 294 295 /* 1. If the size of an object is larger than two eightbytes, or in 296 C++, is a non-POD structure or union type, or contains 297 unaligned fields, it has class memory. */ 298 if (len > 16 || amd64_non_pod_p (type)) 299 { 300 class[0] = class[1] = AMD64_MEMORY; 301 return; 302 } 303 304 /* 2. Both eightbytes get initialized to class NO_CLASS. */ 305 class[0] = class[1] = AMD64_NO_CLASS; 306 307 /* 3. Each field of an object is classified recursively so that 308 always two fields are considered. The resulting class is 309 calculated according to the classes of the fields in the 310 eightbyte: */ 311 312 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 313 { 314 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); 315 316 /* All fields in an array have the same type. */ 317 amd64_classify (subtype, class); 318 if (len > 8 && class[1] == AMD64_NO_CLASS) 319 class[1] = class[0]; 320 } 321 else 322 { 323 int i; 324 325 /* Structure or union. */ 326 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT 327 || TYPE_CODE (type) == TYPE_CODE_UNION); 328 329 for (i = 0; i < TYPE_NFIELDS (type); i++) 330 { 331 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); 332 int pos = TYPE_FIELD_BITPOS (type, i) / 64; 333 enum amd64_reg_class subclass[2]; 334 335 /* Ignore static fields. */ 336 if (TYPE_FIELD_STATIC (type, i)) 337 continue; 338 339 gdb_assert (pos == 0 || pos == 1); 340 341 amd64_classify (subtype, subclass); 342 class[pos] = amd64_merge_classes (class[pos], subclass[0]); 343 if (pos == 0) 344 class[1] = amd64_merge_classes (class[1], subclass[1]); 345 } 346 } 347 348 /* 4. Then a post merger cleanup is done: */ 349 350 /* Rule (a): If one of the classes is MEMORY, the whole argument is 351 passed in memory. */ 352 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) 353 class[0] = class[1] = AMD64_MEMORY; 354 355 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to 356 SSE. */ 357 if (class[0] == AMD64_SSEUP) 358 class[0] = AMD64_SSE; 359 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) 360 class[1] = AMD64_SSE; 361} 362 363/* Classify TYPE, and store the result in CLASS. */ 364 365static void 366amd64_classify (struct type *type, enum amd64_reg_class class[2]) 367{ 368 enum type_code code = TYPE_CODE (type); 369 int len = TYPE_LENGTH (type); 370 371 class[0] = class[1] = AMD64_NO_CLASS; 372 373 /* Arguments of types (signed and unsigned) _Bool, char, short, int, 374 long, long long, and pointers are in the INTEGER class. */ 375 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM 376 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) 377 && (len == 1 || len == 2 || len == 4 || len == 8)) 378 class[0] = AMD64_INTEGER; 379 380 /* Arguments of types float, double and __m64 are in class SSE. */ 381 else if (code == TYPE_CODE_FLT && (len == 4 || len == 8)) 382 /* FIXME: __m64 . */ 383 class[0] = AMD64_SSE; 384 385 /* Arguments of types __float128 and __m128 are split into two 386 halves. The least significant ones belong to class SSE, the most 387 significant one to class SSEUP. */ 388 /* FIXME: __float128, __m128. */ 389 390 /* The 64-bit mantissa of arguments of type long double belongs to 391 class X87, the 16-bit exponent plus 6 bytes of padding belongs to 392 class X87UP. */ 393 else if (code == TYPE_CODE_FLT && len == 16) 394 /* Class X87 and X87UP. */ 395 class[0] = AMD64_X87, class[1] = AMD64_X87UP; 396 397 /* Aggregates. */ 398 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT 399 || code == TYPE_CODE_UNION) 400 amd64_classify_aggregate (type, class); 401} 402 403static enum return_value_convention 404amd64_return_value (struct gdbarch *gdbarch, struct type *type, 405 struct regcache *regcache, 406 void *readbuf, const void *writebuf) 407{ 408 enum amd64_reg_class class[2]; 409 int len = TYPE_LENGTH (type); 410 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; 411 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; 412 int integer_reg = 0; 413 int sse_reg = 0; 414 int i; 415 416 gdb_assert (!(readbuf && writebuf)); 417 418 /* 1. Classify the return type with the classification algorithm. */ 419 amd64_classify (type, class); 420 421 /* 2. If the type has class MEMORY, then the caller provides space 422 for the return value and passes the address of this storage in 423 %rdi as if it were the first argument to the function. In 424 effect, this address becomes a hidden first argument. */ 425 if (class[0] == AMD64_MEMORY) 426 return RETURN_VALUE_STRUCT_CONVENTION; 427 428 gdb_assert (class[1] != AMD64_MEMORY); 429 gdb_assert (len <= 16); 430 431 for (i = 0; len > 0; i++, len -= 8) 432 { 433 int regnum = -1; 434 int offset = 0; 435 436 switch (class[i]) 437 { 438 case AMD64_INTEGER: 439 /* 3. If the class is INTEGER, the next available register 440 of the sequence %rax, %rdx is used. */ 441 regnum = integer_regnum[integer_reg++]; 442 break; 443 444 case AMD64_SSE: 445 /* 4. If the class is SSE, the next available SSE register 446 of the sequence %xmm0, %xmm1 is used. */ 447 regnum = sse_regnum[sse_reg++]; 448 break; 449 450 case AMD64_SSEUP: 451 /* 5. If the class is SSEUP, the eightbyte is passed in the 452 upper half of the last used SSE register. */ 453 gdb_assert (sse_reg > 0); 454 regnum = sse_regnum[sse_reg - 1]; 455 offset = 8; 456 break; 457 458 case AMD64_X87: 459 /* 6. If the class is X87, the value is returned on the X87 460 stack in %st0 as 80-bit x87 number. */ 461 regnum = AMD64_ST0_REGNUM; 462 if (writebuf) 463 i387_return_value (gdbarch, regcache); 464 break; 465 466 case AMD64_X87UP: 467 /* 7. If the class is X87UP, the value is returned together 468 with the previous X87 value in %st0. */ 469 gdb_assert (i > 0 && class[0] == AMD64_X87); 470 regnum = AMD64_ST0_REGNUM; 471 offset = 8; 472 len = 2; 473 break; 474 475 case AMD64_NO_CLASS: 476 continue; 477 478 default: 479 gdb_assert (!"Unexpected register class."); 480 } 481 482 gdb_assert (regnum != -1); 483 484 if (readbuf) 485 regcache_raw_read_part (regcache, regnum, offset, min (len, 8), 486 (char *) readbuf + i * 8); 487 if (writebuf) 488 regcache_raw_write_part (regcache, regnum, offset, min (len, 8), 489 (const char *) writebuf + i * 8); 490 } 491 492 return RETURN_VALUE_REGISTER_CONVENTION; 493} 494 495 496static CORE_ADDR 497amd64_push_arguments (struct regcache *regcache, int nargs, 498 struct value **args, CORE_ADDR sp, int struct_return) 499{ 500 static int integer_regnum[] = 501 { 502 AMD64_RDI_REGNUM, /* %rdi */ 503 AMD64_RSI_REGNUM, /* %rsi */ 504 AMD64_RDX_REGNUM, /* %rdx */ 505 AMD64_RCX_REGNUM, /* %rcx */ 506 8, /* %r8 */ 507 9 /* %r9 */ 508 }; 509 static int sse_regnum[] = 510 { 511 /* %xmm0 ... %xmm7 */ 512 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 513 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 514 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 515 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 516 }; 517 struct value **stack_args = alloca (nargs * sizeof (struct value *)); 518 int num_stack_args = 0; 519 int num_elements = 0; 520 int element = 0; 521 int integer_reg = 0; 522 int sse_reg = 0; 523 int i; 524 525 /* Reserve a register for the "hidden" argument. */ 526 if (struct_return) 527 integer_reg++; 528 529 for (i = 0; i < nargs; i++) 530 { 531 struct type *type = VALUE_TYPE (args[i]); 532 int len = TYPE_LENGTH (type); 533 enum amd64_reg_class class[2]; 534 int needed_integer_regs = 0; 535 int needed_sse_regs = 0; 536 int j; 537 538 /* Classify argument. */ 539 amd64_classify (type, class); 540 541 /* Calculate the number of integer and SSE registers needed for 542 this argument. */ 543 for (j = 0; j < 2; j++) 544 { 545 if (class[j] == AMD64_INTEGER) 546 needed_integer_regs++; 547 else if (class[j] == AMD64_SSE) 548 needed_sse_regs++; 549 } 550 551 /* Check whether enough registers are available, and if the 552 argument should be passed in registers at all. */ 553 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) 554 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) 555 || (needed_integer_regs == 0 && needed_sse_regs == 0)) 556 { 557 /* The argument will be passed on the stack. */ 558 num_elements += ((len + 7) / 8); 559 stack_args[num_stack_args++] = args[i]; 560 } 561 else 562 { 563 /* The argument will be passed in registers. */ 564 char *valbuf = VALUE_CONTENTS (args[i]); 565 char buf[8]; 566 567 gdb_assert (len <= 16); 568 569 for (j = 0; len > 0; j++, len -= 8) 570 { 571 int regnum = -1; 572 int offset = 0; 573 574 switch (class[j]) 575 { 576 case AMD64_INTEGER: 577 regnum = integer_regnum[integer_reg++]; 578 break; 579 580 case AMD64_SSE: 581 regnum = sse_regnum[sse_reg++]; 582 break; 583 584 case AMD64_SSEUP: 585 gdb_assert (sse_reg > 0); 586 regnum = sse_regnum[sse_reg - 1]; 587 offset = 8; 588 break; 589 590 default: 591 gdb_assert (!"Unexpected register class."); 592 } 593 594 gdb_assert (regnum != -1); 595 memset (buf, 0, sizeof buf); 596 memcpy (buf, valbuf + j * 8, min (len, 8)); 597 regcache_raw_write_part (regcache, regnum, offset, 8, buf); 598 } 599 } 600 } 601 602 /* Allocate space for the arguments on the stack. */ 603 sp -= num_elements * 8; 604 605 /* The psABI says that "The end of the input argument area shall be 606 aligned on a 16 byte boundary." */ 607 sp &= ~0xf; 608 609 /* Write out the arguments to the stack. */ 610 for (i = 0; i < num_stack_args; i++) 611 { 612 struct type *type = VALUE_TYPE (stack_args[i]); 613 char *valbuf = VALUE_CONTENTS (stack_args[i]); 614 int len = TYPE_LENGTH (type); 615 616 write_memory (sp + element * 8, valbuf, len); 617 element += ((len + 7) / 8); 618 } 619 620 /* The psABI says that "For calls that may call functions that use 621 varargs or stdargs (prototype-less calls or calls to functions 622 containing ellipsis (...) in the declaration) %al is used as 623 hidden argument to specify the number of SSE registers used. */ 624 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); 625 return sp; 626} 627 628static CORE_ADDR 629amd64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 630 struct regcache *regcache, CORE_ADDR bp_addr, 631 int nargs, struct value **args, CORE_ADDR sp, 632 int struct_return, CORE_ADDR struct_addr) 633{ 634 char buf[8]; 635 636 /* Pass arguments. */ 637 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); 638 639 /* Pass "hidden" argument". */ 640 if (struct_return) 641 { 642 store_unsigned_integer (buf, 8, struct_addr); 643 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); 644 } 645 646 /* Store return address. */ 647 sp -= 8; 648 store_unsigned_integer (buf, 8, bp_addr); 649 write_memory (sp, buf, 8); 650 651 /* Finally, update the stack pointer... */ 652 store_unsigned_integer (buf, 8, sp); 653 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); 654 655 /* ...and fake a frame pointer. */ 656 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); 657 658 return sp + 16; 659} 660 661 662/* The maximum number of saved registers. This should include %rip. */ 663#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS 664 665struct amd64_frame_cache 666{ 667 /* Base address. */ 668 CORE_ADDR base; 669 CORE_ADDR sp_offset; 670 CORE_ADDR pc; 671 672 /* Saved registers. */ 673 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; 674 CORE_ADDR saved_sp; 675 676 /* Do we have a frame? */ 677 int frameless_p; 678}; 679 680/* Allocate and initialize a frame cache. */ 681 682static struct amd64_frame_cache * 683amd64_alloc_frame_cache (void) 684{ 685 struct amd64_frame_cache *cache; 686 int i; 687 688 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); 689 690 /* Base address. */ 691 cache->base = 0; 692 cache->sp_offset = -8; 693 cache->pc = 0; 694 695 /* Saved registers. We initialize these to -1 since zero is a valid 696 offset (that's where %rbp is supposed to be stored). */ 697 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 698 cache->saved_regs[i] = -1; 699 cache->saved_sp = 0; 700 701 /* Frameless until proven otherwise. */ 702 cache->frameless_p = 1; 703 704 return cache; 705} 706 707/* Do a limited analysis of the prologue at PC and update CACHE 708 accordingly. Bail out early if CURRENT_PC is reached. Return the 709 address where the analysis stopped. 710 711 We will handle only functions beginning with: 712 713 pushq %rbp 0x55 714 movq %rsp, %rbp 0x48 0x89 0xe5 715 716 Any function that doesn't start with this sequence will be assumed 717 to have no prologue and thus no valid frame pointer in %rbp. */ 718 719static CORE_ADDR 720amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, 721 struct amd64_frame_cache *cache) 722{ 723 static unsigned char proto[3] = { 0x48, 0x89, 0xe5 }; 724 unsigned char buf[3]; 725 unsigned char op; 726 727 if (current_pc <= pc) 728 return current_pc; 729 730 op = read_memory_unsigned_integer (pc, 1); 731 732 if (op == 0x55) /* pushq %rbp */ 733 { 734 /* Take into account that we've executed the `pushq %rbp' that 735 starts this instruction sequence. */ 736 cache->saved_regs[AMD64_RBP_REGNUM] = 0; 737 cache->sp_offset += 8; 738 739 /* If that's all, return now. */ 740 if (current_pc <= pc + 1) 741 return current_pc; 742 743 /* Check for `movq %rsp, %rbp'. */ 744 read_memory (pc + 1, buf, 3); 745 if (memcmp (buf, proto, 3) != 0) 746 return pc + 1; 747 748 /* OK, we actually have a frame. */ 749 cache->frameless_p = 0; 750 return pc + 4; 751 } 752 753 return pc; 754} 755 756/* Return PC of first real instruction. */ 757 758static CORE_ADDR 759amd64_skip_prologue (CORE_ADDR start_pc) 760{ 761 struct amd64_frame_cache cache; 762 CORE_ADDR pc; 763 764 pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache); 765 if (cache.frameless_p) 766 return start_pc; 767 768 return pc; 769} 770 771 772/* Normal frames. */ 773 774static struct amd64_frame_cache * 775amd64_frame_cache (struct frame_info *next_frame, void **this_cache) 776{ 777 struct amd64_frame_cache *cache; 778 char buf[8]; 779 int i; 780 781 if (*this_cache) 782 return *this_cache; 783 784 cache = amd64_alloc_frame_cache (); 785 *this_cache = cache; 786 787 cache->pc = frame_func_unwind (next_frame); 788 if (cache->pc != 0) 789 amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); 790 791 if (cache->frameless_p) 792 { 793 /* We didn't find a valid frame. If we're at the start of a 794 function, or somewhere half-way its prologue, the function's 795 frame probably hasn't been fully setup yet. Try to 796 reconstruct the base address for the stack frame by looking 797 at the stack pointer. For truly "frameless" functions this 798 might work too. */ 799 800 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); 801 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; 802 } 803 else 804 { 805 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); 806 cache->base = extract_unsigned_integer (buf, 8); 807 } 808 809 /* Now that we have the base address for the stack frame we can 810 calculate the value of %rsp in the calling frame. */ 811 cache->saved_sp = cache->base + 16; 812 813 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a 814 frame we find it at the same offset from the reconstructed base 815 address. */ 816 cache->saved_regs[AMD64_RIP_REGNUM] = 8; 817 818 /* Adjust all the saved registers such that they contain addresses 819 instead of offsets. */ 820 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 821 if (cache->saved_regs[i] != -1) 822 cache->saved_regs[i] += cache->base; 823 824 return cache; 825} 826 827static void 828amd64_frame_this_id (struct frame_info *next_frame, void **this_cache, 829 struct frame_id *this_id) 830{ 831 struct amd64_frame_cache *cache = 832 amd64_frame_cache (next_frame, this_cache); 833 834 /* This marks the outermost frame. */ 835 if (cache->base == 0) 836 return; 837 838 (*this_id) = frame_id_build (cache->base + 16, cache->pc); 839} 840 841static void 842amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache, 843 int regnum, int *optimizedp, 844 enum lval_type *lvalp, CORE_ADDR *addrp, 845 int *realnump, void *valuep) 846{ 847 struct amd64_frame_cache *cache = 848 amd64_frame_cache (next_frame, this_cache); 849 850 gdb_assert (regnum >= 0); 851 852 if (regnum == SP_REGNUM && cache->saved_sp) 853 { 854 *optimizedp = 0; 855 *lvalp = not_lval; 856 *addrp = 0; 857 *realnump = -1; 858 if (valuep) 859 { 860 /* Store the value. */ 861 store_unsigned_integer (valuep, 8, cache->saved_sp); 862 } 863 return; 864 } 865 866 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 867 { 868 *optimizedp = 0; 869 *lvalp = lval_memory; 870 *addrp = cache->saved_regs[regnum]; 871 *realnump = -1; 872 if (valuep) 873 { 874 /* Read the value in from memory. */ 875 read_memory (*addrp, valuep, 876 register_size (current_gdbarch, regnum)); 877 } 878 return; 879 } 880 881 frame_register_unwind (next_frame, regnum, 882 optimizedp, lvalp, addrp, realnump, valuep); 883} 884 885static const struct frame_unwind amd64_frame_unwind = 886{ 887 NORMAL_FRAME, 888 amd64_frame_this_id, 889 amd64_frame_prev_register 890}; 891 892static const struct frame_unwind * 893amd64_frame_sniffer (struct frame_info *next_frame) 894{ 895 return &amd64_frame_unwind; 896} 897 898 899/* Signal trampolines. */ 900 901/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and 902 64-bit variants. This would require using identical frame caches 903 on both platforms. */ 904 905static struct amd64_frame_cache * 906amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) 907{ 908 struct amd64_frame_cache *cache; 909 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 910 CORE_ADDR addr; 911 char buf[8]; 912 int i; 913 914 if (*this_cache) 915 return *this_cache; 916 917 cache = amd64_alloc_frame_cache (); 918 919 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); 920 cache->base = extract_unsigned_integer (buf, 8) - 8; 921 922 addr = tdep->sigcontext_addr (next_frame); 923 gdb_assert (tdep->sc_reg_offset); 924 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); 925 for (i = 0; i < tdep->sc_num_regs; i++) 926 if (tdep->sc_reg_offset[i] != -1) 927 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 928 929 *this_cache = cache; 930 return cache; 931} 932 933static void 934amd64_sigtramp_frame_this_id (struct frame_info *next_frame, 935 void **this_cache, struct frame_id *this_id) 936{ 937 struct amd64_frame_cache *cache = 938 amd64_sigtramp_frame_cache (next_frame, this_cache); 939 940 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame)); 941} 942 943static void 944amd64_sigtramp_frame_prev_register (struct frame_info *next_frame, 945 void **this_cache, 946 int regnum, int *optimizedp, 947 enum lval_type *lvalp, CORE_ADDR *addrp, 948 int *realnump, void *valuep) 949{ 950 /* Make sure we've initialized the cache. */ 951 amd64_sigtramp_frame_cache (next_frame, this_cache); 952 953 amd64_frame_prev_register (next_frame, this_cache, regnum, 954 optimizedp, lvalp, addrp, realnump, valuep); 955} 956 957static const struct frame_unwind amd64_sigtramp_frame_unwind = 958{ 959 SIGTRAMP_FRAME, 960 amd64_sigtramp_frame_this_id, 961 amd64_sigtramp_frame_prev_register 962}; 963 964static const struct frame_unwind * 965amd64_sigtramp_frame_sniffer (struct frame_info *next_frame) 966{ 967 CORE_ADDR pc = frame_pc_unwind (next_frame); 968 char *name; 969 970 find_pc_partial_function (pc, &name, NULL, NULL); 971 if (PC_IN_SIGTRAMP (pc, name)) 972 { 973 gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr); 974 975 return &amd64_sigtramp_frame_unwind; 976 } 977 978 return NULL; 979} 980 981 982static CORE_ADDR 983amd64_frame_base_address (struct frame_info *next_frame, void **this_cache) 984{ 985 struct amd64_frame_cache *cache = 986 amd64_frame_cache (next_frame, this_cache); 987 988 return cache->base; 989} 990 991static const struct frame_base amd64_frame_base = 992{ 993 &amd64_frame_unwind, 994 amd64_frame_base_address, 995 amd64_frame_base_address, 996 amd64_frame_base_address 997}; 998 999static struct frame_id 1000amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 1001{ 1002 char buf[8]; 1003 CORE_ADDR fp; 1004 1005 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); 1006 fp = extract_unsigned_integer (buf, 8); 1007 1008 return frame_id_build (fp + 16, frame_pc_unwind (next_frame)); 1009} 1010 1011/* 16 byte align the SP per frame requirements. */ 1012 1013static CORE_ADDR 1014amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 1015{ 1016 return sp & -(CORE_ADDR)16; 1017} 1018 1019 1020/* Supply register REGNUM from the floating-point register set REGSET 1021 to register cache REGCACHE. If REGNUM is -1, do this for all 1022 registers in REGSET. */ 1023 1024static void 1025amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, 1026 int regnum, const void *fpregs, size_t len) 1027{ 1028 const struct gdbarch_tdep *tdep = regset->descr; 1029 1030 gdb_assert (len == tdep->sizeof_fpregset); 1031 amd64_supply_fxsave (regcache, regnum, fpregs); 1032} 1033 1034/* Return the appropriate register set for the core section identified 1035 by SECT_NAME and SECT_SIZE. */ 1036 1037static const struct regset * 1038amd64_regset_from_core_section (struct gdbarch *gdbarch, 1039 const char *sect_name, size_t sect_size) 1040{ 1041 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1042 1043 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) 1044 { 1045 if (tdep->fpregset == NULL) 1046 { 1047 tdep->fpregset = XMALLOC (struct regset); 1048 tdep->fpregset->descr = tdep; 1049 tdep->fpregset->supply_regset = amd64_supply_fpregset; 1050 } 1051 1052 return tdep->fpregset; 1053 } 1054 1055 return i386_regset_from_core_section (gdbarch, sect_name, sect_size); 1056} 1057 1058 1059void 1060amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 1061{ 1062 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1063 1064 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its 1065 floating-point registers. */ 1066 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; 1067 1068 /* AMD64 has an FPU and 16 SSE registers. */ 1069 tdep->st0_regnum = AMD64_ST0_REGNUM; 1070 tdep->num_xmm_regs = 16; 1071 1072 /* This is what all the fuss is about. */ 1073 set_gdbarch_long_bit (gdbarch, 64); 1074 set_gdbarch_long_long_bit (gdbarch, 64); 1075 set_gdbarch_ptr_bit (gdbarch, 64); 1076 1077 /* In contrast to the i386, on AMD64 a `long double' actually takes 1078 up 128 bits, even though it's still based on the i387 extended 1079 floating-point format which has only 80 significant bits. */ 1080 set_gdbarch_long_double_bit (gdbarch, 128); 1081 1082 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); 1083 set_gdbarch_register_name (gdbarch, amd64_register_name); 1084 set_gdbarch_register_type (gdbarch, amd64_register_type); 1085 1086 /* Register numbers of various important registers. */ 1087 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ 1088 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ 1089 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ 1090 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ 1091 1092 /* The "default" register numbering scheme for AMD64 is referred to 1093 as the "DWARF Register Number Mapping" in the System V psABI. 1094 The preferred debugging format for all known AMD64 targets is 1095 actually DWARF2, and GCC doesn't seem to support DWARF (that is 1096 DWARF-1), but we provide the same mapping just in case. This 1097 mapping is also used for stabs, which GCC does support. */ 1098 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1099 set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1100 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1101 1102 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to 1103 be in use on any of the supported AMD64 targets. */ 1104 1105 /* Call dummy code. */ 1106 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); 1107 set_gdbarch_frame_align (gdbarch, amd64_frame_align); 1108 set_gdbarch_frame_red_zone_size (gdbarch, 128); 1109 1110 set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p); 1111 set_gdbarch_register_to_value (gdbarch, i387_register_to_value); 1112 set_gdbarch_value_to_register (gdbarch, i387_value_to_register); 1113 1114 set_gdbarch_return_value (gdbarch, amd64_return_value); 1115 1116 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); 1117 1118 /* Avoid wiring in the MMX registers for now. */ 1119 set_gdbarch_num_pseudo_regs (gdbarch, 0); 1120 tdep->mm0_regnum = -1; 1121 1122 set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id); 1123 1124 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now, 1125 since all supported AMD64 targets are ELF, but that might change 1126 in the future. */ 1127 set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section); 1128 1129 frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer); 1130 frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer); 1131 frame_base_set_default (gdbarch, &amd64_frame_base); 1132 1133 /* If we have a register mapping, enable the generic core file support. */ 1134 if (tdep->gregset_reg_offset) 1135 set_gdbarch_regset_from_core_section (gdbarch, 1136 amd64_regset_from_core_section); 1137} 1138 1139 1140#define I387_ST0_REGNUM AMD64_ST0_REGNUM 1141 1142/* The 64-bit FXSAVE format differs from the 32-bit format in the 1143 sense that the instruction pointer and data pointer are simply 1144 64-bit offsets into the code segment and the data segment instead 1145 of a selector offset pair. The functions below store the upper 32 1146 bits of these pointers (instead of just the 16-bits of the segment 1147 selector). */ 1148 1149/* Fill register REGNUM in REGCACHE with the appropriate 1150 floating-point or SSE register value from *FXSAVE. If REGNUM is 1151 -1, do this for all registers. This function masks off any of the 1152 reserved bits in *FXSAVE. */ 1153 1154void 1155amd64_supply_fxsave (struct regcache *regcache, int regnum, 1156 const void *fxsave) 1157{ 1158 i387_supply_fxsave (regcache, regnum, fxsave); 1159 1160 if (fxsave) 1161 { 1162 const char *regs = fxsave; 1163 1164 if (regnum == -1 || regnum == I387_FISEG_REGNUM) 1165 regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12); 1166 if (regnum == -1 || regnum == I387_FOSEG_REGNUM) 1167 regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20); 1168 } 1169} 1170 1171/* Fill register REGNUM (if it is a floating-point or SSE register) in 1172 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for 1173 all registers. This function doesn't touch any of the reserved 1174 bits in *FXSAVE. */ 1175 1176void 1177amd64_collect_fxsave (const struct regcache *regcache, int regnum, 1178 void *fxsave) 1179{ 1180 char *regs = fxsave; 1181 1182 i387_collect_fxsave (regcache, regnum, fxsave); 1183 1184 if (regnum == -1 || regnum == I387_FISEG_REGNUM) 1185 regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12); 1186 if (regnum == -1 || regnum == I387_FOSEG_REGNUM) 1187 regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20); 1188} 1189 1190/* Fill register REGNUM (if it is a floating-point or SSE register) in 1191 *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do 1192 this for all registers. This function doesn't touch any of the 1193 reserved bits in *FXSAVE. */ 1194 1195void 1196amd64_fill_fxsave (char *fxsave, int regnum) 1197{ 1198 amd64_collect_fxsave (current_regcache, regnum, fxsave); 1199} 1200