1117395Skan;; AltiVec patterns. 2169689Skan;; Copyright (C) 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 3117395Skan;; Contributed by Aldy Hernandez (aldy@quesejoda.com) 4117395Skan 5132718Skan;; This file is part of GCC. 6117395Skan 7132718Skan;; GCC is free software; you can redistribute it and/or modify it 8132718Skan;; under the terms of the GNU General Public License as published 9132718Skan;; by the Free Software Foundation; either version 2, or (at your 10132718Skan;; option) any later version. 11117395Skan 12132718Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 13132718Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14132718Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15132718Skan;; License for more details. 16117395Skan 17117395Skan;; You should have received a copy of the GNU General Public License 18132718Skan;; along with GCC; see the file COPYING. If not, write to the 19169689Skan;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 20169689Skan;; MA 02110-1301, USA. 21117395Skan 22132718Skan(define_constants 23169689Skan [(UNSPEC_VCMPBFP 50) 24169689Skan (UNSPEC_VCMPEQUB 51) 25169689Skan (UNSPEC_VCMPEQUH 52) 26169689Skan (UNSPEC_VCMPEQUW 53) 27169689Skan (UNSPEC_VCMPEQFP 54) 28169689Skan (UNSPEC_VCMPGEFP 55) 29169689Skan (UNSPEC_VCMPGTUB 56) 30169689Skan (UNSPEC_VCMPGTSB 57) 31169689Skan (UNSPEC_VCMPGTUH 58) 32169689Skan (UNSPEC_VCMPGTSH 59) 33169689Skan (UNSPEC_VCMPGTUW 60) 34169689Skan (UNSPEC_VCMPGTSW 61) 35169689Skan (UNSPEC_VCMPGTFP 62) 36169689Skan (UNSPEC_VMSUMU 65) 37169689Skan (UNSPEC_VMSUMM 66) 38169689Skan (UNSPEC_VMSUMSHM 68) 39169689Skan (UNSPEC_VMSUMUHS 69) 40169689Skan (UNSPEC_VMSUMSHS 70) 41169689Skan (UNSPEC_VMHADDSHS 71) 42169689Skan (UNSPEC_VMHRADDSHS 72) 43169689Skan (UNSPEC_VMLADDUHM 73) 44169689Skan (UNSPEC_VADDCUW 75) 45169689Skan (UNSPEC_VADDU 76) 46169689Skan (UNSPEC_VADDS 77) 47169689Skan (UNSPEC_VAVGU 80) 48169689Skan (UNSPEC_VAVGS 81) 49169689Skan (UNSPEC_VMULEUB 83) 50169689Skan (UNSPEC_VMULESB 84) 51169689Skan (UNSPEC_VMULEUH 85) 52169689Skan (UNSPEC_VMULESH 86) 53169689Skan (UNSPEC_VMULOUB 87) 54169689Skan (UNSPEC_VMULOSB 88) 55169689Skan (UNSPEC_VMULOUH 89) 56169689Skan (UNSPEC_VMULOSH 90) 57169689Skan (UNSPEC_VPKUHUM 93) 58169689Skan (UNSPEC_VPKUWUM 94) 59169689Skan (UNSPEC_VPKPX 95) 60169689Skan (UNSPEC_VPKSHSS 97) 61169689Skan (UNSPEC_VPKSWSS 99) 62169689Skan (UNSPEC_VPKUHUS 100) 63169689Skan (UNSPEC_VPKSHUS 101) 64169689Skan (UNSPEC_VPKUWUS 102) 65169689Skan (UNSPEC_VPKSWUS 103) 66169689Skan (UNSPEC_VRL 104) 67169689Skan (UNSPEC_VSL 107) 68169689Skan (UNSPEC_VSLV4SI 110) 69169689Skan (UNSPEC_VSLO 111) 70169689Skan (UNSPEC_VSR 118) 71169689Skan (UNSPEC_VSRO 119) 72169689Skan (UNSPEC_VSUBCUW 124) 73169689Skan (UNSPEC_VSUBU 125) 74169689Skan (UNSPEC_VSUBS 126) 75169689Skan (UNSPEC_VSUM4UBS 131) 76169689Skan (UNSPEC_VSUM4S 132) 77169689Skan (UNSPEC_VSUM2SWS 134) 78169689Skan (UNSPEC_VSUMSWS 135) 79169689Skan (UNSPEC_VPERM 144) 80169689Skan (UNSPEC_VRFIP 148) 81169689Skan (UNSPEC_VRFIN 149) 82169689Skan (UNSPEC_VRFIM 150) 83169689Skan (UNSPEC_VCFUX 151) 84169689Skan (UNSPEC_VCFSX 152) 85169689Skan (UNSPEC_VCTUXS 153) 86169689Skan (UNSPEC_VCTSXS 154) 87169689Skan (UNSPEC_VLOGEFP 155) 88169689Skan (UNSPEC_VEXPTEFP 156) 89169689Skan (UNSPEC_VRSQRTEFP 157) 90169689Skan (UNSPEC_VREFP 158) 91169689Skan (UNSPEC_VSEL4SI 159) 92169689Skan (UNSPEC_VSEL4SF 160) 93169689Skan (UNSPEC_VSEL8HI 161) 94169689Skan (UNSPEC_VSEL16QI 162) 95169689Skan (UNSPEC_VLSDOI 163) 96169689Skan (UNSPEC_VUPKHSB 167) 97169689Skan (UNSPEC_VUPKHPX 168) 98169689Skan (UNSPEC_VUPKHSH 169) 99169689Skan (UNSPEC_VUPKLSB 170) 100169689Skan (UNSPEC_VUPKLPX 171) 101169689Skan (UNSPEC_VUPKLSH 172) 102169689Skan (UNSPEC_PREDICATE 173) 103169689Skan (UNSPEC_DST 190) 104169689Skan (UNSPEC_DSTT 191) 105169689Skan (UNSPEC_DSTST 192) 106169689Skan (UNSPEC_DSTSTT 193) 107169689Skan (UNSPEC_LVSL 194) 108169689Skan (UNSPEC_LVSR 195) 109169689Skan (UNSPEC_LVE 196) 110169689Skan (UNSPEC_STVX 201) 111169689Skan (UNSPEC_STVXL 202) 112169689Skan (UNSPEC_STVE 203) 113169689Skan (UNSPEC_SET_VSCR 213) 114169689Skan (UNSPEC_GET_VRSAVE 214) 115169689Skan (UNSPEC_REALIGN_LOAD 215) 116169689Skan (UNSPEC_REDUC_PLUS 217) 117169689Skan (UNSPEC_VECSH 219) 118169689Skan (UNSPEC_VCOND_V4SI 301) 119169689Skan (UNSPEC_VCOND_V4SF 302) 120169689Skan (UNSPEC_VCOND_V8HI 303) 121169689Skan (UNSPEC_VCOND_V16QI 304) 122169689Skan (UNSPEC_VCONDU_V4SI 305) 123169689Skan (UNSPEC_VCONDU_V8HI 306) 124169689Skan (UNSPEC_VCONDU_V16QI 307) 125132718Skan ]) 126132718Skan 127169689Skan(define_constants 128169689Skan [(UNSPECV_SET_VRSAVE 30) 129169689Skan (UNSPECV_MTVSCR 186) 130169689Skan (UNSPECV_MFVSCR 187) 131169689Skan (UNSPECV_DSSALL 188) 132169689Skan (UNSPECV_DSS 189) 133169689Skan ]) 134117395Skan 135169689Skan;; Vec int modes 136169689Skan(define_mode_macro VI [V4SI V8HI V16QI]) 137169689Skan;; Short vec in modes 138169689Skan(define_mode_macro VIshort [V8HI V16QI]) 139169689Skan;; Vec float modes 140169689Skan(define_mode_macro VF [V4SF]) 141169689Skan;; Vec modes, pity mode macros are not composable 142169689Skan(define_mode_macro V [V4SI V8HI V16QI V4SF]) 143117395Skan 144169689Skan(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")]) 145117395Skan 146169689Skan;; Generic LVX load instruction. 147169689Skan(define_insn "altivec_lvx_<mode>" 148169689Skan [(set (match_operand:V 0 "altivec_register_operand" "=v") 149169689Skan (match_operand:V 1 "memory_operand" "Z"))] 150117395Skan "TARGET_ALTIVEC" 151117395Skan "lvx %0,%y1" 152117395Skan [(set_attr "type" "vecload")]) 153117395Skan 154117395Skan;; Generic STVX store instruction. 155169689Skan(define_insn "altivec_stvx_<mode>" 156169689Skan [(set (match_operand:V 0 "memory_operand" "=Z") 157169689Skan (match_operand:V 1 "altivec_register_operand" "v"))] 158117395Skan "TARGET_ALTIVEC" 159117395Skan "stvx %1,%y0" 160117395Skan [(set_attr "type" "vecstore")]) 161117395Skan 162117395Skan;; Vector move instructions. 163169689Skan(define_expand "mov<mode>" 164169689Skan [(set (match_operand:V 0 "nonimmediate_operand" "") 165169689Skan (match_operand:V 1 "any_operand" ""))] 166117395Skan "TARGET_ALTIVEC" 167169689Skan{ 168169689Skan rs6000_emit_move (operands[0], operands[1], <MODE>mode); 169169689Skan DONE; 170169689Skan}) 171117395Skan 172169689Skan(define_insn "*mov<mode>_internal" 173169689Skan [(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v") 174169689Skan (match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))] 175132718Skan "TARGET_ALTIVEC 176169689Skan && (register_operand (operands[0], <MODE>mode) 177169689Skan || register_operand (operands[1], <MODE>mode))" 178132718Skan{ 179132718Skan switch (which_alternative) 180132718Skan { 181169689Skan case 0: return "stvx %1,%y0"; 182169689Skan case 1: return "lvx %0,%y1"; 183169689Skan case 2: return "vor %0,%1,%1"; 184169689Skan case 3: return "#"; 185169689Skan case 4: return "#"; 186169689Skan case 5: return "#"; 187132718Skan case 6: return output_vec_const_move (operands); 188169689Skan default: gcc_unreachable (); 189132718Skan } 190169689Skan} 191132718Skan [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")]) 192117395Skan 193132718Skan(define_split 194132718Skan [(set (match_operand:V4SI 0 "nonimmediate_operand" "") 195132718Skan (match_operand:V4SI 1 "input_operand" ""))] 196132718Skan "TARGET_ALTIVEC && reload_completed 197132718Skan && gpr_or_gpr_p (operands[0], operands[1])" 198132718Skan [(pc)] 199132718Skan{ 200169689Skan rs6000_split_multireg_move (operands[0], operands[1]); DONE; 201169689Skan}) 202117395Skan 203132718Skan(define_split 204132718Skan [(set (match_operand:V8HI 0 "nonimmediate_operand" "") 205132718Skan (match_operand:V8HI 1 "input_operand" ""))] 206132718Skan "TARGET_ALTIVEC && reload_completed 207132718Skan && gpr_or_gpr_p (operands[0], operands[1])" 208132718Skan [(pc)] 209132718Skan{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 210132718Skan 211132718Skan(define_split 212117395Skan [(set (match_operand:V16QI 0 "nonimmediate_operand" "") 213132718Skan (match_operand:V16QI 1 "input_operand" ""))] 214132718Skan "TARGET_ALTIVEC && reload_completed 215132718Skan && gpr_or_gpr_p (operands[0], operands[1])" 216132718Skan [(pc)] 217132718Skan{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 218132718Skan 219132718Skan(define_split 220169689Skan [(set (match_operand:V4SF 0 "nonimmediate_operand" "") 221169689Skan (match_operand:V4SF 1 "input_operand" ""))] 222169689Skan "TARGET_ALTIVEC && reload_completed 223169689Skan && gpr_or_gpr_p (operands[0], operands[1])" 224169689Skan [(pc)] 225169689Skan{ 226169689Skan rs6000_split_multireg_move (operands[0], operands[1]); DONE; 227169689Skan}) 228169689Skan 229169689Skan(define_split 230169689Skan [(set (match_operand:VI 0 "altivec_register_operand" "") 231169689Skan (match_operand:VI 1 "easy_vector_constant_add_self" ""))] 232132718Skan "TARGET_ALTIVEC && reload_completed" 233132718Skan [(set (match_dup 0) (match_dup 3)) 234169689Skan (set (match_dup 0) (plus:VI (match_dup 0) 235169689Skan (match_dup 0)))] 236132718Skan{ 237169689Skan rtx dup = gen_easy_altivec_constant (operands[1]); 238169689Skan rtx const_vec; 239132718Skan 240169689Skan /* Divide the operand of the resulting VEC_DUPLICATE, and use 241169689Skan simplify_rtx to make a CONST_VECTOR. */ 242169689Skan XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode, 243169689Skan XEXP (dup, 0), const1_rtx); 244169689Skan const_vec = simplify_rtx (dup); 245117395Skan 246169689Skan if (GET_MODE (const_vec) == <MODE>mode) 247169689Skan operands[3] = const_vec; 248169689Skan else 249169689Skan operands[3] = gen_lowpart (<MODE>mode, const_vec); 250169689Skan}) 251117395Skan 252117395Skan(define_insn "get_vrsave_internal" 253117395Skan [(set (match_operand:SI 0 "register_operand" "=r") 254169689Skan (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))] 255117395Skan "TARGET_ALTIVEC" 256117395Skan{ 257117395Skan if (TARGET_MACHO) 258169689Skan return "mfspr %0,256"; 259117395Skan else 260169689Skan return "mfvrsave %0"; 261169689Skan} 262132718Skan [(set_attr "type" "*")]) 263117395Skan 264117395Skan(define_insn "*set_vrsave_internal" 265117395Skan [(match_parallel 0 "vrsave_operation" 266117395Skan [(set (reg:SI 109) 267117395Skan (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") 268169689Skan (reg:SI 109)] UNSPECV_SET_VRSAVE))])] 269117395Skan "TARGET_ALTIVEC" 270117395Skan{ 271117395Skan if (TARGET_MACHO) 272169689Skan return "mtspr 256,%1"; 273117395Skan else 274169689Skan return "mtvrsave %1"; 275169689Skan} 276132718Skan [(set_attr "type" "*")]) 277117395Skan 278169689Skan(define_insn "*save_world" 279169689Skan [(match_parallel 0 "save_world_operation" 280169689Skan [(clobber (match_operand:SI 1 "register_operand" "=l")) 281169689Skan (use (match_operand:SI 2 "call_operand" "s"))])] 282169689Skan "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT" 283169689Skan "bl %z2" 284169689Skan [(set_attr "type" "branch") 285169689Skan (set_attr "length" "4")]) 286117395Skan 287169689Skan(define_insn "*restore_world" 288169689Skan [(match_parallel 0 "restore_world_operation" 289169689Skan [(return) 290169689Skan (use (match_operand:SI 1 "register_operand" "l")) 291169689Skan (use (match_operand:SI 2 "call_operand" "s")) 292169689Skan (clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])] 293169689Skan "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT" 294169689Skan "b %z2") 295117395Skan 296169689Skan;; Simple binary operations. 297117395Skan 298169689Skan;; add 299169689Skan(define_insn "add<mode>3" 300169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 301169689Skan (plus:VI (match_operand:VI 1 "register_operand" "v") 302169689Skan (match_operand:VI 2 "register_operand" "v")))] 303117395Skan "TARGET_ALTIVEC" 304169689Skan "vaddu<VI_char>m %0,%1,%2" 305117395Skan [(set_attr "type" "vecsimple")]) 306117395Skan 307117395Skan(define_insn "addv4sf3" 308117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 309117395Skan (plus:V4SF (match_operand:V4SF 1 "register_operand" "v") 310117395Skan (match_operand:V4SF 2 "register_operand" "v")))] 311117395Skan "TARGET_ALTIVEC" 312117395Skan "vaddfp %0,%1,%2" 313117395Skan [(set_attr "type" "vecfloat")]) 314117395Skan 315117395Skan(define_insn "altivec_vaddcuw" 316117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 317117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 318169689Skan (match_operand:V4SI 2 "register_operand" "v")] 319169689Skan UNSPEC_VADDCUW))] 320117395Skan "TARGET_ALTIVEC" 321117395Skan "vaddcuw %0,%1,%2" 322117395Skan [(set_attr "type" "vecsimple")]) 323117395Skan 324169689Skan(define_insn "altivec_vaddu<VI_char>s" 325169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 326169689Skan (unspec:VI [(match_operand:VI 1 "register_operand" "v") 327169689Skan (match_operand:VI 2 "register_operand" "v")] 328169689Skan UNSPEC_VADDU)) 329169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 330117395Skan "TARGET_ALTIVEC" 331169689Skan "vaddu<VI_char>s %0,%1,%2" 332117395Skan [(set_attr "type" "vecsimple")]) 333117395Skan 334169689Skan(define_insn "altivec_vadds<VI_char>s" 335169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 336169689Skan (unspec:VI [(match_operand:VI 1 "register_operand" "v") 337169689Skan (match_operand:VI 2 "register_operand" "v")] 338169689Skan UNSPEC_VADDS)) 339169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 340117395Skan "TARGET_ALTIVEC" 341169689Skan "vadds<VI_char>s %0,%1,%2" 342117395Skan [(set_attr "type" "vecsimple")]) 343117395Skan 344169689Skan;; sub 345169689Skan(define_insn "sub<mode>3" 346169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 347169689Skan (minus:VI (match_operand:VI 1 "register_operand" "v") 348169689Skan (match_operand:VI 2 "register_operand" "v")))] 349117395Skan "TARGET_ALTIVEC" 350169689Skan "vsubu<VI_char>m %0,%1,%2" 351117395Skan [(set_attr "type" "vecsimple")]) 352117395Skan 353169689Skan(define_insn "subv4sf3" 354169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 355169689Skan (minus:V4SF (match_operand:V4SF 1 "register_operand" "v") 356169689Skan (match_operand:V4SF 2 "register_operand" "v")))] 357117395Skan "TARGET_ALTIVEC" 358169689Skan "vsubfp %0,%1,%2" 359169689Skan [(set_attr "type" "vecfloat")]) 360117395Skan 361169689Skan(define_insn "altivec_vsubcuw" 362117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 363117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 364169689Skan (match_operand:V4SI 2 "register_operand" "v")] 365169689Skan UNSPEC_VSUBCUW))] 366117395Skan "TARGET_ALTIVEC" 367169689Skan "vsubcuw %0,%1,%2" 368117395Skan [(set_attr "type" "vecsimple")]) 369117395Skan 370169689Skan(define_insn "altivec_vsubu<VI_char>s" 371169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 372169689Skan (unspec:VI [(match_operand:VI 1 "register_operand" "v") 373169689Skan (match_operand:VI 2 "register_operand" "v")] 374169689Skan UNSPEC_VSUBU)) 375169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 376117395Skan "TARGET_ALTIVEC" 377169689Skan "vsubu<VI_char>s %0,%1,%2" 378117395Skan [(set_attr "type" "vecsimple")]) 379117395Skan 380169689Skan(define_insn "altivec_vsubs<VI_char>s" 381169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 382169689Skan (unspec:VI [(match_operand:VI 1 "register_operand" "v") 383169689Skan (match_operand:VI 2 "register_operand" "v")] 384169689Skan UNSPEC_VSUBS)) 385169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 386117395Skan "TARGET_ALTIVEC" 387169689Skan "vsubs<VI_char>s %0,%1,%2" 388117395Skan [(set_attr "type" "vecsimple")]) 389117395Skan 390169689Skan;; 391169689Skan(define_insn "altivec_vavgu<VI_char>" 392169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 393169689Skan (unspec:VI [(match_operand:VI 1 "register_operand" "v") 394169689Skan (match_operand:VI 2 "register_operand" "v")] 395169689Skan UNSPEC_VAVGU))] 396117395Skan "TARGET_ALTIVEC" 397169689Skan "vavgu<VI_char> %0,%1,%2" 398117395Skan [(set_attr "type" "vecsimple")]) 399117395Skan 400169689Skan(define_insn "altivec_vavgs<VI_char>" 401169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 402169689Skan (unspec:VI [(match_operand:VI 1 "register_operand" "v") 403169689Skan (match_operand:VI 2 "register_operand" "v")] 404169689Skan UNSPEC_VAVGS))] 405117395Skan "TARGET_ALTIVEC" 406169689Skan "vavgs<VI_char> %0,%1,%2" 407117395Skan [(set_attr "type" "vecsimple")]) 408117395Skan 409117395Skan(define_insn "altivec_vcmpbfp" 410117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 411117395Skan (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 412169689Skan (match_operand:V4SF 2 "register_operand" "v")] 413169689Skan UNSPEC_VCMPBFP))] 414117395Skan "TARGET_ALTIVEC" 415117395Skan "vcmpbfp %0,%1,%2" 416117395Skan [(set_attr "type" "veccmp")]) 417117395Skan 418117395Skan(define_insn "altivec_vcmpequb" 419117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 420117395Skan (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 421169689Skan (match_operand:V16QI 2 "register_operand" "v")] 422169689Skan UNSPEC_VCMPEQUB))] 423117395Skan "TARGET_ALTIVEC" 424117395Skan "vcmpequb %0,%1,%2" 425117395Skan [(set_attr "type" "vecsimple")]) 426117395Skan 427117395Skan(define_insn "altivec_vcmpequh" 428117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 429117395Skan (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 430169689Skan (match_operand:V8HI 2 "register_operand" "v")] 431169689Skan UNSPEC_VCMPEQUH))] 432117395Skan "TARGET_ALTIVEC" 433117395Skan "vcmpequh %0,%1,%2" 434117395Skan [(set_attr "type" "vecsimple")]) 435117395Skan 436117395Skan(define_insn "altivec_vcmpequw" 437117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 438117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 439169689Skan (match_operand:V4SI 2 "register_operand" "v")] 440169689Skan UNSPEC_VCMPEQUW))] 441117395Skan "TARGET_ALTIVEC" 442117395Skan "vcmpequw %0,%1,%2" 443117395Skan [(set_attr "type" "vecsimple")]) 444117395Skan 445117395Skan(define_insn "altivec_vcmpeqfp" 446117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 447117395Skan (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 448169689Skan (match_operand:V4SF 2 "register_operand" "v")] 449169689Skan UNSPEC_VCMPEQFP))] 450117395Skan "TARGET_ALTIVEC" 451117395Skan "vcmpeqfp %0,%1,%2" 452117395Skan [(set_attr "type" "veccmp")]) 453117395Skan 454117395Skan(define_insn "altivec_vcmpgefp" 455117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 456117395Skan (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 457169689Skan (match_operand:V4SF 2 "register_operand" "v")] 458169689Skan UNSPEC_VCMPGEFP))] 459117395Skan "TARGET_ALTIVEC" 460117395Skan "vcmpgefp %0,%1,%2" 461117395Skan [(set_attr "type" "veccmp")]) 462117395Skan 463117395Skan(define_insn "altivec_vcmpgtub" 464117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 465117395Skan (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 466169689Skan (match_operand:V16QI 2 "register_operand" "v")] 467169689Skan UNSPEC_VCMPGTUB))] 468117395Skan "TARGET_ALTIVEC" 469117395Skan "vcmpgtub %0,%1,%2" 470117395Skan [(set_attr "type" "vecsimple")]) 471117395Skan 472117395Skan(define_insn "altivec_vcmpgtsb" 473117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 474117395Skan (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 475169689Skan (match_operand:V16QI 2 "register_operand" "v")] 476169689Skan UNSPEC_VCMPGTSB))] 477117395Skan "TARGET_ALTIVEC" 478117395Skan "vcmpgtsb %0,%1,%2" 479117395Skan [(set_attr "type" "vecsimple")]) 480117395Skan 481117395Skan(define_insn "altivec_vcmpgtuh" 482117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 483117395Skan (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 484169689Skan (match_operand:V8HI 2 "register_operand" "v")] 485169689Skan UNSPEC_VCMPGTUH))] 486117395Skan "TARGET_ALTIVEC" 487117395Skan "vcmpgtuh %0,%1,%2" 488117395Skan [(set_attr "type" "vecsimple")]) 489117395Skan 490117395Skan(define_insn "altivec_vcmpgtsh" 491117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 492117395Skan (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 493169689Skan (match_operand:V8HI 2 "register_operand" "v")] 494169689Skan UNSPEC_VCMPGTSH))] 495117395Skan "TARGET_ALTIVEC" 496117395Skan "vcmpgtsh %0,%1,%2" 497117395Skan [(set_attr "type" "vecsimple")]) 498117395Skan 499117395Skan(define_insn "altivec_vcmpgtuw" 500117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 501117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 502169689Skan (match_operand:V4SI 2 "register_operand" "v")] 503169689Skan UNSPEC_VCMPGTUW))] 504117395Skan "TARGET_ALTIVEC" 505117395Skan "vcmpgtuw %0,%1,%2" 506117395Skan [(set_attr "type" "vecsimple")]) 507117395Skan 508117395Skan(define_insn "altivec_vcmpgtsw" 509117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 510117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 511169689Skan (match_operand:V4SI 2 "register_operand" "v")] 512169689Skan UNSPEC_VCMPGTSW))] 513117395Skan "TARGET_ALTIVEC" 514117395Skan "vcmpgtsw %0,%1,%2" 515117395Skan [(set_attr "type" "vecsimple")]) 516117395Skan 517117395Skan(define_insn "altivec_vcmpgtfp" 518117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 519117395Skan (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 520169689Skan (match_operand:V4SF 2 "register_operand" "v")] 521169689Skan UNSPEC_VCMPGTFP))] 522117395Skan "TARGET_ALTIVEC" 523117395Skan "vcmpgtfp %0,%1,%2" 524117395Skan [(set_attr "type" "veccmp")]) 525117395Skan 526117395Skan;; Fused multiply add 527117395Skan(define_insn "altivec_vmaddfp" 528117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 529117395Skan (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") 530117395Skan (match_operand:V4SF 2 "register_operand" "v")) 531117395Skan (match_operand:V4SF 3 "register_operand" "v")))] 532117395Skan "TARGET_ALTIVEC" 533117395Skan "vmaddfp %0,%1,%2,%3" 534117395Skan [(set_attr "type" "vecfloat")]) 535117395Skan 536117395Skan;; We do multiply as a fused multiply-add with an add of a -0.0 vector. 537117395Skan 538117395Skan(define_expand "mulv4sf3" 539117395Skan [(use (match_operand:V4SF 0 "register_operand" "")) 540117395Skan (use (match_operand:V4SF 1 "register_operand" "")) 541117395Skan (use (match_operand:V4SF 2 "register_operand" ""))] 542117395Skan "TARGET_ALTIVEC && TARGET_FUSED_MADD" 543117395Skan " 544117395Skan{ 545117395Skan rtx neg0; 546117395Skan 547117395Skan /* Generate [-0.0, -0.0, -0.0, -0.0]. */ 548169689Skan neg0 = gen_reg_rtx (V4SImode); 549169689Skan emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx)); 550169689Skan emit_insn (gen_altivec_vslw (neg0, neg0, neg0)); 551117395Skan 552117395Skan /* Use the multiply-add. */ 553117395Skan emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2], 554169689Skan gen_lowpart (V4SFmode, neg0))); 555117395Skan DONE; 556117395Skan}") 557117395Skan 558169689Skan;; 32 bit integer multiplication 559169689Skan;; A_high = Operand_0 & 0xFFFF0000 >> 16 560169689Skan;; A_low = Operand_0 & 0xFFFF 561169689Skan;; B_high = Operand_1 & 0xFFFF0000 >> 16 562169689Skan;; B_low = Operand_1 & 0xFFFF 563169689Skan;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16 564169689Skan 565169689Skan;; (define_insn "mulv4si3" 566169689Skan;; [(set (match_operand:V4SI 0 "register_operand" "=v") 567169689Skan;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v") 568169689Skan;; (match_operand:V4SI 2 "register_operand" "v")))] 569169689Skan(define_expand "mulv4si3" 570169689Skan [(use (match_operand:V4SI 0 "register_operand" "")) 571169689Skan (use (match_operand:V4SI 1 "register_operand" "")) 572169689Skan (use (match_operand:V4SI 2 "register_operand" ""))] 573169689Skan "TARGET_ALTIVEC" 574169689Skan " 575169689Skan { 576169689Skan rtx zero; 577169689Skan rtx swap; 578169689Skan rtx small_swap; 579169689Skan rtx sixteen; 580169689Skan rtx one; 581169689Skan rtx two; 582169689Skan rtx low_product; 583169689Skan rtx high_product; 584169689Skan 585169689Skan zero = gen_reg_rtx (V4SImode); 586169689Skan emit_insn (gen_altivec_vspltisw (zero, const0_rtx)); 587169689Skan 588169689Skan sixteen = gen_reg_rtx (V4SImode); 589169689Skan emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16))); 590169689Skan 591169689Skan swap = gen_reg_rtx (V4SImode); 592169689Skan emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen)); 593169689Skan 594169689Skan one = gen_reg_rtx (V8HImode); 595169689Skan convert_move (one, operands[1], 0); 596169689Skan 597169689Skan two = gen_reg_rtx (V8HImode); 598169689Skan convert_move (two, operands[2], 0); 599169689Skan 600169689Skan small_swap = gen_reg_rtx (V8HImode); 601169689Skan convert_move (small_swap, swap, 0); 602169689Skan 603169689Skan low_product = gen_reg_rtx (V4SImode); 604169689Skan emit_insn (gen_altivec_vmulouh (low_product, one, two)); 605169689Skan 606169689Skan high_product = gen_reg_rtx (V4SImode); 607169689Skan emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero)); 608169689Skan 609169689Skan emit_insn (gen_altivec_vslw (high_product, high_product, sixteen)); 610169689Skan 611169689Skan emit_insn (gen_addv4si3 (operands[0], high_product, low_product)); 612169689Skan 613169689Skan DONE; 614169689Skan }") 615169689Skan 616169689Skan 617117395Skan;; Fused multiply subtract 618117395Skan(define_insn "altivec_vnmsubfp" 619117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 620146895Skan (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") 621117395Skan (match_operand:V4SF 2 "register_operand" "v")) 622146895Skan (match_operand:V4SF 3 "register_operand" "v"))))] 623117395Skan "TARGET_ALTIVEC" 624117395Skan "vnmsubfp %0,%1,%2,%3" 625117395Skan [(set_attr "type" "vecfloat")]) 626117395Skan 627169689Skan(define_insn "altivec_vmsumu<VI_char>m" 628117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 629169689Skan (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v") 630169689Skan (match_operand:VIshort 2 "register_operand" "v") 631169689Skan (match_operand:V4SI 3 "register_operand" "v")] 632169689Skan UNSPEC_VMSUMU))] 633117395Skan "TARGET_ALTIVEC" 634169689Skan "vmsumu<VI_char>m %0,%1,%2,%3" 635117395Skan [(set_attr "type" "veccomplex")]) 636117395Skan 637169689Skan(define_insn "altivec_vmsumm<VI_char>m" 638117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 639169689Skan (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v") 640169689Skan (match_operand:VIshort 2 "register_operand" "v") 641169689Skan (match_operand:V4SI 3 "register_operand" "v")] 642169689Skan UNSPEC_VMSUMM))] 643117395Skan "TARGET_ALTIVEC" 644169689Skan "vmsumm<VI_char>m %0,%1,%2,%3" 645117395Skan [(set_attr "type" "veccomplex")]) 646117395Skan 647117395Skan(define_insn "altivec_vmsumshm" 648117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 649117395Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 650117395Skan (match_operand:V8HI 2 "register_operand" "v") 651169689Skan (match_operand:V4SI 3 "register_operand" "v")] 652169689Skan UNSPEC_VMSUMSHM))] 653117395Skan "TARGET_ALTIVEC" 654132718Skan "vmsumshm %0,%1,%2,%3" 655117395Skan [(set_attr "type" "veccomplex")]) 656117395Skan 657117395Skan(define_insn "altivec_vmsumuhs" 658117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 659117395Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 660117395Skan (match_operand:V8HI 2 "register_operand" "v") 661169689Skan (match_operand:V4SI 3 "register_operand" "v")] 662169689Skan UNSPEC_VMSUMUHS)) 663169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 664117395Skan "TARGET_ALTIVEC" 665132718Skan "vmsumuhs %0,%1,%2,%3" 666117395Skan [(set_attr "type" "veccomplex")]) 667117395Skan 668117395Skan(define_insn "altivec_vmsumshs" 669117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 670117395Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 671117395Skan (match_operand:V8HI 2 "register_operand" "v") 672169689Skan (match_operand:V4SI 3 "register_operand" "v")] 673169689Skan UNSPEC_VMSUMSHS)) 674169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 675117395Skan "TARGET_ALTIVEC" 676132718Skan "vmsumshs %0,%1,%2,%3" 677117395Skan [(set_attr "type" "veccomplex")]) 678117395Skan 679169689Skan;; max 680117395Skan 681169689Skan(define_insn "umax<mode>3" 682169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 683169689Skan (umax:VI (match_operand:VI 1 "register_operand" "v") 684169689Skan (match_operand:VI 2 "register_operand" "v")))] 685117395Skan "TARGET_ALTIVEC" 686169689Skan "vmaxu<VI_char> %0,%1,%2" 687117395Skan [(set_attr "type" "vecsimple")]) 688117395Skan 689169689Skan(define_insn "smax<mode>3" 690169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 691169689Skan (smax:VI (match_operand:VI 1 "register_operand" "v") 692169689Skan (match_operand:VI 2 "register_operand" "v")))] 693117395Skan "TARGET_ALTIVEC" 694169689Skan "vmaxs<VI_char> %0,%1,%2" 695117395Skan [(set_attr "type" "vecsimple")]) 696117395Skan 697169689Skan(define_insn "smaxv4sf3" 698169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 699169689Skan (smax:V4SF (match_operand:V4SF 1 "register_operand" "v") 700169689Skan (match_operand:V4SF 2 "register_operand" "v")))] 701117395Skan "TARGET_ALTIVEC" 702169689Skan "vmaxfp %0,%1,%2" 703169689Skan [(set_attr "type" "veccmp")]) 704117395Skan 705169689Skan(define_insn "umin<mode>3" 706169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 707169689Skan (umin:VI (match_operand:VI 1 "register_operand" "v") 708169689Skan (match_operand:VI 2 "register_operand" "v")))] 709117395Skan "TARGET_ALTIVEC" 710169689Skan "vminu<VI_char> %0,%1,%2" 711117395Skan [(set_attr "type" "vecsimple")]) 712117395Skan 713169689Skan(define_insn "smin<mode>3" 714169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 715169689Skan (smin:VI (match_operand:VI 1 "register_operand" "v") 716169689Skan (match_operand:VI 2 "register_operand" "v")))] 717117395Skan "TARGET_ALTIVEC" 718169689Skan "vmins<VI_char> %0,%1,%2" 719117395Skan [(set_attr "type" "vecsimple")]) 720117395Skan 721169689Skan(define_insn "sminv4sf3" 722117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 723169689Skan (smin:V4SF (match_operand:V4SF 1 "register_operand" "v") 724117395Skan (match_operand:V4SF 2 "register_operand" "v")))] 725117395Skan "TARGET_ALTIVEC" 726169689Skan "vminfp %0,%1,%2" 727117395Skan [(set_attr "type" "veccmp")]) 728117395Skan 729117395Skan(define_insn "altivec_vmhaddshs" 730117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 731117395Skan (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 732117395Skan (match_operand:V8HI 2 "register_operand" "v") 733169689Skan (match_operand:V8HI 3 "register_operand" "v")] 734169689Skan UNSPEC_VMHADDSHS)) 735169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 736117395Skan "TARGET_ALTIVEC" 737132718Skan "vmhaddshs %0,%1,%2,%3" 738117395Skan [(set_attr "type" "veccomplex")]) 739169689Skan 740117395Skan(define_insn "altivec_vmhraddshs" 741117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 742117395Skan (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 743117395Skan (match_operand:V8HI 2 "register_operand" "v") 744169689Skan (match_operand:V8HI 3 "register_operand" "v")] 745169689Skan UNSPEC_VMHRADDSHS)) 746169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 747117395Skan "TARGET_ALTIVEC" 748132718Skan "vmhraddshs %0,%1,%2,%3" 749117395Skan [(set_attr "type" "veccomplex")]) 750169689Skan 751117395Skan(define_insn "altivec_vmladduhm" 752117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 753117395Skan (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 754117395Skan (match_operand:V8HI 2 "register_operand" "v") 755169689Skan (match_operand:V8HI 3 "register_operand" "v")] 756169689Skan UNSPEC_VMLADDUHM))] 757117395Skan "TARGET_ALTIVEC" 758132718Skan "vmladduhm %0,%1,%2,%3" 759117395Skan [(set_attr "type" "veccomplex")]) 760117395Skan 761117395Skan(define_insn "altivec_vmrghb" 762117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 763117395Skan (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v") 764169689Skan (parallel [(const_int 0) 765169689Skan (const_int 8) 766169689Skan (const_int 1) 767117395Skan (const_int 9) 768169689Skan (const_int 2) 769117395Skan (const_int 10) 770169689Skan (const_int 3) 771169689Skan (const_int 11) 772169689Skan (const_int 4) 773117395Skan (const_int 12) 774169689Skan (const_int 5) 775117395Skan (const_int 13) 776169689Skan (const_int 6) 777169689Skan (const_int 14) 778169689Skan (const_int 7) 779169689Skan (const_int 15)])) 780169689Skan (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v") 781169689Skan (parallel [(const_int 8) 782117395Skan (const_int 0) 783169689Skan (const_int 9) 784117395Skan (const_int 1) 785169689Skan (const_int 10) 786117395Skan (const_int 2) 787169689Skan (const_int 11) 788169689Skan (const_int 3) 789169689Skan (const_int 12) 790117395Skan (const_int 4) 791169689Skan (const_int 13) 792117395Skan (const_int 5) 793169689Skan (const_int 14) 794117395Skan (const_int 6) 795169689Skan (const_int 15) 796117395Skan (const_int 7)])) 797169689Skan (const_int 21845)))] 798117395Skan "TARGET_ALTIVEC" 799117395Skan "vmrghb %0,%1,%2" 800117395Skan [(set_attr "type" "vecperm")]) 801117395Skan 802117395Skan(define_insn "altivec_vmrghh" 803117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 804117395Skan (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v") 805169689Skan (parallel [(const_int 0) 806169689Skan (const_int 4) 807169689Skan (const_int 1) 808117395Skan (const_int 5) 809169689Skan (const_int 2) 810117395Skan (const_int 6) 811169689Skan (const_int 3) 812169689Skan (const_int 7)])) 813169689Skan (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v") 814169689Skan (parallel [(const_int 4) 815117395Skan (const_int 0) 816169689Skan (const_int 5) 817117395Skan (const_int 1) 818169689Skan (const_int 6) 819117395Skan (const_int 2) 820169689Skan (const_int 7) 821117395Skan (const_int 3)])) 822169689Skan (const_int 85)))] 823117395Skan "TARGET_ALTIVEC" 824117395Skan "vmrghh %0,%1,%2" 825117395Skan [(set_attr "type" "vecperm")]) 826117395Skan 827117395Skan(define_insn "altivec_vmrghw" 828117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 829117395Skan (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v") 830169689Skan (parallel [(const_int 0) 831169689Skan (const_int 2) 832169689Skan (const_int 1) 833169689Skan (const_int 3)])) 834169689Skan (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v") 835117395Skan (parallel [(const_int 2) 836169689Skan (const_int 0) 837169689Skan (const_int 3) 838117395Skan (const_int 1)])) 839169689Skan (const_int 5)))] 840117395Skan "TARGET_ALTIVEC" 841117395Skan "vmrghw %0,%1,%2" 842117395Skan [(set_attr "type" "vecperm")]) 843117395Skan 844117395Skan(define_insn "altivec_vmrglb" 845117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 846169689Skan (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v") 847169689Skan (parallel [(const_int 8) 848169689Skan (const_int 0) 849169689Skan (const_int 9) 850117395Skan (const_int 1) 851169689Skan (const_int 10) 852117395Skan (const_int 2) 853169689Skan (const_int 11) 854169689Skan (const_int 3) 855169689Skan (const_int 12) 856117395Skan (const_int 4) 857169689Skan (const_int 13) 858117395Skan (const_int 5) 859169689Skan (const_int 14) 860169689Skan (const_int 6) 861169689Skan (const_int 15) 862169689Skan (const_int 7)])) 863169689Skan (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v") 864169689Skan (parallel [(const_int 0) 865117395Skan (const_int 8) 866169689Skan (const_int 1) 867117395Skan (const_int 9) 868169689Skan (const_int 2) 869117395Skan (const_int 10) 870169689Skan (const_int 3) 871169689Skan (const_int 11) 872169689Skan (const_int 4) 873117395Skan (const_int 12) 874169689Skan (const_int 5) 875117395Skan (const_int 13) 876169689Skan (const_int 6) 877117395Skan (const_int 14) 878169689Skan (const_int 7) 879117395Skan (const_int 15)])) 880169689Skan (const_int 21845)))] 881117395Skan "TARGET_ALTIVEC" 882117395Skan "vmrglb %0,%1,%2" 883117395Skan [(set_attr "type" "vecperm")]) 884117395Skan 885117395Skan(define_insn "altivec_vmrglh" 886117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 887169689Skan (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v") 888169689Skan (parallel [(const_int 4) 889169689Skan (const_int 0) 890169689Skan (const_int 5) 891117395Skan (const_int 1) 892169689Skan (const_int 6) 893117395Skan (const_int 2) 894169689Skan (const_int 7) 895169689Skan (const_int 3)])) 896169689Skan (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v") 897169689Skan (parallel [(const_int 0) 898117395Skan (const_int 4) 899169689Skan (const_int 1) 900117395Skan (const_int 5) 901169689Skan (const_int 2) 902117395Skan (const_int 6) 903169689Skan (const_int 3) 904117395Skan (const_int 7)])) 905169689Skan (const_int 85)))] 906117395Skan "TARGET_ALTIVEC" 907117395Skan "vmrglh %0,%1,%2" 908117395Skan [(set_attr "type" "vecperm")]) 909117395Skan 910117395Skan(define_insn "altivec_vmrglw" 911117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 912169689Skan (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v") 913169689Skan (parallel [(const_int 2) 914169689Skan (const_int 0) 915169689Skan (const_int 3) 916169689Skan (const_int 1)])) 917169689Skan (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v") 918117395Skan (parallel [(const_int 0) 919169689Skan (const_int 2) 920169689Skan (const_int 1) 921117395Skan (const_int 3)])) 922169689Skan (const_int 5)))] 923117395Skan "TARGET_ALTIVEC" 924117395Skan "vmrglw %0,%1,%2" 925117395Skan [(set_attr "type" "vecperm")]) 926117395Skan 927117395Skan(define_insn "altivec_vmuleub" 928117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 929117395Skan (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 930169689Skan (match_operand:V16QI 2 "register_operand" "v")] 931169689Skan UNSPEC_VMULEUB))] 932117395Skan "TARGET_ALTIVEC" 933117395Skan "vmuleub %0,%1,%2" 934117395Skan [(set_attr "type" "veccomplex")]) 935117395Skan 936117395Skan(define_insn "altivec_vmulesb" 937117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 938117395Skan (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 939169689Skan (match_operand:V16QI 2 "register_operand" "v")] 940169689Skan UNSPEC_VMULESB))] 941117395Skan "TARGET_ALTIVEC" 942117395Skan "vmulesb %0,%1,%2" 943117395Skan [(set_attr "type" "veccomplex")]) 944117395Skan 945117395Skan(define_insn "altivec_vmuleuh" 946117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 947117395Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 948169689Skan (match_operand:V8HI 2 "register_operand" "v")] 949169689Skan UNSPEC_VMULEUH))] 950117395Skan "TARGET_ALTIVEC" 951117395Skan "vmuleuh %0,%1,%2" 952117395Skan [(set_attr "type" "veccomplex")]) 953117395Skan 954117395Skan(define_insn "altivec_vmulesh" 955117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 956117395Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 957169689Skan (match_operand:V8HI 2 "register_operand" "v")] 958169689Skan UNSPEC_VMULESH))] 959117395Skan "TARGET_ALTIVEC" 960117395Skan "vmulesh %0,%1,%2" 961117395Skan [(set_attr "type" "veccomplex")]) 962117395Skan 963117395Skan(define_insn "altivec_vmuloub" 964117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 965117395Skan (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 966169689Skan (match_operand:V16QI 2 "register_operand" "v")] 967169689Skan UNSPEC_VMULOUB))] 968117395Skan "TARGET_ALTIVEC" 969117395Skan "vmuloub %0,%1,%2" 970117395Skan [(set_attr "type" "veccomplex")]) 971117395Skan 972117395Skan(define_insn "altivec_vmulosb" 973117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 974117395Skan (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 975169689Skan (match_operand:V16QI 2 "register_operand" "v")] 976169689Skan UNSPEC_VMULOSB))] 977117395Skan "TARGET_ALTIVEC" 978117395Skan "vmulosb %0,%1,%2" 979117395Skan [(set_attr "type" "veccomplex")]) 980117395Skan 981117395Skan(define_insn "altivec_vmulouh" 982117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 983117395Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 984169689Skan (match_operand:V8HI 2 "register_operand" "v")] 985169689Skan UNSPEC_VMULOUH))] 986117395Skan "TARGET_ALTIVEC" 987117395Skan "vmulouh %0,%1,%2" 988117395Skan [(set_attr "type" "veccomplex")]) 989117395Skan 990117395Skan(define_insn "altivec_vmulosh" 991117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 992117395Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 993169689Skan (match_operand:V8HI 2 "register_operand" "v")] 994169689Skan UNSPEC_VMULOSH))] 995117395Skan "TARGET_ALTIVEC" 996117395Skan "vmulosh %0,%1,%2" 997117395Skan [(set_attr "type" "veccomplex")]) 998117395Skan 999169689Skan 1000169689Skan;; logical ops 1001169689Skan 1002169689Skan(define_insn "and<mode>3" 1003169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1004169689Skan (and:VI (match_operand:VI 1 "register_operand" "v") 1005169689Skan (match_operand:VI 2 "register_operand" "v")))] 1006117395Skan "TARGET_ALTIVEC" 1007169689Skan "vand %0,%1,%2" 1008117395Skan [(set_attr "type" "vecsimple")]) 1009117395Skan 1010169689Skan(define_insn "ior<mode>3" 1011169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1012169689Skan (ior:VI (match_operand:VI 1 "register_operand" "v") 1013169689Skan (match_operand:VI 2 "register_operand" "v")))] 1014117395Skan "TARGET_ALTIVEC" 1015117395Skan "vor %0,%1,%2" 1016117395Skan [(set_attr "type" "vecsimple")]) 1017117395Skan 1018169689Skan(define_insn "xor<mode>3" 1019169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1020169689Skan (xor:VI (match_operand:VI 1 "register_operand" "v") 1021169689Skan (match_operand:VI 2 "register_operand" "v")))] 1022169689Skan "TARGET_ALTIVEC" 1023169689Skan "vxor %0,%1,%2" 1024169689Skan [(set_attr "type" "vecsimple")]) 1025169689Skan 1026169689Skan(define_insn "xorv4sf3" 1027169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1028169689Skan (xor:V4SF (match_operand:V4SF 1 "register_operand" "v") 1029169689Skan (match_operand:V4SF 2 "register_operand" "v")))] 1030169689Skan "TARGET_ALTIVEC" 1031169689Skan "vxor %0,%1,%2" 1032169689Skan [(set_attr "type" "vecsimple")]) 1033169689Skan 1034169689Skan(define_insn "one_cmpl<mode>2" 1035169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1036169689Skan (not:VI (match_operand:VI 1 "register_operand" "v")))] 1037169689Skan "TARGET_ALTIVEC" 1038169689Skan "vnor %0,%1,%1" 1039169689Skan [(set_attr "type" "vecsimple")]) 1040169689Skan 1041169689Skan(define_insn "altivec_nor<mode>3" 1042169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1043169689Skan (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v") 1044169689Skan (match_operand:VI 2 "register_operand" "v"))))] 1045169689Skan "TARGET_ALTIVEC" 1046169689Skan "vnor %0,%1,%2" 1047169689Skan [(set_attr "type" "vecsimple")]) 1048169689Skan 1049169689Skan(define_insn "andc<mode>3" 1050169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1051169689Skan (and:VI (not:VI (match_operand:VI 2 "register_operand" "v")) 1052169689Skan (match_operand:VI 1 "register_operand" "v")))] 1053169689Skan "TARGET_ALTIVEC" 1054169689Skan "vandc %0,%1,%2" 1055169689Skan [(set_attr "type" "vecsimple")]) 1056169689Skan 1057169689Skan(define_insn "*andc3_v4sf" 1058169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1059169689Skan (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v")) 1060169689Skan (match_operand:V4SF 1 "register_operand" "v")))] 1061169689Skan "TARGET_ALTIVEC" 1062169689Skan "vandc %0,%1,%2" 1063169689Skan [(set_attr "type" "vecsimple")]) 1064169689Skan 1065117395Skan(define_insn "altivec_vpkuhum" 1066117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 1067117395Skan (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 1068169689Skan (match_operand:V8HI 2 "register_operand" "v")] 1069169689Skan UNSPEC_VPKUHUM))] 1070117395Skan "TARGET_ALTIVEC" 1071117395Skan "vpkuhum %0,%1,%2" 1072117395Skan [(set_attr "type" "vecperm")]) 1073117395Skan 1074117395Skan(define_insn "altivec_vpkuwum" 1075117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1076117395Skan (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 1077169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1078169689Skan UNSPEC_VPKUWUM))] 1079117395Skan "TARGET_ALTIVEC" 1080117395Skan "vpkuwum %0,%1,%2" 1081117395Skan [(set_attr "type" "vecperm")]) 1082117395Skan 1083117395Skan(define_insn "altivec_vpkpx" 1084117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1085117395Skan (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 1086169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1087169689Skan UNSPEC_VPKPX))] 1088117395Skan "TARGET_ALTIVEC" 1089117395Skan "vpkpx %0,%1,%2" 1090117395Skan [(set_attr "type" "vecperm")]) 1091117395Skan 1092117395Skan(define_insn "altivec_vpkshss" 1093117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 1094117395Skan (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 1095169689Skan (match_operand:V8HI 2 "register_operand" "v")] 1096169689Skan UNSPEC_VPKSHSS)) 1097169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1098117395Skan "TARGET_ALTIVEC" 1099117395Skan "vpkshss %0,%1,%2" 1100117395Skan [(set_attr "type" "vecperm")]) 1101117395Skan 1102117395Skan(define_insn "altivec_vpkswss" 1103117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1104117395Skan (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 1105169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1106169689Skan UNSPEC_VPKSWSS)) 1107169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1108117395Skan "TARGET_ALTIVEC" 1109117395Skan "vpkswss %0,%1,%2" 1110117395Skan [(set_attr "type" "vecperm")]) 1111117395Skan 1112117395Skan(define_insn "altivec_vpkuhus" 1113117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 1114117395Skan (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 1115169689Skan (match_operand:V8HI 2 "register_operand" "v")] 1116169689Skan UNSPEC_VPKUHUS)) 1117169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1118117395Skan "TARGET_ALTIVEC" 1119117395Skan "vpkuhus %0,%1,%2" 1120117395Skan [(set_attr "type" "vecperm")]) 1121117395Skan 1122117395Skan(define_insn "altivec_vpkshus" 1123117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 1124117395Skan (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 1125169689Skan (match_operand:V8HI 2 "register_operand" "v")] 1126169689Skan UNSPEC_VPKSHUS)) 1127169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1128117395Skan "TARGET_ALTIVEC" 1129117395Skan "vpkshus %0,%1,%2" 1130117395Skan [(set_attr "type" "vecperm")]) 1131117395Skan 1132117395Skan(define_insn "altivec_vpkuwus" 1133117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1134117395Skan (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 1135169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1136169689Skan UNSPEC_VPKUWUS)) 1137169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1138117395Skan "TARGET_ALTIVEC" 1139117395Skan "vpkuwus %0,%1,%2" 1140117395Skan [(set_attr "type" "vecperm")]) 1141117395Skan 1142117395Skan(define_insn "altivec_vpkswus" 1143117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1144117395Skan (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 1145169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1146169689Skan UNSPEC_VPKSWUS)) 1147169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1148117395Skan "TARGET_ALTIVEC" 1149117395Skan "vpkswus %0,%1,%2" 1150117395Skan [(set_attr "type" "vecperm")]) 1151117395Skan 1152169689Skan(define_insn "altivec_vrl<VI_char>" 1153169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1154169689Skan (unspec:VI [(match_operand:VI 1 "register_operand" "v") 1155169689Skan (match_operand:VI 2 "register_operand" "v")] 1156169689Skan UNSPEC_VRL))] 1157117395Skan "TARGET_ALTIVEC" 1158169689Skan "vrl<VI_char> %0,%1,%2" 1159117395Skan [(set_attr "type" "vecsimple")]) 1160117395Skan 1161169689Skan(define_insn "altivec_vsl<VI_char>" 1162169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1163169689Skan (unspec:VI [(match_operand:VI 1 "register_operand" "v") 1164169689Skan (match_operand:VI 2 "register_operand" "v")] 1165169689Skan UNSPEC_VSL))] 1166117395Skan "TARGET_ALTIVEC" 1167169689Skan "vsl<VI_char> %0,%1,%2" 1168117395Skan [(set_attr "type" "vecsimple")]) 1169117395Skan 1170117395Skan(define_insn "altivec_vsl" 1171117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1172117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1173169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1174169689Skan UNSPEC_VSLV4SI))] 1175117395Skan "TARGET_ALTIVEC" 1176117395Skan "vsl %0,%1,%2" 1177117395Skan [(set_attr "type" "vecperm")]) 1178117395Skan 1179117395Skan(define_insn "altivec_vslo" 1180117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1181117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1182169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1183169689Skan UNSPEC_VSLO))] 1184117395Skan "TARGET_ALTIVEC" 1185117395Skan "vslo %0,%1,%2" 1186117395Skan [(set_attr "type" "vecperm")]) 1187117395Skan 1188169689Skan(define_insn "lshr<mode>3" 1189169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1190169689Skan (lshiftrt:VI (match_operand:VI 1 "register_operand" "v") 1191169689Skan (match_operand:VI 2 "register_operand" "v") ))] 1192117395Skan "TARGET_ALTIVEC" 1193169689Skan "vsr<VI_char> %0,%1,%2" 1194117395Skan [(set_attr "type" "vecsimple")]) 1195117395Skan 1196169689Skan(define_insn "ashr<mode>3" 1197169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1198169689Skan (ashiftrt:VI (match_operand:VI 1 "register_operand" "v") 1199169689Skan (match_operand:VI 2 "register_operand" "v") ))] 1200117395Skan "TARGET_ALTIVEC" 1201169689Skan "vsra<VI_char> %0,%1,%2" 1202117395Skan [(set_attr "type" "vecsimple")]) 1203117395Skan 1204117395Skan(define_insn "altivec_vsr" 1205117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1206117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1207169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1208169689Skan UNSPEC_VSR))] 1209117395Skan "TARGET_ALTIVEC" 1210117395Skan "vsr %0,%1,%2" 1211117395Skan [(set_attr "type" "vecperm")]) 1212117395Skan 1213117395Skan(define_insn "altivec_vsro" 1214117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1215117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1216169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1217169689Skan UNSPEC_VSRO))] 1218117395Skan "TARGET_ALTIVEC" 1219117395Skan "vsro %0,%1,%2" 1220117395Skan [(set_attr "type" "vecperm")]) 1221117395Skan 1222117395Skan(define_insn "altivec_vsum4ubs" 1223117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1224117395Skan (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 1225169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1226169689Skan UNSPEC_VSUM4UBS)) 1227169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1228117395Skan "TARGET_ALTIVEC" 1229117395Skan "vsum4ubs %0,%1,%2" 1230117395Skan [(set_attr "type" "veccomplex")]) 1231117395Skan 1232169689Skan(define_insn "altivec_vsum4s<VI_char>s" 1233117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1234169689Skan (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v") 1235169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1236169689Skan UNSPEC_VSUM4S)) 1237169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1238117395Skan "TARGET_ALTIVEC" 1239169689Skan "vsum4s<VI_char>s %0,%1,%2" 1240117395Skan [(set_attr "type" "veccomplex")]) 1241117395Skan 1242117395Skan(define_insn "altivec_vsum2sws" 1243117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1244117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1245169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1246169689Skan UNSPEC_VSUM2SWS)) 1247169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1248117395Skan "TARGET_ALTIVEC" 1249117395Skan "vsum2sws %0,%1,%2" 1250117395Skan [(set_attr "type" "veccomplex")]) 1251117395Skan 1252117395Skan(define_insn "altivec_vsumsws" 1253117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1254117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1255169689Skan (match_operand:V4SI 2 "register_operand" "v")] 1256169689Skan UNSPEC_VSUMSWS)) 1257169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1258117395Skan "TARGET_ALTIVEC" 1259117395Skan "vsumsws %0,%1,%2" 1260117395Skan [(set_attr "type" "veccomplex")]) 1261117395Skan 1262117395Skan(define_insn "altivec_vspltb" 1263117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 1264169689Skan (vec_duplicate:V16QI 1265169689Skan (vec_select:QI (match_operand:V16QI 1 "register_operand" "v") 1266169689Skan (parallel 1267169689Skan [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] 1268117395Skan "TARGET_ALTIVEC" 1269117395Skan "vspltb %0,%1,%2" 1270117395Skan [(set_attr "type" "vecperm")]) 1271117395Skan 1272117395Skan(define_insn "altivec_vsplth" 1273117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1274169689Skan (vec_duplicate:V8HI 1275169689Skan (vec_select:HI (match_operand:V8HI 1 "register_operand" "v") 1276169689Skan (parallel 1277169689Skan [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] 1278117395Skan "TARGET_ALTIVEC" 1279117395Skan "vsplth %0,%1,%2" 1280117395Skan [(set_attr "type" "vecperm")]) 1281117395Skan 1282117395Skan(define_insn "altivec_vspltw" 1283117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1284169689Skan (vec_duplicate:V4SI 1285169689Skan (vec_select:SI (match_operand:V4SI 1 "register_operand" "v") 1286169689Skan (parallel 1287169689Skan [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] 1288117395Skan "TARGET_ALTIVEC" 1289117395Skan "vspltw %0,%1,%2" 1290117395Skan [(set_attr "type" "vecperm")]) 1291117395Skan 1292169689Skan(define_insn "*altivec_vspltsf" 1293169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1294169689Skan (vec_duplicate:V4SF 1295169689Skan (vec_select:SF (match_operand:V4SF 1 "register_operand" "v") 1296169689Skan (parallel 1297169689Skan [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] 1298117395Skan "TARGET_ALTIVEC" 1299169689Skan "vspltw %0,%1,%2" 1300132718Skan [(set_attr "type" "vecperm")]) 1301117395Skan 1302169689Skan(define_insn "altivec_vspltis<VI_char>" 1303169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1304169689Skan (vec_duplicate:VI 1305169689Skan (match_operand:QI 1 "s5bit_cint_operand" "i")))] 1306117395Skan "TARGET_ALTIVEC" 1307169689Skan "vspltis<VI_char> %0,%1" 1308132718Skan [(set_attr "type" "vecperm")]) 1309117395Skan 1310117395Skan(define_insn "ftruncv4sf2" 1311117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1312117395Skan (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] 1313117395Skan "TARGET_ALTIVEC" 1314132718Skan "vrfiz %0,%1" 1315117395Skan [(set_attr "type" "vecfloat")]) 1316117395Skan 1317169689Skan(define_insn "altivec_vperm_<mode>" 1318169689Skan [(set (match_operand:V 0 "register_operand" "=v") 1319169689Skan (unspec:V [(match_operand:V 1 "register_operand" "v") 1320169689Skan (match_operand:V 2 "register_operand" "v") 1321169689Skan (match_operand:V16QI 3 "register_operand" "v")] 1322169689Skan UNSPEC_VPERM))] 1323117395Skan "TARGET_ALTIVEC" 1324117395Skan "vperm %0,%1,%2,%3" 1325117395Skan [(set_attr "type" "vecperm")]) 1326117395Skan 1327117395Skan(define_insn "altivec_vrfip" 1328117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1329169689Skan (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 1330169689Skan UNSPEC_VRFIP))] 1331117395Skan "TARGET_ALTIVEC" 1332132718Skan "vrfip %0,%1" 1333117395Skan [(set_attr "type" "vecfloat")]) 1334117395Skan 1335117395Skan(define_insn "altivec_vrfin" 1336117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1337169689Skan (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 1338169689Skan UNSPEC_VRFIN))] 1339117395Skan "TARGET_ALTIVEC" 1340132718Skan "vrfin %0,%1" 1341117395Skan [(set_attr "type" "vecfloat")]) 1342117395Skan 1343117395Skan(define_insn "altivec_vrfim" 1344117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1345169689Skan (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 1346169689Skan UNSPEC_VRFIM))] 1347117395Skan "TARGET_ALTIVEC" 1348132718Skan "vrfim %0,%1" 1349117395Skan [(set_attr "type" "vecfloat")]) 1350117395Skan 1351117395Skan(define_insn "altivec_vcfux" 1352117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1353117395Skan (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") 1354169689Skan (match_operand:QI 2 "immediate_operand" "i")] 1355169689Skan UNSPEC_VCFUX))] 1356117395Skan "TARGET_ALTIVEC" 1357132718Skan "vcfux %0,%1,%2" 1358117395Skan [(set_attr "type" "vecfloat")]) 1359117395Skan 1360117395Skan(define_insn "altivec_vcfsx" 1361117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1362117395Skan (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") 1363169689Skan (match_operand:QI 2 "immediate_operand" "i")] 1364169689Skan UNSPEC_VCFSX))] 1365117395Skan "TARGET_ALTIVEC" 1366132718Skan "vcfsx %0,%1,%2" 1367117395Skan [(set_attr "type" "vecfloat")]) 1368117395Skan 1369117395Skan(define_insn "altivec_vctuxs" 1370117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1371117395Skan (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 1372169689Skan (match_operand:QI 2 "immediate_operand" "i")] 1373169689Skan UNSPEC_VCTUXS)) 1374169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1375117395Skan "TARGET_ALTIVEC" 1376132718Skan "vctuxs %0,%1,%2" 1377117395Skan [(set_attr "type" "vecfloat")]) 1378117395Skan 1379117395Skan(define_insn "altivec_vctsxs" 1380117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1381117395Skan (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 1382169689Skan (match_operand:QI 2 "immediate_operand" "i")] 1383169689Skan UNSPEC_VCTSXS)) 1384169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 1385117395Skan "TARGET_ALTIVEC" 1386132718Skan "vctsxs %0,%1,%2" 1387117395Skan [(set_attr "type" "vecfloat")]) 1388117395Skan 1389117395Skan(define_insn "altivec_vlogefp" 1390117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1391169689Skan (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 1392169689Skan UNSPEC_VLOGEFP))] 1393117395Skan "TARGET_ALTIVEC" 1394132718Skan "vlogefp %0,%1" 1395117395Skan [(set_attr "type" "vecfloat")]) 1396117395Skan 1397117395Skan(define_insn "altivec_vexptefp" 1398117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1399169689Skan (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 1400169689Skan UNSPEC_VEXPTEFP))] 1401117395Skan "TARGET_ALTIVEC" 1402132718Skan "vexptefp %0,%1" 1403117395Skan [(set_attr "type" "vecfloat")]) 1404117395Skan 1405117395Skan(define_insn "altivec_vrsqrtefp" 1406117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1407169689Skan (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 1408169689Skan UNSPEC_VRSQRTEFP))] 1409117395Skan "TARGET_ALTIVEC" 1410132718Skan "vrsqrtefp %0,%1" 1411117395Skan [(set_attr "type" "vecfloat")]) 1412117395Skan 1413117395Skan(define_insn "altivec_vrefp" 1414117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1415169689Skan (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 1416169689Skan UNSPEC_VREFP))] 1417117395Skan "TARGET_ALTIVEC" 1418132718Skan "vrefp %0,%1" 1419117395Skan [(set_attr "type" "vecfloat")]) 1420117395Skan 1421169689Skan(define_expand "vcondv4si" 1422169689Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1423169689Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1424169689Skan (match_operand:V4SI 2 "register_operand" "v") 1425169689Skan (match_operand:V4SI 3 "comparison_operator" "") 1426169689Skan (match_operand:V4SI 4 "register_operand" "v") 1427169689Skan (match_operand:V4SI 5 "register_operand" "v") 1428169689Skan ] UNSPEC_VCOND_V4SI))] 1429169689Skan "TARGET_ALTIVEC" 1430169689Skan " 1431169689Skan{ 1432169689Skan if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], 1433169689Skan operands[3], operands[4], operands[5])) 1434169689Skan DONE; 1435169689Skan else 1436169689Skan FAIL; 1437169689Skan} 1438169689Skan ") 1439169689Skan 1440169689Skan(define_expand "vconduv4si" 1441169689Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1442169689Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1443169689Skan (match_operand:V4SI 2 "register_operand" "v") 1444169689Skan (match_operand:V4SI 3 "comparison_operator" "") 1445169689Skan (match_operand:V4SI 4 "register_operand" "v") 1446169689Skan (match_operand:V4SI 5 "register_operand" "v") 1447169689Skan ] UNSPEC_VCONDU_V4SI))] 1448169689Skan "TARGET_ALTIVEC" 1449169689Skan " 1450169689Skan{ 1451169689Skan if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], 1452169689Skan operands[3], operands[4], operands[5])) 1453169689Skan DONE; 1454169689Skan else 1455169689Skan FAIL; 1456169689Skan} 1457169689Skan ") 1458169689Skan 1459169689Skan(define_expand "vcondv4sf" 1460169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1461169689Skan (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") 1462169689Skan (match_operand:V4SF 2 "register_operand" "v") 1463169689Skan (match_operand:V4SF 3 "comparison_operator" "") 1464169689Skan (match_operand:V4SF 4 "register_operand" "v") 1465169689Skan (match_operand:V4SF 5 "register_operand" "v") 1466169689Skan ] UNSPEC_VCOND_V4SF))] 1467169689Skan "TARGET_ALTIVEC" 1468169689Skan " 1469169689Skan{ 1470169689Skan if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], 1471169689Skan operands[3], operands[4], operands[5])) 1472169689Skan DONE; 1473169689Skan else 1474169689Skan FAIL; 1475169689Skan} 1476169689Skan ") 1477169689Skan 1478169689Skan(define_expand "vcondv8hi" 1479169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1480169689Skan (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 1481169689Skan (match_operand:V8HI 2 "register_operand" "v") 1482169689Skan (match_operand:V8HI 3 "comparison_operator" "") 1483169689Skan (match_operand:V8HI 4 "register_operand" "v") 1484169689Skan (match_operand:V8HI 5 "register_operand" "v") 1485169689Skan ] UNSPEC_VCOND_V8HI))] 1486169689Skan "TARGET_ALTIVEC" 1487169689Skan " 1488169689Skan{ 1489169689Skan if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], 1490169689Skan operands[3], operands[4], operands[5])) 1491169689Skan DONE; 1492169689Skan else 1493169689Skan FAIL; 1494169689Skan} 1495169689Skan ") 1496169689Skan 1497169689Skan(define_expand "vconduv8hi" 1498169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1499169689Skan (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 1500169689Skan (match_operand:V8HI 2 "register_operand" "v") 1501169689Skan (match_operand:V8HI 3 "comparison_operator" "") 1502169689Skan (match_operand:V8HI 4 "register_operand" "v") 1503169689Skan (match_operand:V8HI 5 "register_operand" "v") 1504169689Skan ] UNSPEC_VCONDU_V8HI))] 1505169689Skan "TARGET_ALTIVEC" 1506169689Skan " 1507169689Skan{ 1508169689Skan if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], 1509169689Skan operands[3], operands[4], operands[5])) 1510169689Skan DONE; 1511169689Skan else 1512169689Skan FAIL; 1513169689Skan} 1514169689Skan ") 1515169689Skan 1516169689Skan(define_expand "vcondv16qi" 1517169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1518169689Skan (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v") 1519169689Skan (match_operand:V16QI 2 "register_operand" "v") 1520169689Skan (match_operand:V16QI 3 "comparison_operator" "") 1521169689Skan (match_operand:V16QI 4 "register_operand" "v") 1522169689Skan (match_operand:V16QI 5 "register_operand" "v") 1523169689Skan ] UNSPEC_VCOND_V16QI))] 1524169689Skan "TARGET_ALTIVEC" 1525169689Skan " 1526169689Skan{ 1527169689Skan if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], 1528169689Skan operands[3], operands[4], operands[5])) 1529169689Skan DONE; 1530169689Skan else 1531169689Skan FAIL; 1532169689Skan} 1533169689Skan ") 1534169689Skan 1535169689Skan(define_expand "vconduv16qi" 1536169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1537169689Skan (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v") 1538169689Skan (match_operand:V16QI 2 "register_operand" "v") 1539169689Skan (match_operand:V16QI 3 "comparison_operator" "") 1540169689Skan (match_operand:V16QI 4 "register_operand" "v") 1541169689Skan (match_operand:V16QI 5 "register_operand" "v") 1542169689Skan ] UNSPEC_VCONDU_V16QI))] 1543169689Skan "TARGET_ALTIVEC" 1544169689Skan " 1545169689Skan{ 1546169689Skan if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], 1547169689Skan operands[3], operands[4], operands[5])) 1548169689Skan DONE; 1549169689Skan else 1550169689Skan FAIL; 1551169689Skan} 1552169689Skan ") 1553169689Skan 1554169689Skan 1555169689Skan(define_insn "altivec_vsel_v4si" 1556117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1557117395Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1558117395Skan (match_operand:V4SI 2 "register_operand" "v") 1559169689Skan (match_operand:V4SI 3 "register_operand" "v")] 1560169689Skan UNSPEC_VSEL4SI))] 1561117395Skan "TARGET_ALTIVEC" 1562117395Skan "vsel %0,%1,%2,%3" 1563117395Skan [(set_attr "type" "vecperm")]) 1564117395Skan 1565169689Skan(define_insn "altivec_vsel_v4sf" 1566117395Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1567117395Skan (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") 1568117395Skan (match_operand:V4SF 2 "register_operand" "v") 1569169689Skan (match_operand:V4SI 3 "register_operand" "v")] 1570169689Skan UNSPEC_VSEL4SF))] 1571117395Skan "TARGET_ALTIVEC" 1572117395Skan "vsel %0,%1,%2,%3" 1573117395Skan [(set_attr "type" "vecperm")]) 1574117395Skan 1575169689Skan(define_insn "altivec_vsel_v8hi" 1576117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1577117395Skan (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1578117395Skan (match_operand:V8HI 2 "register_operand" "v") 1579169689Skan (match_operand:V8HI 3 "register_operand" "v")] 1580169689Skan UNSPEC_VSEL8HI))] 1581117395Skan "TARGET_ALTIVEC" 1582117395Skan "vsel %0,%1,%2,%3" 1583117395Skan [(set_attr "type" "vecperm")]) 1584117395Skan 1585169689Skan(define_insn "altivec_vsel_v16qi" 1586117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 1587117395Skan (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1588117395Skan (match_operand:V16QI 2 "register_operand" "v") 1589169689Skan (match_operand:V16QI 3 "register_operand" "v")] 1590169689Skan UNSPEC_VSEL16QI))] 1591117395Skan "TARGET_ALTIVEC" 1592117395Skan "vsel %0,%1,%2,%3" 1593117395Skan [(set_attr "type" "vecperm")]) 1594117395Skan 1595169689Skan(define_insn "altivec_vsldoi_<mode>" 1596169689Skan [(set (match_operand:V 0 "register_operand" "=v") 1597169689Skan (unspec:V [(match_operand:V 1 "register_operand" "v") 1598169689Skan (match_operand:V 2 "register_operand" "v") 1599169689Skan (match_operand:QI 3 "immediate_operand" "i")] 1600169689Skan UNSPEC_VLSDOI))] 1601117395Skan "TARGET_ALTIVEC" 1602132718Skan "vsldoi %0,%1,%2,%3" 1603117395Skan [(set_attr "type" "vecperm")]) 1604117395Skan 1605117395Skan(define_insn "altivec_vupkhsb" 1606117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1607169689Skan (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 1608169689Skan UNSPEC_VUPKHSB))] 1609117395Skan "TARGET_ALTIVEC" 1610132718Skan "vupkhsb %0,%1" 1611117395Skan [(set_attr "type" "vecperm")]) 1612117395Skan 1613117395Skan(define_insn "altivec_vupkhpx" 1614117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1615169689Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 1616169689Skan UNSPEC_VUPKHPX))] 1617117395Skan "TARGET_ALTIVEC" 1618132718Skan "vupkhpx %0,%1" 1619117395Skan [(set_attr "type" "vecperm")]) 1620117395Skan 1621117395Skan(define_insn "altivec_vupkhsh" 1622117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1623169689Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 1624169689Skan UNSPEC_VUPKHSH))] 1625117395Skan "TARGET_ALTIVEC" 1626132718Skan "vupkhsh %0,%1" 1627117395Skan [(set_attr "type" "vecperm")]) 1628117395Skan 1629117395Skan(define_insn "altivec_vupklsb" 1630117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1631169689Skan (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 1632169689Skan UNSPEC_VUPKLSB))] 1633117395Skan "TARGET_ALTIVEC" 1634132718Skan "vupklsb %0,%1" 1635117395Skan [(set_attr "type" "vecperm")]) 1636117395Skan 1637117395Skan(define_insn "altivec_vupklpx" 1638117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1639169689Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 1640169689Skan UNSPEC_VUPKLPX))] 1641117395Skan "TARGET_ALTIVEC" 1642132718Skan "vupklpx %0,%1" 1643117395Skan [(set_attr "type" "vecperm")]) 1644117395Skan 1645117395Skan(define_insn "altivec_vupklsh" 1646117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1647169689Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 1648169689Skan UNSPEC_VUPKLSH))] 1649117395Skan "TARGET_ALTIVEC" 1650132718Skan "vupklsh %0,%1" 1651117395Skan [(set_attr "type" "vecperm")]) 1652117395Skan 1653117395Skan;; AltiVec predicates. 1654117395Skan 1655117395Skan(define_expand "cr6_test_for_zero" 1656117395Skan [(set (match_operand:SI 0 "register_operand" "=r") 1657117395Skan (eq:SI (reg:CC 74) 1658117395Skan (const_int 0)))] 1659117395Skan "TARGET_ALTIVEC" 1660117395Skan "") 1661117395Skan 1662117395Skan(define_expand "cr6_test_for_zero_reverse" 1663117395Skan [(set (match_operand:SI 0 "register_operand" "=r") 1664117395Skan (eq:SI (reg:CC 74) 1665117395Skan (const_int 0))) 1666117395Skan (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] 1667117395Skan "TARGET_ALTIVEC" 1668117395Skan "") 1669117395Skan 1670117395Skan(define_expand "cr6_test_for_lt" 1671117395Skan [(set (match_operand:SI 0 "register_operand" "=r") 1672117395Skan (lt:SI (reg:CC 74) 1673117395Skan (const_int 0)))] 1674117395Skan "TARGET_ALTIVEC" 1675117395Skan "") 1676117395Skan 1677117395Skan(define_expand "cr6_test_for_lt_reverse" 1678117395Skan [(set (match_operand:SI 0 "register_operand" "=r") 1679117395Skan (lt:SI (reg:CC 74) 1680117395Skan (const_int 0))) 1681117395Skan (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] 1682117395Skan "TARGET_ALTIVEC" 1683117395Skan "") 1684117395Skan 1685117395Skan;; We can get away with generating the opcode on the fly (%3 below) 1686117395Skan;; because all the predicates have the same scheduling parameters. 1687117395Skan 1688169689Skan(define_insn "altivec_predicate_<mode>" 1689117395Skan [(set (reg:CC 74) 1690169689Skan (unspec:CC [(match_operand:V 1 "register_operand" "v") 1691169689Skan (match_operand:V 2 "register_operand" "v") 1692169689Skan (match_operand 3 "any_operand" "")] UNSPEC_PREDICATE)) 1693169689Skan (clobber (match_scratch:V 0 "=v"))] 1694117395Skan "TARGET_ALTIVEC" 1695117395Skan "%3 %0,%1,%2" 1696117395Skan[(set_attr "type" "veccmp")]) 1697117395Skan 1698117395Skan(define_insn "altivec_mtvscr" 1699117395Skan [(set (reg:SI 110) 1700117395Skan (unspec_volatile:SI 1701169689Skan [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))] 1702117395Skan "TARGET_ALTIVEC" 1703117395Skan "mtvscr %0" 1704117395Skan [(set_attr "type" "vecsimple")]) 1705117395Skan 1706117395Skan(define_insn "altivec_mfvscr" 1707117395Skan [(set (match_operand:V8HI 0 "register_operand" "=v") 1708169689Skan (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))] 1709117395Skan "TARGET_ALTIVEC" 1710117395Skan "mfvscr %0" 1711117395Skan [(set_attr "type" "vecsimple")]) 1712117395Skan 1713117395Skan(define_insn "altivec_dssall" 1714169689Skan [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)] 1715117395Skan "TARGET_ALTIVEC" 1716117395Skan "dssall" 1717117395Skan [(set_attr "type" "vecsimple")]) 1718117395Skan 1719117395Skan(define_insn "altivec_dss" 1720169689Skan [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")] 1721169689Skan UNSPECV_DSS)] 1722117395Skan "TARGET_ALTIVEC" 1723117395Skan "dss %0" 1724117395Skan [(set_attr "type" "vecsimple")]) 1725117395Skan 1726117395Skan(define_insn "altivec_dst" 1727169689Skan [(unspec [(match_operand 0 "register_operand" "b") 1728117395Skan (match_operand:SI 1 "register_operand" "r") 1729169689Skan (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)] 1730169689Skan "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode" 1731169689Skan "dst %0,%1,%2" 1732117395Skan [(set_attr "type" "vecsimple")]) 1733117395Skan 1734117395Skan(define_insn "altivec_dstt" 1735169689Skan [(unspec [(match_operand 0 "register_operand" "b") 1736117395Skan (match_operand:SI 1 "register_operand" "r") 1737169689Skan (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)] 1738169689Skan "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode" 1739169689Skan "dstt %0,%1,%2" 1740117395Skan [(set_attr "type" "vecsimple")]) 1741117395Skan 1742117395Skan(define_insn "altivec_dstst" 1743169689Skan [(unspec [(match_operand 0 "register_operand" "b") 1744117395Skan (match_operand:SI 1 "register_operand" "r") 1745169689Skan (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)] 1746169689Skan "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode" 1747169689Skan "dstst %0,%1,%2" 1748117395Skan [(set_attr "type" "vecsimple")]) 1749117395Skan 1750117395Skan(define_insn "altivec_dststt" 1751169689Skan [(unspec [(match_operand 0 "register_operand" "b") 1752117395Skan (match_operand:SI 1 "register_operand" "r") 1753169689Skan (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)] 1754169689Skan "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode" 1755169689Skan "dststt %0,%1,%2" 1756117395Skan [(set_attr "type" "vecsimple")]) 1757117395Skan 1758117395Skan(define_insn "altivec_lvsl" 1759117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 1760169689Skan (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))] 1761117395Skan "TARGET_ALTIVEC" 1762132718Skan "lvsl %0,%y1" 1763117395Skan [(set_attr "type" "vecload")]) 1764117395Skan 1765117395Skan(define_insn "altivec_lvsr" 1766117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 1767169689Skan (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))] 1768117395Skan "TARGET_ALTIVEC" 1769132718Skan "lvsr %0,%y1" 1770117395Skan [(set_attr "type" "vecload")]) 1771117395Skan 1772169689Skan(define_expand "build_vector_mask_for_load" 1773169689Skan [(set (match_operand:V16QI 0 "register_operand" "") 1774169689Skan (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))] 1775169689Skan "TARGET_ALTIVEC" 1776169689Skan " 1777169689Skan{ 1778169689Skan rtx addr; 1779169689Skan rtx temp; 1780169689Skan 1781169689Skan gcc_assert (GET_CODE (operands[1]) == MEM); 1782169689Skan 1783169689Skan addr = XEXP (operands[1], 0); 1784169689Skan temp = gen_reg_rtx (GET_MODE (addr)); 1785169689Skan emit_insn (gen_rtx_SET (VOIDmode, temp, 1786169689Skan gen_rtx_NEG (GET_MODE (addr), addr))); 1787169689Skan emit_insn (gen_altivec_lvsr (operands[0], 1788169689Skan replace_equiv_address (operands[1], temp))); 1789169689Skan DONE; 1790169689Skan}") 1791169689Skan 1792117395Skan;; Parallel some of the LVE* and STV*'s with unspecs because some have 1793117395Skan;; identical rtl but different instructions-- and gcc gets confused. 1794117395Skan 1795169689Skan(define_insn "altivec_lve<VI_char>x" 1796117395Skan [(parallel 1797169689Skan [(set (match_operand:VI 0 "register_operand" "=v") 1798169689Skan (match_operand:VI 1 "memory_operand" "Z")) 1799169689Skan (unspec [(const_int 0)] UNSPEC_LVE)])] 1800117395Skan "TARGET_ALTIVEC" 1801169689Skan "lve<VI_char>x %0,%y1" 1802117395Skan [(set_attr "type" "vecload")]) 1803117395Skan 1804169689Skan(define_insn "*altivec_lvesfx" 1805117395Skan [(parallel 1806169689Skan [(set (match_operand:V4SF 0 "register_operand" "=v") 1807169689Skan (match_operand:V4SF 1 "memory_operand" "Z")) 1808169689Skan (unspec [(const_int 0)] UNSPEC_LVE)])] 1809117395Skan "TARGET_ALTIVEC" 1810132718Skan "lvewx %0,%y1" 1811117395Skan [(set_attr "type" "vecload")]) 1812117395Skan 1813117395Skan(define_insn "altivec_lvxl" 1814117395Skan [(parallel 1815117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1816169689Skan (match_operand:V4SI 1 "memory_operand" "Z")) 1817169689Skan (unspec [(const_int 0)] UNSPEC_SET_VSCR)])] 1818117395Skan "TARGET_ALTIVEC" 1819132718Skan "lvxl %0,%y1" 1820117395Skan [(set_attr "type" "vecload")]) 1821117395Skan 1822117395Skan(define_insn "altivec_lvx" 1823117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 1824169689Skan (match_operand:V4SI 1 "memory_operand" "Z"))] 1825117395Skan "TARGET_ALTIVEC" 1826132718Skan "lvx %0,%y1" 1827117395Skan [(set_attr "type" "vecload")]) 1828117395Skan 1829117395Skan(define_insn "altivec_stvx" 1830117395Skan [(parallel 1831169689Skan [(set (match_operand:V4SI 0 "memory_operand" "=Z") 1832132718Skan (match_operand:V4SI 1 "register_operand" "v")) 1833169689Skan (unspec [(const_int 0)] UNSPEC_STVX)])] 1834117395Skan "TARGET_ALTIVEC" 1835132718Skan "stvx %1,%y0" 1836117395Skan [(set_attr "type" "vecstore")]) 1837117395Skan 1838117395Skan(define_insn "altivec_stvxl" 1839117395Skan [(parallel 1840169689Skan [(set (match_operand:V4SI 0 "memory_operand" "=Z") 1841132718Skan (match_operand:V4SI 1 "register_operand" "v")) 1842169689Skan (unspec [(const_int 0)] UNSPEC_STVXL)])] 1843117395Skan "TARGET_ALTIVEC" 1844132718Skan "stvxl %1,%y0" 1845117395Skan [(set_attr "type" "vecstore")]) 1846117395Skan 1847169689Skan(define_insn "altivec_stve<VI_char>x" 1848117395Skan [(parallel 1849169689Skan [(set (match_operand:VI 0 "memory_operand" "=Z") 1850169689Skan (match_operand:VI 1 "register_operand" "v")) 1851169689Skan (unspec [(const_int 0)] UNSPEC_STVE)])] 1852117395Skan "TARGET_ALTIVEC" 1853169689Skan "stve<VI_char>x %1,%y0" 1854117395Skan [(set_attr "type" "vecstore")]) 1855117395Skan 1856169689Skan(define_insn "*altivec_stvesfx" 1857117395Skan [(parallel 1858169689Skan [(set (match_operand:V4SF 0 "memory_operand" "=Z") 1859169689Skan (match_operand:V4SF 1 "register_operand" "v")) 1860169689Skan (unspec [(const_int 0)] UNSPEC_STVE)])] 1861117395Skan "TARGET_ALTIVEC" 1862169689Skan "stvewx %1,%y0" 1863117395Skan [(set_attr "type" "vecstore")]) 1864117395Skan 1865169689Skan(define_expand "vec_init<mode>" 1866169689Skan [(match_operand:V 0 "register_operand" "") 1867169689Skan (match_operand 1 "" "")] 1868117395Skan "TARGET_ALTIVEC" 1869169689Skan{ 1870169689Skan rs6000_expand_vector_init (operands[0], operands[1]); 1871169689Skan DONE; 1872169689Skan}) 1873117395Skan 1874169689Skan(define_expand "vec_setv4si" 1875169689Skan [(match_operand:V4SI 0 "register_operand" "") 1876169689Skan (match_operand:SI 1 "register_operand" "") 1877169689Skan (match_operand 2 "const_int_operand" "")] 1878117395Skan "TARGET_ALTIVEC" 1879169689Skan{ 1880169689Skan rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2])); 1881169689Skan DONE; 1882169689Skan}) 1883117395Skan 1884169689Skan(define_expand "vec_setv8hi" 1885169689Skan [(match_operand:V8HI 0 "register_operand" "") 1886169689Skan (match_operand:HI 1 "register_operand" "") 1887169689Skan (match_operand 2 "const_int_operand" "")] 1888117395Skan "TARGET_ALTIVEC" 1889169689Skan{ 1890169689Skan rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2])); 1891169689Skan DONE; 1892169689Skan}) 1893117395Skan 1894169689Skan(define_expand "vec_setv16qi" 1895169689Skan [(match_operand:V16QI 0 "register_operand" "") 1896169689Skan (match_operand:QI 1 "register_operand" "") 1897169689Skan (match_operand 2 "const_int_operand" "")] 1898117395Skan "TARGET_ALTIVEC" 1899169689Skan{ 1900169689Skan rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2])); 1901169689Skan DONE; 1902169689Skan}) 1903117395Skan 1904169689Skan(define_expand "vec_setv4sf" 1905169689Skan [(match_operand:V4SF 0 "register_operand" "") 1906169689Skan (match_operand:SF 1 "register_operand" "") 1907169689Skan (match_operand 2 "const_int_operand" "")] 1908117395Skan "TARGET_ALTIVEC" 1909169689Skan{ 1910169689Skan rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2])); 1911169689Skan DONE; 1912169689Skan}) 1913117395Skan 1914169689Skan(define_expand "vec_extractv4si" 1915169689Skan [(match_operand:SI 0 "register_operand" "") 1916169689Skan (match_operand:V4SI 1 "register_operand" "") 1917169689Skan (match_operand 2 "const_int_operand" "")] 1918169689Skan "TARGET_ALTIVEC" 1919169689Skan{ 1920169689Skan rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2])); 1921169689Skan DONE; 1922169689Skan}) 1923169689Skan 1924169689Skan(define_expand "vec_extractv8hi" 1925169689Skan [(match_operand:HI 0 "register_operand" "") 1926169689Skan (match_operand:V8HI 1 "register_operand" "") 1927169689Skan (match_operand 2 "const_int_operand" "")] 1928169689Skan "TARGET_ALTIVEC" 1929169689Skan{ 1930169689Skan rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2])); 1931169689Skan DONE; 1932169689Skan}) 1933169689Skan 1934169689Skan(define_expand "vec_extractv16qi" 1935169689Skan [(match_operand:QI 0 "register_operand" "") 1936169689Skan (match_operand:V16QI 1 "register_operand" "") 1937169689Skan (match_operand 2 "const_int_operand" "")] 1938169689Skan "TARGET_ALTIVEC" 1939169689Skan{ 1940169689Skan rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2])); 1941169689Skan DONE; 1942169689Skan}) 1943169689Skan 1944169689Skan(define_expand "vec_extractv4sf" 1945169689Skan [(match_operand:SF 0 "register_operand" "") 1946169689Skan (match_operand:V4SF 1 "register_operand" "") 1947169689Skan (match_operand 2 "const_int_operand" "")] 1948169689Skan "TARGET_ALTIVEC" 1949169689Skan{ 1950169689Skan rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2])); 1951169689Skan DONE; 1952169689Skan}) 1953169689Skan 1954169689Skan;; Generate 1955169689Skan;; vspltis? SCRATCH0,0 1956169689Skan;; vsubu?m SCRATCH2,SCRATCH1,%1 1957169689Skan;; vmaxs? %0,%1,SCRATCH2" 1958169689Skan(define_expand "abs<mode>2" 1959169689Skan [(set (match_dup 2) (vec_duplicate:VI (const_int 0))) 1960169689Skan (set (match_dup 3) 1961169689Skan (minus:VI (match_dup 2) 1962169689Skan (match_operand:VI 1 "register_operand" "v"))) 1963169689Skan (set (match_operand:VI 0 "register_operand" "=v") 1964169689Skan (smax:VI (match_dup 1) (match_dup 3)))] 1965169689Skan "TARGET_ALTIVEC" 1966169689Skan{ 1967169689Skan operands[2] = gen_reg_rtx (GET_MODE (operands[0])); 1968169689Skan operands[3] = gen_reg_rtx (GET_MODE (operands[0])); 1969169689Skan}) 1970169689Skan 1971169689Skan;; Generate 1972169689Skan;; vspltisw SCRATCH1,-1 1973169689Skan;; vslw SCRATCH2,SCRATCH1,SCRATCH1 1974169689Skan;; vandc %0,%1,SCRATCH2 1975169689Skan(define_expand "absv4sf2" 1976169689Skan [(set (match_dup 2) 1977169689Skan (vec_duplicate:V4SI (const_int -1))) 1978169689Skan (set (match_dup 3) 1979169689Skan (unspec:V4SI [(match_dup 2) (match_dup 2)] UNSPEC_VSL)) 1980169689Skan (set (match_operand:V4SF 0 "register_operand" "=v") 1981169689Skan (and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0)) 1982169689Skan (match_operand:V4SF 1 "register_operand" "v")))] 1983169689Skan "TARGET_ALTIVEC" 1984169689Skan{ 1985169689Skan operands[2] = gen_reg_rtx (V4SImode); 1986169689Skan operands[3] = gen_reg_rtx (V4SImode); 1987169689Skan}) 1988169689Skan 1989169689Skan;; Generate 1990169689Skan;; vspltis? SCRATCH0,0 1991169689Skan;; vsubs?s SCRATCH2,SCRATCH1,%1 1992169689Skan;; vmaxs? %0,%1,SCRATCH2" 1993169689Skan(define_expand "altivec_abss_<mode>" 1994169689Skan [(set (match_dup 2) (vec_duplicate:VI (const_int 0))) 1995169689Skan (parallel [(set (match_dup 3) 1996169689Skan (unspec:VI [(match_dup 2) 1997169689Skan (match_operand:VI 1 "register_operand" "v")] 1998169689Skan UNSPEC_VSUBS)) 1999169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]) 2000169689Skan (set (match_operand:VI 0 "register_operand" "=v") 2001169689Skan (smax:VI (match_dup 1) (match_dup 3)))] 2002169689Skan "TARGET_ALTIVEC" 2003169689Skan{ 2004169689Skan operands[2] = gen_reg_rtx (GET_MODE (operands[0])); 2005169689Skan operands[3] = gen_reg_rtx (GET_MODE (operands[0])); 2006169689Skan}) 2007169689Skan 2008169689Skan;; Vector shift left in bits. Currently supported ony for shift 2009169689Skan;; amounts that can be expressed as byte shifts (divisible by 8). 2010169689Skan;; General shift amounts can be supported using vslo + vsl. We're 2011169689Skan;; not expecting to see these yet (the vectorizer currently 2012169689Skan;; generates only shifts divisible by byte_size). 2013169689Skan(define_expand "vec_shl_<mode>" 2014169689Skan [(set (match_operand:V 0 "register_operand" "=v") 2015169689Skan (unspec:V [(match_operand:V 1 "register_operand" "v") 2016169689Skan (match_operand:QI 2 "reg_or_short_operand" "")] 2017169689Skan UNSPEC_VECSH))] 2018169689Skan "TARGET_ALTIVEC" 2019169689Skan " 2020169689Skan{ 2021169689Skan rtx bitshift = operands[2]; 2022169689Skan rtx byteshift = gen_reg_rtx (QImode); 2023169689Skan HOST_WIDE_INT bitshift_val; 2024169689Skan HOST_WIDE_INT byteshift_val; 2025169689Skan 2026169689Skan if (! CONSTANT_P (bitshift)) 2027169689Skan FAIL; 2028169689Skan bitshift_val = INTVAL (bitshift); 2029169689Skan if (bitshift_val & 0x7) 2030169689Skan FAIL; 2031169689Skan byteshift_val = bitshift_val >> 3; 2032169689Skan byteshift = gen_rtx_CONST_INT (QImode, byteshift_val); 2033169689Skan emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1], 2034169689Skan byteshift)); 2035169689Skan DONE; 2036169689Skan}") 2037169689Skan 2038169689Skan;; Vector shift left in bits. Currently supported ony for shift 2039169689Skan;; amounts that can be expressed as byte shifts (divisible by 8). 2040169689Skan;; General shift amounts can be supported using vsro + vsr. We're 2041169689Skan;; not expecting to see these yet (the vectorizer currently 2042169689Skan;; generates only shifts divisible by byte_size). 2043169689Skan(define_expand "vec_shr_<mode>" 2044169689Skan [(set (match_operand:V 0 "register_operand" "=v") 2045169689Skan (unspec:V [(match_operand:V 1 "register_operand" "v") 2046169689Skan (match_operand:QI 2 "reg_or_short_operand" "")] 2047169689Skan UNSPEC_VECSH))] 2048169689Skan "TARGET_ALTIVEC" 2049169689Skan " 2050169689Skan{ 2051169689Skan rtx bitshift = operands[2]; 2052169689Skan rtx byteshift = gen_reg_rtx (QImode); 2053169689Skan HOST_WIDE_INT bitshift_val; 2054169689Skan HOST_WIDE_INT byteshift_val; 2055169689Skan 2056169689Skan if (! CONSTANT_P (bitshift)) 2057169689Skan FAIL; 2058169689Skan bitshift_val = INTVAL (bitshift); 2059169689Skan if (bitshift_val & 0x7) 2060169689Skan FAIL; 2061169689Skan byteshift_val = 16 - (bitshift_val >> 3); 2062169689Skan byteshift = gen_rtx_CONST_INT (QImode, byteshift_val); 2063169689Skan emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1], 2064169689Skan byteshift)); 2065169689Skan DONE; 2066169689Skan}") 2067169689Skan 2068169689Skan(define_insn "altivec_vsumsws_nomode" 2069169689Skan [(set (match_operand 0 "register_operand" "=v") 2070169689Skan (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 2071169689Skan (match_operand:V4SI 2 "register_operand" "v")] 2072169689Skan UNSPEC_VSUMSWS)) 2073169689Skan (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] 2074169689Skan "TARGET_ALTIVEC" 2075169689Skan "vsumsws %0,%1,%2" 2076169689Skan [(set_attr "type" "veccomplex")]) 2077169689Skan 2078169689Skan(define_expand "reduc_splus_<mode>" 2079169689Skan [(set (match_operand:VIshort 0 "register_operand" "=v") 2080169689Skan (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")] 2081169689Skan UNSPEC_REDUC_PLUS))] 2082169689Skan "TARGET_ALTIVEC" 2083169689Skan " 2084169689Skan{ 2085169689Skan rtx vzero = gen_reg_rtx (V4SImode); 2086169689Skan rtx vtmp1 = gen_reg_rtx (V4SImode); 2087169689Skan 2088169689Skan emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); 2089169689Skan emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero)); 2090169689Skan emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero)); 2091169689Skan DONE; 2092169689Skan}") 2093169689Skan 2094169689Skan(define_expand "reduc_uplus_v16qi" 2095117395Skan [(set (match_operand:V16QI 0 "register_operand" "=v") 2096169689Skan (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 2097169689Skan UNSPEC_REDUC_PLUS))] 2098117395Skan "TARGET_ALTIVEC" 2099169689Skan " 2100169689Skan{ 2101169689Skan rtx vzero = gen_reg_rtx (V4SImode); 2102169689Skan rtx vtmp1 = gen_reg_rtx (V4SImode); 2103117395Skan 2104169689Skan emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); 2105169689Skan emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero)); 2106169689Skan emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero)); 2107169689Skan DONE; 2108169689Skan}") 2109169689Skan 2110169689Skan(define_insn "vec_realign_load_<mode>" 2111169689Skan [(set (match_operand:V 0 "register_operand" "=v") 2112169689Skan (unspec:V [(match_operand:V 1 "register_operand" "v") 2113169689Skan (match_operand:V 2 "register_operand" "v") 2114169689Skan (match_operand:V16QI 3 "register_operand" "v")] 2115169689Skan UNSPEC_REALIGN_LOAD))] 2116117395Skan "TARGET_ALTIVEC" 2117169689Skan "vperm %0,%1,%2,%3" 2118169689Skan [(set_attr "type" "vecperm")]) 2119117395Skan 2120169689Skan(define_expand "neg<mode>2" 2121169689Skan [(use (match_operand:VI 0 "register_operand" "")) 2122169689Skan (use (match_operand:VI 1 "register_operand" ""))] 2123169689Skan "TARGET_ALTIVEC" 2124169689Skan " 2125169689Skan{ 2126169689Skan rtx vzero; 2127169689Skan 2128169689Skan vzero = gen_reg_rtx (GET_MODE (operands[0])); 2129169689Skan emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx)); 2130169689Skan emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1])); 2131169689Skan 2132169689Skan DONE; 2133169689Skan}") 2134169689Skan 2135169689Skan(define_expand "udot_prod<mode>" 2136117395Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 2137169689Skan (plus:V4SI (match_operand:V4SI 3 "register_operand" "v") 2138169689Skan (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v") 2139169689Skan (match_operand:VIshort 2 "register_operand" "v")] 2140169689Skan UNSPEC_VMSUMU)))] 2141117395Skan "TARGET_ALTIVEC" 2142169689Skan " 2143169689Skan{ 2144169689Skan emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3])); 2145169689Skan DONE; 2146169689Skan}") 2147169689Skan 2148169689Skan(define_expand "sdot_prodv8hi" 2149169689Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 2150169689Skan (plus:V4SI (match_operand:V4SI 3 "register_operand" "v") 2151169689Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 2152169689Skan (match_operand:V8HI 2 "register_operand" "v")] 2153169689Skan UNSPEC_VMSUMSHM)))] 2154169689Skan "TARGET_ALTIVEC" 2155169689Skan " 2156169689Skan{ 2157169689Skan emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3])); 2158169689Skan DONE; 2159169689Skan}") 2160169689Skan 2161169689Skan(define_expand "widen_usum<mode>3" 2162169689Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 2163169689Skan (plus:V4SI (match_operand:V4SI 2 "register_operand" "v") 2164169689Skan (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")] 2165169689Skan UNSPEC_VMSUMU)))] 2166169689Skan "TARGET_ALTIVEC" 2167169689Skan " 2168169689Skan{ 2169169689Skan rtx vones = gen_reg_rtx (GET_MODE (operands[1])); 2170169689Skan 2171169689Skan emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx)); 2172169689Skan emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2])); 2173169689Skan DONE; 2174169689Skan}") 2175169689Skan 2176169689Skan(define_expand "widen_ssumv16qi3" 2177169689Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 2178169689Skan (plus:V4SI (match_operand:V4SI 2 "register_operand" "v") 2179169689Skan (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")] 2180169689Skan UNSPEC_VMSUMM)))] 2181169689Skan "TARGET_ALTIVEC" 2182169689Skan " 2183169689Skan{ 2184169689Skan rtx vones = gen_reg_rtx (V16QImode); 2185169689Skan 2186169689Skan emit_insn (gen_altivec_vspltisb (vones, const1_rtx)); 2187169689Skan emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2])); 2188169689Skan DONE; 2189169689Skan}") 2190169689Skan 2191169689Skan(define_expand "widen_ssumv8hi3" 2192169689Skan [(set (match_operand:V4SI 0 "register_operand" "=v") 2193169689Skan (plus:V4SI (match_operand:V4SI 2 "register_operand" "v") 2194169689Skan (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 2195169689Skan UNSPEC_VMSUMSHM)))] 2196169689Skan "TARGET_ALTIVEC" 2197169689Skan " 2198169689Skan{ 2199169689Skan rtx vones = gen_reg_rtx (V8HImode); 2200169689Skan 2201169689Skan emit_insn (gen_altivec_vspltish (vones, const1_rtx)); 2202169689Skan emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2])); 2203169689Skan DONE; 2204169689Skan}") 2205169689Skan 2206169689Skan(define_expand "negv4sf2" 2207169689Skan [(use (match_operand:V4SF 0 "register_operand" "")) 2208169689Skan (use (match_operand:V4SF 1 "register_operand" ""))] 2209169689Skan "TARGET_ALTIVEC" 2210169689Skan " 2211169689Skan{ 2212169689Skan rtx neg0; 2213169689Skan 2214169689Skan /* Generate [-0.0, -0.0, -0.0, -0.0]. */ 2215169689Skan neg0 = gen_reg_rtx (V4SImode); 2216169689Skan emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx)); 2217169689Skan emit_insn (gen_altivec_vslw (neg0, neg0, neg0)); 2218169689Skan 2219169689Skan /* XOR */ 2220169689Skan emit_insn (gen_xorv4sf3 (operands[0], 2221169689Skan gen_lowpart (V4SFmode, neg0), operands[1])); 2222169689Skan 2223169689Skan DONE; 2224169689Skan}") 2225