tc-i386.h revision 77312
114125Speter/* tc-i386.h -- Header file for tc-i386.c 214125Speter Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 314125Speter Free Software Foundation. 414125Speter 514125Speter This file is part of GAS, the GNU Assembler. 614125Speter 714125Speter GAS is free software; you can redistribute it and/or modify 814125Speter it under the terms of the GNU General Public License as published by 914125Speter the Free Software Foundation; either version 2, or (at your option) 1014125Speter any later version. 1114125Speter 1214125Speter GAS is distributed in the hope that it will be useful, 1314125Speter but WITHOUT ANY WARRANTY; without even the implied warranty of 1414125Speter MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1514125Speter GNU General Public License for more details. 1614125Speter 1714125Speter You should have received a copy of the GNU General Public License 1814125Speter along with GAS; see the file COPYING. If not, write to the Free 1914125Speter Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2014125Speter 02111-1307, USA. */ 2114125Speter 2214125Speter 2314125Speter/* $FreeBSD: head/contrib/binutils/gas/config/tc-i386.h 77312 2001-05-28 06:11:56Z obrien $ */ 2414125Speter 2514125Speter 2614125Speter#ifndef TC_I386 2714125Speter#define TC_I386 1 2814125Speter 2914125Speter#ifdef ANSI_PROTOTYPES 3014125Speterstruct fix; 3114125Speter#endif 3274499Salfred 3374499Salfred#define TARGET_BYTES_BIG_ENDIAN 0 3414125Speter 3514125Speter#ifdef TE_LYNX 3630376Scharnier#define TARGET_FORMAT "coff-i386-lynx" 3730376Scharnier#endif 3830376Scharnier 39180025Sdfr#ifdef BFD_ASSEMBLER 4014125Speter/* This is used to determine relocation types in tc-i386.c. The first 4130376Scharnier parameter is the current relocation type, the second one is the desired 4214125Speter type. The idea is that if the original type is already some kind of PIC 4314125Speter relocation, we leave it alone, otherwise we give it the desired type */ 4414125Speter 4514125Speter#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) 4614125Speterextern int tc_i386_fix_adjustable PARAMS ((struct fix *)); 4799786Salfred 4814125Speter#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE) 4914125Speter/* This arranges for gas/write.c to not apply a relocation if 5014125Speter tc_fix_adjustable() says it is not adjustable. 5114125Speter The "! symbol_used_in_reloc_p" test is there specifically to cover 5214125Speter the case of non-global symbols in linkonce sections. It's the 5314125Speter generally correct thing to do though; If a reloc is going to be 5414125Speter emitted against a symbol then we don't want to adjust the fixup by 5514125Speter applying the reloc during assembly. The reloc will be applied by 5614125Speter the linker during final link. */ 5714125Speter#define TC_FIX_ADJUSTABLE(fixP) \ 5814125Speter (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP)) 5914125Speter#endif 6014125Speter 6114125Speter/* This expression evaluates to false if the relocation is for a local object 6214125Speter for which we still want to do the relocation at runtime. True if we 6314125Speter are willing to perform this relocation while building the .o file. 6414125Speter This is only used for pcrel relocations, so GOTOFF does not need to be 6514125Speter checked here. I am not sure if some of the others are ever used with 6614125Speter pcrel, but it is easier to be safe than sorry. */ 6714125Speter 6814125Speter#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \ 6914125Speter ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \ 7014125Speter && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \ 7114125Speter && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \ 7214125Speter && ((FIX)->fx_addsy == NULL \ 7314125Speter || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \ 7414125Speter && ! S_IS_WEAK ((FIX)->fx_addsy) \ 7514125Speter && S_IS_DEFINED ((FIX)->fx_addsy) \ 7614125Speter && ! S_IS_COMMON ((FIX)->fx_addsy)))) 7714125Speter 7814125Speter#define TARGET_ARCH bfd_arch_i386 7914125Speter#define TARGET_MACH (i386_mach ()) 8014125Speterextern unsigned long i386_mach PARAMS ((void)); 8114125Speter 82180025Sdfr#ifdef TE_FreeBSD 8314125Speter#define AOUT_TARGET_FORMAT "a.out-i386-freebsd" 8414125Speter#endif 85180025Sdfr#ifdef TE_NetBSD 86180025Sdfr#define AOUT_TARGET_FORMAT "a.out-i386-netbsd" 8714125Speter#endif 8814125Speter#ifdef TE_386BSD 8914125Speter#define AOUT_TARGET_FORMAT "a.out-i386-bsd" 9014125Speter#endif 9114125Speter#ifdef TE_LINUX 9214125Speter#define AOUT_TARGET_FORMAT "a.out-i386-linux" 9314125Speter#endif 94180025Sdfr#ifdef TE_Mach 95180025Sdfr#define AOUT_TARGET_FORMAT "a.out-mach3" 96180025Sdfr#endif 97180025Sdfr#ifdef TE_DYNIX 98180025Sdfr#define AOUT_TARGET_FORMAT "a.out-i386-dynix" 99180025Sdfr#endif 100180025Sdfr#ifndef AOUT_TARGET_FORMAT 101180025Sdfr#define AOUT_TARGET_FORMAT "a.out-i386" 102180025Sdfr#endif 103180025Sdfr 104180025Sdfr#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 105180025Sdfr || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 106180025Sdfrextern const char *i386_target_format PARAMS ((void)); 107180025Sdfr#define TARGET_FORMAT i386_target_format () 108180025Sdfr#else 109180025Sdfr#ifdef OBJ_ELF 110180025Sdfr#define TARGET_FORMAT "elf32-i386" 111180025Sdfr#endif 112180025Sdfr#ifdef OBJ_AOUT 113180025Sdfr#define TARGET_FORMAT AOUT_TARGET_FORMAT 114180025Sdfr#endif 115180025Sdfr#endif 116180025Sdfr 117180025Sdfr#else /* ! BFD_ASSEMBLER */ 11814125Speter 11914125Speter/* COFF STUFF */ 12014125Speter 121180025Sdfr#define COFF_MAGIC I386MAGIC 122180025Sdfr#define BFD_ARCH bfd_arch_i386 12314125Speter#define COFF_FLAGS F_AR32WR 12414125Speter#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7) 12514125Speter#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP) 12614125Speterextern short tc_coff_fix2rtype PARAMS ((struct fix *)); 12714125Speter#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag) 12814125Speterextern int tc_coff_sizemachdep PARAMS ((fragS *frag)); 12914125Speter 13014125Speter#ifdef TE_GO32 13114125Speter/* DJGPP now expects some sections to be 2**4 aligned. */ 13214125Speter#define SUB_SEGMENT_ALIGN(SEG) \ 13314125Speter ((strcmp (obj_segment_name (SEG), ".text") == 0 \ 13414125Speter || strcmp (obj_segment_name (SEG), ".data") == 0 \ 13514125Speter || strcmp (obj_segment_name (SEG), ".bss") == 0 \ 13614125Speter || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \ 13714125Speter || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \ 13814125Speter || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \ 13914125Speter ? 4 \ 14014125Speter : 2) 14114125Speter#else 14214125Speter#define SUB_SEGMENT_ALIGN(SEG) 2 14314125Speter#endif 14414125Speter 14514125Speter#define TC_RVA_RELOC 7 14614125Speter/* Need this for PIC relocations */ 14714125Speter#define NEED_FX_R_TYPE 14814125Speter 14914125Speter#ifdef TE_386BSD 15014125Speter/* The BSDI linker apparently rejects objects with a machine type of 15114125Speter M_386 (100). */ 15214125Speter#define AOUT_MACHTYPE 0 15314125Speter#else 15414125Speter#define AOUT_MACHTYPE 100 15514125Speter#endif 15614125Speter 15714125Speter#undef REVERSE_SORT_RELOCS 15814125Speter 15914125Speter#endif /* ! BFD_ASSEMBLER */ 16014125Speter 16114125Speter#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp) 16214125Speterextern int tc_i386_force_relocation PARAMS ((struct fix *)); 16314125Speter 16414125Speter#ifdef BFD_ASSEMBLER 16514125Speter#define NO_RELOC BFD_RELOC_NONE 16614125Speter#else 16714125Speter#define NO_RELOC 0 16814125Speter#endif 16914125Speter#define tc_coff_symbol_emit_hook(a) ; /* not used */ 17099798Salfred 17114125Speter#ifndef BFD_ASSEMBLER 17214125Speter#ifndef OBJ_AOUT 17314125Speter#ifndef TE_PE 17414125Speter#ifndef TE_GO32 17514125Speter/* Local labels starts with .L */ 17614125Speter#define LOCAL_LABEL(name) (name[0] == '.' \ 17714125Speter && (name[1] == 'L' || name[1] == 'X' || name[1] == '.')) 17814125Speter#endif 17914125Speter#endif 18014125Speter#endif 18114125Speter#endif 18214125Speter 18314125Speter#define LOCAL_LABELS_FB 1 18430376Scharnier 18514125Speter#define tc_aout_pre_write_hook(x) {;} /* not used */ 18614125Speter#define tc_crawl_symbol_chain(a) {;} /* not used */ 18714125Speter#define tc_headers_hook(a) {;} /* not used */ 18814125Speter 18914125Speterextern const char extra_symbol_chars[]; 19014125Speter#define tc_symbol_chars extra_symbol_chars 19121786Salex 192171816Struckman#define MAX_OPERANDS 3 /* max operands per insn */ 19314125Speter#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ 19414125Speter#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ 19514125Speter 19614125Speter/* Prefixes will be emitted in the order defined below. 19714125Speter WAIT_PREFIX must be the first prefix since FWAIT is really is an 19814125Speter instruction, and so must come before any prefixes. */ 19914125Speter#define WAIT_PREFIX 0 20014125Speter#define LOCKREP_PREFIX 1 20114125Speter#define ADDR_PREFIX 2 20214125Speter#define DATA_PREFIX 3 20330376Scharnier#define SEG_PREFIX 4 20414125Speter#define REX_PREFIX 5 /* must come last. */ 20514125Speter#define MAX_PREFIXES 6 /* max prefixes per opcode */ 20614125Speter 20714125Speter/* we define the syntax here (modulo base,index,scale syntax) */ 20814125Speter#define REGISTER_PREFIX '%' 20914125Speter#define IMMEDIATE_PREFIX '$' 21014125Speter#define ABSOLUTE_PREFIX '*' 21114125Speter 21214125Speter#define TWO_BYTE_OPCODE_ESCAPE 0x0f 21314125Speter#define NOP_OPCODE (char) 0x90 21414125Speter 21514125Speter/* register numbers */ 21614125Speter#define EBP_REG_NUM 5 21714125Speter#define ESP_REG_NUM 4 21814125Speter 21914125Speter/* modrm_byte.regmem for twobyte escape */ 22014125Speter#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 22114125Speter/* index_base_byte.index for no index register addressing */ 22214125Speter#define NO_INDEX_REGISTER ESP_REG_NUM 22314125Speter/* index_base_byte.base for no base register addressing */ 22414125Speter#define NO_BASE_REGISTER EBP_REG_NUM 22514125Speter#define NO_BASE_REGISTER_16 6 22614125Speter 22714125Speter/* these are the instruction mnemonic suffixes. */ 22814125Speter#define WORD_MNEM_SUFFIX 'w' 22914125Speter#define BYTE_MNEM_SUFFIX 'b' 23014125Speter#define SHORT_MNEM_SUFFIX 's' 23114125Speter#define LONG_MNEM_SUFFIX 'l' 23214125Speter#define QWORD_MNEM_SUFFIX 'q' 23314125Speter/* Intel Syntax */ 23414125Speter#define LONG_DOUBLE_MNEM_SUFFIX 'x' 23514125Speter 23614125Speter/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 23714125Speter#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 23814125Speter#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 23914125Speter 24014125Speter#define END_OF_INSN '\0' 24114125Speter 24214125Speter/* Intel Syntax */ 24314125Speter/* Values 0-4 map onto scale factor */ 24414125Speter#define BYTE_PTR 0 24514125Speter#define WORD_PTR 1 24614125Speter#define DWORD_PTR 2 24714125Speter#define QWORD_PTR 3 24814125Speter#define XWORD_PTR 4 24914125Speter#define SHORT 5 25014125Speter#define OFFSET_FLAT 6 25114125Speter#define FLAT 7 25214125Speter#define NONE_FOUND 8 25314125Speter 25414125Spetertypedef struct 25514125Speter{ 25614125Speter /* instruction name sans width suffix ("mov" for movl insns) */ 25714125Speter char *name; 25814125Speter 25914125Speter /* how many operands */ 26014125Speter unsigned int operands; 26114125Speter 26214125Speter /* base_opcode is the fundamental opcode byte without optional 26314125Speter prefix(es). */ 26414125Speter unsigned int base_opcode; 26514125Speter 26614125Speter /* extension_opcode is the 3 bit extension for group <n> insns. 26714125Speter This field is also used to store the 8-bit opcode suffix for the 26814125Speter AMD 3DNow! instructions. 26914125Speter If this template has no extension opcode (the usual case) use None */ 27014125Speter unsigned int extension_opcode; 27114125Speter#define None 0xffff /* If no extension_opcode is possible. */ 272121560Speter 273121560Speter /* cpu feature flags */ 27414125Speter unsigned int cpu_flags; 27514125Speter#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ 27614125Speter#define Cpu186 0x2 /* i186 or better required */ 27714125Speter#define Cpu286 0x4 /* i286 or better required */ 27814125Speter#define Cpu386 0x8 /* i386 or better required */ 27914125Speter#define Cpu486 0x10 /* i486 or better required */ 28014125Speter#define Cpu586 0x20 /* i585 or better required */ 28114125Speter#define Cpu686 0x40 /* i686 or better required */ 28214125Speter#define CpuP4 0x80 /* Pentium4 or better required */ 28314125Speter#define CpuK6 0x100 /* AMD K6 or better required*/ 28414125Speter#define CpuAthlon 0x200 /* AMD Athlon or better required*/ 28514125Speter#define CpuSledgehammer 0x400 /* Sledgehammer or better required */ 28614125Speter#define CpuMMX 0x800 /* MMX support required */ 28714125Speter#define CpuSSE 0x1000 /* Streaming SIMD extensions required */ 28814125Speter#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */ 28914125Speter#define Cpu3dnow 0x4000 /* 3dnow! support required */ 29014125Speter#define CpuUnknown 0x8000 /* The CPU is unknown, be on the safe side. */ 29114125Speter 29214125Speter /* These flags are set by gas depending on the flag_code. */ 29314125Speter#define Cpu64 0x4000000 /* 64bit support required */ 29414125Speter#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ 29514125Speter 29614125Speter /* The default value for unknown CPUs - enable all features to avoid problems. */ 29714125Speter#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon) 29814125Speter 29914125Speter /* the bits in opcode_modifier are used to generate the final opcode from 30014125Speter the base_opcode. These bits also are used to detect alternate forms of 30114125Speter the same instruction */ 30214125Speter unsigned int opcode_modifier; 30314125Speter 30414125Speter /* opcode_modifier bits: */ 30514125Speter#define W 0x1 /* set if operands can be words or dwords 30614125Speter encoded the canonical way */ 30714125Speter#define D 0x2 /* D = 0 if Reg --> Regmem; 30814125Speter D = 1 if Regmem --> Reg: MUST BE 0x2 */ 30914125Speter#define Modrm 0x4 31014125Speter#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ 31114125Speter#define ShortForm 0x10 /* register is in low 3 bits of opcode */ 31214125Speter#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ 31314125Speter#define Jump 0x40 /* special case for jump insns. */ 31414125Speter#define JumpDword 0x80 /* call and jump */ 31514125Speter#define JumpByte 0x100 /* loop and jecxz */ 31614125Speter#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ 31714125Speter#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ 31814125Speter#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ 31914125Speter#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ 32014125Speter#define Size16 0x2000 /* needs size prefix if in 32-bit mode */ 32114125Speter#define Size32 0x4000 /* needs size prefix if in 16-bit mode */ 32214125Speter#define Size64 0x8000 /* needs size prefix if in 16-bit mode */ 32314125Speter#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ 32414125Speter#define DefaultSize 0x20000 /* default insn size depends on mode */ 32514125Speter#define No_bSuf 0x40000 /* b suffix on instruction illegal */ 32614125Speter#define No_wSuf 0x80000 /* w suffix on instruction illegal */ 32714125Speter#define No_lSuf 0x100000 /* l suffix on instruction illegal */ 32814125Speter#define No_sSuf 0x200000 /* s suffix on instruction illegal */ 32914125Speter#define No_qSuf 0x400000 /* q suffix on instruction illegal */ 33014125Speter#define No_xSuf 0x800000 /* x suffix on instruction illegal */ 33114125Speter#define FWait 0x1000000 /* instruction needs FWAIT */ 33214125Speter#define IsString 0x2000000 /* quick test for string instructions */ 33314125Speter#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ 33414125Speter#define IsPrefix 0x8000000 /* opcode is a prefix */ 33514125Speter#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ 33614125Speter#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ 33714125Speter#define Rex64 0x40000000 /* instruction require Rex64 prefix. */ 33814125Speter#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ 33914125Speter 34014125Speter /* operand_types[i] describes the type of operand i. This is made 34114125Speter by OR'ing together all of the possible type masks. (e.g. 34214125Speter 'operand_types[i] = Reg|Imm' specifies that operand i can be 34314125Speter either a register or an immediate operand. */ 34414125Speter unsigned int operand_types[3]; 34514125Speter 34614125Speter /* operand_types[i] bits */ 34714125Speter /* register */ 34814125Speter#define Reg8 0x1 /* 8 bit reg */ 34914125Speter#define Reg16 0x2 /* 16 bit reg */ 35014125Speter#define Reg32 0x4 /* 32 bit reg */ 35114125Speter#define Reg64 0x8 /* 64 bit reg */ 35214125Speter /* immediate */ 35314125Speter#define Imm8 0x10 /* 8 bit immediate */ 35414125Speter#define Imm8S 0x20 /* 8 bit immediate sign extended */ 35514125Speter#define Imm16 0x40 /* 16 bit immediate */ 35614125Speter#define Imm32 0x80 /* 32 bit immediate */ 35714125Speter#define Imm32S 0x100 /* 32 bit immediate sign extended */ 35814125Speter#define Imm64 0x200 /* 64 bit immediate */ 35914125Speter#define Imm1 0x400 /* 1 bit immediate */ 36014125Speter /* memory */ 36114125Speter#define BaseIndex 0x800 362 /* Disp8,16,32 are used in different ways, depending on the 363 instruction. For jumps, they specify the size of the PC relative 364 displacement, for baseindex type instructions, they specify the 365 size of the offset relative to the base register, and for memory 366 offset instructions such as `mov 1234,%al' they specify the size of 367 the offset relative to the segment base. */ 368#define Disp8 0x1000 /* 8 bit displacement */ 369#define Disp16 0x2000 /* 16 bit displacement */ 370#define Disp32 0x4000 /* 32 bit displacement */ 371#define Disp32S 0x8000 /* 32 bit signed displacement */ 372#define Disp64 0x10000 /* 64 bit displacement */ 373 /* specials */ 374#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ 375#define ShiftCount 0x40000 /* register to hold shift cound = cl */ 376#define Control 0x80000 /* Control register */ 377#define Debug 0x100000 /* Debug register */ 378#define Test 0x200000 /* Test register */ 379#define FloatReg 0x400000 /* Float register */ 380#define FloatAcc 0x800000 /* Float stack top %st(0) */ 381#define SReg2 0x1000000 /* 2 bit segment register */ 382#define SReg3 0x2000000 /* 3 bit segment register */ 383#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ 384#define JumpAbsolute 0x8000000 385#define RegMMX 0x10000000 /* MMX register */ 386#define RegXMM 0x20000000 /* XMM registers in PIII */ 387#define EsSeg 0x40000000 /* String insn operand with fixed es segment */ 388 389 /* InvMem is for instructions with a modrm byte that only allow a 390 general register encoding in the i.tm.mode and i.tm.regmem fields, 391 eg. control reg moves. They really ought to support a memory form, 392 but don't, so we add an InvMem flag to the register operand to 393 indicate that it should be encoded in the i.tm.regmem field. */ 394#define InvMem 0x80000000 395 396#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ 397#define WordReg (Reg16|Reg32|Reg64) 398#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) 399#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ 400#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ 401#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ 402#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ 403 /* The following aliases are defined because the opcode table 404 carefully specifies the allowed memory types for each instruction. 405 At the moment we can only tell a memory reference size by the 406 instruction suffix, so there's not much point in defining Mem8, 407 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use 408 the suffix directly to check memory operands. */ 409#define LLongMem AnyMem /* 64 bits (or more) */ 410#define LongMem AnyMem /* 32 bit memory ref */ 411#define ShortMem AnyMem /* 16 bit memory ref */ 412#define WordMem AnyMem /* 16 or 32 bit memory ref */ 413#define ByteMem AnyMem /* 8 bit memory ref */ 414} 415template; 416 417/* 418 'templates' is for grouping together 'template' structures for opcodes 419 of the same name. This is only used for storing the insns in the grand 420 ole hash table of insns. 421 The templates themselves start at START and range up to (but not including) 422 END. 423 */ 424typedef struct 425{ 426 const template *start; 427 const template *end; 428} 429templates; 430 431/* these are for register name --> number & type hash lookup */ 432typedef struct 433{ 434 char *reg_name; 435 unsigned int reg_type; 436 unsigned int reg_flags; 437#define RegRex 0x1 /* Extended register. */ 438#define RegRex64 0x2 /* Extended 8 bit register. */ 439 unsigned int reg_num; 440} 441reg_entry; 442 443typedef struct 444{ 445 char *seg_name; 446 unsigned int seg_prefix; 447} 448seg_entry; 449 450/* 386 operand encoding bytes: see 386 book for details of this. */ 451typedef struct 452{ 453 unsigned int regmem; /* codes register or memory operand */ 454 unsigned int reg; /* codes register operand (or extended opcode) */ 455 unsigned int mode; /* how to interpret regmem & reg */ 456} 457modrm_byte; 458 459/* x86-64 extension prefix. */ 460typedef struct 461 { 462 unsigned int mode64; 463 unsigned int extX; /* Used to extend modrm reg field. */ 464 unsigned int extY; /* Used to extend SIB index field. */ 465 unsigned int extZ; /* Used to extend modrm reg/mem, SIB base, modrm base fields. */ 466 unsigned int empty; /* Used to old-style byte registers to new style. */ 467 } 468rex_byte; 469 470/* 386 opcode byte to code indirect addressing. */ 471typedef struct 472{ 473 unsigned base; 474 unsigned index; 475 unsigned scale; 476} 477sib_byte; 478 479/* x86 arch names and features */ 480typedef struct 481{ 482 const char *name; /* arch name */ 483 unsigned int flags; /* cpu feature flags */ 484} 485arch_entry; 486 487/* The name of the global offset table generated by the compiler. Allow 488 this to be overridden if need be. */ 489#ifndef GLOBAL_OFFSET_TABLE_NAME 490#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" 491#endif 492 493#ifdef BFD_ASSEMBLER 494void i386_validate_fix PARAMS ((struct fix *)); 495#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP) 496#endif 497 498#endif /* TC_I386 */ 499 500#define md_operand(x) 501 502extern const struct relax_type md_relax_table[]; 503#define TC_GENERIC_RELAX_TABLE md_relax_table 504 505#define md_do_align(n, fill, len, max, around) \ 506if ((n) && !need_pass_2 \ 507 && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \ 508 && subseg_text_p (now_seg)) \ 509 { \ 510 frag_align_code ((n), (max)); \ 511 goto around; \ 512 } 513 514#define MAX_MEM_FOR_RS_ALIGN_CODE 15 515 516extern void i386_align_code PARAMS ((fragS *, int)); 517 518#define HANDLE_ALIGN(fragP) \ 519if (fragP->fr_type == rs_align_code) \ 520 i386_align_code (fragP, (fragP->fr_next->fr_address \ 521 - fragP->fr_address \ 522 - fragP->fr_fix)); 523 524/* call md_apply_fix3 with segment instead of md_apply_fix */ 525#define MD_APPLY_FIX3 526 527void i386_print_statistics PARAMS ((FILE *)); 528#define tc_print_statistics i386_print_statistics 529 530#define md_number_to_chars number_to_chars_littleendian 531 532#ifdef SCO_ELF 533#define tc_init_after_args() sco_id () 534extern void sco_id PARAMS ((void)); 535#endif 536 537#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ 538