tc-arm.c revision 218822
1/* tc-arm.c -- Assemble for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 3 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 6 Modified by David Taylor (dtaylor@armltd.co.uk) 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) 8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) 9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) 10 11 This file is part of GAS, the GNU Assembler. 12 13 GAS is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2, or (at your option) 16 any later version. 17 18 GAS is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with GAS; see the file COPYING. If not, write to the Free 25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 26 02110-1301, USA. */ 27 28#include <limits.h> 29#include <stdarg.h> 30#define NO_RELOC 0 31#include "as.h" 32#include "safe-ctype.h" 33#include "subsegs.h" 34#include "obstack.h" 35 36#include "opcode/arm.h" 37 38#ifdef OBJ_ELF 39#include "elf/arm.h" 40#include "dw2gencfi.h" 41#endif 42 43#include "dwarf2dbg.h" 44 45#define WARN_DEPRECATED 1 46 47#ifdef OBJ_ELF 48/* Must be at least the size of the largest unwind opcode (currently two). */ 49#define ARM_OPCODE_CHUNK_SIZE 8 50 51/* This structure holds the unwinding state. */ 52 53static struct 54{ 55 symbolS * proc_start; 56 symbolS * table_entry; 57 symbolS * personality_routine; 58 int personality_index; 59 /* The segment containing the function. */ 60 segT saved_seg; 61 subsegT saved_subseg; 62 /* Opcodes generated from this function. */ 63 unsigned char * opcodes; 64 int opcode_count; 65 int opcode_alloc; 66 /* The number of bytes pushed to the stack. */ 67 offsetT frame_size; 68 /* We don't add stack adjustment opcodes immediately so that we can merge 69 multiple adjustments. We can also omit the final adjustment 70 when using a frame pointer. */ 71 offsetT pending_offset; 72 /* These two fields are set by both unwind_movsp and unwind_setfp. They 73 hold the reg+offset to use when restoring sp from a frame pointer. */ 74 offsetT fp_offset; 75 int fp_reg; 76 /* Nonzero if an unwind_setfp directive has been seen. */ 77 unsigned fp_used:1; 78 /* Nonzero if the last opcode restores sp from fp_reg. */ 79 unsigned sp_restored:1; 80} unwind; 81 82/* Bit N indicates that an R_ARM_NONE relocation has been output for 83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be 84 emitted only once per section, to save unnecessary bloat. */ 85static unsigned int marked_pr_dependency = 0; 86 87#endif /* OBJ_ELF */ 88 89/* Results from operand parsing worker functions. */ 90 91typedef enum 92{ 93 PARSE_OPERAND_SUCCESS, 94 PARSE_OPERAND_FAIL, 95 PARSE_OPERAND_FAIL_NO_BACKTRACK 96} parse_operand_result; 97 98enum arm_float_abi 99{ 100 ARM_FLOAT_ABI_HARD, 101 ARM_FLOAT_ABI_SOFTFP, 102 ARM_FLOAT_ABI_SOFT 103}; 104 105/* Types of processor to assemble for. */ 106#ifndef CPU_DEFAULT 107#if defined __XSCALE__ 108#define CPU_DEFAULT ARM_ARCH_XSCALE 109#else 110#if defined __thumb__ 111#define CPU_DEFAULT ARM_ARCH_V5T 112#endif 113#endif 114#endif 115 116#ifndef FPU_DEFAULT 117# ifdef TE_LINUX 118# define FPU_DEFAULT FPU_ARCH_FPA 119# elif defined (TE_NetBSD) 120# ifdef OBJ_ELF 121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ 122# else 123 /* Legacy a.out format. */ 124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ 125# endif 126# elif defined (TE_VXWORKS) 127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ 128# else 129 /* For backwards compatibility, default to FPA. */ 130# define FPU_DEFAULT FPU_ARCH_FPA 131# endif 132#endif /* ifndef FPU_DEFAULT */ 133 134#define streq(a, b) (strcmp (a, b) == 0) 135 136static arm_feature_set cpu_variant; 137static arm_feature_set arm_arch_used; 138static arm_feature_set thumb_arch_used; 139 140/* Flags stored in private area of BFD structure. */ 141static int uses_apcs_26 = FALSE; 142static int atpcs = FALSE; 143static int support_interwork = FALSE; 144static int uses_apcs_float = FALSE; 145static int pic_code = FALSE; 146 147/* Variables that we set while parsing command-line options. Once all 148 options have been read we re-process these values to set the real 149 assembly flags. */ 150static const arm_feature_set *legacy_cpu = NULL; 151static const arm_feature_set *legacy_fpu = NULL; 152 153static const arm_feature_set *mcpu_cpu_opt = NULL; 154static const arm_feature_set *mcpu_fpu_opt = NULL; 155static const arm_feature_set *march_cpu_opt = NULL; 156static const arm_feature_set *march_fpu_opt = NULL; 157static const arm_feature_set *mfpu_opt = NULL; 158static const arm_feature_set *object_arch = NULL; 159 160/* Constants for known architecture features. */ 161static const arm_feature_set fpu_default = FPU_DEFAULT; 162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; 163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; 164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; 165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; 166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; 167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; 168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; 169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; 170 171#ifdef CPU_DEFAULT 172static const arm_feature_set cpu_default = CPU_DEFAULT; 173#endif 174 175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); 176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); 177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); 178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); 179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); 180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); 181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); 182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); 183static const arm_feature_set arm_ext_v4t_5 = 184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); 185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); 186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); 187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); 188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); 189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); 190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); 191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); 192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); 193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); 194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); 195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); 196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); 197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); 198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); 199 200static const arm_feature_set arm_arch_any = ARM_ANY; 201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); 202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; 203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; 204 205static const arm_feature_set arm_cext_iwmmxt2 = 206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2); 207static const arm_feature_set arm_cext_iwmmxt = 208 ARM_FEATURE (0, ARM_CEXT_IWMMXT); 209static const arm_feature_set arm_cext_xscale = 210 ARM_FEATURE (0, ARM_CEXT_XSCALE); 211static const arm_feature_set arm_cext_maverick = 212 ARM_FEATURE (0, ARM_CEXT_MAVERICK); 213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); 214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); 215static const arm_feature_set fpu_vfp_ext_v1xd = 216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD); 217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); 218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); 219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); 220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); 221static const arm_feature_set fpu_vfp_v3_or_neon_ext = 222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); 223 224static int mfloat_abi_opt = -1; 225/* Record user cpu selection for object attributes. */ 226static arm_feature_set selected_cpu = ARM_ARCH_NONE; 227/* Must be long enough to hold any of the names in arm_cpus. */ 228static char selected_cpu_name[16]; 229#ifdef OBJ_ELF 230# ifdef EABI_DEFAULT 231static int meabi_flags = EABI_DEFAULT; 232# else 233static int meabi_flags = EF_ARM_EABI_UNKNOWN; 234# endif 235 236bfd_boolean 237arm_is_eabi(void) 238{ 239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); 240} 241#endif 242 243#ifdef OBJ_ELF 244/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 245symbolS * GOT_symbol; 246#endif 247 248/* 0: assemble for ARM, 249 1: assemble for Thumb, 250 2: assemble for Thumb even though target CPU does not support thumb 251 instructions. */ 252static int thumb_mode = 0; 253 254/* If unified_syntax is true, we are processing the new unified 255 ARM/Thumb syntax. Important differences from the old ARM mode: 256 257 - Immediate operands do not require a # prefix. 258 - Conditional affixes always appear at the end of the 259 instruction. (For backward compatibility, those instructions 260 that formerly had them in the middle, continue to accept them 261 there.) 262 - The IT instruction may appear, and if it does is validated 263 against subsequent conditional affixes. It does not generate 264 machine code. 265 266 Important differences from the old Thumb mode: 267 268 - Immediate operands do not require a # prefix. 269 - Most of the V6T2 instructions are only available in unified mode. 270 - The .N and .W suffixes are recognized and honored (it is an error 271 if they cannot be honored). 272 - All instructions set the flags if and only if they have an 's' affix. 273 - Conditional affixes may be used. They are validated against 274 preceding IT instructions. Unlike ARM mode, you cannot use a 275 conditional affix except in the scope of an IT instruction. */ 276 277static bfd_boolean unified_syntax = FALSE; 278 279enum neon_el_type 280{ 281 NT_invtype, 282 NT_untyped, 283 NT_integer, 284 NT_float, 285 NT_poly, 286 NT_signed, 287 NT_unsigned 288}; 289 290struct neon_type_el 291{ 292 enum neon_el_type type; 293 unsigned size; 294}; 295 296#define NEON_MAX_TYPE_ELS 4 297 298struct neon_type 299{ 300 struct neon_type_el el[NEON_MAX_TYPE_ELS]; 301 unsigned elems; 302}; 303 304struct arm_it 305{ 306 const char * error; 307 unsigned long instruction; 308 int size; 309 int size_req; 310 int cond; 311 /* "uncond_value" is set to the value in place of the conditional field in 312 unconditional versions of the instruction, or -1 if nothing is 313 appropriate. */ 314 int uncond_value; 315 struct neon_type vectype; 316 /* Set to the opcode if the instruction needs relaxation. 317 Zero if the instruction is not relaxed. */ 318 unsigned long relax; 319 struct 320 { 321 bfd_reloc_code_real_type type; 322 expressionS exp; 323 int pc_rel; 324 } reloc; 325 326 struct 327 { 328 unsigned reg; 329 signed int imm; 330 struct neon_type_el vectype; 331 unsigned present : 1; /* Operand present. */ 332 unsigned isreg : 1; /* Operand was a register. */ 333 unsigned immisreg : 1; /* .imm field is a second register. */ 334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ 335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */ 336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */ 337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV 338 instructions. This allows us to disambiguate ARM <-> vector insns. */ 339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ 340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ 341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */ 342 unsigned issingle : 1; /* Operand is VFP single-precision register. */ 343 unsigned hasreloc : 1; /* Operand has relocation suffix. */ 344 unsigned writeback : 1; /* Operand has trailing ! */ 345 unsigned preind : 1; /* Preindexed address. */ 346 unsigned postind : 1; /* Postindexed address. */ 347 unsigned negative : 1; /* Index register was negated. */ 348 unsigned shifted : 1; /* Shift applied to operation. */ 349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ 350 } operands[6]; 351}; 352 353static struct arm_it inst; 354 355#define NUM_FLOAT_VALS 8 356 357const char * fp_const[] = 358{ 359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 360}; 361 362/* Number of littlenums required to hold an extended precision number. */ 363#define MAX_LITTLENUMS 6 364 365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; 366 367#define FAIL (-1) 368#define SUCCESS (0) 369 370#define SUFF_S 1 371#define SUFF_D 2 372#define SUFF_E 3 373#define SUFF_P 4 374 375#define CP_T_X 0x00008000 376#define CP_T_Y 0x00400000 377 378#define CONDS_BIT 0x00100000 379#define LOAD_BIT 0x00100000 380 381#define DOUBLE_LOAD_FLAG 0x00000001 382 383struct asm_cond 384{ 385 const char * template; 386 unsigned long value; 387}; 388 389#define COND_ALWAYS 0xE 390 391struct asm_psr 392{ 393 const char *template; 394 unsigned long field; 395}; 396 397struct asm_barrier_opt 398{ 399 const char *template; 400 unsigned long value; 401}; 402 403/* The bit that distinguishes CPSR and SPSR. */ 404#define SPSR_BIT (1 << 22) 405 406/* The individual PSR flag bits. */ 407#define PSR_c (1 << 16) 408#define PSR_x (1 << 17) 409#define PSR_s (1 << 18) 410#define PSR_f (1 << 19) 411 412struct reloc_entry 413{ 414 char *name; 415 bfd_reloc_code_real_type reloc; 416}; 417 418enum vfp_reg_pos 419{ 420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, 421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn 422}; 423 424enum vfp_ldstm_type 425{ 426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX 427}; 428 429/* Bits for DEFINED field in neon_typed_alias. */ 430#define NTA_HASTYPE 1 431#define NTA_HASINDEX 2 432 433struct neon_typed_alias 434{ 435 unsigned char defined; 436 unsigned char index; 437 struct neon_type_el eltype; 438}; 439 440/* ARM register categories. This includes coprocessor numbers and various 441 architecture extensions' registers. */ 442enum arm_reg_type 443{ 444 REG_TYPE_RN, 445 REG_TYPE_CP, 446 REG_TYPE_CN, 447 REG_TYPE_FN, 448 REG_TYPE_VFS, 449 REG_TYPE_VFD, 450 REG_TYPE_NQ, 451 REG_TYPE_VFSD, 452 REG_TYPE_NDQ, 453 REG_TYPE_NSDQ, 454 REG_TYPE_VFC, 455 REG_TYPE_MVF, 456 REG_TYPE_MVD, 457 REG_TYPE_MVFX, 458 REG_TYPE_MVDX, 459 REG_TYPE_MVAX, 460 REG_TYPE_DSPSC, 461 REG_TYPE_MMXWR, 462 REG_TYPE_MMXWC, 463 REG_TYPE_MMXWCG, 464 REG_TYPE_XSCALE, 465}; 466 467/* Structure for a hash table entry for a register. 468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra 469 information which states whether a vector type or index is specified (for a 470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */ 471struct reg_entry 472{ 473 const char *name; 474 unsigned char number; 475 unsigned char type; 476 unsigned char builtin; 477 struct neon_typed_alias *neon; 478}; 479 480/* Diagnostics used when we don't get a register of the expected type. */ 481const char *const reg_expected_msgs[] = 482{ 483 N_("ARM register expected"), 484 N_("bad or missing co-processor number"), 485 N_("co-processor register expected"), 486 N_("FPA register expected"), 487 N_("VFP single precision register expected"), 488 N_("VFP/Neon double precision register expected"), 489 N_("Neon quad precision register expected"), 490 N_("VFP single or double precision register expected"), 491 N_("Neon double or quad precision register expected"), 492 N_("VFP single, double or Neon quad precision register expected"), 493 N_("VFP system register expected"), 494 N_("Maverick MVF register expected"), 495 N_("Maverick MVD register expected"), 496 N_("Maverick MVFX register expected"), 497 N_("Maverick MVDX register expected"), 498 N_("Maverick MVAX register expected"), 499 N_("Maverick DSPSC register expected"), 500 N_("iWMMXt data register expected"), 501 N_("iWMMXt control register expected"), 502 N_("iWMMXt scalar register expected"), 503 N_("XScale accumulator register expected"), 504}; 505 506/* Some well known registers that we refer to directly elsewhere. */ 507#define REG_SP 13 508#define REG_LR 14 509#define REG_PC 15 510 511/* ARM instructions take 4bytes in the object file, Thumb instructions 512 take 2: */ 513#define INSN_SIZE 4 514 515struct asm_opcode 516{ 517 /* Basic string to match. */ 518 const char *template; 519 520 /* Parameters to instruction. */ 521 unsigned char operands[8]; 522 523 /* Conditional tag - see opcode_lookup. */ 524 unsigned int tag : 4; 525 526 /* Basic instruction code. */ 527 unsigned int avalue : 28; 528 529 /* Thumb-format instruction code. */ 530 unsigned int tvalue; 531 532 /* Which architecture variant provides this instruction. */ 533 const arm_feature_set *avariant; 534 const arm_feature_set *tvariant; 535 536 /* Function to call to encode instruction in ARM format. */ 537 void (* aencode) (void); 538 539 /* Function to call to encode instruction in Thumb format. */ 540 void (* tencode) (void); 541}; 542 543/* Defines for various bits that we will want to toggle. */ 544#define INST_IMMEDIATE 0x02000000 545#define OFFSET_REG 0x02000000 546#define HWOFFSET_IMM 0x00400000 547#define SHIFT_BY_REG 0x00000010 548#define PRE_INDEX 0x01000000 549#define INDEX_UP 0x00800000 550#define WRITE_BACK 0x00200000 551#define LDM_TYPE_2_OR_3 0x00400000 552#define CPSI_MMOD 0x00020000 553 554#define LITERAL_MASK 0xf000f000 555#define OPCODE_MASK 0xfe1fffff 556#define V4_STR_BIT 0x00000020 557 558#define T2_SUBS_PC_LR 0xf3de8f00 559 560#define DATA_OP_SHIFT 21 561 562#define T2_OPCODE_MASK 0xfe1fffff 563#define T2_DATA_OP_SHIFT 21 564 565/* Codes to distinguish the arithmetic instructions. */ 566#define OPCODE_AND 0 567#define OPCODE_EOR 1 568#define OPCODE_SUB 2 569#define OPCODE_RSB 3 570#define OPCODE_ADD 4 571#define OPCODE_ADC 5 572#define OPCODE_SBC 6 573#define OPCODE_RSC 7 574#define OPCODE_TST 8 575#define OPCODE_TEQ 9 576#define OPCODE_CMP 10 577#define OPCODE_CMN 11 578#define OPCODE_ORR 12 579#define OPCODE_MOV 13 580#define OPCODE_BIC 14 581#define OPCODE_MVN 15 582 583#define T2_OPCODE_AND 0 584#define T2_OPCODE_BIC 1 585#define T2_OPCODE_ORR 2 586#define T2_OPCODE_ORN 3 587#define T2_OPCODE_EOR 4 588#define T2_OPCODE_ADD 8 589#define T2_OPCODE_ADC 10 590#define T2_OPCODE_SBC 11 591#define T2_OPCODE_SUB 13 592#define T2_OPCODE_RSB 14 593 594#define T_OPCODE_MUL 0x4340 595#define T_OPCODE_TST 0x4200 596#define T_OPCODE_CMN 0x42c0 597#define T_OPCODE_NEG 0x4240 598#define T_OPCODE_MVN 0x43c0 599 600#define T_OPCODE_ADD_R3 0x1800 601#define T_OPCODE_SUB_R3 0x1a00 602#define T_OPCODE_ADD_HI 0x4400 603#define T_OPCODE_ADD_ST 0xb000 604#define T_OPCODE_SUB_ST 0xb080 605#define T_OPCODE_ADD_SP 0xa800 606#define T_OPCODE_ADD_PC 0xa000 607#define T_OPCODE_ADD_I8 0x3000 608#define T_OPCODE_SUB_I8 0x3800 609#define T_OPCODE_ADD_I3 0x1c00 610#define T_OPCODE_SUB_I3 0x1e00 611 612#define T_OPCODE_ASR_R 0x4100 613#define T_OPCODE_LSL_R 0x4080 614#define T_OPCODE_LSR_R 0x40c0 615#define T_OPCODE_ROR_R 0x41c0 616#define T_OPCODE_ASR_I 0x1000 617#define T_OPCODE_LSL_I 0x0000 618#define T_OPCODE_LSR_I 0x0800 619 620#define T_OPCODE_MOV_I8 0x2000 621#define T_OPCODE_CMP_I8 0x2800 622#define T_OPCODE_CMP_LR 0x4280 623#define T_OPCODE_MOV_HR 0x4600 624#define T_OPCODE_CMP_HR 0x4500 625 626#define T_OPCODE_LDR_PC 0x4800 627#define T_OPCODE_LDR_SP 0x9800 628#define T_OPCODE_STR_SP 0x9000 629#define T_OPCODE_LDR_IW 0x6800 630#define T_OPCODE_STR_IW 0x6000 631#define T_OPCODE_LDR_IH 0x8800 632#define T_OPCODE_STR_IH 0x8000 633#define T_OPCODE_LDR_IB 0x7800 634#define T_OPCODE_STR_IB 0x7000 635#define T_OPCODE_LDR_RW 0x5800 636#define T_OPCODE_STR_RW 0x5000 637#define T_OPCODE_LDR_RH 0x5a00 638#define T_OPCODE_STR_RH 0x5200 639#define T_OPCODE_LDR_RB 0x5c00 640#define T_OPCODE_STR_RB 0x5400 641 642#define T_OPCODE_PUSH 0xb400 643#define T_OPCODE_POP 0xbc00 644 645#define T_OPCODE_BRANCH 0xe000 646 647#define THUMB_SIZE 2 /* Size of thumb instruction. */ 648#define THUMB_PP_PC_LR 0x0100 649#define THUMB_LOAD_BIT 0x0800 650#define THUMB2_LOAD_BIT 0x00100000 651 652#define BAD_ARGS _("bad arguments to instruction") 653#define BAD_PC _("r15 not allowed here") 654#define BAD_COND _("instruction cannot be conditional") 655#define BAD_OVERLAP _("registers may not be the same") 656#define BAD_HIREG _("lo register required") 657#define BAD_THUMB32 _("instruction not supported in Thumb16 mode") 658#define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); 659#define BAD_BRANCH _("branch must be last instruction in IT block") 660#define BAD_NOT_IT _("instruction not allowed in IT block") 661#define BAD_FPU _("selected FPU does not support instruction") 662 663static struct hash_control *arm_ops_hsh; 664static struct hash_control *arm_cond_hsh; 665static struct hash_control *arm_shift_hsh; 666static struct hash_control *arm_psr_hsh; 667static struct hash_control *arm_v7m_psr_hsh; 668static struct hash_control *arm_reg_hsh; 669static struct hash_control *arm_reloc_hsh; 670static struct hash_control *arm_barrier_opt_hsh; 671 672/* Stuff needed to resolve the label ambiguity 673 As: 674 ... 675 label: <insn> 676 may differ from: 677 ... 678 label: 679 <insn> 680*/ 681 682symbolS * last_label_seen; 683static int label_is_thumb_function_name = FALSE; 684 685/* Literal pool structure. Held on a per-section 686 and per-sub-section basis. */ 687 688#define MAX_LITERAL_POOL_SIZE 1024 689typedef struct literal_pool 690{ 691 expressionS literals [MAX_LITERAL_POOL_SIZE]; 692 unsigned int next_free_entry; 693 unsigned int id; 694 symbolS * symbol; 695 segT section; 696 subsegT sub_section; 697 struct literal_pool * next; 698} literal_pool; 699 700/* Pointer to a linked list of literal pools. */ 701literal_pool * list_of_pools = NULL; 702 703/* State variables for IT block handling. */ 704static bfd_boolean current_it_mask = 0; 705static int current_cc; 706 707 708/* Pure syntax. */ 709 710/* This array holds the chars that always start a comment. If the 711 pre-processor is disabled, these aren't very useful. */ 712const char comment_chars[] = "@"; 713 714/* This array holds the chars that only start a comment at the beginning of 715 a line. If the line seems to have the form '# 123 filename' 716 .line and .file directives will appear in the pre-processed output. */ 717/* Note that input_file.c hand checks for '#' at the beginning of the 718 first line of the input file. This is because the compiler outputs 719 #NO_APP at the beginning of its output. */ 720/* Also note that comments like this one will always work. */ 721const char line_comment_chars[] = "#"; 722 723const char line_separator_chars[] = ";"; 724 725/* Chars that can be used to separate mant 726 from exp in floating point numbers. */ 727const char EXP_CHARS[] = "eE"; 728 729/* Chars that mean this number is a floating point constant. */ 730/* As in 0f12.456 */ 731/* or 0d1.2345e12 */ 732 733const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 734 735/* Prefix characters that indicate the start of an immediate 736 value. */ 737#define is_immediate_prefix(C) ((C) == '#' || (C) == '$') 738 739/* Separator character handling. */ 740 741#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) 742 743static inline int 744skip_past_char (char ** str, char c) 745{ 746 if (**str == c) 747 { 748 (*str)++; 749 return SUCCESS; 750 } 751 else 752 return FAIL; 753} 754#define skip_past_comma(str) skip_past_char (str, ',') 755 756/* Arithmetic expressions (possibly involving symbols). */ 757 758/* Return TRUE if anything in the expression is a bignum. */ 759 760static int 761walk_no_bignums (symbolS * sp) 762{ 763 if (symbol_get_value_expression (sp)->X_op == O_big) 764 return 1; 765 766 if (symbol_get_value_expression (sp)->X_add_symbol) 767 { 768 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) 769 || (symbol_get_value_expression (sp)->X_op_symbol 770 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); 771 } 772 773 return 0; 774} 775 776static int in_my_get_expression = 0; 777 778/* Third argument to my_get_expression. */ 779#define GE_NO_PREFIX 0 780#define GE_IMM_PREFIX 1 781#define GE_OPT_PREFIX 2 782/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) 783 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ 784#define GE_OPT_PREFIX_BIG 3 785 786static int 787my_get_expression (expressionS * ep, char ** str, int prefix_mode) 788{ 789 char * save_in; 790 segT seg; 791 792 /* In unified syntax, all prefixes are optional. */ 793 if (unified_syntax) 794 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode 795 : GE_OPT_PREFIX; 796 797 switch (prefix_mode) 798 { 799 case GE_NO_PREFIX: break; 800 case GE_IMM_PREFIX: 801 if (!is_immediate_prefix (**str)) 802 { 803 inst.error = _("immediate expression requires a # prefix"); 804 return FAIL; 805 } 806 (*str)++; 807 break; 808 case GE_OPT_PREFIX: 809 case GE_OPT_PREFIX_BIG: 810 if (is_immediate_prefix (**str)) 811 (*str)++; 812 break; 813 default: abort (); 814 } 815 816 memset (ep, 0, sizeof (expressionS)); 817 818 save_in = input_line_pointer; 819 input_line_pointer = *str; 820 in_my_get_expression = 1; 821 seg = expression (ep); 822 in_my_get_expression = 0; 823 824 if (ep->X_op == O_illegal) 825 { 826 /* We found a bad expression in md_operand(). */ 827 *str = input_line_pointer; 828 input_line_pointer = save_in; 829 if (inst.error == NULL) 830 inst.error = _("bad expression"); 831 return 1; 832 } 833 834#ifdef OBJ_AOUT 835 if (seg != absolute_section 836 && seg != text_section 837 && seg != data_section 838 && seg != bss_section 839 && seg != undefined_section) 840 { 841 inst.error = _("bad segment"); 842 *str = input_line_pointer; 843 input_line_pointer = save_in; 844 return 1; 845 } 846#endif 847 848 /* Get rid of any bignums now, so that we don't generate an error for which 849 we can't establish a line number later on. Big numbers are never valid 850 in instructions, which is where this routine is always called. */ 851 if (prefix_mode != GE_OPT_PREFIX_BIG 852 && (ep->X_op == O_big 853 || (ep->X_add_symbol 854 && (walk_no_bignums (ep->X_add_symbol) 855 || (ep->X_op_symbol 856 && walk_no_bignums (ep->X_op_symbol)))))) 857 { 858 inst.error = _("invalid constant"); 859 *str = input_line_pointer; 860 input_line_pointer = save_in; 861 return 1; 862 } 863 864 *str = input_line_pointer; 865 input_line_pointer = save_in; 866 return 0; 867} 868 869/* Turn a string in input_line_pointer into a floating point constant 870 of type TYPE, and store the appropriate bytes in *LITP. The number 871 of LITTLENUMS emitted is stored in *SIZEP. An error message is 872 returned, or NULL on OK. 873 874 Note that fp constants aren't represent in the normal way on the ARM. 875 In big endian mode, things are as expected. However, in little endian 876 mode fp constants are big-endian word-wise, and little-endian byte-wise 877 within the words. For example, (double) 1.1 in big endian mode is 878 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is 879 the byte sequence 99 99 f1 3f 9a 99 99 99. 880 881 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ 882 883char * 884md_atof (int type, char * litP, int * sizeP) 885{ 886 int prec; 887 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 888 char *t; 889 int i; 890 891 switch (type) 892 { 893 case 'f': 894 case 'F': 895 case 's': 896 case 'S': 897 prec = 2; 898 break; 899 900 case 'd': 901 case 'D': 902 case 'r': 903 case 'R': 904 prec = 4; 905 break; 906 907 case 'x': 908 case 'X': 909 prec = 6; 910 break; 911 912 case 'p': 913 case 'P': 914 prec = 6; 915 break; 916 917 default: 918 *sizeP = 0; 919 return _("bad call to MD_ATOF()"); 920 } 921 922 t = atof_ieee (input_line_pointer, type, words); 923 if (t) 924 input_line_pointer = t; 925 *sizeP = prec * 2; 926 927 if (target_big_endian) 928 { 929 for (i = 0; i < prec; i++) 930 { 931 md_number_to_chars (litP, (valueT) words[i], 2); 932 litP += 2; 933 } 934 } 935 else 936 { 937 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 938 for (i = prec - 1; i >= 0; i--) 939 { 940 md_number_to_chars (litP, (valueT) words[i], 2); 941 litP += 2; 942 } 943 else 944 /* For a 4 byte float the order of elements in `words' is 1 0. 945 For an 8 byte float the order is 1 0 3 2. */ 946 for (i = 0; i < prec; i += 2) 947 { 948 md_number_to_chars (litP, (valueT) words[i + 1], 2); 949 md_number_to_chars (litP + 2, (valueT) words[i], 2); 950 litP += 4; 951 } 952 } 953 954 return 0; 955} 956 957/* We handle all bad expressions here, so that we can report the faulty 958 instruction in the error message. */ 959void 960md_operand (expressionS * expr) 961{ 962 if (in_my_get_expression) 963 expr->X_op = O_illegal; 964} 965 966/* Immediate values. */ 967 968/* Generic immediate-value read function for use in directives. 969 Accepts anything that 'expression' can fold to a constant. 970 *val receives the number. */ 971#ifdef OBJ_ELF 972static int 973immediate_for_directive (int *val) 974{ 975 expressionS exp; 976 exp.X_op = O_illegal; 977 978 if (is_immediate_prefix (*input_line_pointer)) 979 { 980 input_line_pointer++; 981 expression (&exp); 982 } 983 984 if (exp.X_op != O_constant) 985 { 986 as_bad (_("expected #constant")); 987 ignore_rest_of_line (); 988 return FAIL; 989 } 990 *val = exp.X_add_number; 991 return SUCCESS; 992} 993#endif 994 995/* Register parsing. */ 996 997/* Generic register parser. CCP points to what should be the 998 beginning of a register name. If it is indeed a valid register 999 name, advance CCP over it and return the reg_entry structure; 1000 otherwise return NULL. Does not issue diagnostics. */ 1001 1002static struct reg_entry * 1003arm_reg_parse_multi (char **ccp) 1004{ 1005 char *start = *ccp; 1006 char *p; 1007 struct reg_entry *reg; 1008 1009#ifdef REGISTER_PREFIX 1010 if (*start != REGISTER_PREFIX) 1011 return NULL; 1012 start++; 1013#endif 1014#ifdef OPTIONAL_REGISTER_PREFIX 1015 if (*start == OPTIONAL_REGISTER_PREFIX) 1016 start++; 1017#endif 1018 1019 p = start; 1020 if (!ISALPHA (*p) || !is_name_beginner (*p)) 1021 return NULL; 1022 1023 do 1024 p++; 1025 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); 1026 1027 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); 1028 1029 if (!reg) 1030 return NULL; 1031 1032 *ccp = p; 1033 return reg; 1034} 1035 1036static int 1037arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, 1038 enum arm_reg_type type) 1039{ 1040 /* Alternative syntaxes are accepted for a few register classes. */ 1041 switch (type) 1042 { 1043 case REG_TYPE_MVF: 1044 case REG_TYPE_MVD: 1045 case REG_TYPE_MVFX: 1046 case REG_TYPE_MVDX: 1047 /* Generic coprocessor register names are allowed for these. */ 1048 if (reg && reg->type == REG_TYPE_CN) 1049 return reg->number; 1050 break; 1051 1052 case REG_TYPE_CP: 1053 /* For backward compatibility, a bare number is valid here. */ 1054 { 1055 unsigned long processor = strtoul (start, ccp, 10); 1056 if (*ccp != start && processor <= 15) 1057 return processor; 1058 } 1059 1060 case REG_TYPE_MMXWC: 1061 /* WC includes WCG. ??? I'm not sure this is true for all 1062 instructions that take WC registers. */ 1063 if (reg && reg->type == REG_TYPE_MMXWCG) 1064 return reg->number; 1065 break; 1066 1067 default: 1068 break; 1069 } 1070 1071 return FAIL; 1072} 1073 1074/* As arm_reg_parse_multi, but the register must be of type TYPE, and the 1075 return value is the register number or FAIL. */ 1076 1077static int 1078arm_reg_parse (char **ccp, enum arm_reg_type type) 1079{ 1080 char *start = *ccp; 1081 struct reg_entry *reg = arm_reg_parse_multi (ccp); 1082 int ret; 1083 1084 /* Do not allow a scalar (reg+index) to parse as a register. */ 1085 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) 1086 return FAIL; 1087 1088 if (reg && reg->type == type) 1089 return reg->number; 1090 1091 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) 1092 return ret; 1093 1094 *ccp = start; 1095 return FAIL; 1096} 1097 1098/* Parse a Neon type specifier. *STR should point at the leading '.' 1099 character. Does no verification at this stage that the type fits the opcode 1100 properly. E.g., 1101 1102 .i32.i32.s16 1103 .s32.f32 1104 .u16 1105 1106 Can all be legally parsed by this function. 1107 1108 Fills in neon_type struct pointer with parsed information, and updates STR 1109 to point after the parsed type specifier. Returns SUCCESS if this was a legal 1110 type, FAIL if not. */ 1111 1112static int 1113parse_neon_type (struct neon_type *type, char **str) 1114{ 1115 char *ptr = *str; 1116 1117 if (type) 1118 type->elems = 0; 1119 1120 while (type->elems < NEON_MAX_TYPE_ELS) 1121 { 1122 enum neon_el_type thistype = NT_untyped; 1123 unsigned thissize = -1u; 1124 1125 if (*ptr != '.') 1126 break; 1127 1128 ptr++; 1129 1130 /* Just a size without an explicit type. */ 1131 if (ISDIGIT (*ptr)) 1132 goto parsesize; 1133 1134 switch (TOLOWER (*ptr)) 1135 { 1136 case 'i': thistype = NT_integer; break; 1137 case 'f': thistype = NT_float; break; 1138 case 'p': thistype = NT_poly; break; 1139 case 's': thistype = NT_signed; break; 1140 case 'u': thistype = NT_unsigned; break; 1141 case 'd': 1142 thistype = NT_float; 1143 thissize = 64; 1144 ptr++; 1145 goto done; 1146 default: 1147 as_bad (_("unexpected character `%c' in type specifier"), *ptr); 1148 return FAIL; 1149 } 1150 1151 ptr++; 1152 1153 /* .f is an abbreviation for .f32. */ 1154 if (thistype == NT_float && !ISDIGIT (*ptr)) 1155 thissize = 32; 1156 else 1157 { 1158 parsesize: 1159 thissize = strtoul (ptr, &ptr, 10); 1160 1161 if (thissize != 8 && thissize != 16 && thissize != 32 1162 && thissize != 64) 1163 { 1164 as_bad (_("bad size %d in type specifier"), thissize); 1165 return FAIL; 1166 } 1167 } 1168 1169 done: 1170 if (type) 1171 { 1172 type->el[type->elems].type = thistype; 1173 type->el[type->elems].size = thissize; 1174 type->elems++; 1175 } 1176 } 1177 1178 /* Empty/missing type is not a successful parse. */ 1179 if (type->elems == 0) 1180 return FAIL; 1181 1182 *str = ptr; 1183 1184 return SUCCESS; 1185} 1186 1187/* Errors may be set multiple times during parsing or bit encoding 1188 (particularly in the Neon bits), but usually the earliest error which is set 1189 will be the most meaningful. Avoid overwriting it with later (cascading) 1190 errors by calling this function. */ 1191 1192static void 1193first_error (const char *err) 1194{ 1195 if (!inst.error) 1196 inst.error = err; 1197} 1198 1199/* Parse a single type, e.g. ".s32", leading period included. */ 1200static int 1201parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) 1202{ 1203 char *str = *ccp; 1204 struct neon_type optype; 1205 1206 if (*str == '.') 1207 { 1208 if (parse_neon_type (&optype, &str) == SUCCESS) 1209 { 1210 if (optype.elems == 1) 1211 *vectype = optype.el[0]; 1212 else 1213 { 1214 first_error (_("only one type should be specified for operand")); 1215 return FAIL; 1216 } 1217 } 1218 else 1219 { 1220 first_error (_("vector type expected")); 1221 return FAIL; 1222 } 1223 } 1224 else 1225 return FAIL; 1226 1227 *ccp = str; 1228 1229 return SUCCESS; 1230} 1231 1232/* Special meanings for indices (which have a range of 0-7), which will fit into 1233 a 4-bit integer. */ 1234 1235#define NEON_ALL_LANES 15 1236#define NEON_INTERLEAVE_LANES 14 1237 1238/* Parse either a register or a scalar, with an optional type. Return the 1239 register number, and optionally fill in the actual type of the register 1240 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and 1241 type/index information in *TYPEINFO. */ 1242 1243static int 1244parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, 1245 enum arm_reg_type *rtype, 1246 struct neon_typed_alias *typeinfo) 1247{ 1248 char *str = *ccp; 1249 struct reg_entry *reg = arm_reg_parse_multi (&str); 1250 struct neon_typed_alias atype; 1251 struct neon_type_el parsetype; 1252 1253 atype.defined = 0; 1254 atype.index = -1; 1255 atype.eltype.type = NT_invtype; 1256 atype.eltype.size = -1; 1257 1258 /* Try alternate syntax for some types of register. Note these are mutually 1259 exclusive with the Neon syntax extensions. */ 1260 if (reg == NULL) 1261 { 1262 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); 1263 if (altreg != FAIL) 1264 *ccp = str; 1265 if (typeinfo) 1266 *typeinfo = atype; 1267 return altreg; 1268 } 1269 1270 /* Undo polymorphism when a set of register types may be accepted. */ 1271 if ((type == REG_TYPE_NDQ 1272 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) 1273 || (type == REG_TYPE_VFSD 1274 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) 1275 || (type == REG_TYPE_NSDQ 1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD 1277 || reg->type == REG_TYPE_NQ)) 1278 || (type == REG_TYPE_MMXWC 1279 && (reg->type == REG_TYPE_MMXWCG))) 1280 type = reg->type; 1281 1282 if (type != reg->type) 1283 return FAIL; 1284 1285 if (reg->neon) 1286 atype = *reg->neon; 1287 1288 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) 1289 { 1290 if ((atype.defined & NTA_HASTYPE) != 0) 1291 { 1292 first_error (_("can't redefine type for operand")); 1293 return FAIL; 1294 } 1295 atype.defined |= NTA_HASTYPE; 1296 atype.eltype = parsetype; 1297 } 1298 1299 if (skip_past_char (&str, '[') == SUCCESS) 1300 { 1301 if (type != REG_TYPE_VFD) 1302 { 1303 first_error (_("only D registers may be indexed")); 1304 return FAIL; 1305 } 1306 1307 if ((atype.defined & NTA_HASINDEX) != 0) 1308 { 1309 first_error (_("can't change index for operand")); 1310 return FAIL; 1311 } 1312 1313 atype.defined |= NTA_HASINDEX; 1314 1315 if (skip_past_char (&str, ']') == SUCCESS) 1316 atype.index = NEON_ALL_LANES; 1317 else 1318 { 1319 expressionS exp; 1320 1321 my_get_expression (&exp, &str, GE_NO_PREFIX); 1322 1323 if (exp.X_op != O_constant) 1324 { 1325 first_error (_("constant expression required")); 1326 return FAIL; 1327 } 1328 1329 if (skip_past_char (&str, ']') == FAIL) 1330 return FAIL; 1331 1332 atype.index = exp.X_add_number; 1333 } 1334 } 1335 1336 if (typeinfo) 1337 *typeinfo = atype; 1338 1339 if (rtype) 1340 *rtype = type; 1341 1342 *ccp = str; 1343 1344 return reg->number; 1345} 1346 1347/* Like arm_reg_parse, but allow allow the following extra features: 1348 - If RTYPE is non-zero, return the (possibly restricted) type of the 1349 register (e.g. Neon double or quad reg when either has been requested). 1350 - If this is a Neon vector type with additional type information, fill 1351 in the struct pointed to by VECTYPE (if non-NULL). 1352 This function will fault on encountering a scalar. 1353*/ 1354 1355static int 1356arm_typed_reg_parse (char **ccp, enum arm_reg_type type, 1357 enum arm_reg_type *rtype, struct neon_type_el *vectype) 1358{ 1359 struct neon_typed_alias atype; 1360 char *str = *ccp; 1361 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); 1362 1363 if (reg == FAIL) 1364 return FAIL; 1365 1366 /* Do not allow a scalar (reg+index) to parse as a register. */ 1367 if ((atype.defined & NTA_HASINDEX) != 0) 1368 { 1369 first_error (_("register operand expected, but got scalar")); 1370 return FAIL; 1371 } 1372 1373 if (vectype) 1374 *vectype = atype.eltype; 1375 1376 *ccp = str; 1377 1378 return reg; 1379} 1380 1381#define NEON_SCALAR_REG(X) ((X) >> 4) 1382#define NEON_SCALAR_INDEX(X) ((X) & 15) 1383 1384/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't 1385 have enough information to be able to do a good job bounds-checking. So, we 1386 just do easy checks here, and do further checks later. */ 1387 1388static int 1389parse_scalar (char **ccp, int elsize, struct neon_type_el *type) 1390{ 1391 int reg; 1392 char *str = *ccp; 1393 struct neon_typed_alias atype; 1394 1395 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); 1396 1397 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) 1398 return FAIL; 1399 1400 if (atype.index == NEON_ALL_LANES) 1401 { 1402 first_error (_("scalar must have an index")); 1403 return FAIL; 1404 } 1405 else if (atype.index >= 64 / elsize) 1406 { 1407 first_error (_("scalar index out of range")); 1408 return FAIL; 1409 } 1410 1411 if (type) 1412 *type = atype.eltype; 1413 1414 *ccp = str; 1415 1416 return reg * 16 + atype.index; 1417} 1418 1419/* Parse an ARM register list. Returns the bitmask, or FAIL. */ 1420static long 1421parse_reg_list (char ** strp) 1422{ 1423 char * str = * strp; 1424 long range = 0; 1425 int another_range; 1426 1427 /* We come back here if we get ranges concatenated by '+' or '|'. */ 1428 do 1429 { 1430 another_range = 0; 1431 1432 if (*str == '{') 1433 { 1434 int in_range = 0; 1435 int cur_reg = -1; 1436 1437 str++; 1438 do 1439 { 1440 int reg; 1441 1442 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) 1443 { 1444 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 1445 return FAIL; 1446 } 1447 1448 if (in_range) 1449 { 1450 int i; 1451 1452 if (reg <= cur_reg) 1453 { 1454 first_error (_("bad range in register list")); 1455 return FAIL; 1456 } 1457 1458 for (i = cur_reg + 1; i < reg; i++) 1459 { 1460 if (range & (1 << i)) 1461 as_tsktsk 1462 (_("Warning: duplicated register (r%d) in register list"), 1463 i); 1464 else 1465 range |= 1 << i; 1466 } 1467 in_range = 0; 1468 } 1469 1470 if (range & (1 << reg)) 1471 as_tsktsk (_("Warning: duplicated register (r%d) in register list"), 1472 reg); 1473 else if (reg <= cur_reg) 1474 as_tsktsk (_("Warning: register range not in ascending order")); 1475 1476 range |= 1 << reg; 1477 cur_reg = reg; 1478 } 1479 while (skip_past_comma (&str) != FAIL 1480 || (in_range = 1, *str++ == '-')); 1481 str--; 1482 1483 if (*str++ != '}') 1484 { 1485 first_error (_("missing `}'")); 1486 return FAIL; 1487 } 1488 } 1489 else 1490 { 1491 expressionS expr; 1492 1493 if (my_get_expression (&expr, &str, GE_NO_PREFIX)) 1494 return FAIL; 1495 1496 if (expr.X_op == O_constant) 1497 { 1498 if (expr.X_add_number 1499 != (expr.X_add_number & 0x0000ffff)) 1500 { 1501 inst.error = _("invalid register mask"); 1502 return FAIL; 1503 } 1504 1505 if ((range & expr.X_add_number) != 0) 1506 { 1507 int regno = range & expr.X_add_number; 1508 1509 regno &= -regno; 1510 regno = (1 << regno) - 1; 1511 as_tsktsk 1512 (_("Warning: duplicated register (r%d) in register list"), 1513 regno); 1514 } 1515 1516 range |= expr.X_add_number; 1517 } 1518 else 1519 { 1520 if (inst.reloc.type != 0) 1521 { 1522 inst.error = _("expression too complex"); 1523 return FAIL; 1524 } 1525 1526 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); 1527 inst.reloc.type = BFD_RELOC_ARM_MULTI; 1528 inst.reloc.pc_rel = 0; 1529 } 1530 } 1531 1532 if (*str == '|' || *str == '+') 1533 { 1534 str++; 1535 another_range = 1; 1536 } 1537 } 1538 while (another_range); 1539 1540 *strp = str; 1541 return range; 1542} 1543 1544/* Types of registers in a list. */ 1545 1546enum reg_list_els 1547{ 1548 REGLIST_VFP_S, 1549 REGLIST_VFP_D, 1550 REGLIST_NEON_D 1551}; 1552 1553/* Parse a VFP register list. If the string is invalid return FAIL. 1554 Otherwise return the number of registers, and set PBASE to the first 1555 register. Parses registers of type ETYPE. 1556 If REGLIST_NEON_D is used, several syntax enhancements are enabled: 1557 - Q registers can be used to specify pairs of D registers 1558 - { } can be omitted from around a singleton register list 1559 FIXME: This is not implemented, as it would require backtracking in 1560 some cases, e.g.: 1561 vtbl.8 d3,d4,d5 1562 This could be done (the meaning isn't really ambiguous), but doesn't 1563 fit in well with the current parsing framework. 1564 - 32 D registers may be used (also true for VFPv3). 1565 FIXME: Types are ignored in these register lists, which is probably a 1566 bug. */ 1567 1568static int 1569parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) 1570{ 1571 char *str = *ccp; 1572 int base_reg; 1573 int new_base; 1574 enum arm_reg_type regtype = 0; 1575 int max_regs = 0; 1576 int count = 0; 1577 int warned = 0; 1578 unsigned long mask = 0; 1579 int i; 1580 1581 if (*str != '{') 1582 { 1583 inst.error = _("expecting {"); 1584 return FAIL; 1585 } 1586 1587 str++; 1588 1589 switch (etype) 1590 { 1591 case REGLIST_VFP_S: 1592 regtype = REG_TYPE_VFS; 1593 max_regs = 32; 1594 break; 1595 1596 case REGLIST_VFP_D: 1597 regtype = REG_TYPE_VFD; 1598 break; 1599 1600 case REGLIST_NEON_D: 1601 regtype = REG_TYPE_NDQ; 1602 break; 1603 } 1604 1605 if (etype != REGLIST_VFP_S) 1606 { 1607 /* VFPv3 allows 32 D registers. */ 1608 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 1609 { 1610 max_regs = 32; 1611 if (thumb_mode) 1612 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 1613 fpu_vfp_ext_v3); 1614 else 1615 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 1616 fpu_vfp_ext_v3); 1617 } 1618 else 1619 max_regs = 16; 1620 } 1621 1622 base_reg = max_regs; 1623 1624 do 1625 { 1626 int setmask = 1, addregs = 1; 1627 1628 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); 1629 1630 if (new_base == FAIL) 1631 { 1632 first_error (_(reg_expected_msgs[regtype])); 1633 return FAIL; 1634 } 1635 1636 if (new_base >= max_regs) 1637 { 1638 first_error (_("register out of range in list")); 1639 return FAIL; 1640 } 1641 1642 /* Note: a value of 2 * n is returned for the register Q<n>. */ 1643 if (regtype == REG_TYPE_NQ) 1644 { 1645 setmask = 3; 1646 addregs = 2; 1647 } 1648 1649 if (new_base < base_reg) 1650 base_reg = new_base; 1651 1652 if (mask & (setmask << new_base)) 1653 { 1654 first_error (_("invalid register list")); 1655 return FAIL; 1656 } 1657 1658 if ((mask >> new_base) != 0 && ! warned) 1659 { 1660 as_tsktsk (_("register list not in ascending order")); 1661 warned = 1; 1662 } 1663 1664 mask |= setmask << new_base; 1665 count += addregs; 1666 1667 if (*str == '-') /* We have the start of a range expression */ 1668 { 1669 int high_range; 1670 1671 str++; 1672 1673 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) 1674 == FAIL) 1675 { 1676 inst.error = gettext (reg_expected_msgs[regtype]); 1677 return FAIL; 1678 } 1679 1680 if (high_range >= max_regs) 1681 { 1682 first_error (_("register out of range in list")); 1683 return FAIL; 1684 } 1685 1686 if (regtype == REG_TYPE_NQ) 1687 high_range = high_range + 1; 1688 1689 if (high_range <= new_base) 1690 { 1691 inst.error = _("register range not in ascending order"); 1692 return FAIL; 1693 } 1694 1695 for (new_base += addregs; new_base <= high_range; new_base += addregs) 1696 { 1697 if (mask & (setmask << new_base)) 1698 { 1699 inst.error = _("invalid register list"); 1700 return FAIL; 1701 } 1702 1703 mask |= setmask << new_base; 1704 count += addregs; 1705 } 1706 } 1707 } 1708 while (skip_past_comma (&str) != FAIL); 1709 1710 str++; 1711 1712 /* Sanity check -- should have raised a parse error above. */ 1713 if (count == 0 || count > max_regs) 1714 abort (); 1715 1716 *pbase = base_reg; 1717 1718 /* Final test -- the registers must be consecutive. */ 1719 mask >>= base_reg; 1720 for (i = 0; i < count; i++) 1721 { 1722 if ((mask & (1u << i)) == 0) 1723 { 1724 inst.error = _("non-contiguous register range"); 1725 return FAIL; 1726 } 1727 } 1728 1729 *ccp = str; 1730 1731 return count; 1732} 1733 1734/* True if two alias types are the same. */ 1735 1736static int 1737neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) 1738{ 1739 if (!a && !b) 1740 return 1; 1741 1742 if (!a || !b) 1743 return 0; 1744 1745 if (a->defined != b->defined) 1746 return 0; 1747 1748 if ((a->defined & NTA_HASTYPE) != 0 1749 && (a->eltype.type != b->eltype.type 1750 || a->eltype.size != b->eltype.size)) 1751 return 0; 1752 1753 if ((a->defined & NTA_HASINDEX) != 0 1754 && (a->index != b->index)) 1755 return 0; 1756 1757 return 1; 1758} 1759 1760/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. 1761 The base register is put in *PBASE. 1762 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of 1763 the return value. 1764 The register stride (minus one) is put in bit 4 of the return value. 1765 Bits [6:5] encode the list length (minus one). 1766 The type of the list elements is put in *ELTYPE, if non-NULL. */ 1767 1768#define NEON_LANE(X) ((X) & 0xf) 1769#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) 1770#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) 1771 1772static int 1773parse_neon_el_struct_list (char **str, unsigned *pbase, 1774 struct neon_type_el *eltype) 1775{ 1776 char *ptr = *str; 1777 int base_reg = -1; 1778 int reg_incr = -1; 1779 int count = 0; 1780 int lane = -1; 1781 int leading_brace = 0; 1782 enum arm_reg_type rtype = REG_TYPE_NDQ; 1783 int addregs = 1; 1784 const char *const incr_error = "register stride must be 1 or 2"; 1785 const char *const type_error = "mismatched element/structure types in list"; 1786 struct neon_typed_alias firsttype; 1787 1788 if (skip_past_char (&ptr, '{') == SUCCESS) 1789 leading_brace = 1; 1790 1791 do 1792 { 1793 struct neon_typed_alias atype; 1794 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); 1795 1796 if (getreg == FAIL) 1797 { 1798 first_error (_(reg_expected_msgs[rtype])); 1799 return FAIL; 1800 } 1801 1802 if (base_reg == -1) 1803 { 1804 base_reg = getreg; 1805 if (rtype == REG_TYPE_NQ) 1806 { 1807 reg_incr = 1; 1808 addregs = 2; 1809 } 1810 firsttype = atype; 1811 } 1812 else if (reg_incr == -1) 1813 { 1814 reg_incr = getreg - base_reg; 1815 if (reg_incr < 1 || reg_incr > 2) 1816 { 1817 first_error (_(incr_error)); 1818 return FAIL; 1819 } 1820 } 1821 else if (getreg != base_reg + reg_incr * count) 1822 { 1823 first_error (_(incr_error)); 1824 return FAIL; 1825 } 1826 1827 if (!neon_alias_types_same (&atype, &firsttype)) 1828 { 1829 first_error (_(type_error)); 1830 return FAIL; 1831 } 1832 1833 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list 1834 modes. */ 1835 if (ptr[0] == '-') 1836 { 1837 struct neon_typed_alias htype; 1838 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; 1839 if (lane == -1) 1840 lane = NEON_INTERLEAVE_LANES; 1841 else if (lane != NEON_INTERLEAVE_LANES) 1842 { 1843 first_error (_(type_error)); 1844 return FAIL; 1845 } 1846 if (reg_incr == -1) 1847 reg_incr = 1; 1848 else if (reg_incr != 1) 1849 { 1850 first_error (_("don't use Rn-Rm syntax with non-unit stride")); 1851 return FAIL; 1852 } 1853 ptr++; 1854 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); 1855 if (hireg == FAIL) 1856 { 1857 first_error (_(reg_expected_msgs[rtype])); 1858 return FAIL; 1859 } 1860 if (!neon_alias_types_same (&htype, &firsttype)) 1861 { 1862 first_error (_(type_error)); 1863 return FAIL; 1864 } 1865 count += hireg + dregs - getreg; 1866 continue; 1867 } 1868 1869 /* If we're using Q registers, we can't use [] or [n] syntax. */ 1870 if (rtype == REG_TYPE_NQ) 1871 { 1872 count += 2; 1873 continue; 1874 } 1875 1876 if ((atype.defined & NTA_HASINDEX) != 0) 1877 { 1878 if (lane == -1) 1879 lane = atype.index; 1880 else if (lane != atype.index) 1881 { 1882 first_error (_(type_error)); 1883 return FAIL; 1884 } 1885 } 1886 else if (lane == -1) 1887 lane = NEON_INTERLEAVE_LANES; 1888 else if (lane != NEON_INTERLEAVE_LANES) 1889 { 1890 first_error (_(type_error)); 1891 return FAIL; 1892 } 1893 count++; 1894 } 1895 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); 1896 1897 /* No lane set by [x]. We must be interleaving structures. */ 1898 if (lane == -1) 1899 lane = NEON_INTERLEAVE_LANES; 1900 1901 /* Sanity check. */ 1902 if (lane == -1 || base_reg == -1 || count < 1 || count > 4 1903 || (count > 1 && reg_incr == -1)) 1904 { 1905 first_error (_("error parsing element/structure list")); 1906 return FAIL; 1907 } 1908 1909 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) 1910 { 1911 first_error (_("expected }")); 1912 return FAIL; 1913 } 1914 1915 if (reg_incr == -1) 1916 reg_incr = 1; 1917 1918 if (eltype) 1919 *eltype = firsttype.eltype; 1920 1921 *pbase = base_reg; 1922 *str = ptr; 1923 1924 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); 1925} 1926 1927/* Parse an explicit relocation suffix on an expression. This is 1928 either nothing, or a word in parentheses. Note that if !OBJ_ELF, 1929 arm_reloc_hsh contains no entries, so this function can only 1930 succeed if there is no () after the word. Returns -1 on error, 1931 BFD_RELOC_UNUSED if there wasn't any suffix. */ 1932static int 1933parse_reloc (char **str) 1934{ 1935 struct reloc_entry *r; 1936 char *p, *q; 1937 1938 if (**str != '(') 1939 return BFD_RELOC_UNUSED; 1940 1941 p = *str + 1; 1942 q = p; 1943 1944 while (*q && *q != ')' && *q != ',') 1945 q++; 1946 if (*q != ')') 1947 return -1; 1948 1949 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) 1950 return -1; 1951 1952 *str = q + 1; 1953 return r->reloc; 1954} 1955 1956/* Directives: register aliases. */ 1957 1958static struct reg_entry * 1959insert_reg_alias (char *str, int number, int type) 1960{ 1961 struct reg_entry *new; 1962 const char *name; 1963 1964 if ((new = hash_find (arm_reg_hsh, str)) != 0) 1965 { 1966 if (new->builtin) 1967 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); 1968 1969 /* Only warn about a redefinition if it's not defined as the 1970 same register. */ 1971 else if (new->number != number || new->type != type) 1972 as_warn (_("ignoring redefinition of register alias '%s'"), str); 1973 1974 return 0; 1975 } 1976 1977 name = xstrdup (str); 1978 new = xmalloc (sizeof (struct reg_entry)); 1979 1980 new->name = name; 1981 new->number = number; 1982 new->type = type; 1983 new->builtin = FALSE; 1984 new->neon = NULL; 1985 1986 if (hash_insert (arm_reg_hsh, name, (PTR) new)) 1987 abort (); 1988 1989 return new; 1990} 1991 1992static void 1993insert_neon_reg_alias (char *str, int number, int type, 1994 struct neon_typed_alias *atype) 1995{ 1996 struct reg_entry *reg = insert_reg_alias (str, number, type); 1997 1998 if (!reg) 1999 { 2000 first_error (_("attempt to redefine typed alias")); 2001 return; 2002 } 2003 2004 if (atype) 2005 { 2006 reg->neon = xmalloc (sizeof (struct neon_typed_alias)); 2007 *reg->neon = *atype; 2008 } 2009} 2010 2011/* Look for the .req directive. This is of the form: 2012 2013 new_register_name .req existing_register_name 2014 2015 If we find one, or if it looks sufficiently like one that we want to 2016 handle any error here, return non-zero. Otherwise return zero. */ 2017 2018static int 2019create_register_alias (char * newname, char *p) 2020{ 2021 struct reg_entry *old; 2022 char *oldname, *nbuf; 2023 size_t nlen; 2024 2025 /* The input scrubber ensures that whitespace after the mnemonic is 2026 collapsed to single spaces. */ 2027 oldname = p; 2028 if (strncmp (oldname, " .req ", 6) != 0) 2029 return 0; 2030 2031 oldname += 6; 2032 if (*oldname == '\0') 2033 return 0; 2034 2035 old = hash_find (arm_reg_hsh, oldname); 2036 if (!old) 2037 { 2038 as_warn (_("unknown register '%s' -- .req ignored"), oldname); 2039 return 1; 2040 } 2041 2042 /* If TC_CASE_SENSITIVE is defined, then newname already points to 2043 the desired alias name, and p points to its end. If not, then 2044 the desired alias name is in the global original_case_string. */ 2045#ifdef TC_CASE_SENSITIVE 2046 nlen = p - newname; 2047#else 2048 newname = original_case_string; 2049 nlen = strlen (newname); 2050#endif 2051 2052 nbuf = alloca (nlen + 1); 2053 memcpy (nbuf, newname, nlen); 2054 nbuf[nlen] = '\0'; 2055 2056 /* Create aliases under the new name as stated; an all-lowercase 2057 version of the new name; and an all-uppercase version of the new 2058 name. */ 2059 insert_reg_alias (nbuf, old->number, old->type); 2060 2061 for (p = nbuf; *p; p++) 2062 *p = TOUPPER (*p); 2063 2064 if (strncmp (nbuf, newname, nlen)) 2065 insert_reg_alias (nbuf, old->number, old->type); 2066 2067 for (p = nbuf; *p; p++) 2068 *p = TOLOWER (*p); 2069 2070 if (strncmp (nbuf, newname, nlen)) 2071 insert_reg_alias (nbuf, old->number, old->type); 2072 2073 return 1; 2074} 2075 2076/* Create a Neon typed/indexed register alias using directives, e.g.: 2077 X .dn d5.s32[1] 2078 Y .qn 6.s16 2079 Z .dn d7 2080 T .dn Z[0] 2081 These typed registers can be used instead of the types specified after the 2082 Neon mnemonic, so long as all operands given have types. Types can also be 2083 specified directly, e.g.: 2084 vadd d0.s32, d1.s32, d2.s32 2085*/ 2086 2087static int 2088create_neon_reg_alias (char *newname, char *p) 2089{ 2090 enum arm_reg_type basetype; 2091 struct reg_entry *basereg; 2092 struct reg_entry mybasereg; 2093 struct neon_type ntype; 2094 struct neon_typed_alias typeinfo; 2095 char *namebuf, *nameend; 2096 int namelen; 2097 2098 typeinfo.defined = 0; 2099 typeinfo.eltype.type = NT_invtype; 2100 typeinfo.eltype.size = -1; 2101 typeinfo.index = -1; 2102 2103 nameend = p; 2104 2105 if (strncmp (p, " .dn ", 5) == 0) 2106 basetype = REG_TYPE_VFD; 2107 else if (strncmp (p, " .qn ", 5) == 0) 2108 basetype = REG_TYPE_NQ; 2109 else 2110 return 0; 2111 2112 p += 5; 2113 2114 if (*p == '\0') 2115 return 0; 2116 2117 basereg = arm_reg_parse_multi (&p); 2118 2119 if (basereg && basereg->type != basetype) 2120 { 2121 as_bad (_("bad type for register")); 2122 return 0; 2123 } 2124 2125 if (basereg == NULL) 2126 { 2127 expressionS exp; 2128 /* Try parsing as an integer. */ 2129 my_get_expression (&exp, &p, GE_NO_PREFIX); 2130 if (exp.X_op != O_constant) 2131 { 2132 as_bad (_("expression must be constant")); 2133 return 0; 2134 } 2135 basereg = &mybasereg; 2136 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 2137 : exp.X_add_number; 2138 basereg->neon = 0; 2139 } 2140 2141 if (basereg->neon) 2142 typeinfo = *basereg->neon; 2143 2144 if (parse_neon_type (&ntype, &p) == SUCCESS) 2145 { 2146 /* We got a type. */ 2147 if (typeinfo.defined & NTA_HASTYPE) 2148 { 2149 as_bad (_("can't redefine the type of a register alias")); 2150 return 0; 2151 } 2152 2153 typeinfo.defined |= NTA_HASTYPE; 2154 if (ntype.elems != 1) 2155 { 2156 as_bad (_("you must specify a single type only")); 2157 return 0; 2158 } 2159 typeinfo.eltype = ntype.el[0]; 2160 } 2161 2162 if (skip_past_char (&p, '[') == SUCCESS) 2163 { 2164 expressionS exp; 2165 /* We got a scalar index. */ 2166 2167 if (typeinfo.defined & NTA_HASINDEX) 2168 { 2169 as_bad (_("can't redefine the index of a scalar alias")); 2170 return 0; 2171 } 2172 2173 my_get_expression (&exp, &p, GE_NO_PREFIX); 2174 2175 if (exp.X_op != O_constant) 2176 { 2177 as_bad (_("scalar index must be constant")); 2178 return 0; 2179 } 2180 2181 typeinfo.defined |= NTA_HASINDEX; 2182 typeinfo.index = exp.X_add_number; 2183 2184 if (skip_past_char (&p, ']') == FAIL) 2185 { 2186 as_bad (_("expecting ]")); 2187 return 0; 2188 } 2189 } 2190 2191 namelen = nameend - newname; 2192 namebuf = alloca (namelen + 1); 2193 strncpy (namebuf, newname, namelen); 2194 namebuf[namelen] = '\0'; 2195 2196 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2197 typeinfo.defined != 0 ? &typeinfo : NULL); 2198 2199 /* Insert name in all uppercase. */ 2200 for (p = namebuf; *p; p++) 2201 *p = TOUPPER (*p); 2202 2203 if (strncmp (namebuf, newname, namelen)) 2204 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2205 typeinfo.defined != 0 ? &typeinfo : NULL); 2206 2207 /* Insert name in all lowercase. */ 2208 for (p = namebuf; *p; p++) 2209 *p = TOLOWER (*p); 2210 2211 if (strncmp (namebuf, newname, namelen)) 2212 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2213 typeinfo.defined != 0 ? &typeinfo : NULL); 2214 2215 return 1; 2216} 2217 2218/* Should never be called, as .req goes between the alias and the 2219 register name, not at the beginning of the line. */ 2220static void 2221s_req (int a ATTRIBUTE_UNUSED) 2222{ 2223 as_bad (_("invalid syntax for .req directive")); 2224} 2225 2226static void 2227s_dn (int a ATTRIBUTE_UNUSED) 2228{ 2229 as_bad (_("invalid syntax for .dn directive")); 2230} 2231 2232static void 2233s_qn (int a ATTRIBUTE_UNUSED) 2234{ 2235 as_bad (_("invalid syntax for .qn directive")); 2236} 2237 2238/* The .unreq directive deletes an alias which was previously defined 2239 by .req. For example: 2240 2241 my_alias .req r11 2242 .unreq my_alias */ 2243 2244static void 2245s_unreq (int a ATTRIBUTE_UNUSED) 2246{ 2247 char * name; 2248 char saved_char; 2249 2250 name = input_line_pointer; 2251 2252 while (*input_line_pointer != 0 2253 && *input_line_pointer != ' ' 2254 && *input_line_pointer != '\n') 2255 ++input_line_pointer; 2256 2257 saved_char = *input_line_pointer; 2258 *input_line_pointer = 0; 2259 2260 if (!*name) 2261 as_bad (_("invalid syntax for .unreq directive")); 2262 else 2263 { 2264 struct reg_entry *reg = hash_find (arm_reg_hsh, name); 2265 2266 if (!reg) 2267 as_bad (_("unknown register alias '%s'"), name); 2268 else if (reg->builtin) 2269 as_warn (_("ignoring attempt to undefine built-in register '%s'"), 2270 name); 2271 else 2272 { 2273 hash_delete (arm_reg_hsh, name); 2274 free ((char *) reg->name); 2275 if (reg->neon) 2276 free (reg->neon); 2277 free (reg); 2278 } 2279 } 2280 2281 *input_line_pointer = saved_char; 2282 demand_empty_rest_of_line (); 2283} 2284 2285/* Directives: Instruction set selection. */ 2286 2287#ifdef OBJ_ELF 2288/* This code is to handle mapping symbols as defined in the ARM ELF spec. 2289 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). 2290 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), 2291 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ 2292 2293static enum mstate mapstate = MAP_UNDEFINED; 2294 2295void 2296mapping_state (enum mstate state) 2297{ 2298 symbolS * symbolP; 2299 const char * symname; 2300 int type; 2301 2302 if (mapstate == state) 2303 /* The mapping symbol has already been emitted. 2304 There is nothing else to do. */ 2305 return; 2306 2307 mapstate = state; 2308 2309 switch (state) 2310 { 2311 case MAP_DATA: 2312 symname = "$d"; 2313 type = BSF_NO_FLAGS; 2314 break; 2315 case MAP_ARM: 2316 symname = "$a"; 2317 type = BSF_NO_FLAGS; 2318 break; 2319 case MAP_THUMB: 2320 symname = "$t"; 2321 type = BSF_NO_FLAGS; 2322 break; 2323 case MAP_UNDEFINED: 2324 return; 2325 default: 2326 abort (); 2327 } 2328 2329 seg_info (now_seg)->tc_segment_info_data.mapstate = state; 2330 2331 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); 2332 symbol_table_insert (symbolP); 2333 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; 2334 2335 switch (state) 2336 { 2337 case MAP_ARM: 2338 THUMB_SET_FUNC (symbolP, 0); 2339 ARM_SET_THUMB (symbolP, 0); 2340 ARM_SET_INTERWORK (symbolP, support_interwork); 2341 break; 2342 2343 case MAP_THUMB: 2344 THUMB_SET_FUNC (symbolP, 1); 2345 ARM_SET_THUMB (symbolP, 1); 2346 ARM_SET_INTERWORK (symbolP, support_interwork); 2347 break; 2348 2349 case MAP_DATA: 2350 default: 2351 return; 2352 } 2353} 2354#else 2355#define mapping_state(x) /* nothing */ 2356#endif 2357 2358/* Find the real, Thumb encoded start of a Thumb function. */ 2359 2360static symbolS * 2361find_real_start (symbolS * symbolP) 2362{ 2363 char * real_start; 2364 const char * name = S_GET_NAME (symbolP); 2365 symbolS * new_target; 2366 2367 /* This definition must agree with the one in gcc/config/arm/thumb.c. */ 2368#define STUB_NAME ".real_start_of" 2369 2370 if (name == NULL) 2371 abort (); 2372 2373 /* The compiler may generate BL instructions to local labels because 2374 it needs to perform a branch to a far away location. These labels 2375 do not have a corresponding ".real_start_of" label. We check 2376 both for S_IS_LOCAL and for a leading dot, to give a way to bypass 2377 the ".real_start_of" convention for nonlocal branches. */ 2378 if (S_IS_LOCAL (symbolP) || name[0] == '.') 2379 return symbolP; 2380 2381 real_start = ACONCAT ((STUB_NAME, name, NULL)); 2382 new_target = symbol_find (real_start); 2383 2384 if (new_target == NULL) 2385 { 2386 as_warn ("Failed to find real start of function: %s\n", name); 2387 new_target = symbolP; 2388 } 2389 2390 return new_target; 2391} 2392 2393static void 2394opcode_select (int width) 2395{ 2396 switch (width) 2397 { 2398 case 16: 2399 if (! thumb_mode) 2400 { 2401 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 2402 as_bad (_("selected processor does not support THUMB opcodes")); 2403 2404 thumb_mode = 1; 2405 /* No need to force the alignment, since we will have been 2406 coming from ARM mode, which is word-aligned. */ 2407 record_alignment (now_seg, 1); 2408 } 2409 mapping_state (MAP_THUMB); 2410 break; 2411 2412 case 32: 2413 if (thumb_mode) 2414 { 2415 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 2416 as_bad (_("selected processor does not support ARM opcodes")); 2417 2418 thumb_mode = 0; 2419 2420 if (!need_pass_2) 2421 frag_align (2, 0, 0); 2422 2423 record_alignment (now_seg, 1); 2424 } 2425 mapping_state (MAP_ARM); 2426 break; 2427 2428 default: 2429 as_bad (_("invalid instruction size selected (%d)"), width); 2430 } 2431} 2432 2433static void 2434s_arm (int ignore ATTRIBUTE_UNUSED) 2435{ 2436 opcode_select (32); 2437 demand_empty_rest_of_line (); 2438} 2439 2440static void 2441s_thumb (int ignore ATTRIBUTE_UNUSED) 2442{ 2443 opcode_select (16); 2444 demand_empty_rest_of_line (); 2445} 2446 2447static void 2448s_code (int unused ATTRIBUTE_UNUSED) 2449{ 2450 int temp; 2451 2452 temp = get_absolute_expression (); 2453 switch (temp) 2454 { 2455 case 16: 2456 case 32: 2457 opcode_select (temp); 2458 break; 2459 2460 default: 2461 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); 2462 } 2463} 2464 2465static void 2466s_force_thumb (int ignore ATTRIBUTE_UNUSED) 2467{ 2468 /* If we are not already in thumb mode go into it, EVEN if 2469 the target processor does not support thumb instructions. 2470 This is used by gcc/config/arm/lib1funcs.asm for example 2471 to compile interworking support functions even if the 2472 target processor should not support interworking. */ 2473 if (! thumb_mode) 2474 { 2475 thumb_mode = 2; 2476 record_alignment (now_seg, 1); 2477 } 2478 2479 demand_empty_rest_of_line (); 2480} 2481 2482static void 2483s_thumb_func (int ignore ATTRIBUTE_UNUSED) 2484{ 2485 s_thumb (0); 2486 2487 /* The following label is the name/address of the start of a Thumb function. 2488 We need to know this for the interworking support. */ 2489 label_is_thumb_function_name = TRUE; 2490} 2491 2492/* Perform a .set directive, but also mark the alias as 2493 being a thumb function. */ 2494 2495static void 2496s_thumb_set (int equiv) 2497{ 2498 /* XXX the following is a duplicate of the code for s_set() in read.c 2499 We cannot just call that code as we need to get at the symbol that 2500 is created. */ 2501 char * name; 2502 char delim; 2503 char * end_name; 2504 symbolS * symbolP; 2505 2506 /* Especial apologies for the random logic: 2507 This just grew, and could be parsed much more simply! 2508 Dean - in haste. */ 2509 name = input_line_pointer; 2510 delim = get_symbol_end (); 2511 end_name = input_line_pointer; 2512 *end_name = delim; 2513 2514 if (*input_line_pointer != ',') 2515 { 2516 *end_name = 0; 2517 as_bad (_("expected comma after name \"%s\""), name); 2518 *end_name = delim; 2519 ignore_rest_of_line (); 2520 return; 2521 } 2522 2523 input_line_pointer++; 2524 *end_name = 0; 2525 2526 if (name[0] == '.' && name[1] == '\0') 2527 { 2528 /* XXX - this should not happen to .thumb_set. */ 2529 abort (); 2530 } 2531 2532 if ((symbolP = symbol_find (name)) == NULL 2533 && (symbolP = md_undefined_symbol (name)) == NULL) 2534 { 2535#ifndef NO_LISTING 2536 /* When doing symbol listings, play games with dummy fragments living 2537 outside the normal fragment chain to record the file and line info 2538 for this symbol. */ 2539 if (listing & LISTING_SYMBOLS) 2540 { 2541 extern struct list_info_struct * listing_tail; 2542 fragS * dummy_frag = xmalloc (sizeof (fragS)); 2543 2544 memset (dummy_frag, 0, sizeof (fragS)); 2545 dummy_frag->fr_type = rs_fill; 2546 dummy_frag->line = listing_tail; 2547 symbolP = symbol_new (name, undefined_section, 0, dummy_frag); 2548 dummy_frag->fr_symbol = symbolP; 2549 } 2550 else 2551#endif 2552 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 2553 2554#ifdef OBJ_COFF 2555 /* "set" symbols are local unless otherwise specified. */ 2556 SF_SET_LOCAL (symbolP); 2557#endif /* OBJ_COFF */ 2558 } /* Make a new symbol. */ 2559 2560 symbol_table_insert (symbolP); 2561 2562 * end_name = delim; 2563 2564 if (equiv 2565 && S_IS_DEFINED (symbolP) 2566 && S_GET_SEGMENT (symbolP) != reg_section) 2567 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 2568 2569 pseudo_set (symbolP); 2570 2571 demand_empty_rest_of_line (); 2572 2573 /* XXX Now we come to the Thumb specific bit of code. */ 2574 2575 THUMB_SET_FUNC (symbolP, 1); 2576 ARM_SET_THUMB (symbolP, 1); 2577#if defined OBJ_ELF || defined OBJ_COFF 2578 ARM_SET_INTERWORK (symbolP, support_interwork); 2579#endif 2580} 2581 2582/* Directives: Mode selection. */ 2583 2584/* .syntax [unified|divided] - choose the new unified syntax 2585 (same for Arm and Thumb encoding, modulo slight differences in what 2586 can be represented) or the old divergent syntax for each mode. */ 2587static void 2588s_syntax (int unused ATTRIBUTE_UNUSED) 2589{ 2590 char *name, delim; 2591 2592 name = input_line_pointer; 2593 delim = get_symbol_end (); 2594 2595 if (!strcasecmp (name, "unified")) 2596 unified_syntax = TRUE; 2597 else if (!strcasecmp (name, "divided")) 2598 unified_syntax = FALSE; 2599 else 2600 { 2601 as_bad (_("unrecognized syntax mode \"%s\""), name); 2602 return; 2603 } 2604 *input_line_pointer = delim; 2605 demand_empty_rest_of_line (); 2606} 2607 2608/* Directives: sectioning and alignment. */ 2609 2610/* Same as s_align_ptwo but align 0 => align 2. */ 2611 2612static void 2613s_align (int unused ATTRIBUTE_UNUSED) 2614{ 2615 int temp; 2616 bfd_boolean fill_p; 2617 long temp_fill; 2618 long max_alignment = 15; 2619 2620 temp = get_absolute_expression (); 2621 if (temp > max_alignment) 2622 as_bad (_("alignment too large: %d assumed"), temp = max_alignment); 2623 else if (temp < 0) 2624 { 2625 as_bad (_("alignment negative. 0 assumed.")); 2626 temp = 0; 2627 } 2628 2629 if (*input_line_pointer == ',') 2630 { 2631 input_line_pointer++; 2632 temp_fill = get_absolute_expression (); 2633 fill_p = TRUE; 2634 } 2635 else 2636 { 2637 fill_p = FALSE; 2638 temp_fill = 0; 2639 } 2640 2641 if (!temp) 2642 temp = 2; 2643 2644 /* Only make a frag if we HAVE to. */ 2645 if (temp && !need_pass_2) 2646 { 2647 if (!fill_p && subseg_text_p (now_seg)) 2648 frag_align_code (temp, 0); 2649 else 2650 frag_align (temp, (int) temp_fill, 0); 2651 } 2652 demand_empty_rest_of_line (); 2653 2654 record_alignment (now_seg, temp); 2655} 2656 2657static void 2658s_bss (int ignore ATTRIBUTE_UNUSED) 2659{ 2660 /* We don't support putting frags in the BSS segment, we fake it by 2661 marking in_bss, then looking at s_skip for clues. */ 2662 subseg_set (bss_section, 0); 2663 demand_empty_rest_of_line (); 2664 mapping_state (MAP_DATA); 2665} 2666 2667static void 2668s_even (int ignore ATTRIBUTE_UNUSED) 2669{ 2670 /* Never make frag if expect extra pass. */ 2671 if (!need_pass_2) 2672 frag_align (1, 0, 0); 2673 2674 record_alignment (now_seg, 1); 2675 2676 demand_empty_rest_of_line (); 2677} 2678 2679/* Directives: Literal pools. */ 2680 2681static literal_pool * 2682find_literal_pool (void) 2683{ 2684 literal_pool * pool; 2685 2686 for (pool = list_of_pools; pool != NULL; pool = pool->next) 2687 { 2688 if (pool->section == now_seg 2689 && pool->sub_section == now_subseg) 2690 break; 2691 } 2692 2693 return pool; 2694} 2695 2696static literal_pool * 2697find_or_make_literal_pool (void) 2698{ 2699 /* Next literal pool ID number. */ 2700 static unsigned int latest_pool_num = 1; 2701 literal_pool * pool; 2702 2703 pool = find_literal_pool (); 2704 2705 if (pool == NULL) 2706 { 2707 /* Create a new pool. */ 2708 pool = xmalloc (sizeof (* pool)); 2709 if (! pool) 2710 return NULL; 2711 2712 pool->next_free_entry = 0; 2713 pool->section = now_seg; 2714 pool->sub_section = now_subseg; 2715 pool->next = list_of_pools; 2716 pool->symbol = NULL; 2717 2718 /* Add it to the list. */ 2719 list_of_pools = pool; 2720 } 2721 2722 /* New pools, and emptied pools, will have a NULL symbol. */ 2723 if (pool->symbol == NULL) 2724 { 2725 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, 2726 (valueT) 0, &zero_address_frag); 2727 pool->id = latest_pool_num ++; 2728 } 2729 2730 /* Done. */ 2731 return pool; 2732} 2733 2734/* Add the literal in the global 'inst' 2735 structure to the relevent literal pool. */ 2736 2737static int 2738add_to_lit_pool (void) 2739{ 2740 literal_pool * pool; 2741 unsigned int entry; 2742 2743 pool = find_or_make_literal_pool (); 2744 2745 /* Check if this literal value is already in the pool. */ 2746 for (entry = 0; entry < pool->next_free_entry; entry ++) 2747 { 2748 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2749 && (inst.reloc.exp.X_op == O_constant) 2750 && (pool->literals[entry].X_add_number 2751 == inst.reloc.exp.X_add_number) 2752 && (pool->literals[entry].X_unsigned 2753 == inst.reloc.exp.X_unsigned)) 2754 break; 2755 2756 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2757 && (inst.reloc.exp.X_op == O_symbol) 2758 && (pool->literals[entry].X_add_number 2759 == inst.reloc.exp.X_add_number) 2760 && (pool->literals[entry].X_add_symbol 2761 == inst.reloc.exp.X_add_symbol) 2762 && (pool->literals[entry].X_op_symbol 2763 == inst.reloc.exp.X_op_symbol)) 2764 break; 2765 } 2766 2767 /* Do we need to create a new entry? */ 2768 if (entry == pool->next_free_entry) 2769 { 2770 if (entry >= MAX_LITERAL_POOL_SIZE) 2771 { 2772 inst.error = _("literal pool overflow"); 2773 return FAIL; 2774 } 2775 2776 pool->literals[entry] = inst.reloc.exp; 2777 pool->next_free_entry += 1; 2778 } 2779 2780 inst.reloc.exp.X_op = O_symbol; 2781 inst.reloc.exp.X_add_number = ((int) entry) * 4; 2782 inst.reloc.exp.X_add_symbol = pool->symbol; 2783 2784 return SUCCESS; 2785} 2786 2787/* Can't use symbol_new here, so have to create a symbol and then at 2788 a later date assign it a value. Thats what these functions do. */ 2789 2790static void 2791symbol_locate (symbolS * symbolP, 2792 const char * name, /* It is copied, the caller can modify. */ 2793 segT segment, /* Segment identifier (SEG_<something>). */ 2794 valueT valu, /* Symbol value. */ 2795 fragS * frag) /* Associated fragment. */ 2796{ 2797 unsigned int name_length; 2798 char * preserved_copy_of_name; 2799 2800 name_length = strlen (name) + 1; /* +1 for \0. */ 2801 obstack_grow (¬es, name, name_length); 2802 preserved_copy_of_name = obstack_finish (¬es); 2803 2804#ifdef tc_canonicalize_symbol_name 2805 preserved_copy_of_name = 2806 tc_canonicalize_symbol_name (preserved_copy_of_name); 2807#endif 2808 2809 S_SET_NAME (symbolP, preserved_copy_of_name); 2810 2811 S_SET_SEGMENT (symbolP, segment); 2812 S_SET_VALUE (symbolP, valu); 2813 symbol_clear_list_pointers (symbolP); 2814 2815 symbol_set_frag (symbolP, frag); 2816 2817 /* Link to end of symbol chain. */ 2818 { 2819 extern int symbol_table_frozen; 2820 2821 if (symbol_table_frozen) 2822 abort (); 2823 } 2824 2825 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); 2826 2827 obj_symbol_new_hook (symbolP); 2828 2829#ifdef tc_symbol_new_hook 2830 tc_symbol_new_hook (symbolP); 2831#endif 2832 2833#ifdef DEBUG_SYMS 2834 verify_symbol_chain (symbol_rootP, symbol_lastP); 2835#endif /* DEBUG_SYMS */ 2836} 2837 2838 2839static void 2840s_ltorg (int ignored ATTRIBUTE_UNUSED) 2841{ 2842 unsigned int entry; 2843 literal_pool * pool; 2844 char sym_name[20]; 2845 2846 pool = find_literal_pool (); 2847 if (pool == NULL 2848 || pool->symbol == NULL 2849 || pool->next_free_entry == 0) 2850 return; 2851 2852 mapping_state (MAP_DATA); 2853 2854 /* Align pool as you have word accesses. 2855 Only make a frag if we have to. */ 2856 if (!need_pass_2) 2857 frag_align (2, 0, 0); 2858 2859 record_alignment (now_seg, 2); 2860 2861 sprintf (sym_name, "$$lit_\002%x", pool->id); 2862 2863 symbol_locate (pool->symbol, sym_name, now_seg, 2864 (valueT) frag_now_fix (), frag_now); 2865 symbol_table_insert (pool->symbol); 2866 2867 ARM_SET_THUMB (pool->symbol, thumb_mode); 2868 2869#if defined OBJ_COFF || defined OBJ_ELF 2870 ARM_SET_INTERWORK (pool->symbol, support_interwork); 2871#endif 2872 2873 for (entry = 0; entry < pool->next_free_entry; entry ++) 2874 /* First output the expression in the instruction to the pool. */ 2875 emit_expr (&(pool->literals[entry]), 4); /* .word */ 2876 2877 /* Mark the pool as empty. */ 2878 pool->next_free_entry = 0; 2879 pool->symbol = NULL; 2880} 2881 2882#ifdef OBJ_ELF 2883/* Forward declarations for functions below, in the MD interface 2884 section. */ 2885static void fix_new_arm (fragS *, int, short, expressionS *, int, int); 2886static valueT create_unwind_entry (int); 2887static void start_unwind_section (const segT, int); 2888static void add_unwind_opcode (valueT, int); 2889static void flush_pending_unwind (void); 2890 2891/* Directives: Data. */ 2892 2893static void 2894s_arm_elf_cons (int nbytes) 2895{ 2896 expressionS exp; 2897 2898#ifdef md_flush_pending_output 2899 md_flush_pending_output (); 2900#endif 2901 2902 if (is_it_end_of_statement ()) 2903 { 2904 demand_empty_rest_of_line (); 2905 return; 2906 } 2907 2908#ifdef md_cons_align 2909 md_cons_align (nbytes); 2910#endif 2911 2912 mapping_state (MAP_DATA); 2913 do 2914 { 2915 int reloc; 2916 char *base = input_line_pointer; 2917 2918 expression (& exp); 2919 2920 if (exp.X_op != O_symbol) 2921 emit_expr (&exp, (unsigned int) nbytes); 2922 else 2923 { 2924 char *before_reloc = input_line_pointer; 2925 reloc = parse_reloc (&input_line_pointer); 2926 if (reloc == -1) 2927 { 2928 as_bad (_("unrecognized relocation suffix")); 2929 ignore_rest_of_line (); 2930 return; 2931 } 2932 else if (reloc == BFD_RELOC_UNUSED) 2933 emit_expr (&exp, (unsigned int) nbytes); 2934 else 2935 { 2936 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); 2937 int size = bfd_get_reloc_size (howto); 2938 2939 if (reloc == BFD_RELOC_ARM_PLT32) 2940 { 2941 as_bad (_("(plt) is only valid on branch targets")); 2942 reloc = BFD_RELOC_UNUSED; 2943 size = 0; 2944 } 2945 2946 if (size > nbytes) 2947 as_bad (_("%s relocations do not fit in %d bytes"), 2948 howto->name, nbytes); 2949 else 2950 { 2951 /* We've parsed an expression stopping at O_symbol. 2952 But there may be more expression left now that we 2953 have parsed the relocation marker. Parse it again. 2954 XXX Surely there is a cleaner way to do this. */ 2955 char *p = input_line_pointer; 2956 int offset; 2957 char *save_buf = alloca (input_line_pointer - base); 2958 memcpy (save_buf, base, input_line_pointer - base); 2959 memmove (base + (input_line_pointer - before_reloc), 2960 base, before_reloc - base); 2961 2962 input_line_pointer = base + (input_line_pointer-before_reloc); 2963 expression (&exp); 2964 memcpy (base, save_buf, p - base); 2965 2966 offset = nbytes - size; 2967 p = frag_more ((int) nbytes); 2968 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, 2969 size, &exp, 0, reloc); 2970 } 2971 } 2972 } 2973 } 2974 while (*input_line_pointer++ == ','); 2975 2976 /* Put terminator back into stream. */ 2977 input_line_pointer --; 2978 demand_empty_rest_of_line (); 2979} 2980 2981 2982/* Parse a .rel31 directive. */ 2983 2984static void 2985s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) 2986{ 2987 expressionS exp; 2988 char *p; 2989 valueT highbit; 2990 2991 highbit = 0; 2992 if (*input_line_pointer == '1') 2993 highbit = 0x80000000; 2994 else if (*input_line_pointer != '0') 2995 as_bad (_("expected 0 or 1")); 2996 2997 input_line_pointer++; 2998 if (*input_line_pointer != ',') 2999 as_bad (_("missing comma")); 3000 input_line_pointer++; 3001 3002#ifdef md_flush_pending_output 3003 md_flush_pending_output (); 3004#endif 3005 3006#ifdef md_cons_align 3007 md_cons_align (4); 3008#endif 3009 3010 mapping_state (MAP_DATA); 3011 3012 expression (&exp); 3013 3014 p = frag_more (4); 3015 md_number_to_chars (p, highbit, 4); 3016 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, 3017 BFD_RELOC_ARM_PREL31); 3018 3019 demand_empty_rest_of_line (); 3020} 3021 3022/* Directives: AEABI stack-unwind tables. */ 3023 3024/* Parse an unwind_fnstart directive. Simply records the current location. */ 3025 3026static void 3027s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) 3028{ 3029 demand_empty_rest_of_line (); 3030 /* Mark the start of the function. */ 3031 unwind.proc_start = expr_build_dot (); 3032 3033 /* Reset the rest of the unwind info. */ 3034 unwind.opcode_count = 0; 3035 unwind.table_entry = NULL; 3036 unwind.personality_routine = NULL; 3037 unwind.personality_index = -1; 3038 unwind.frame_size = 0; 3039 unwind.fp_offset = 0; 3040 unwind.fp_reg = 13; 3041 unwind.fp_used = 0; 3042 unwind.sp_restored = 0; 3043} 3044 3045 3046/* Parse a handlerdata directive. Creates the exception handling table entry 3047 for the function. */ 3048 3049static void 3050s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) 3051{ 3052 demand_empty_rest_of_line (); 3053 if (unwind.table_entry) 3054 as_bad (_("dupicate .handlerdata directive")); 3055 3056 create_unwind_entry (1); 3057} 3058 3059/* Parse an unwind_fnend directive. Generates the index table entry. */ 3060 3061static void 3062s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) 3063{ 3064 long where; 3065 char *ptr; 3066 valueT val; 3067 3068 demand_empty_rest_of_line (); 3069 3070 /* Add eh table entry. */ 3071 if (unwind.table_entry == NULL) 3072 val = create_unwind_entry (0); 3073 else 3074 val = 0; 3075 3076 /* Add index table entry. This is two words. */ 3077 start_unwind_section (unwind.saved_seg, 1); 3078 frag_align (2, 0, 0); 3079 record_alignment (now_seg, 2); 3080 3081 ptr = frag_more (8); 3082 where = frag_now_fix () - 8; 3083 3084 /* Self relative offset of the function start. */ 3085 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, 3086 BFD_RELOC_ARM_PREL31); 3087 3088 /* Indicate dependency on EHABI-defined personality routines to the 3089 linker, if it hasn't been done already. */ 3090 if (unwind.personality_index >= 0 && unwind.personality_index < 3 3091 && !(marked_pr_dependency & (1 << unwind.personality_index))) 3092 { 3093 static const char *const name[] = { 3094 "__aeabi_unwind_cpp_pr0", 3095 "__aeabi_unwind_cpp_pr1", 3096 "__aeabi_unwind_cpp_pr2" 3097 }; 3098 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); 3099 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); 3100 marked_pr_dependency |= 1 << unwind.personality_index; 3101 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency 3102 = marked_pr_dependency; 3103 } 3104 3105 if (val) 3106 /* Inline exception table entry. */ 3107 md_number_to_chars (ptr + 4, val, 4); 3108 else 3109 /* Self relative offset of the table entry. */ 3110 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, 3111 BFD_RELOC_ARM_PREL31); 3112 3113 /* Restore the original section. */ 3114 subseg_set (unwind.saved_seg, unwind.saved_subseg); 3115} 3116 3117 3118/* Parse an unwind_cantunwind directive. */ 3119 3120static void 3121s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) 3122{ 3123 demand_empty_rest_of_line (); 3124 if (unwind.personality_routine || unwind.personality_index != -1) 3125 as_bad (_("personality routine specified for cantunwind frame")); 3126 3127 unwind.personality_index = -2; 3128} 3129 3130 3131/* Parse a personalityindex directive. */ 3132 3133static void 3134s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) 3135{ 3136 expressionS exp; 3137 3138 if (unwind.personality_routine || unwind.personality_index != -1) 3139 as_bad (_("duplicate .personalityindex directive")); 3140 3141 expression (&exp); 3142 3143 if (exp.X_op != O_constant 3144 || exp.X_add_number < 0 || exp.X_add_number > 15) 3145 { 3146 as_bad (_("bad personality routine number")); 3147 ignore_rest_of_line (); 3148 return; 3149 } 3150 3151 unwind.personality_index = exp.X_add_number; 3152 3153 demand_empty_rest_of_line (); 3154} 3155 3156 3157/* Parse a personality directive. */ 3158 3159static void 3160s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) 3161{ 3162 char *name, *p, c; 3163 3164 if (unwind.personality_routine || unwind.personality_index != -1) 3165 as_bad (_("duplicate .personality directive")); 3166 3167 name = input_line_pointer; 3168 c = get_symbol_end (); 3169 p = input_line_pointer; 3170 unwind.personality_routine = symbol_find_or_make (name); 3171 *p = c; 3172 demand_empty_rest_of_line (); 3173} 3174 3175 3176/* Parse a directive saving core registers. */ 3177 3178static void 3179s_arm_unwind_save_core (void) 3180{ 3181 valueT op; 3182 long range; 3183 int n; 3184 3185 range = parse_reg_list (&input_line_pointer); 3186 if (range == FAIL) 3187 { 3188 as_bad (_("expected register list")); 3189 ignore_rest_of_line (); 3190 return; 3191 } 3192 3193 demand_empty_rest_of_line (); 3194 3195 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} 3196 into .unwind_save {..., sp...}. We aren't bothered about the value of 3197 ip because it is clobbered by calls. */ 3198 if (unwind.sp_restored && unwind.fp_reg == 12 3199 && (range & 0x3000) == 0x1000) 3200 { 3201 unwind.opcode_count--; 3202 unwind.sp_restored = 0; 3203 range = (range | 0x2000) & ~0x1000; 3204 unwind.pending_offset = 0; 3205 } 3206 3207 /* Pop r4-r15. */ 3208 if (range & 0xfff0) 3209 { 3210 /* See if we can use the short opcodes. These pop a block of up to 8 3211 registers starting with r4, plus maybe r14. */ 3212 for (n = 0; n < 8; n++) 3213 { 3214 /* Break at the first non-saved register. */ 3215 if ((range & (1 << (n + 4))) == 0) 3216 break; 3217 } 3218 /* See if there are any other bits set. */ 3219 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) 3220 { 3221 /* Use the long form. */ 3222 op = 0x8000 | ((range >> 4) & 0xfff); 3223 add_unwind_opcode (op, 2); 3224 } 3225 else 3226 { 3227 /* Use the short form. */ 3228 if (range & 0x4000) 3229 op = 0xa8; /* Pop r14. */ 3230 else 3231 op = 0xa0; /* Do not pop r14. */ 3232 op |= (n - 1); 3233 add_unwind_opcode (op, 1); 3234 } 3235 } 3236 3237 /* Pop r0-r3. */ 3238 if (range & 0xf) 3239 { 3240 op = 0xb100 | (range & 0xf); 3241 add_unwind_opcode (op, 2); 3242 } 3243 3244 /* Record the number of bytes pushed. */ 3245 for (n = 0; n < 16; n++) 3246 { 3247 if (range & (1 << n)) 3248 unwind.frame_size += 4; 3249 } 3250} 3251 3252 3253/* Parse a directive saving FPA registers. */ 3254 3255static void 3256s_arm_unwind_save_fpa (int reg) 3257{ 3258 expressionS exp; 3259 int num_regs; 3260 valueT op; 3261 3262 /* Get Number of registers to transfer. */ 3263 if (skip_past_comma (&input_line_pointer) != FAIL) 3264 expression (&exp); 3265 else 3266 exp.X_op = O_illegal; 3267 3268 if (exp.X_op != O_constant) 3269 { 3270 as_bad (_("expected , <constant>")); 3271 ignore_rest_of_line (); 3272 return; 3273 } 3274 3275 num_regs = exp.X_add_number; 3276 3277 if (num_regs < 1 || num_regs > 4) 3278 { 3279 as_bad (_("number of registers must be in the range [1:4]")); 3280 ignore_rest_of_line (); 3281 return; 3282 } 3283 3284 demand_empty_rest_of_line (); 3285 3286 if (reg == 4) 3287 { 3288 /* Short form. */ 3289 op = 0xb4 | (num_regs - 1); 3290 add_unwind_opcode (op, 1); 3291 } 3292 else 3293 { 3294 /* Long form. */ 3295 op = 0xc800 | (reg << 4) | (num_regs - 1); 3296 add_unwind_opcode (op, 2); 3297 } 3298 unwind.frame_size += num_regs * 12; 3299} 3300 3301 3302/* Parse a directive saving VFP registers for ARMv6 and above. */ 3303 3304static void 3305s_arm_unwind_save_vfp_armv6 (void) 3306{ 3307 int count; 3308 unsigned int start; 3309 valueT op; 3310 int num_vfpv3_regs = 0; 3311 int num_regs_below_16; 3312 3313 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); 3314 if (count == FAIL) 3315 { 3316 as_bad (_("expected register list")); 3317 ignore_rest_of_line (); 3318 return; 3319 } 3320 3321 demand_empty_rest_of_line (); 3322 3323 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather 3324 than FSTMX/FLDMX-style ones). */ 3325 3326 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ 3327 if (start >= 16) 3328 num_vfpv3_regs = count; 3329 else if (start + count > 16) 3330 num_vfpv3_regs = start + count - 16; 3331 3332 if (num_vfpv3_regs > 0) 3333 { 3334 int start_offset = start > 16 ? start - 16 : 0; 3335 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); 3336 add_unwind_opcode (op, 2); 3337 } 3338 3339 /* Generate opcode for registers numbered in the range 0 .. 15. */ 3340 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; 3341 assert (num_regs_below_16 + num_vfpv3_regs == count); 3342 if (num_regs_below_16 > 0) 3343 { 3344 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); 3345 add_unwind_opcode (op, 2); 3346 } 3347 3348 unwind.frame_size += count * 8; 3349} 3350 3351 3352/* Parse a directive saving VFP registers for pre-ARMv6. */ 3353 3354static void 3355s_arm_unwind_save_vfp (void) 3356{ 3357 int count; 3358 unsigned int reg; 3359 valueT op; 3360 3361 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); 3362 if (count == FAIL) 3363 { 3364 as_bad (_("expected register list")); 3365 ignore_rest_of_line (); 3366 return; 3367 } 3368 3369 demand_empty_rest_of_line (); 3370 3371 if (reg == 8) 3372 { 3373 /* Short form. */ 3374 op = 0xb8 | (count - 1); 3375 add_unwind_opcode (op, 1); 3376 } 3377 else 3378 { 3379 /* Long form. */ 3380 op = 0xb300 | (reg << 4) | (count - 1); 3381 add_unwind_opcode (op, 2); 3382 } 3383 unwind.frame_size += count * 8 + 4; 3384} 3385 3386 3387/* Parse a directive saving iWMMXt data registers. */ 3388 3389static void 3390s_arm_unwind_save_mmxwr (void) 3391{ 3392 int reg; 3393 int hi_reg; 3394 int i; 3395 unsigned mask = 0; 3396 valueT op; 3397 3398 if (*input_line_pointer == '{') 3399 input_line_pointer++; 3400 3401 do 3402 { 3403 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3404 3405 if (reg == FAIL) 3406 { 3407 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3408 goto error; 3409 } 3410 3411 if (mask >> reg) 3412 as_tsktsk (_("register list not in ascending order")); 3413 mask |= 1 << reg; 3414 3415 if (*input_line_pointer == '-') 3416 { 3417 input_line_pointer++; 3418 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3419 if (hi_reg == FAIL) 3420 { 3421 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3422 goto error; 3423 } 3424 else if (reg >= hi_reg) 3425 { 3426 as_bad (_("bad register range")); 3427 goto error; 3428 } 3429 for (; reg < hi_reg; reg++) 3430 mask |= 1 << reg; 3431 } 3432 } 3433 while (skip_past_comma (&input_line_pointer) != FAIL); 3434 3435 if (*input_line_pointer == '}') 3436 input_line_pointer++; 3437 3438 demand_empty_rest_of_line (); 3439 3440 /* Generate any deferred opcodes because we're going to be looking at 3441 the list. */ 3442 flush_pending_unwind (); 3443 3444 for (i = 0; i < 16; i++) 3445 { 3446 if (mask & (1 << i)) 3447 unwind.frame_size += 8; 3448 } 3449 3450 /* Attempt to combine with a previous opcode. We do this because gcc 3451 likes to output separate unwind directives for a single block of 3452 registers. */ 3453 if (unwind.opcode_count > 0) 3454 { 3455 i = unwind.opcodes[unwind.opcode_count - 1]; 3456 if ((i & 0xf8) == 0xc0) 3457 { 3458 i &= 7; 3459 /* Only merge if the blocks are contiguous. */ 3460 if (i < 6) 3461 { 3462 if ((mask & 0xfe00) == (1 << 9)) 3463 { 3464 mask |= ((1 << (i + 11)) - 1) & 0xfc00; 3465 unwind.opcode_count--; 3466 } 3467 } 3468 else if (i == 6 && unwind.opcode_count >= 2) 3469 { 3470 i = unwind.opcodes[unwind.opcode_count - 2]; 3471 reg = i >> 4; 3472 i &= 0xf; 3473 3474 op = 0xffff << (reg - 1); 3475 if (reg > 0 3476 && ((mask & op) == (1u << (reg - 1)))) 3477 { 3478 op = (1 << (reg + i + 1)) - 1; 3479 op &= ~((1 << reg) - 1); 3480 mask |= op; 3481 unwind.opcode_count -= 2; 3482 } 3483 } 3484 } 3485 } 3486 3487 hi_reg = 15; 3488 /* We want to generate opcodes in the order the registers have been 3489 saved, ie. descending order. */ 3490 for (reg = 15; reg >= -1; reg--) 3491 { 3492 /* Save registers in blocks. */ 3493 if (reg < 0 3494 || !(mask & (1 << reg))) 3495 { 3496 /* We found an unsaved reg. Generate opcodes to save the 3497 preceeding block. */ 3498 if (reg != hi_reg) 3499 { 3500 if (reg == 9) 3501 { 3502 /* Short form. */ 3503 op = 0xc0 | (hi_reg - 10); 3504 add_unwind_opcode (op, 1); 3505 } 3506 else 3507 { 3508 /* Long form. */ 3509 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); 3510 add_unwind_opcode (op, 2); 3511 } 3512 } 3513 hi_reg = reg - 1; 3514 } 3515 } 3516 3517 return; 3518error: 3519 ignore_rest_of_line (); 3520} 3521 3522static void 3523s_arm_unwind_save_mmxwcg (void) 3524{ 3525 int reg; 3526 int hi_reg; 3527 unsigned mask = 0; 3528 valueT op; 3529 3530 if (*input_line_pointer == '{') 3531 input_line_pointer++; 3532 3533 do 3534 { 3535 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3536 3537 if (reg == FAIL) 3538 { 3539 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3540 goto error; 3541 } 3542 3543 reg -= 8; 3544 if (mask >> reg) 3545 as_tsktsk (_("register list not in ascending order")); 3546 mask |= 1 << reg; 3547 3548 if (*input_line_pointer == '-') 3549 { 3550 input_line_pointer++; 3551 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3552 if (hi_reg == FAIL) 3553 { 3554 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3555 goto error; 3556 } 3557 else if (reg >= hi_reg) 3558 { 3559 as_bad (_("bad register range")); 3560 goto error; 3561 } 3562 for (; reg < hi_reg; reg++) 3563 mask |= 1 << reg; 3564 } 3565 } 3566 while (skip_past_comma (&input_line_pointer) != FAIL); 3567 3568 if (*input_line_pointer == '}') 3569 input_line_pointer++; 3570 3571 demand_empty_rest_of_line (); 3572 3573 /* Generate any deferred opcodes because we're going to be looking at 3574 the list. */ 3575 flush_pending_unwind (); 3576 3577 for (reg = 0; reg < 16; reg++) 3578 { 3579 if (mask & (1 << reg)) 3580 unwind.frame_size += 4; 3581 } 3582 op = 0xc700 | mask; 3583 add_unwind_opcode (op, 2); 3584 return; 3585error: 3586 ignore_rest_of_line (); 3587} 3588 3589 3590/* Parse an unwind_save directive. 3591 If the argument is non-zero, this is a .vsave directive. */ 3592 3593static void 3594s_arm_unwind_save (int arch_v6) 3595{ 3596 char *peek; 3597 struct reg_entry *reg; 3598 bfd_boolean had_brace = FALSE; 3599 3600 /* Figure out what sort of save we have. */ 3601 peek = input_line_pointer; 3602 3603 if (*peek == '{') 3604 { 3605 had_brace = TRUE; 3606 peek++; 3607 } 3608 3609 reg = arm_reg_parse_multi (&peek); 3610 3611 if (!reg) 3612 { 3613 as_bad (_("register expected")); 3614 ignore_rest_of_line (); 3615 return; 3616 } 3617 3618 switch (reg->type) 3619 { 3620 case REG_TYPE_FN: 3621 if (had_brace) 3622 { 3623 as_bad (_("FPA .unwind_save does not take a register list")); 3624 ignore_rest_of_line (); 3625 return; 3626 } 3627 s_arm_unwind_save_fpa (reg->number); 3628 return; 3629 3630 case REG_TYPE_RN: s_arm_unwind_save_core (); return; 3631 case REG_TYPE_VFD: 3632 if (arch_v6) 3633 s_arm_unwind_save_vfp_armv6 (); 3634 else 3635 s_arm_unwind_save_vfp (); 3636 return; 3637 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; 3638 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; 3639 3640 default: 3641 as_bad (_(".unwind_save does not support this kind of register")); 3642 ignore_rest_of_line (); 3643 } 3644} 3645 3646 3647/* Parse an unwind_movsp directive. */ 3648 3649static void 3650s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) 3651{ 3652 int reg; 3653 valueT op; 3654 int offset; 3655 3656 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3657 if (reg == FAIL) 3658 { 3659 as_bad (_(reg_expected_msgs[REG_TYPE_RN])); 3660 ignore_rest_of_line (); 3661 return; 3662 } 3663 3664 /* Optional constant. */ 3665 if (skip_past_comma (&input_line_pointer) != FAIL) 3666 { 3667 if (immediate_for_directive (&offset) == FAIL) 3668 return; 3669 } 3670 else 3671 offset = 0; 3672 3673 demand_empty_rest_of_line (); 3674 3675 if (reg == REG_SP || reg == REG_PC) 3676 { 3677 as_bad (_("SP and PC not permitted in .unwind_movsp directive")); 3678 return; 3679 } 3680 3681 if (unwind.fp_reg != REG_SP) 3682 as_bad (_("unexpected .unwind_movsp directive")); 3683 3684 /* Generate opcode to restore the value. */ 3685 op = 0x90 | reg; 3686 add_unwind_opcode (op, 1); 3687 3688 /* Record the information for later. */ 3689 unwind.fp_reg = reg; 3690 unwind.fp_offset = unwind.frame_size - offset; 3691 unwind.sp_restored = 1; 3692} 3693 3694/* Parse an unwind_pad directive. */ 3695 3696static void 3697s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) 3698{ 3699 int offset; 3700 3701 if (immediate_for_directive (&offset) == FAIL) 3702 return; 3703 3704 if (offset & 3) 3705 { 3706 as_bad (_("stack increment must be multiple of 4")); 3707 ignore_rest_of_line (); 3708 return; 3709 } 3710 3711 /* Don't generate any opcodes, just record the details for later. */ 3712 unwind.frame_size += offset; 3713 unwind.pending_offset += offset; 3714 3715 demand_empty_rest_of_line (); 3716} 3717 3718/* Parse an unwind_setfp directive. */ 3719 3720static void 3721s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) 3722{ 3723 int sp_reg; 3724 int fp_reg; 3725 int offset; 3726 3727 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3728 if (skip_past_comma (&input_line_pointer) == FAIL) 3729 sp_reg = FAIL; 3730 else 3731 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3732 3733 if (fp_reg == FAIL || sp_reg == FAIL) 3734 { 3735 as_bad (_("expected <reg>, <reg>")); 3736 ignore_rest_of_line (); 3737 return; 3738 } 3739 3740 /* Optional constant. */ 3741 if (skip_past_comma (&input_line_pointer) != FAIL) 3742 { 3743 if (immediate_for_directive (&offset) == FAIL) 3744 return; 3745 } 3746 else 3747 offset = 0; 3748 3749 demand_empty_rest_of_line (); 3750 3751 if (sp_reg != 13 && sp_reg != unwind.fp_reg) 3752 { 3753 as_bad (_("register must be either sp or set by a previous" 3754 "unwind_movsp directive")); 3755 return; 3756 } 3757 3758 /* Don't generate any opcodes, just record the information for later. */ 3759 unwind.fp_reg = fp_reg; 3760 unwind.fp_used = 1; 3761 if (sp_reg == 13) 3762 unwind.fp_offset = unwind.frame_size - offset; 3763 else 3764 unwind.fp_offset -= offset; 3765} 3766 3767/* Parse an unwind_raw directive. */ 3768 3769static void 3770s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) 3771{ 3772 expressionS exp; 3773 /* This is an arbitrary limit. */ 3774 unsigned char op[16]; 3775 int count; 3776 3777 expression (&exp); 3778 if (exp.X_op == O_constant 3779 && skip_past_comma (&input_line_pointer) != FAIL) 3780 { 3781 unwind.frame_size += exp.X_add_number; 3782 expression (&exp); 3783 } 3784 else 3785 exp.X_op = O_illegal; 3786 3787 if (exp.X_op != O_constant) 3788 { 3789 as_bad (_("expected <offset>, <opcode>")); 3790 ignore_rest_of_line (); 3791 return; 3792 } 3793 3794 count = 0; 3795 3796 /* Parse the opcode. */ 3797 for (;;) 3798 { 3799 if (count >= 16) 3800 { 3801 as_bad (_("unwind opcode too long")); 3802 ignore_rest_of_line (); 3803 } 3804 if (exp.X_op != O_constant || exp.X_add_number & ~0xff) 3805 { 3806 as_bad (_("invalid unwind opcode")); 3807 ignore_rest_of_line (); 3808 return; 3809 } 3810 op[count++] = exp.X_add_number; 3811 3812 /* Parse the next byte. */ 3813 if (skip_past_comma (&input_line_pointer) == FAIL) 3814 break; 3815 3816 expression (&exp); 3817 } 3818 3819 /* Add the opcode bytes in reverse order. */ 3820 while (count--) 3821 add_unwind_opcode (op[count], 1); 3822 3823 demand_empty_rest_of_line (); 3824} 3825 3826 3827/* Parse a .eabi_attribute directive. */ 3828 3829static void 3830s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) 3831{ 3832 s_vendor_attribute (OBJ_ATTR_PROC); 3833} 3834#endif /* OBJ_ELF */ 3835 3836static void s_arm_arch (int); 3837static void s_arm_object_arch (int); 3838static void s_arm_cpu (int); 3839static void s_arm_fpu (int); 3840 3841#ifdef TE_PE 3842 3843static void 3844pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 3845{ 3846 expressionS exp; 3847 3848 do 3849 { 3850 expression (&exp); 3851 if (exp.X_op == O_symbol) 3852 exp.X_op = O_secrel; 3853 3854 emit_expr (&exp, 4); 3855 } 3856 while (*input_line_pointer++ == ','); 3857 3858 input_line_pointer--; 3859 demand_empty_rest_of_line (); 3860} 3861#endif /* TE_PE */ 3862 3863/* This table describes all the machine specific pseudo-ops the assembler 3864 has to support. The fields are: 3865 pseudo-op name without dot 3866 function to call to execute this pseudo-op 3867 Integer arg to pass to the function. */ 3868 3869const pseudo_typeS md_pseudo_table[] = 3870{ 3871 /* Never called because '.req' does not start a line. */ 3872 { "req", s_req, 0 }, 3873 /* Following two are likewise never called. */ 3874 { "dn", s_dn, 0 }, 3875 { "qn", s_qn, 0 }, 3876 { "unreq", s_unreq, 0 }, 3877 { "bss", s_bss, 0 }, 3878 { "align", s_align, 0 }, 3879 { "arm", s_arm, 0 }, 3880 { "thumb", s_thumb, 0 }, 3881 { "code", s_code, 0 }, 3882 { "force_thumb", s_force_thumb, 0 }, 3883 { "thumb_func", s_thumb_func, 0 }, 3884 { "thumb_set", s_thumb_set, 0 }, 3885 { "even", s_even, 0 }, 3886 { "ltorg", s_ltorg, 0 }, 3887 { "pool", s_ltorg, 0 }, 3888 { "syntax", s_syntax, 0 }, 3889 { "cpu", s_arm_cpu, 0 }, 3890 { "arch", s_arm_arch, 0 }, 3891 { "object_arch", s_arm_object_arch, 0 }, 3892 { "fpu", s_arm_fpu, 0 }, 3893#ifdef OBJ_ELF 3894 { "word", s_arm_elf_cons, 4 }, 3895 { "long", s_arm_elf_cons, 4 }, 3896 { "rel31", s_arm_rel31, 0 }, 3897 { "fnstart", s_arm_unwind_fnstart, 0 }, 3898 { "fnend", s_arm_unwind_fnend, 0 }, 3899 { "cantunwind", s_arm_unwind_cantunwind, 0 }, 3900 { "personality", s_arm_unwind_personality, 0 }, 3901 { "personalityindex", s_arm_unwind_personalityindex, 0 }, 3902 { "handlerdata", s_arm_unwind_handlerdata, 0 }, 3903 { "save", s_arm_unwind_save, 0 }, 3904 { "vsave", s_arm_unwind_save, 1 }, 3905 { "movsp", s_arm_unwind_movsp, 0 }, 3906 { "pad", s_arm_unwind_pad, 0 }, 3907 { "setfp", s_arm_unwind_setfp, 0 }, 3908 { "unwind_raw", s_arm_unwind_raw, 0 }, 3909 { "eabi_attribute", s_arm_eabi_attribute, 0 }, 3910#else 3911 { "word", cons, 4}, 3912 3913 /* These are used for dwarf. */ 3914 {"2byte", cons, 2}, 3915 {"4byte", cons, 4}, 3916 {"8byte", cons, 8}, 3917 /* These are used for dwarf2. */ 3918 { "file", (void (*) (int)) dwarf2_directive_file, 0 }, 3919 { "loc", dwarf2_directive_loc, 0 }, 3920 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, 3921#endif 3922 { "extend", float_cons, 'x' }, 3923 { "ldouble", float_cons, 'x' }, 3924 { "packed", float_cons, 'p' }, 3925#ifdef TE_PE 3926 {"secrel32", pe_directive_secrel, 0}, 3927#endif 3928 { 0, 0, 0 } 3929}; 3930 3931/* Parser functions used exclusively in instruction operands. */ 3932 3933/* Generic immediate-value read function for use in insn parsing. 3934 STR points to the beginning of the immediate (the leading #); 3935 VAL receives the value; if the value is outside [MIN, MAX] 3936 issue an error. PREFIX_OPT is true if the immediate prefix is 3937 optional. */ 3938 3939static int 3940parse_immediate (char **str, int *val, int min, int max, 3941 bfd_boolean prefix_opt) 3942{ 3943 expressionS exp; 3944 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); 3945 if (exp.X_op != O_constant) 3946 { 3947 inst.error = _("constant expression required"); 3948 return FAIL; 3949 } 3950 3951 if (exp.X_add_number < min || exp.X_add_number > max) 3952 { 3953 inst.error = _("immediate value out of range"); 3954 return FAIL; 3955 } 3956 3957 *val = exp.X_add_number; 3958 return SUCCESS; 3959} 3960 3961/* Less-generic immediate-value read function with the possibility of loading a 3962 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate 3963 instructions. Puts the result directly in inst.operands[i]. */ 3964 3965static int 3966parse_big_immediate (char **str, int i) 3967{ 3968 expressionS exp; 3969 char *ptr = *str; 3970 3971 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); 3972 3973 if (exp.X_op == O_constant) 3974 { 3975 inst.operands[i].imm = exp.X_add_number & 0xffffffff; 3976 /* If we're on a 64-bit host, then a 64-bit number can be returned using 3977 O_constant. We have to be careful not to break compilation for 3978 32-bit X_add_number, though. */ 3979 if ((exp.X_add_number & ~0xffffffffl) != 0) 3980 { 3981 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ 3982 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; 3983 inst.operands[i].regisimm = 1; 3984 } 3985 } 3986 else if (exp.X_op == O_big 3987 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 3988 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) 3989 { 3990 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; 3991 /* Bignums have their least significant bits in 3992 generic_bignum[0]. Make sure we put 32 bits in imm and 3993 32 bits in reg, in a (hopefully) portable way. */ 3994 assert (parts != 0); 3995 inst.operands[i].imm = 0; 3996 for (j = 0; j < parts; j++, idx++) 3997 inst.operands[i].imm |= generic_bignum[idx] 3998 << (LITTLENUM_NUMBER_OF_BITS * j); 3999 inst.operands[i].reg = 0; 4000 for (j = 0; j < parts; j++, idx++) 4001 inst.operands[i].reg |= generic_bignum[idx] 4002 << (LITTLENUM_NUMBER_OF_BITS * j); 4003 inst.operands[i].regisimm = 1; 4004 } 4005 else 4006 return FAIL; 4007 4008 *str = ptr; 4009 4010 return SUCCESS; 4011} 4012 4013/* Returns the pseudo-register number of an FPA immediate constant, 4014 or FAIL if there isn't a valid constant here. */ 4015 4016static int 4017parse_fpa_immediate (char ** str) 4018{ 4019 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4020 char * save_in; 4021 expressionS exp; 4022 int i; 4023 int j; 4024 4025 /* First try and match exact strings, this is to guarantee 4026 that some formats will work even for cross assembly. */ 4027 4028 for (i = 0; fp_const[i]; i++) 4029 { 4030 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) 4031 { 4032 char *start = *str; 4033 4034 *str += strlen (fp_const[i]); 4035 if (is_end_of_line[(unsigned char) **str]) 4036 return i + 8; 4037 *str = start; 4038 } 4039 } 4040 4041 /* Just because we didn't get a match doesn't mean that the constant 4042 isn't valid, just that it is in a format that we don't 4043 automatically recognize. Try parsing it with the standard 4044 expression routines. */ 4045 4046 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); 4047 4048 /* Look for a raw floating point number. */ 4049 if ((save_in = atof_ieee (*str, 'x', words)) != NULL 4050 && is_end_of_line[(unsigned char) *save_in]) 4051 { 4052 for (i = 0; i < NUM_FLOAT_VALS; i++) 4053 { 4054 for (j = 0; j < MAX_LITTLENUMS; j++) 4055 { 4056 if (words[j] != fp_values[i][j]) 4057 break; 4058 } 4059 4060 if (j == MAX_LITTLENUMS) 4061 { 4062 *str = save_in; 4063 return i + 8; 4064 } 4065 } 4066 } 4067 4068 /* Try and parse a more complex expression, this will probably fail 4069 unless the code uses a floating point prefix (eg "0f"). */ 4070 save_in = input_line_pointer; 4071 input_line_pointer = *str; 4072 if (expression (&exp) == absolute_section 4073 && exp.X_op == O_big 4074 && exp.X_add_number < 0) 4075 { 4076 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. 4077 Ditto for 15. */ 4078 if (gen_to_words (words, 5, (long) 15) == 0) 4079 { 4080 for (i = 0; i < NUM_FLOAT_VALS; i++) 4081 { 4082 for (j = 0; j < MAX_LITTLENUMS; j++) 4083 { 4084 if (words[j] != fp_values[i][j]) 4085 break; 4086 } 4087 4088 if (j == MAX_LITTLENUMS) 4089 { 4090 *str = input_line_pointer; 4091 input_line_pointer = save_in; 4092 return i + 8; 4093 } 4094 } 4095 } 4096 } 4097 4098 *str = input_line_pointer; 4099 input_line_pointer = save_in; 4100 inst.error = _("invalid FPA immediate expression"); 4101 return FAIL; 4102} 4103 4104/* Returns 1 if a number has "quarter-precision" float format 4105 0baBbbbbbc defgh000 00000000 00000000. */ 4106 4107static int 4108is_quarter_float (unsigned imm) 4109{ 4110 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; 4111 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; 4112} 4113 4114/* Parse an 8-bit "quarter-precision" floating point number of the form: 4115 0baBbbbbbc defgh000 00000000 00000000. 4116 The zero and minus-zero cases need special handling, since they can't be 4117 encoded in the "quarter-precision" float format, but can nonetheless be 4118 loaded as integer constants. */ 4119 4120static unsigned 4121parse_qfloat_immediate (char **ccp, int *immed) 4122{ 4123 char *str = *ccp; 4124 char *fpnum; 4125 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4126 int found_fpchar = 0; 4127 4128 skip_past_char (&str, '#'); 4129 4130 /* We must not accidentally parse an integer as a floating-point number. Make 4131 sure that the value we parse is not an integer by checking for special 4132 characters '.' or 'e'. 4133 FIXME: This is a horrible hack, but doing better is tricky because type 4134 information isn't in a very usable state at parse time. */ 4135 fpnum = str; 4136 skip_whitespace (fpnum); 4137 4138 if (strncmp (fpnum, "0x", 2) == 0) 4139 return FAIL; 4140 else 4141 { 4142 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) 4143 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') 4144 { 4145 found_fpchar = 1; 4146 break; 4147 } 4148 4149 if (!found_fpchar) 4150 return FAIL; 4151 } 4152 4153 if ((str = atof_ieee (str, 's', words)) != NULL) 4154 { 4155 unsigned fpword = 0; 4156 int i; 4157 4158 /* Our FP word must be 32 bits (single-precision FP). */ 4159 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) 4160 { 4161 fpword <<= LITTLENUM_NUMBER_OF_BITS; 4162 fpword |= words[i]; 4163 } 4164 4165 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) 4166 *immed = fpword; 4167 else 4168 return FAIL; 4169 4170 *ccp = str; 4171 4172 return SUCCESS; 4173 } 4174 4175 return FAIL; 4176} 4177 4178/* Shift operands. */ 4179enum shift_kind 4180{ 4181 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX 4182}; 4183 4184struct asm_shift_name 4185{ 4186 const char *name; 4187 enum shift_kind kind; 4188}; 4189 4190/* Third argument to parse_shift. */ 4191enum parse_shift_mode 4192{ 4193 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ 4194 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ 4195 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ 4196 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ 4197 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ 4198}; 4199 4200/* Parse a <shift> specifier on an ARM data processing instruction. 4201 This has three forms: 4202 4203 (LSL|LSR|ASL|ASR|ROR) Rs 4204 (LSL|LSR|ASL|ASR|ROR) #imm 4205 RRX 4206 4207 Note that ASL is assimilated to LSL in the instruction encoding, and 4208 RRX to ROR #0 (which cannot be written as such). */ 4209 4210static int 4211parse_shift (char **str, int i, enum parse_shift_mode mode) 4212{ 4213 const struct asm_shift_name *shift_name; 4214 enum shift_kind shift; 4215 char *s = *str; 4216 char *p = s; 4217 int reg; 4218 4219 for (p = *str; ISALPHA (*p); p++) 4220 ; 4221 4222 if (p == *str) 4223 { 4224 inst.error = _("shift expression expected"); 4225 return FAIL; 4226 } 4227 4228 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); 4229 4230 if (shift_name == NULL) 4231 { 4232 inst.error = _("shift expression expected"); 4233 return FAIL; 4234 } 4235 4236 shift = shift_name->kind; 4237 4238 switch (mode) 4239 { 4240 case NO_SHIFT_RESTRICT: 4241 case SHIFT_IMMEDIATE: break; 4242 4243 case SHIFT_LSL_OR_ASR_IMMEDIATE: 4244 if (shift != SHIFT_LSL && shift != SHIFT_ASR) 4245 { 4246 inst.error = _("'LSL' or 'ASR' required"); 4247 return FAIL; 4248 } 4249 break; 4250 4251 case SHIFT_LSL_IMMEDIATE: 4252 if (shift != SHIFT_LSL) 4253 { 4254 inst.error = _("'LSL' required"); 4255 return FAIL; 4256 } 4257 break; 4258 4259 case SHIFT_ASR_IMMEDIATE: 4260 if (shift != SHIFT_ASR) 4261 { 4262 inst.error = _("'ASR' required"); 4263 return FAIL; 4264 } 4265 break; 4266 4267 default: abort (); 4268 } 4269 4270 if (shift != SHIFT_RRX) 4271 { 4272 /* Whitespace can appear here if the next thing is a bare digit. */ 4273 skip_whitespace (p); 4274 4275 if (mode == NO_SHIFT_RESTRICT 4276 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4277 { 4278 inst.operands[i].imm = reg; 4279 inst.operands[i].immisreg = 1; 4280 } 4281 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4282 return FAIL; 4283 } 4284 inst.operands[i].shift_kind = shift; 4285 inst.operands[i].shifted = 1; 4286 *str = p; 4287 return SUCCESS; 4288} 4289 4290/* Parse a <shifter_operand> for an ARM data processing instruction: 4291 4292 #<immediate> 4293 #<immediate>, <rotate> 4294 <Rm> 4295 <Rm>, <shift> 4296 4297 where <shift> is defined by parse_shift above, and <rotate> is a 4298 multiple of 2 between 0 and 30. Validation of immediate operands 4299 is deferred to md_apply_fix. */ 4300 4301static int 4302parse_shifter_operand (char **str, int i) 4303{ 4304 int value; 4305 expressionS expr; 4306 4307 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) 4308 { 4309 inst.operands[i].reg = value; 4310 inst.operands[i].isreg = 1; 4311 4312 /* parse_shift will override this if appropriate */ 4313 inst.reloc.exp.X_op = O_constant; 4314 inst.reloc.exp.X_add_number = 0; 4315 4316 if (skip_past_comma (str) == FAIL) 4317 return SUCCESS; 4318 4319 /* Shift operation on register. */ 4320 return parse_shift (str, i, NO_SHIFT_RESTRICT); 4321 } 4322 4323 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) 4324 return FAIL; 4325 4326 if (skip_past_comma (str) == SUCCESS) 4327 { 4328 /* #x, y -- ie explicit rotation by Y. */ 4329 if (my_get_expression (&expr, str, GE_NO_PREFIX)) 4330 return FAIL; 4331 4332 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) 4333 { 4334 inst.error = _("constant expression expected"); 4335 return FAIL; 4336 } 4337 4338 value = expr.X_add_number; 4339 if (value < 0 || value > 30 || value % 2 != 0) 4340 { 4341 inst.error = _("invalid rotation"); 4342 return FAIL; 4343 } 4344 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) 4345 { 4346 inst.error = _("invalid constant"); 4347 return FAIL; 4348 } 4349 4350 /* Convert to decoded value. md_apply_fix will put it back. */ 4351 inst.reloc.exp.X_add_number 4352 = (((inst.reloc.exp.X_add_number << (32 - value)) 4353 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); 4354 } 4355 4356 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 4357 inst.reloc.pc_rel = 0; 4358 return SUCCESS; 4359} 4360 4361/* Group relocation information. Each entry in the table contains the 4362 textual name of the relocation as may appear in assembler source 4363 and must end with a colon. 4364 Along with this textual name are the relocation codes to be used if 4365 the corresponding instruction is an ALU instruction (ADD or SUB only), 4366 an LDR, an LDRS, or an LDC. */ 4367 4368struct group_reloc_table_entry 4369{ 4370 const char *name; 4371 int alu_code; 4372 int ldr_code; 4373 int ldrs_code; 4374 int ldc_code; 4375}; 4376 4377typedef enum 4378{ 4379 /* Varieties of non-ALU group relocation. */ 4380 4381 GROUP_LDR, 4382 GROUP_LDRS, 4383 GROUP_LDC 4384} group_reloc_type; 4385 4386static struct group_reloc_table_entry group_reloc_table[] = 4387 { /* Program counter relative: */ 4388 { "pc_g0_nc", 4389 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ 4390 0, /* LDR */ 4391 0, /* LDRS */ 4392 0 }, /* LDC */ 4393 { "pc_g0", 4394 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ 4395 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ 4396 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ 4397 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ 4398 { "pc_g1_nc", 4399 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ 4400 0, /* LDR */ 4401 0, /* LDRS */ 4402 0 }, /* LDC */ 4403 { "pc_g1", 4404 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ 4405 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ 4406 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ 4407 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ 4408 { "pc_g2", 4409 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ 4410 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ 4411 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ 4412 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ 4413 /* Section base relative */ 4414 { "sb_g0_nc", 4415 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ 4416 0, /* LDR */ 4417 0, /* LDRS */ 4418 0 }, /* LDC */ 4419 { "sb_g0", 4420 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ 4421 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ 4422 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ 4423 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ 4424 { "sb_g1_nc", 4425 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ 4426 0, /* LDR */ 4427 0, /* LDRS */ 4428 0 }, /* LDC */ 4429 { "sb_g1", 4430 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ 4431 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ 4432 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ 4433 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ 4434 { "sb_g2", 4435 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ 4436 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ 4437 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ 4438 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ 4439 4440/* Given the address of a pointer pointing to the textual name of a group 4441 relocation as may appear in assembler source, attempt to find its details 4442 in group_reloc_table. The pointer will be updated to the character after 4443 the trailing colon. On failure, FAIL will be returned; SUCCESS 4444 otherwise. On success, *entry will be updated to point at the relevant 4445 group_reloc_table entry. */ 4446 4447static int 4448find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) 4449{ 4450 unsigned int i; 4451 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) 4452 { 4453 int length = strlen (group_reloc_table[i].name); 4454 4455 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 && 4456 (*str)[length] == ':') 4457 { 4458 *out = &group_reloc_table[i]; 4459 *str += (length + 1); 4460 return SUCCESS; 4461 } 4462 } 4463 4464 return FAIL; 4465} 4466 4467/* Parse a <shifter_operand> for an ARM data processing instruction 4468 (as for parse_shifter_operand) where group relocations are allowed: 4469 4470 #<immediate> 4471 #<immediate>, <rotate> 4472 #:<group_reloc>:<expression> 4473 <Rm> 4474 <Rm>, <shift> 4475 4476 where <group_reloc> is one of the strings defined in group_reloc_table. 4477 The hashes are optional. 4478 4479 Everything else is as for parse_shifter_operand. */ 4480 4481static parse_operand_result 4482parse_shifter_operand_group_reloc (char **str, int i) 4483{ 4484 /* Determine if we have the sequence of characters #: or just : 4485 coming next. If we do, then we check for a group relocation. 4486 If we don't, punt the whole lot to parse_shifter_operand. */ 4487 4488 if (((*str)[0] == '#' && (*str)[1] == ':') 4489 || (*str)[0] == ':') 4490 { 4491 struct group_reloc_table_entry *entry; 4492 4493 if ((*str)[0] == '#') 4494 (*str) += 2; 4495 else 4496 (*str)++; 4497 4498 /* Try to parse a group relocation. Anything else is an error. */ 4499 if (find_group_reloc_table_entry (str, &entry) == FAIL) 4500 { 4501 inst.error = _("unknown group relocation"); 4502 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4503 } 4504 4505 /* We now have the group relocation table entry corresponding to 4506 the name in the assembler source. Next, we parse the expression. */ 4507 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) 4508 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4509 4510 /* Record the relocation type (always the ALU variant here). */ 4511 inst.reloc.type = entry->alu_code; 4512 assert (inst.reloc.type != 0); 4513 4514 return PARSE_OPERAND_SUCCESS; 4515 } 4516 else 4517 return parse_shifter_operand (str, i) == SUCCESS 4518 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; 4519 4520 /* Never reached. */ 4521} 4522 4523/* Parse all forms of an ARM address expression. Information is written 4524 to inst.operands[i] and/or inst.reloc. 4525 4526 Preindexed addressing (.preind=1): 4527 4528 [Rn, #offset] .reg=Rn .reloc.exp=offset 4529 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4530 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4531 .shift_kind=shift .reloc.exp=shift_imm 4532 4533 These three may have a trailing ! which causes .writeback to be set also. 4534 4535 Postindexed addressing (.postind=1, .writeback=1): 4536 4537 [Rn], #offset .reg=Rn .reloc.exp=offset 4538 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4539 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4540 .shift_kind=shift .reloc.exp=shift_imm 4541 4542 Unindexed addressing (.preind=0, .postind=0): 4543 4544 [Rn], {option} .reg=Rn .imm=option .immisreg=0 4545 4546 Other: 4547 4548 [Rn]{!} shorthand for [Rn,#0]{!} 4549 =immediate .isreg=0 .reloc.exp=immediate 4550 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label 4551 4552 It is the caller's responsibility to check for addressing modes not 4553 supported by the instruction, and to set inst.reloc.type. */ 4554 4555static parse_operand_result 4556parse_address_main (char **str, int i, int group_relocations, 4557 group_reloc_type group_type) 4558{ 4559 char *p = *str; 4560 int reg; 4561 4562 if (skip_past_char (&p, '[') == FAIL) 4563 { 4564 if (skip_past_char (&p, '=') == FAIL) 4565 { 4566 /* bare address - translate to PC-relative offset */ 4567 inst.reloc.pc_rel = 1; 4568 inst.operands[i].reg = REG_PC; 4569 inst.operands[i].isreg = 1; 4570 inst.operands[i].preind = 1; 4571 } 4572 /* else a load-constant pseudo op, no special treatment needed here */ 4573 4574 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4575 return PARSE_OPERAND_FAIL; 4576 4577 *str = p; 4578 return PARSE_OPERAND_SUCCESS; 4579 } 4580 4581 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 4582 { 4583 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 4584 return PARSE_OPERAND_FAIL; 4585 } 4586 inst.operands[i].reg = reg; 4587 inst.operands[i].isreg = 1; 4588 4589 if (skip_past_comma (&p) == SUCCESS) 4590 { 4591 inst.operands[i].preind = 1; 4592 4593 if (*p == '+') p++; 4594 else if (*p == '-') p++, inst.operands[i].negative = 1; 4595 4596 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4597 { 4598 inst.operands[i].imm = reg; 4599 inst.operands[i].immisreg = 1; 4600 4601 if (skip_past_comma (&p) == SUCCESS) 4602 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4603 return PARSE_OPERAND_FAIL; 4604 } 4605 else if (skip_past_char (&p, ':') == SUCCESS) 4606 { 4607 /* FIXME: '@' should be used here, but it's filtered out by generic 4608 code before we get to see it here. This may be subject to 4609 change. */ 4610 expressionS exp; 4611 my_get_expression (&exp, &p, GE_NO_PREFIX); 4612 if (exp.X_op != O_constant) 4613 { 4614 inst.error = _("alignment must be constant"); 4615 return PARSE_OPERAND_FAIL; 4616 } 4617 inst.operands[i].imm = exp.X_add_number << 8; 4618 inst.operands[i].immisalign = 1; 4619 /* Alignments are not pre-indexes. */ 4620 inst.operands[i].preind = 0; 4621 } 4622 else 4623 { 4624 if (inst.operands[i].negative) 4625 { 4626 inst.operands[i].negative = 0; 4627 p--; 4628 } 4629 4630 if (group_relocations && 4631 ((*p == '#' && *(p + 1) == ':') || *p == ':')) 4632 4633 { 4634 struct group_reloc_table_entry *entry; 4635 4636 /* Skip over the #: or : sequence. */ 4637 if (*p == '#') 4638 p += 2; 4639 else 4640 p++; 4641 4642 /* Try to parse a group relocation. Anything else is an 4643 error. */ 4644 if (find_group_reloc_table_entry (&p, &entry) == FAIL) 4645 { 4646 inst.error = _("unknown group relocation"); 4647 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4648 } 4649 4650 /* We now have the group relocation table entry corresponding to 4651 the name in the assembler source. Next, we parse the 4652 expression. */ 4653 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4654 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4655 4656 /* Record the relocation type. */ 4657 switch (group_type) 4658 { 4659 case GROUP_LDR: 4660 inst.reloc.type = entry->ldr_code; 4661 break; 4662 4663 case GROUP_LDRS: 4664 inst.reloc.type = entry->ldrs_code; 4665 break; 4666 4667 case GROUP_LDC: 4668 inst.reloc.type = entry->ldc_code; 4669 break; 4670 4671 default: 4672 assert (0); 4673 } 4674 4675 if (inst.reloc.type == 0) 4676 { 4677 inst.error = _("this group relocation is not allowed on this instruction"); 4678 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4679 } 4680 } 4681 else 4682 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4683 return PARSE_OPERAND_FAIL; 4684 } 4685 } 4686 4687 if (skip_past_char (&p, ']') == FAIL) 4688 { 4689 inst.error = _("']' expected"); 4690 return PARSE_OPERAND_FAIL; 4691 } 4692 4693 if (skip_past_char (&p, '!') == SUCCESS) 4694 inst.operands[i].writeback = 1; 4695 4696 else if (skip_past_comma (&p) == SUCCESS) 4697 { 4698 if (skip_past_char (&p, '{') == SUCCESS) 4699 { 4700 /* [Rn], {expr} - unindexed, with option */ 4701 if (parse_immediate (&p, &inst.operands[i].imm, 4702 0, 255, TRUE) == FAIL) 4703 return PARSE_OPERAND_FAIL; 4704 4705 if (skip_past_char (&p, '}') == FAIL) 4706 { 4707 inst.error = _("'}' expected at end of 'option' field"); 4708 return PARSE_OPERAND_FAIL; 4709 } 4710 if (inst.operands[i].preind) 4711 { 4712 inst.error = _("cannot combine index with option"); 4713 return PARSE_OPERAND_FAIL; 4714 } 4715 *str = p; 4716 return PARSE_OPERAND_SUCCESS; 4717 } 4718 else 4719 { 4720 inst.operands[i].postind = 1; 4721 inst.operands[i].writeback = 1; 4722 4723 if (inst.operands[i].preind) 4724 { 4725 inst.error = _("cannot combine pre- and post-indexing"); 4726 return PARSE_OPERAND_FAIL; 4727 } 4728 4729 if (*p == '+') p++; 4730 else if (*p == '-') p++, inst.operands[i].negative = 1; 4731 4732 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4733 { 4734 /* We might be using the immediate for alignment already. If we 4735 are, OR the register number into the low-order bits. */ 4736 if (inst.operands[i].immisalign) 4737 inst.operands[i].imm |= reg; 4738 else 4739 inst.operands[i].imm = reg; 4740 inst.operands[i].immisreg = 1; 4741 4742 if (skip_past_comma (&p) == SUCCESS) 4743 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4744 return PARSE_OPERAND_FAIL; 4745 } 4746 else 4747 { 4748 if (inst.operands[i].negative) 4749 { 4750 inst.operands[i].negative = 0; 4751 p--; 4752 } 4753 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4754 return PARSE_OPERAND_FAIL; 4755 } 4756 } 4757 } 4758 4759 /* If at this point neither .preind nor .postind is set, we have a 4760 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ 4761 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) 4762 { 4763 inst.operands[i].preind = 1; 4764 inst.reloc.exp.X_op = O_constant; 4765 inst.reloc.exp.X_add_number = 0; 4766 } 4767 *str = p; 4768 return PARSE_OPERAND_SUCCESS; 4769} 4770 4771static int 4772parse_address (char **str, int i) 4773{ 4774 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS 4775 ? SUCCESS : FAIL; 4776} 4777 4778static parse_operand_result 4779parse_address_group_reloc (char **str, int i, group_reloc_type type) 4780{ 4781 return parse_address_main (str, i, 1, type); 4782} 4783 4784/* Parse an operand for a MOVW or MOVT instruction. */ 4785static int 4786parse_half (char **str) 4787{ 4788 char * p; 4789 4790 p = *str; 4791 skip_past_char (&p, '#'); 4792 if (strncasecmp (p, ":lower16:", 9) == 0) 4793 inst.reloc.type = BFD_RELOC_ARM_MOVW; 4794 else if (strncasecmp (p, ":upper16:", 9) == 0) 4795 inst.reloc.type = BFD_RELOC_ARM_MOVT; 4796 4797 if (inst.reloc.type != BFD_RELOC_UNUSED) 4798 { 4799 p += 9; 4800 skip_whitespace(p); 4801 } 4802 4803 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4804 return FAIL; 4805 4806 if (inst.reloc.type == BFD_RELOC_UNUSED) 4807 { 4808 if (inst.reloc.exp.X_op != O_constant) 4809 { 4810 inst.error = _("constant expression expected"); 4811 return FAIL; 4812 } 4813 if (inst.reloc.exp.X_add_number < 0 4814 || inst.reloc.exp.X_add_number > 0xffff) 4815 { 4816 inst.error = _("immediate value out of range"); 4817 return FAIL; 4818 } 4819 } 4820 *str = p; 4821 return SUCCESS; 4822} 4823 4824/* Miscellaneous. */ 4825 4826/* Parse a PSR flag operand. The value returned is FAIL on syntax error, 4827 or a bitmask suitable to be or-ed into the ARM msr instruction. */ 4828static int 4829parse_psr (char **str) 4830{ 4831 char *p; 4832 unsigned long psr_field; 4833 const struct asm_psr *psr; 4834 char *start; 4835 4836 /* CPSR's and SPSR's can now be lowercase. This is just a convenience 4837 feature for ease of use and backwards compatibility. */ 4838 p = *str; 4839 if (strncasecmp (p, "SPSR", 4) == 0) 4840 psr_field = SPSR_BIT; 4841 else if (strncasecmp (p, "CPSR", 4) == 0) 4842 psr_field = 0; 4843 else 4844 { 4845 start = p; 4846 do 4847 p++; 4848 while (ISALNUM (*p) || *p == '_'); 4849 4850 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); 4851 if (!psr) 4852 return FAIL; 4853 4854 *str = p; 4855 return psr->field; 4856 } 4857 4858 p += 4; 4859 if (*p == '_') 4860 { 4861 /* A suffix follows. */ 4862 p++; 4863 start = p; 4864 4865 do 4866 p++; 4867 while (ISALNUM (*p) || *p == '_'); 4868 4869 psr = hash_find_n (arm_psr_hsh, start, p - start); 4870 if (!psr) 4871 goto error; 4872 4873 psr_field |= psr->field; 4874 } 4875 else 4876 { 4877 if (ISALNUM (*p)) 4878 goto error; /* Garbage after "[CS]PSR". */ 4879 4880 psr_field |= (PSR_c | PSR_f); 4881 } 4882 *str = p; 4883 return psr_field; 4884 4885 error: 4886 inst.error = _("flag for {c}psr instruction expected"); 4887 return FAIL; 4888} 4889 4890/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a 4891 value suitable for splatting into the AIF field of the instruction. */ 4892 4893static int 4894parse_cps_flags (char **str) 4895{ 4896 int val = 0; 4897 int saw_a_flag = 0; 4898 char *s = *str; 4899 4900 for (;;) 4901 switch (*s++) 4902 { 4903 case '\0': case ',': 4904 goto done; 4905 4906 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; 4907 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; 4908 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; 4909 4910 default: 4911 inst.error = _("unrecognized CPS flag"); 4912 return FAIL; 4913 } 4914 4915 done: 4916 if (saw_a_flag == 0) 4917 { 4918 inst.error = _("missing CPS flags"); 4919 return FAIL; 4920 } 4921 4922 *str = s - 1; 4923 return val; 4924} 4925 4926/* Parse an endian specifier ("BE" or "LE", case insensitive); 4927 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ 4928 4929static int 4930parse_endian_specifier (char **str) 4931{ 4932 int little_endian; 4933 char *s = *str; 4934 4935 if (strncasecmp (s, "BE", 2)) 4936 little_endian = 0; 4937 else if (strncasecmp (s, "LE", 2)) 4938 little_endian = 1; 4939 else 4940 { 4941 inst.error = _("valid endian specifiers are be or le"); 4942 return FAIL; 4943 } 4944 4945 if (ISALNUM (s[2]) || s[2] == '_') 4946 { 4947 inst.error = _("valid endian specifiers are be or le"); 4948 return FAIL; 4949 } 4950 4951 *str = s + 2; 4952 return little_endian; 4953} 4954 4955/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a 4956 value suitable for poking into the rotate field of an sxt or sxta 4957 instruction, or FAIL on error. */ 4958 4959static int 4960parse_ror (char **str) 4961{ 4962 int rot; 4963 char *s = *str; 4964 4965 if (strncasecmp (s, "ROR", 3) == 0) 4966 s += 3; 4967 else 4968 { 4969 inst.error = _("missing rotation field after comma"); 4970 return FAIL; 4971 } 4972 4973 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) 4974 return FAIL; 4975 4976 switch (rot) 4977 { 4978 case 0: *str = s; return 0x0; 4979 case 8: *str = s; return 0x1; 4980 case 16: *str = s; return 0x2; 4981 case 24: *str = s; return 0x3; 4982 4983 default: 4984 inst.error = _("rotation can only be 0, 8, 16, or 24"); 4985 return FAIL; 4986 } 4987} 4988 4989/* Parse a conditional code (from conds[] below). The value returned is in the 4990 range 0 .. 14, or FAIL. */ 4991static int 4992parse_cond (char **str) 4993{ 4994 char *p, *q; 4995 const struct asm_cond *c; 4996 4997 p = q = *str; 4998 while (ISALPHA (*q)) 4999 q++; 5000 5001 c = hash_find_n (arm_cond_hsh, p, q - p); 5002 if (!c) 5003 { 5004 inst.error = _("condition required"); 5005 return FAIL; 5006 } 5007 5008 *str = q; 5009 return c->value; 5010} 5011 5012/* Parse an option for a barrier instruction. Returns the encoding for the 5013 option, or FAIL. */ 5014static int 5015parse_barrier (char **str) 5016{ 5017 char *p, *q; 5018 const struct asm_barrier_opt *o; 5019 5020 p = q = *str; 5021 while (ISALPHA (*q)) 5022 q++; 5023 5024 o = hash_find_n (arm_barrier_opt_hsh, p, q - p); 5025 if (!o) 5026 return FAIL; 5027 5028 *str = q; 5029 return o->value; 5030} 5031 5032/* Parse the operands of a table branch instruction. Similar to a memory 5033 operand. */ 5034static int 5035parse_tb (char **str) 5036{ 5037 char * p = *str; 5038 int reg; 5039 5040 if (skip_past_char (&p, '[') == FAIL) 5041 { 5042 inst.error = _("'[' expected"); 5043 return FAIL; 5044 } 5045 5046 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5047 { 5048 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5049 return FAIL; 5050 } 5051 inst.operands[0].reg = reg; 5052 5053 if (skip_past_comma (&p) == FAIL) 5054 { 5055 inst.error = _("',' expected"); 5056 return FAIL; 5057 } 5058 5059 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5060 { 5061 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5062 return FAIL; 5063 } 5064 inst.operands[0].imm = reg; 5065 5066 if (skip_past_comma (&p) == SUCCESS) 5067 { 5068 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) 5069 return FAIL; 5070 if (inst.reloc.exp.X_add_number != 1) 5071 { 5072 inst.error = _("invalid shift"); 5073 return FAIL; 5074 } 5075 inst.operands[0].shifted = 1; 5076 } 5077 5078 if (skip_past_char (&p, ']') == FAIL) 5079 { 5080 inst.error = _("']' expected"); 5081 return FAIL; 5082 } 5083 *str = p; 5084 return SUCCESS; 5085} 5086 5087/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more 5088 information on the types the operands can take and how they are encoded. 5089 Up to four operands may be read; this function handles setting the 5090 ".present" field for each read operand itself. 5091 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, 5092 else returns FAIL. */ 5093 5094static int 5095parse_neon_mov (char **str, int *which_operand) 5096{ 5097 int i = *which_operand, val; 5098 enum arm_reg_type rtype; 5099 char *ptr = *str; 5100 struct neon_type_el optype; 5101 5102 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5103 { 5104 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 5105 inst.operands[i].reg = val; 5106 inst.operands[i].isscalar = 1; 5107 inst.operands[i].vectype = optype; 5108 inst.operands[i++].present = 1; 5109 5110 if (skip_past_comma (&ptr) == FAIL) 5111 goto wanted_comma; 5112 5113 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5114 goto wanted_arm; 5115 5116 inst.operands[i].reg = val; 5117 inst.operands[i].isreg = 1; 5118 inst.operands[i].present = 1; 5119 } 5120 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) 5121 != FAIL) 5122 { 5123 /* Cases 0, 1, 2, 3, 5 (D only). */ 5124 if (skip_past_comma (&ptr) == FAIL) 5125 goto wanted_comma; 5126 5127 inst.operands[i].reg = val; 5128 inst.operands[i].isreg = 1; 5129 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5130 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5131 inst.operands[i].isvec = 1; 5132 inst.operands[i].vectype = optype; 5133 inst.operands[i++].present = 1; 5134 5135 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5136 { 5137 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 5138 Case 13: VMOV <Sd>, <Rm> */ 5139 inst.operands[i].reg = val; 5140 inst.operands[i].isreg = 1; 5141 inst.operands[i].present = 1; 5142 5143 if (rtype == REG_TYPE_NQ) 5144 { 5145 first_error (_("can't use Neon quad register here")); 5146 return FAIL; 5147 } 5148 else if (rtype != REG_TYPE_VFS) 5149 { 5150 i++; 5151 if (skip_past_comma (&ptr) == FAIL) 5152 goto wanted_comma; 5153 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5154 goto wanted_arm; 5155 inst.operands[i].reg = val; 5156 inst.operands[i].isreg = 1; 5157 inst.operands[i].present = 1; 5158 } 5159 } 5160 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) 5161 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> 5162 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> 5163 Case 10: VMOV.F32 <Sd>, #<imm> 5164 Case 11: VMOV.F64 <Dd>, #<imm> */ 5165 inst.operands[i].immisfloat = 1; 5166 else if (parse_big_immediate (&ptr, i) == SUCCESS) 5167 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> 5168 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ 5169 ; 5170 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, 5171 &optype)) != FAIL) 5172 { 5173 /* Case 0: VMOV<c><q> <Qd>, <Qm> 5174 Case 1: VMOV<c><q> <Dd>, <Dm> 5175 Case 8: VMOV.F32 <Sd>, <Sm> 5176 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ 5177 5178 inst.operands[i].reg = val; 5179 inst.operands[i].isreg = 1; 5180 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5181 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5182 inst.operands[i].isvec = 1; 5183 inst.operands[i].vectype = optype; 5184 inst.operands[i].present = 1; 5185 5186 if (skip_past_comma (&ptr) == SUCCESS) 5187 { 5188 /* Case 15. */ 5189 i++; 5190 5191 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5192 goto wanted_arm; 5193 5194 inst.operands[i].reg = val; 5195 inst.operands[i].isreg = 1; 5196 inst.operands[i++].present = 1; 5197 5198 if (skip_past_comma (&ptr) == FAIL) 5199 goto wanted_comma; 5200 5201 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5202 goto wanted_arm; 5203 5204 inst.operands[i].reg = val; 5205 inst.operands[i].isreg = 1; 5206 inst.operands[i++].present = 1; 5207 } 5208 } 5209 else 5210 { 5211 first_error (_("expected <Rm> or <Dm> or <Qm> operand")); 5212 return FAIL; 5213 } 5214 } 5215 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5216 { 5217 /* Cases 6, 7. */ 5218 inst.operands[i].reg = val; 5219 inst.operands[i].isreg = 1; 5220 inst.operands[i++].present = 1; 5221 5222 if (skip_past_comma (&ptr) == FAIL) 5223 goto wanted_comma; 5224 5225 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5226 { 5227 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 5228 inst.operands[i].reg = val; 5229 inst.operands[i].isscalar = 1; 5230 inst.operands[i].present = 1; 5231 inst.operands[i].vectype = optype; 5232 } 5233 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5234 { 5235 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 5236 inst.operands[i].reg = val; 5237 inst.operands[i].isreg = 1; 5238 inst.operands[i++].present = 1; 5239 5240 if (skip_past_comma (&ptr) == FAIL) 5241 goto wanted_comma; 5242 5243 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) 5244 == FAIL) 5245 { 5246 first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); 5247 return FAIL; 5248 } 5249 5250 inst.operands[i].reg = val; 5251 inst.operands[i].isreg = 1; 5252 inst.operands[i].isvec = 1; 5253 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5254 inst.operands[i].vectype = optype; 5255 inst.operands[i].present = 1; 5256 5257 if (rtype == REG_TYPE_VFS) 5258 { 5259 /* Case 14. */ 5260 i++; 5261 if (skip_past_comma (&ptr) == FAIL) 5262 goto wanted_comma; 5263 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, 5264 &optype)) == FAIL) 5265 { 5266 first_error (_(reg_expected_msgs[REG_TYPE_VFS])); 5267 return FAIL; 5268 } 5269 inst.operands[i].reg = val; 5270 inst.operands[i].isreg = 1; 5271 inst.operands[i].isvec = 1; 5272 inst.operands[i].issingle = 1; 5273 inst.operands[i].vectype = optype; 5274 inst.operands[i].present = 1; 5275 } 5276 } 5277 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) 5278 != FAIL) 5279 { 5280 /* Case 13. */ 5281 inst.operands[i].reg = val; 5282 inst.operands[i].isreg = 1; 5283 inst.operands[i].isvec = 1; 5284 inst.operands[i].issingle = 1; 5285 inst.operands[i].vectype = optype; 5286 inst.operands[i++].present = 1; 5287 } 5288 } 5289 else 5290 { 5291 first_error (_("parse error")); 5292 return FAIL; 5293 } 5294 5295 /* Successfully parsed the operands. Update args. */ 5296 *which_operand = i; 5297 *str = ptr; 5298 return SUCCESS; 5299 5300 wanted_comma: 5301 first_error (_("expected comma")); 5302 return FAIL; 5303 5304 wanted_arm: 5305 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 5306 return FAIL; 5307} 5308 5309/* Matcher codes for parse_operands. */ 5310enum operand_parse_code 5311{ 5312 OP_stop, /* end of line */ 5313 5314 OP_RR, /* ARM register */ 5315 OP_RRnpc, /* ARM register, not r15 */ 5316 OP_RRnpcb, /* ARM register, not r15, in square brackets */ 5317 OP_RRw, /* ARM register, not r15, optional trailing ! */ 5318 OP_RCP, /* Coprocessor number */ 5319 OP_RCN, /* Coprocessor register */ 5320 OP_RF, /* FPA register */ 5321 OP_RVS, /* VFP single precision register */ 5322 OP_RVD, /* VFP double precision register (0..15) */ 5323 OP_RND, /* Neon double precision register (0..31) */ 5324 OP_RNQ, /* Neon quad precision register */ 5325 OP_RVSD, /* VFP single or double precision register */ 5326 OP_RNDQ, /* Neon double or quad precision register */ 5327 OP_RNSDQ, /* Neon single, double or quad precision register */ 5328 OP_RNSC, /* Neon scalar D[X] */ 5329 OP_RVC, /* VFP control register */ 5330 OP_RMF, /* Maverick F register */ 5331 OP_RMD, /* Maverick D register */ 5332 OP_RMFX, /* Maverick FX register */ 5333 OP_RMDX, /* Maverick DX register */ 5334 OP_RMAX, /* Maverick AX register */ 5335 OP_RMDS, /* Maverick DSPSC register */ 5336 OP_RIWR, /* iWMMXt wR register */ 5337 OP_RIWC, /* iWMMXt wC register */ 5338 OP_RIWG, /* iWMMXt wCG register */ 5339 OP_RXA, /* XScale accumulator register */ 5340 5341 OP_REGLST, /* ARM register list */ 5342 OP_VRSLST, /* VFP single-precision register list */ 5343 OP_VRDLST, /* VFP double-precision register list */ 5344 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ 5345 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ 5346 OP_NSTRLST, /* Neon element/structure list */ 5347 5348 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ 5349 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ 5350 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ 5351 OP_RR_RNSC, /* ARM reg or Neon scalar. */ 5352 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ 5353 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ 5354 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ 5355 OP_VMOV, /* Neon VMOV operands. */ 5356 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ 5357 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ 5358 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ 5359 5360 OP_I0, /* immediate zero */ 5361 OP_I7, /* immediate value 0 .. 7 */ 5362 OP_I15, /* 0 .. 15 */ 5363 OP_I16, /* 1 .. 16 */ 5364 OP_I16z, /* 0 .. 16 */ 5365 OP_I31, /* 0 .. 31 */ 5366 OP_I31w, /* 0 .. 31, optional trailing ! */ 5367 OP_I32, /* 1 .. 32 */ 5368 OP_I32z, /* 0 .. 32 */ 5369 OP_I63, /* 0 .. 63 */ 5370 OP_I63s, /* -64 .. 63 */ 5371 OP_I64, /* 1 .. 64 */ 5372 OP_I64z, /* 0 .. 64 */ 5373 OP_I255, /* 0 .. 255 */ 5374 5375 OP_I4b, /* immediate, prefix optional, 1 .. 4 */ 5376 OP_I7b, /* 0 .. 7 */ 5377 OP_I15b, /* 0 .. 15 */ 5378 OP_I31b, /* 0 .. 31 */ 5379 5380 OP_SH, /* shifter operand */ 5381 OP_SHG, /* shifter operand with possible group relocation */ 5382 OP_ADDR, /* Memory address expression (any mode) */ 5383 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ 5384 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ 5385 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ 5386 OP_EXP, /* arbitrary expression */ 5387 OP_EXPi, /* same, with optional immediate prefix */ 5388 OP_EXPr, /* same, with optional relocation suffix */ 5389 OP_HALF, /* 0 .. 65535 or low/high reloc. */ 5390 5391 OP_CPSF, /* CPS flags */ 5392 OP_ENDI, /* Endianness specifier */ 5393 OP_PSR, /* CPSR/SPSR mask for msr */ 5394 OP_COND, /* conditional code */ 5395 OP_TB, /* Table branch. */ 5396 5397 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ 5398 OP_APSR_RR, /* ARM register or "APSR_nzcv". */ 5399 5400 OP_RRnpc_I0, /* ARM register or literal 0 */ 5401 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ 5402 OP_RR_EXi, /* ARM register or expression with imm prefix */ 5403 OP_RF_IF, /* FPA register or immediate */ 5404 OP_RIWR_RIWC, /* iWMMXt R or C reg */ 5405 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ 5406 5407 /* Optional operands. */ 5408 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ 5409 OP_oI31b, /* 0 .. 31 */ 5410 OP_oI32b, /* 1 .. 32 */ 5411 OP_oIffffb, /* 0 .. 65535 */ 5412 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ 5413 5414 OP_oRR, /* ARM register */ 5415 OP_oRRnpc, /* ARM register, not the PC */ 5416 OP_oRRw, /* ARM register, not r15, optional trailing ! */ 5417 OP_oRND, /* Optional Neon double precision register */ 5418 OP_oRNQ, /* Optional Neon quad precision register */ 5419 OP_oRNDQ, /* Optional Neon double or quad precision register */ 5420 OP_oRNSDQ, /* Optional single, double or quad precision vector register */ 5421 OP_oSHll, /* LSL immediate */ 5422 OP_oSHar, /* ASR immediate */ 5423 OP_oSHllar, /* LSL or ASR immediate */ 5424 OP_oROR, /* ROR 0/8/16/24 */ 5425 OP_oBARRIER, /* Option argument for a barrier instruction. */ 5426 5427 OP_FIRST_OPTIONAL = OP_oI7b 5428}; 5429 5430/* Generic instruction operand parser. This does no encoding and no 5431 semantic validation; it merely squirrels values away in the inst 5432 structure. Returns SUCCESS or FAIL depending on whether the 5433 specified grammar matched. */ 5434static int 5435parse_operands (char *str, const unsigned char *pattern) 5436{ 5437 unsigned const char *upat = pattern; 5438 char *backtrack_pos = 0; 5439 const char *backtrack_error = 0; 5440 int i, val, backtrack_index = 0; 5441 enum arm_reg_type rtype; 5442 parse_operand_result result; 5443 5444#define po_char_or_fail(chr) do { \ 5445 if (skip_past_char (&str, chr) == FAIL) \ 5446 goto bad_args; \ 5447} while (0) 5448 5449#define po_reg_or_fail(regtype) do { \ 5450 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5451 &inst.operands[i].vectype); \ 5452 if (val == FAIL) \ 5453 { \ 5454 first_error (_(reg_expected_msgs[regtype])); \ 5455 goto failure; \ 5456 } \ 5457 inst.operands[i].reg = val; \ 5458 inst.operands[i].isreg = 1; \ 5459 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5460 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5461 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5462 || rtype == REG_TYPE_VFD \ 5463 || rtype == REG_TYPE_NQ); \ 5464} while (0) 5465 5466#define po_reg_or_goto(regtype, label) do { \ 5467 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5468 &inst.operands[i].vectype); \ 5469 if (val == FAIL) \ 5470 goto label; \ 5471 \ 5472 inst.operands[i].reg = val; \ 5473 inst.operands[i].isreg = 1; \ 5474 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5475 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5476 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5477 || rtype == REG_TYPE_VFD \ 5478 || rtype == REG_TYPE_NQ); \ 5479} while (0) 5480 5481#define po_imm_or_fail(min, max, popt) do { \ 5482 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ 5483 goto failure; \ 5484 inst.operands[i].imm = val; \ 5485} while (0) 5486 5487#define po_scalar_or_goto(elsz, label) do { \ 5488 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \ 5489 if (val == FAIL) \ 5490 goto label; \ 5491 inst.operands[i].reg = val; \ 5492 inst.operands[i].isscalar = 1; \ 5493} while (0) 5494 5495#define po_misc_or_fail(expr) do { \ 5496 if (expr) \ 5497 goto failure; \ 5498} while (0) 5499 5500#define po_misc_or_fail_no_backtrack(expr) do { \ 5501 result = expr; \ 5502 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\ 5503 backtrack_pos = 0; \ 5504 if (result != PARSE_OPERAND_SUCCESS) \ 5505 goto failure; \ 5506} while (0) 5507 5508 skip_whitespace (str); 5509 5510 for (i = 0; upat[i] != OP_stop; i++) 5511 { 5512 if (upat[i] >= OP_FIRST_OPTIONAL) 5513 { 5514 /* Remember where we are in case we need to backtrack. */ 5515 assert (!backtrack_pos); 5516 backtrack_pos = str; 5517 backtrack_error = inst.error; 5518 backtrack_index = i; 5519 } 5520 5521 if (i > 0 && (i > 1 || inst.operands[0].present)) 5522 po_char_or_fail (','); 5523 5524 switch (upat[i]) 5525 { 5526 /* Registers */ 5527 case OP_oRRnpc: 5528 case OP_RRnpc: 5529 case OP_oRR: 5530 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; 5531 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; 5532 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; 5533 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; 5534 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; 5535 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; 5536 case OP_oRND: 5537 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; 5538 case OP_RVC: 5539 po_reg_or_goto (REG_TYPE_VFC, coproc_reg); 5540 break; 5541 /* Also accept generic coprocessor regs for unknown registers. */ 5542 coproc_reg: 5543 po_reg_or_fail (REG_TYPE_CN); 5544 break; 5545 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; 5546 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; 5547 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; 5548 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; 5549 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; 5550 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; 5551 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; 5552 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; 5553 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; 5554 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; 5555 case OP_oRNQ: 5556 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; 5557 case OP_oRNDQ: 5558 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; 5559 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; 5560 case OP_oRNSDQ: 5561 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; 5562 5563 /* Neon scalar. Using an element size of 8 means that some invalid 5564 scalars are accepted here, so deal with those in later code. */ 5565 case OP_RNSC: po_scalar_or_goto (8, failure); break; 5566 5567 /* WARNING: We can expand to two operands here. This has the potential 5568 to totally confuse the backtracking mechanism! It will be OK at 5569 least as long as we don't try to use optional args as well, 5570 though. */ 5571 case OP_NILO: 5572 { 5573 po_reg_or_goto (REG_TYPE_NDQ, try_imm); 5574 inst.operands[i].present = 1; 5575 i++; 5576 skip_past_comma (&str); 5577 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); 5578 break; 5579 one_reg_only: 5580 /* Optional register operand was omitted. Unfortunately, it's in 5581 operands[i-1] and we need it to be in inst.operands[i]. Fix that 5582 here (this is a bit grotty). */ 5583 inst.operands[i] = inst.operands[i-1]; 5584 inst.operands[i-1].present = 0; 5585 break; 5586 try_imm: 5587 /* There's a possibility of getting a 64-bit immediate here, so 5588 we need special handling. */ 5589 if (parse_big_immediate (&str, i) == FAIL) 5590 { 5591 inst.error = _("immediate value is out of range"); 5592 goto failure; 5593 } 5594 } 5595 break; 5596 5597 case OP_RNDQ_I0: 5598 { 5599 po_reg_or_goto (REG_TYPE_NDQ, try_imm0); 5600 break; 5601 try_imm0: 5602 po_imm_or_fail (0, 0, TRUE); 5603 } 5604 break; 5605 5606 case OP_RVSD_I0: 5607 po_reg_or_goto (REG_TYPE_VFSD, try_imm0); 5608 break; 5609 5610 case OP_RR_RNSC: 5611 { 5612 po_scalar_or_goto (8, try_rr); 5613 break; 5614 try_rr: 5615 po_reg_or_fail (REG_TYPE_RN); 5616 } 5617 break; 5618 5619 case OP_RNSDQ_RNSC: 5620 { 5621 po_scalar_or_goto (8, try_nsdq); 5622 break; 5623 try_nsdq: 5624 po_reg_or_fail (REG_TYPE_NSDQ); 5625 } 5626 break; 5627 5628 case OP_RNDQ_RNSC: 5629 { 5630 po_scalar_or_goto (8, try_ndq); 5631 break; 5632 try_ndq: 5633 po_reg_or_fail (REG_TYPE_NDQ); 5634 } 5635 break; 5636 5637 case OP_RND_RNSC: 5638 { 5639 po_scalar_or_goto (8, try_vfd); 5640 break; 5641 try_vfd: 5642 po_reg_or_fail (REG_TYPE_VFD); 5643 } 5644 break; 5645 5646 case OP_VMOV: 5647 /* WARNING: parse_neon_mov can move the operand counter, i. If we're 5648 not careful then bad things might happen. */ 5649 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); 5650 break; 5651 5652 case OP_RNDQ_IMVNb: 5653 { 5654 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); 5655 break; 5656 try_mvnimm: 5657 /* There's a possibility of getting a 64-bit immediate here, so 5658 we need special handling. */ 5659 if (parse_big_immediate (&str, i) == FAIL) 5660 { 5661 inst.error = _("immediate value is out of range"); 5662 goto failure; 5663 } 5664 } 5665 break; 5666 5667 case OP_RNDQ_I63b: 5668 { 5669 po_reg_or_goto (REG_TYPE_NDQ, try_shimm); 5670 break; 5671 try_shimm: 5672 po_imm_or_fail (0, 63, TRUE); 5673 } 5674 break; 5675 5676 case OP_RRnpcb: 5677 po_char_or_fail ('['); 5678 po_reg_or_fail (REG_TYPE_RN); 5679 po_char_or_fail (']'); 5680 break; 5681 5682 case OP_RRw: 5683 case OP_oRRw: 5684 po_reg_or_fail (REG_TYPE_RN); 5685 if (skip_past_char (&str, '!') == SUCCESS) 5686 inst.operands[i].writeback = 1; 5687 break; 5688 5689 /* Immediates */ 5690 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; 5691 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; 5692 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; 5693 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; 5694 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; 5695 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; 5696 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; 5697 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; 5698 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; 5699 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; 5700 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; 5701 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; 5702 5703 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; 5704 case OP_oI7b: 5705 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; 5706 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; 5707 case OP_oI31b: 5708 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; 5709 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; 5710 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; 5711 5712 /* Immediate variants */ 5713 case OP_oI255c: 5714 po_char_or_fail ('{'); 5715 po_imm_or_fail (0, 255, TRUE); 5716 po_char_or_fail ('}'); 5717 break; 5718 5719 case OP_I31w: 5720 /* The expression parser chokes on a trailing !, so we have 5721 to find it first and zap it. */ 5722 { 5723 char *s = str; 5724 while (*s && *s != ',') 5725 s++; 5726 if (s[-1] == '!') 5727 { 5728 s[-1] = '\0'; 5729 inst.operands[i].writeback = 1; 5730 } 5731 po_imm_or_fail (0, 31, TRUE); 5732 if (str == s - 1) 5733 str = s; 5734 } 5735 break; 5736 5737 /* Expressions */ 5738 case OP_EXPi: EXPi: 5739 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5740 GE_OPT_PREFIX)); 5741 break; 5742 5743 case OP_EXP: 5744 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5745 GE_NO_PREFIX)); 5746 break; 5747 5748 case OP_EXPr: EXPr: 5749 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5750 GE_NO_PREFIX)); 5751 if (inst.reloc.exp.X_op == O_symbol) 5752 { 5753 val = parse_reloc (&str); 5754 if (val == -1) 5755 { 5756 inst.error = _("unrecognized relocation suffix"); 5757 goto failure; 5758 } 5759 else if (val != BFD_RELOC_UNUSED) 5760 { 5761 inst.operands[i].imm = val; 5762 inst.operands[i].hasreloc = 1; 5763 } 5764 } 5765 break; 5766 5767 /* Operand for MOVW or MOVT. */ 5768 case OP_HALF: 5769 po_misc_or_fail (parse_half (&str)); 5770 break; 5771 5772 /* Register or expression */ 5773 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; 5774 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; 5775 5776 /* Register or immediate */ 5777 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; 5778 I0: po_imm_or_fail (0, 0, FALSE); break; 5779 5780 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; 5781 IF: 5782 if (!is_immediate_prefix (*str)) 5783 goto bad_args; 5784 str++; 5785 val = parse_fpa_immediate (&str); 5786 if (val == FAIL) 5787 goto failure; 5788 /* FPA immediates are encoded as registers 8-15. 5789 parse_fpa_immediate has already applied the offset. */ 5790 inst.operands[i].reg = val; 5791 inst.operands[i].isreg = 1; 5792 break; 5793 5794 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; 5795 I32z: po_imm_or_fail (0, 32, FALSE); break; 5796 5797 /* Two kinds of register */ 5798 case OP_RIWR_RIWC: 5799 { 5800 struct reg_entry *rege = arm_reg_parse_multi (&str); 5801 if (!rege 5802 || (rege->type != REG_TYPE_MMXWR 5803 && rege->type != REG_TYPE_MMXWC 5804 && rege->type != REG_TYPE_MMXWCG)) 5805 { 5806 inst.error = _("iWMMXt data or control register expected"); 5807 goto failure; 5808 } 5809 inst.operands[i].reg = rege->number; 5810 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); 5811 } 5812 break; 5813 5814 case OP_RIWC_RIWG: 5815 { 5816 struct reg_entry *rege = arm_reg_parse_multi (&str); 5817 if (!rege 5818 || (rege->type != REG_TYPE_MMXWC 5819 && rege->type != REG_TYPE_MMXWCG)) 5820 { 5821 inst.error = _("iWMMXt control register expected"); 5822 goto failure; 5823 } 5824 inst.operands[i].reg = rege->number; 5825 inst.operands[i].isreg = 1; 5826 } 5827 break; 5828 5829 /* Misc */ 5830 case OP_CPSF: val = parse_cps_flags (&str); break; 5831 case OP_ENDI: val = parse_endian_specifier (&str); break; 5832 case OP_oROR: val = parse_ror (&str); break; 5833 case OP_PSR: val = parse_psr (&str); break; 5834 case OP_COND: val = parse_cond (&str); break; 5835 case OP_oBARRIER:val = parse_barrier (&str); break; 5836 5837 case OP_RVC_PSR: 5838 po_reg_or_goto (REG_TYPE_VFC, try_psr); 5839 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ 5840 break; 5841 try_psr: 5842 val = parse_psr (&str); 5843 break; 5844 5845 case OP_APSR_RR: 5846 po_reg_or_goto (REG_TYPE_RN, try_apsr); 5847 break; 5848 try_apsr: 5849 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS 5850 instruction). */ 5851 if (strncasecmp (str, "APSR_", 5) == 0) 5852 { 5853 unsigned found = 0; 5854 str += 5; 5855 while (found < 15) 5856 switch (*str++) 5857 { 5858 case 'c': found = (found & 1) ? 16 : found | 1; break; 5859 case 'n': found = (found & 2) ? 16 : found | 2; break; 5860 case 'z': found = (found & 4) ? 16 : found | 4; break; 5861 case 'v': found = (found & 8) ? 16 : found | 8; break; 5862 default: found = 16; 5863 } 5864 if (found != 15) 5865 goto failure; 5866 inst.operands[i].isvec = 1; 5867 } 5868 else 5869 goto failure; 5870 break; 5871 5872 case OP_TB: 5873 po_misc_or_fail (parse_tb (&str)); 5874 break; 5875 5876 /* Register lists */ 5877 case OP_REGLST: 5878 val = parse_reg_list (&str); 5879 if (*str == '^') 5880 { 5881 inst.operands[1].writeback = 1; 5882 str++; 5883 } 5884 break; 5885 5886 case OP_VRSLST: 5887 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); 5888 break; 5889 5890 case OP_VRDLST: 5891 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); 5892 break; 5893 5894 case OP_VRSDLST: 5895 /* Allow Q registers too. */ 5896 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5897 REGLIST_NEON_D); 5898 if (val == FAIL) 5899 { 5900 inst.error = NULL; 5901 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5902 REGLIST_VFP_S); 5903 inst.operands[i].issingle = 1; 5904 } 5905 break; 5906 5907 case OP_NRDLST: 5908 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5909 REGLIST_NEON_D); 5910 break; 5911 5912 case OP_NSTRLST: 5913 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, 5914 &inst.operands[i].vectype); 5915 break; 5916 5917 /* Addressing modes */ 5918 case OP_ADDR: 5919 po_misc_or_fail (parse_address (&str, i)); 5920 break; 5921 5922 case OP_ADDRGLDR: 5923 po_misc_or_fail_no_backtrack ( 5924 parse_address_group_reloc (&str, i, GROUP_LDR)); 5925 break; 5926 5927 case OP_ADDRGLDRS: 5928 po_misc_or_fail_no_backtrack ( 5929 parse_address_group_reloc (&str, i, GROUP_LDRS)); 5930 break; 5931 5932 case OP_ADDRGLDC: 5933 po_misc_or_fail_no_backtrack ( 5934 parse_address_group_reloc (&str, i, GROUP_LDC)); 5935 break; 5936 5937 case OP_SH: 5938 po_misc_or_fail (parse_shifter_operand (&str, i)); 5939 break; 5940 5941 case OP_SHG: 5942 po_misc_or_fail_no_backtrack ( 5943 parse_shifter_operand_group_reloc (&str, i)); 5944 break; 5945 5946 case OP_oSHll: 5947 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); 5948 break; 5949 5950 case OP_oSHar: 5951 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); 5952 break; 5953 5954 case OP_oSHllar: 5955 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); 5956 break; 5957 5958 default: 5959 as_fatal ("unhandled operand code %d", upat[i]); 5960 } 5961 5962 /* Various value-based sanity checks and shared operations. We 5963 do not signal immediate failures for the register constraints; 5964 this allows a syntax error to take precedence. */ 5965 switch (upat[i]) 5966 { 5967 case OP_oRRnpc: 5968 case OP_RRnpc: 5969 case OP_RRnpcb: 5970 case OP_RRw: 5971 case OP_oRRw: 5972 case OP_RRnpc_I0: 5973 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) 5974 inst.error = BAD_PC; 5975 break; 5976 5977 case OP_CPSF: 5978 case OP_ENDI: 5979 case OP_oROR: 5980 case OP_PSR: 5981 case OP_RVC_PSR: 5982 case OP_COND: 5983 case OP_oBARRIER: 5984 case OP_REGLST: 5985 case OP_VRSLST: 5986 case OP_VRDLST: 5987 case OP_VRSDLST: 5988 case OP_NRDLST: 5989 case OP_NSTRLST: 5990 if (val == FAIL) 5991 goto failure; 5992 inst.operands[i].imm = val; 5993 break; 5994 5995 default: 5996 break; 5997 } 5998 5999 /* If we get here, this operand was successfully parsed. */ 6000 inst.operands[i].present = 1; 6001 continue; 6002 6003 bad_args: 6004 inst.error = BAD_ARGS; 6005 6006 failure: 6007 if (!backtrack_pos) 6008 { 6009 /* The parse routine should already have set inst.error, but set a 6010 defaut here just in case. */ 6011 if (!inst.error) 6012 inst.error = _("syntax error"); 6013 return FAIL; 6014 } 6015 6016 /* Do not backtrack over a trailing optional argument that 6017 absorbed some text. We will only fail again, with the 6018 'garbage following instruction' error message, which is 6019 probably less helpful than the current one. */ 6020 if (backtrack_index == i && backtrack_pos != str 6021 && upat[i+1] == OP_stop) 6022 { 6023 if (!inst.error) 6024 inst.error = _("syntax error"); 6025 return FAIL; 6026 } 6027 6028 /* Try again, skipping the optional argument at backtrack_pos. */ 6029 str = backtrack_pos; 6030 inst.error = backtrack_error; 6031 inst.operands[backtrack_index].present = 0; 6032 i = backtrack_index; 6033 backtrack_pos = 0; 6034 } 6035 6036 /* Check that we have parsed all the arguments. */ 6037 if (*str != '\0' && !inst.error) 6038 inst.error = _("garbage following instruction"); 6039 6040 return inst.error ? FAIL : SUCCESS; 6041} 6042 6043#undef po_char_or_fail 6044#undef po_reg_or_fail 6045#undef po_reg_or_goto 6046#undef po_imm_or_fail 6047#undef po_scalar_or_fail 6048 6049/* Shorthand macro for instruction encoding functions issuing errors. */ 6050#define constraint(expr, err) do { \ 6051 if (expr) \ 6052 { \ 6053 inst.error = err; \ 6054 return; \ 6055 } \ 6056} while (0) 6057 6058/* Functions for operand encoding. ARM, then Thumb. */ 6059 6060#define rotate_left(v, n) (v << n | v >> (32 - n)) 6061 6062/* If VAL can be encoded in the immediate field of an ARM instruction, 6063 return the encoded form. Otherwise, return FAIL. */ 6064 6065static unsigned int 6066encode_arm_immediate (unsigned int val) 6067{ 6068 unsigned int a, i; 6069 6070 for (i = 0; i < 32; i += 2) 6071 if ((a = rotate_left (val, i)) <= 0xff) 6072 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ 6073 6074 return FAIL; 6075} 6076 6077/* If VAL can be encoded in the immediate field of a Thumb32 instruction, 6078 return the encoded form. Otherwise, return FAIL. */ 6079static unsigned int 6080encode_thumb32_immediate (unsigned int val) 6081{ 6082 unsigned int a, i; 6083 6084 if (val <= 0xff) 6085 return val; 6086 6087 for (i = 1; i <= 24; i++) 6088 { 6089 a = val >> i; 6090 if ((val & ~(0xff << i)) == 0) 6091 return ((val >> i) & 0x7f) | ((32 - i) << 7); 6092 } 6093 6094 a = val & 0xff; 6095 if (val == ((a << 16) | a)) 6096 return 0x100 | a; 6097 if (val == ((a << 24) | (a << 16) | (a << 8) | a)) 6098 return 0x300 | a; 6099 6100 a = val & 0xff00; 6101 if (val == ((a << 16) | a)) 6102 return 0x200 | (a >> 8); 6103 6104 return FAIL; 6105} 6106/* Encode a VFP SP or DP register number into inst.instruction. */ 6107 6108static void 6109encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) 6110{ 6111 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) 6112 && reg > 15) 6113 { 6114 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 6115 { 6116 if (thumb_mode) 6117 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 6118 fpu_vfp_ext_v3); 6119 else 6120 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 6121 fpu_vfp_ext_v3); 6122 } 6123 else 6124 { 6125 first_error (_("D register out of range for selected VFP version")); 6126 return; 6127 } 6128 } 6129 6130 switch (pos) 6131 { 6132 case VFP_REG_Sd: 6133 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); 6134 break; 6135 6136 case VFP_REG_Sn: 6137 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); 6138 break; 6139 6140 case VFP_REG_Sm: 6141 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); 6142 break; 6143 6144 case VFP_REG_Dd: 6145 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); 6146 break; 6147 6148 case VFP_REG_Dn: 6149 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); 6150 break; 6151 6152 case VFP_REG_Dm: 6153 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); 6154 break; 6155 6156 default: 6157 abort (); 6158 } 6159} 6160 6161/* Encode a <shift> in an ARM-format instruction. The immediate, 6162 if any, is handled by md_apply_fix. */ 6163static void 6164encode_arm_shift (int i) 6165{ 6166 if (inst.operands[i].shift_kind == SHIFT_RRX) 6167 inst.instruction |= SHIFT_ROR << 5; 6168 else 6169 { 6170 inst.instruction |= inst.operands[i].shift_kind << 5; 6171 if (inst.operands[i].immisreg) 6172 { 6173 inst.instruction |= SHIFT_BY_REG; 6174 inst.instruction |= inst.operands[i].imm << 8; 6175 } 6176 else 6177 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6178 } 6179} 6180 6181static void 6182encode_arm_shifter_operand (int i) 6183{ 6184 if (inst.operands[i].isreg) 6185 { 6186 inst.instruction |= inst.operands[i].reg; 6187 encode_arm_shift (i); 6188 } 6189 else 6190 inst.instruction |= INST_IMMEDIATE; 6191} 6192 6193/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ 6194static void 6195encode_arm_addr_mode_common (int i, bfd_boolean is_t) 6196{ 6197 assert (inst.operands[i].isreg); 6198 inst.instruction |= inst.operands[i].reg << 16; 6199 6200 if (inst.operands[i].preind) 6201 { 6202 if (is_t) 6203 { 6204 inst.error = _("instruction does not accept preindexed addressing"); 6205 return; 6206 } 6207 inst.instruction |= PRE_INDEX; 6208 if (inst.operands[i].writeback) 6209 inst.instruction |= WRITE_BACK; 6210 6211 } 6212 else if (inst.operands[i].postind) 6213 { 6214 assert (inst.operands[i].writeback); 6215 if (is_t) 6216 inst.instruction |= WRITE_BACK; 6217 } 6218 else /* unindexed - only for coprocessor */ 6219 { 6220 inst.error = _("instruction does not accept unindexed addressing"); 6221 return; 6222 } 6223 6224 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) 6225 && (((inst.instruction & 0x000f0000) >> 16) 6226 == ((inst.instruction & 0x0000f000) >> 12))) 6227 as_warn ((inst.instruction & LOAD_BIT) 6228 ? _("destination register same as write-back base") 6229 : _("source register same as write-back base")); 6230} 6231 6232/* inst.operands[i] was set up by parse_address. Encode it into an 6233 ARM-format mode 2 load or store instruction. If is_t is true, 6234 reject forms that cannot be used with a T instruction (i.e. not 6235 post-indexed). */ 6236static void 6237encode_arm_addr_mode_2 (int i, bfd_boolean is_t) 6238{ 6239 encode_arm_addr_mode_common (i, is_t); 6240 6241 if (inst.operands[i].immisreg) 6242 { 6243 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ 6244 inst.instruction |= inst.operands[i].imm; 6245 if (!inst.operands[i].negative) 6246 inst.instruction |= INDEX_UP; 6247 if (inst.operands[i].shifted) 6248 { 6249 if (inst.operands[i].shift_kind == SHIFT_RRX) 6250 inst.instruction |= SHIFT_ROR << 5; 6251 else 6252 { 6253 inst.instruction |= inst.operands[i].shift_kind << 5; 6254 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6255 } 6256 } 6257 } 6258 else /* immediate offset in inst.reloc */ 6259 { 6260 if (inst.reloc.type == BFD_RELOC_UNUSED) 6261 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; 6262 } 6263} 6264 6265/* inst.operands[i] was set up by parse_address. Encode it into an 6266 ARM-format mode 3 load or store instruction. Reject forms that 6267 cannot be used with such instructions. If is_t is true, reject 6268 forms that cannot be used with a T instruction (i.e. not 6269 post-indexed). */ 6270static void 6271encode_arm_addr_mode_3 (int i, bfd_boolean is_t) 6272{ 6273 if (inst.operands[i].immisreg && inst.operands[i].shifted) 6274 { 6275 inst.error = _("instruction does not accept scaled register index"); 6276 return; 6277 } 6278 6279 encode_arm_addr_mode_common (i, is_t); 6280 6281 if (inst.operands[i].immisreg) 6282 { 6283 inst.instruction |= inst.operands[i].imm; 6284 if (!inst.operands[i].negative) 6285 inst.instruction |= INDEX_UP; 6286 } 6287 else /* immediate offset in inst.reloc */ 6288 { 6289 inst.instruction |= HWOFFSET_IMM; 6290 if (inst.reloc.type == BFD_RELOC_UNUSED) 6291 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; 6292 } 6293} 6294 6295/* inst.operands[i] was set up by parse_address. Encode it into an 6296 ARM-format instruction. Reject all forms which cannot be encoded 6297 into a coprocessor load/store instruction. If wb_ok is false, 6298 reject use of writeback; if unind_ok is false, reject use of 6299 unindexed addressing. If reloc_override is not 0, use it instead 6300 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one 6301 (in which case it is preserved). */ 6302 6303static int 6304encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) 6305{ 6306 inst.instruction |= inst.operands[i].reg << 16; 6307 6308 assert (!(inst.operands[i].preind && inst.operands[i].postind)); 6309 6310 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ 6311 { 6312 assert (!inst.operands[i].writeback); 6313 if (!unind_ok) 6314 { 6315 inst.error = _("instruction does not support unindexed addressing"); 6316 return FAIL; 6317 } 6318 inst.instruction |= inst.operands[i].imm; 6319 inst.instruction |= INDEX_UP; 6320 return SUCCESS; 6321 } 6322 6323 if (inst.operands[i].preind) 6324 inst.instruction |= PRE_INDEX; 6325 6326 if (inst.operands[i].writeback) 6327 { 6328 if (inst.operands[i].reg == REG_PC) 6329 { 6330 inst.error = _("pc may not be used with write-back"); 6331 return FAIL; 6332 } 6333 if (!wb_ok) 6334 { 6335 inst.error = _("instruction does not support writeback"); 6336 return FAIL; 6337 } 6338 inst.instruction |= WRITE_BACK; 6339 } 6340 6341 if (reloc_override) 6342 inst.reloc.type = reloc_override; 6343 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC 6344 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) 6345 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) 6346 { 6347 if (thumb_mode) 6348 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; 6349 else 6350 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; 6351 } 6352 6353 return SUCCESS; 6354} 6355 6356/* inst.reloc.exp describes an "=expr" load pseudo-operation. 6357 Determine whether it can be performed with a move instruction; if 6358 it can, convert inst.instruction to that move instruction and 6359 return 1; if it can't, convert inst.instruction to a literal-pool 6360 load and return 0. If this is not a valid thing to do in the 6361 current context, set inst.error and return 1. 6362 6363 inst.operands[i] describes the destination register. */ 6364 6365static int 6366move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) 6367{ 6368 unsigned long tbit; 6369 6370 if (thumb_p) 6371 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; 6372 else 6373 tbit = LOAD_BIT; 6374 6375 if ((inst.instruction & tbit) == 0) 6376 { 6377 inst.error = _("invalid pseudo operation"); 6378 return 1; 6379 } 6380 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) 6381 { 6382 inst.error = _("constant expression expected"); 6383 return 1; 6384 } 6385 if (inst.reloc.exp.X_op == O_constant) 6386 { 6387 if (thumb_p) 6388 { 6389 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) 6390 { 6391 /* This can be done with a mov(1) instruction. */ 6392 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); 6393 inst.instruction |= inst.reloc.exp.X_add_number; 6394 return 1; 6395 } 6396 } 6397 else 6398 { 6399 int value = encode_arm_immediate (inst.reloc.exp.X_add_number); 6400 if (value != FAIL) 6401 { 6402 /* This can be done with a mov instruction. */ 6403 inst.instruction &= LITERAL_MASK; 6404 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); 6405 inst.instruction |= value & 0xfff; 6406 return 1; 6407 } 6408 6409 value = encode_arm_immediate (~inst.reloc.exp.X_add_number); 6410 if (value != FAIL) 6411 { 6412 /* This can be done with a mvn instruction. */ 6413 inst.instruction &= LITERAL_MASK; 6414 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); 6415 inst.instruction |= value & 0xfff; 6416 return 1; 6417 } 6418 } 6419 } 6420 6421 if (add_to_lit_pool () == FAIL) 6422 { 6423 inst.error = _("literal pool insertion failed"); 6424 return 1; 6425 } 6426 inst.operands[1].reg = REG_PC; 6427 inst.operands[1].isreg = 1; 6428 inst.operands[1].preind = 1; 6429 inst.reloc.pc_rel = 1; 6430 inst.reloc.type = (thumb_p 6431 ? BFD_RELOC_ARM_THUMB_OFFSET 6432 : (mode_3 6433 ? BFD_RELOC_ARM_HWLITERAL 6434 : BFD_RELOC_ARM_LITERAL)); 6435 return 0; 6436} 6437 6438/* Functions for instruction encoding, sorted by subarchitecture. 6439 First some generics; their names are taken from the conventional 6440 bit positions for register arguments in ARM format instructions. */ 6441 6442static void 6443do_noargs (void) 6444{ 6445} 6446 6447static void 6448do_rd (void) 6449{ 6450 inst.instruction |= inst.operands[0].reg << 12; 6451} 6452 6453static void 6454do_rd_rm (void) 6455{ 6456 inst.instruction |= inst.operands[0].reg << 12; 6457 inst.instruction |= inst.operands[1].reg; 6458} 6459 6460static void 6461do_rd_rn (void) 6462{ 6463 inst.instruction |= inst.operands[0].reg << 12; 6464 inst.instruction |= inst.operands[1].reg << 16; 6465} 6466 6467static void 6468do_rn_rd (void) 6469{ 6470 inst.instruction |= inst.operands[0].reg << 16; 6471 inst.instruction |= inst.operands[1].reg << 12; 6472} 6473 6474static void 6475do_rd_rm_rn (void) 6476{ 6477 unsigned Rn = inst.operands[2].reg; 6478 /* Enforce restrictions on SWP instruction. */ 6479 if ((inst.instruction & 0x0fbfffff) == 0x01000090) 6480 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, 6481 _("Rn must not overlap other operands")); 6482 inst.instruction |= inst.operands[0].reg << 12; 6483 inst.instruction |= inst.operands[1].reg; 6484 inst.instruction |= Rn << 16; 6485} 6486 6487static void 6488do_rd_rn_rm (void) 6489{ 6490 inst.instruction |= inst.operands[0].reg << 12; 6491 inst.instruction |= inst.operands[1].reg << 16; 6492 inst.instruction |= inst.operands[2].reg; 6493} 6494 6495static void 6496do_rm_rd_rn (void) 6497{ 6498 inst.instruction |= inst.operands[0].reg; 6499 inst.instruction |= inst.operands[1].reg << 12; 6500 inst.instruction |= inst.operands[2].reg << 16; 6501} 6502 6503static void 6504do_imm0 (void) 6505{ 6506 inst.instruction |= inst.operands[0].imm; 6507} 6508 6509static void 6510do_rd_cpaddr (void) 6511{ 6512 inst.instruction |= inst.operands[0].reg << 12; 6513 encode_arm_cp_address (1, TRUE, TRUE, 0); 6514} 6515 6516/* ARM instructions, in alphabetical order by function name (except 6517 that wrapper functions appear immediately after the function they 6518 wrap). */ 6519 6520/* This is a pseudo-op of the form "adr rd, label" to be converted 6521 into a relative address of the form "add rd, pc, #label-.-8". */ 6522 6523static void 6524do_adr (void) 6525{ 6526 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6527 6528 /* Frag hacking will turn this into a sub instruction if the offset turns 6529 out to be negative. */ 6530 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 6531 inst.reloc.pc_rel = 1; 6532 inst.reloc.exp.X_add_number -= 8; 6533} 6534 6535/* This is a pseudo-op of the form "adrl rd, label" to be converted 6536 into a relative address of the form: 6537 add rd, pc, #low(label-.-8)" 6538 add rd, rd, #high(label-.-8)" */ 6539 6540static void 6541do_adrl (void) 6542{ 6543 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6544 6545 /* Frag hacking will turn this into a sub instruction if the offset turns 6546 out to be negative. */ 6547 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; 6548 inst.reloc.pc_rel = 1; 6549 inst.size = INSN_SIZE * 2; 6550 inst.reloc.exp.X_add_number -= 8; 6551} 6552 6553static void 6554do_arit (void) 6555{ 6556 if (!inst.operands[1].present) 6557 inst.operands[1].reg = inst.operands[0].reg; 6558 inst.instruction |= inst.operands[0].reg << 12; 6559 inst.instruction |= inst.operands[1].reg << 16; 6560 encode_arm_shifter_operand (2); 6561} 6562 6563static void 6564do_barrier (void) 6565{ 6566 if (inst.operands[0].present) 6567 { 6568 constraint ((inst.instruction & 0xf0) != 0x40 6569 && inst.operands[0].imm != 0xf, 6570 "bad barrier type"); 6571 inst.instruction |= inst.operands[0].imm; 6572 } 6573 else 6574 inst.instruction |= 0xf; 6575} 6576 6577static void 6578do_bfc (void) 6579{ 6580 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 6581 constraint (msb > 32, _("bit-field extends past end of register")); 6582 /* The instruction encoding stores the LSB and MSB, 6583 not the LSB and width. */ 6584 inst.instruction |= inst.operands[0].reg << 12; 6585 inst.instruction |= inst.operands[1].imm << 7; 6586 inst.instruction |= (msb - 1) << 16; 6587} 6588 6589static void 6590do_bfi (void) 6591{ 6592 unsigned int msb; 6593 6594 /* #0 in second position is alternative syntax for bfc, which is 6595 the same instruction but with REG_PC in the Rm field. */ 6596 if (!inst.operands[1].isreg) 6597 inst.operands[1].reg = REG_PC; 6598 6599 msb = inst.operands[2].imm + inst.operands[3].imm; 6600 constraint (msb > 32, _("bit-field extends past end of register")); 6601 /* The instruction encoding stores the LSB and MSB, 6602 not the LSB and width. */ 6603 inst.instruction |= inst.operands[0].reg << 12; 6604 inst.instruction |= inst.operands[1].reg; 6605 inst.instruction |= inst.operands[2].imm << 7; 6606 inst.instruction |= (msb - 1) << 16; 6607} 6608 6609static void 6610do_bfx (void) 6611{ 6612 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 6613 _("bit-field extends past end of register")); 6614 inst.instruction |= inst.operands[0].reg << 12; 6615 inst.instruction |= inst.operands[1].reg; 6616 inst.instruction |= inst.operands[2].imm << 7; 6617 inst.instruction |= (inst.operands[3].imm - 1) << 16; 6618} 6619 6620/* ARM V5 breakpoint instruction (argument parse) 6621 BKPT <16 bit unsigned immediate> 6622 Instruction is not conditional. 6623 The bit pattern given in insns[] has the COND_ALWAYS condition, 6624 and it is an error if the caller tried to override that. */ 6625 6626static void 6627do_bkpt (void) 6628{ 6629 /* Top 12 of 16 bits to bits 19:8. */ 6630 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; 6631 6632 /* Bottom 4 of 16 bits to bits 3:0. */ 6633 inst.instruction |= inst.operands[0].imm & 0xf; 6634} 6635 6636static void 6637encode_branch (int default_reloc) 6638{ 6639 if (inst.operands[0].hasreloc) 6640 { 6641 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, 6642 _("the only suffix valid here is '(plt)'")); 6643 inst.reloc.type = BFD_RELOC_ARM_PLT32; 6644 } 6645 else 6646 { 6647 inst.reloc.type = default_reloc; 6648 } 6649 inst.reloc.pc_rel = 1; 6650} 6651 6652static void 6653do_branch (void) 6654{ 6655#ifdef OBJ_ELF 6656 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6657 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6658 else 6659#endif 6660 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6661} 6662 6663static void 6664do_bl (void) 6665{ 6666#ifdef OBJ_ELF 6667 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6668 { 6669 if (inst.cond == COND_ALWAYS) 6670 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6671 else 6672 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6673 } 6674 else 6675#endif 6676 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6677} 6678 6679/* ARM V5 branch-link-exchange instruction (argument parse) 6680 BLX <target_addr> ie BLX(1) 6681 BLX{<condition>} <Rm> ie BLX(2) 6682 Unfortunately, there are two different opcodes for this mnemonic. 6683 So, the insns[].value is not used, and the code here zaps values 6684 into inst.instruction. 6685 Also, the <target_addr> can be 25 bits, hence has its own reloc. */ 6686 6687static void 6688do_blx (void) 6689{ 6690 if (inst.operands[0].isreg) 6691 { 6692 /* Arg is a register; the opcode provided by insns[] is correct. 6693 It is not illegal to do "blx pc", just useless. */ 6694 if (inst.operands[0].reg == REG_PC) 6695 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); 6696 6697 inst.instruction |= inst.operands[0].reg; 6698 } 6699 else 6700 { 6701 /* Arg is an address; this instruction cannot be executed 6702 conditionally, and the opcode must be adjusted. */ 6703 constraint (inst.cond != COND_ALWAYS, BAD_COND); 6704 inst.instruction = 0xfa000000; 6705#ifdef OBJ_ELF 6706 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6707 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6708 else 6709#endif 6710 encode_branch (BFD_RELOC_ARM_PCREL_BLX); 6711 } 6712} 6713 6714static void 6715do_bx (void) 6716{ 6717 if (inst.operands[0].reg == REG_PC) 6718 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); 6719 6720 inst.instruction |= inst.operands[0].reg; 6721} 6722 6723 6724/* ARM v5TEJ. Jump to Jazelle code. */ 6725 6726static void 6727do_bxj (void) 6728{ 6729 if (inst.operands[0].reg == REG_PC) 6730 as_tsktsk (_("use of r15 in bxj is not really useful")); 6731 6732 inst.instruction |= inst.operands[0].reg; 6733} 6734 6735/* Co-processor data operation: 6736 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} 6737 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ 6738static void 6739do_cdp (void) 6740{ 6741 inst.instruction |= inst.operands[0].reg << 8; 6742 inst.instruction |= inst.operands[1].imm << 20; 6743 inst.instruction |= inst.operands[2].reg << 12; 6744 inst.instruction |= inst.operands[3].reg << 16; 6745 inst.instruction |= inst.operands[4].reg; 6746 inst.instruction |= inst.operands[5].imm << 5; 6747} 6748 6749static void 6750do_cmp (void) 6751{ 6752 inst.instruction |= inst.operands[0].reg << 16; 6753 encode_arm_shifter_operand (1); 6754} 6755 6756/* Transfer between coprocessor and ARM registers. 6757 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 6758 MRC2 6759 MCR{cond} 6760 MCR2 6761 6762 No special properties. */ 6763 6764static void 6765do_co_reg (void) 6766{ 6767 inst.instruction |= inst.operands[0].reg << 8; 6768 inst.instruction |= inst.operands[1].imm << 21; 6769 inst.instruction |= inst.operands[2].reg << 12; 6770 inst.instruction |= inst.operands[3].reg << 16; 6771 inst.instruction |= inst.operands[4].reg; 6772 inst.instruction |= inst.operands[5].imm << 5; 6773} 6774 6775/* Transfer between coprocessor register and pair of ARM registers. 6776 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 6777 MCRR2 6778 MRRC{cond} 6779 MRRC2 6780 6781 Two XScale instructions are special cases of these: 6782 6783 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 6784 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 6785 6786 Result unpredicatable if Rd or Rn is R15. */ 6787 6788static void 6789do_co_reg2c (void) 6790{ 6791 inst.instruction |= inst.operands[0].reg << 8; 6792 inst.instruction |= inst.operands[1].imm << 4; 6793 inst.instruction |= inst.operands[2].reg << 12; 6794 inst.instruction |= inst.operands[3].reg << 16; 6795 inst.instruction |= inst.operands[4].reg; 6796} 6797 6798static void 6799do_cpsi (void) 6800{ 6801 inst.instruction |= inst.operands[0].imm << 6; 6802 if (inst.operands[1].present) 6803 { 6804 inst.instruction |= CPSI_MMOD; 6805 inst.instruction |= inst.operands[1].imm; 6806 } 6807} 6808 6809static void 6810do_dbg (void) 6811{ 6812 inst.instruction |= inst.operands[0].imm; 6813} 6814 6815static void 6816do_it (void) 6817{ 6818 /* There is no IT instruction in ARM mode. We 6819 process it but do not generate code for it. */ 6820 inst.size = 0; 6821} 6822 6823static void 6824do_ldmstm (void) 6825{ 6826 int base_reg = inst.operands[0].reg; 6827 int range = inst.operands[1].imm; 6828 6829 inst.instruction |= base_reg << 16; 6830 inst.instruction |= range; 6831 6832 if (inst.operands[1].writeback) 6833 inst.instruction |= LDM_TYPE_2_OR_3; 6834 6835 if (inst.operands[0].writeback) 6836 { 6837 inst.instruction |= WRITE_BACK; 6838 /* Check for unpredictable uses of writeback. */ 6839 if (inst.instruction & LOAD_BIT) 6840 { 6841 /* Not allowed in LDM type 2. */ 6842 if ((inst.instruction & LDM_TYPE_2_OR_3) 6843 && ((range & (1 << REG_PC)) == 0)) 6844 as_warn (_("writeback of base register is UNPREDICTABLE")); 6845 /* Only allowed if base reg not in list for other types. */ 6846 else if (range & (1 << base_reg)) 6847 as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); 6848 } 6849 else /* STM. */ 6850 { 6851 /* Not allowed for type 2. */ 6852 if (inst.instruction & LDM_TYPE_2_OR_3) 6853 as_warn (_("writeback of base register is UNPREDICTABLE")); 6854 /* Only allowed if base reg not in list, or first in list. */ 6855 else if ((range & (1 << base_reg)) 6856 && (range & ((1 << base_reg) - 1))) 6857 as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); 6858 } 6859 } 6860} 6861 6862/* ARMv5TE load-consecutive (argument parse) 6863 Mode is like LDRH. 6864 6865 LDRccD R, mode 6866 STRccD R, mode. */ 6867 6868static void 6869do_ldrd (void) 6870{ 6871 constraint (inst.operands[0].reg % 2 != 0, 6872 _("first destination register must be even")); 6873 constraint (inst.operands[1].present 6874 && inst.operands[1].reg != inst.operands[0].reg + 1, 6875 _("can only load two consecutive registers")); 6876 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6877 constraint (!inst.operands[2].isreg, _("'[' expected")); 6878 6879 if (!inst.operands[1].present) 6880 inst.operands[1].reg = inst.operands[0].reg + 1; 6881 6882 if (inst.instruction & LOAD_BIT) 6883 { 6884 /* encode_arm_addr_mode_3 will diagnose overlap between the base 6885 register and the first register written; we have to diagnose 6886 overlap between the base and the second register written here. */ 6887 6888 if (inst.operands[2].reg == inst.operands[1].reg 6889 && (inst.operands[2].writeback || inst.operands[2].postind)) 6890 as_warn (_("base register written back, and overlaps " 6891 "second destination register")); 6892 6893 /* For an index-register load, the index register must not overlap the 6894 destination (even if not write-back). */ 6895 else if (inst.operands[2].immisreg 6896 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg 6897 || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) 6898 as_warn (_("index register overlaps destination register")); 6899 } 6900 6901 inst.instruction |= inst.operands[0].reg << 12; 6902 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); 6903} 6904 6905static void 6906do_ldrex (void) 6907{ 6908 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 6909 || inst.operands[1].postind || inst.operands[1].writeback 6910 || inst.operands[1].immisreg || inst.operands[1].shifted 6911 || inst.operands[1].negative 6912 /* This can arise if the programmer has written 6913 strex rN, rM, foo 6914 or if they have mistakenly used a register name as the last 6915 operand, eg: 6916 strex rN, rM, rX 6917 It is very difficult to distinguish between these two cases 6918 because "rX" might actually be a label. ie the register 6919 name has been occluded by a symbol of the same name. So we 6920 just generate a general 'bad addressing mode' type error 6921 message and leave it up to the programmer to discover the 6922 true cause and fix their mistake. */ 6923 || (inst.operands[1].reg == REG_PC), 6924 BAD_ADDR_MODE); 6925 6926 constraint (inst.reloc.exp.X_op != O_constant 6927 || inst.reloc.exp.X_add_number != 0, 6928 _("offset must be zero in ARM encoding")); 6929 6930 inst.instruction |= inst.operands[0].reg << 12; 6931 inst.instruction |= inst.operands[1].reg << 16; 6932 inst.reloc.type = BFD_RELOC_UNUSED; 6933} 6934 6935static void 6936do_ldrexd (void) 6937{ 6938 constraint (inst.operands[0].reg % 2 != 0, 6939 _("even register required")); 6940 constraint (inst.operands[1].present 6941 && inst.operands[1].reg != inst.operands[0].reg + 1, 6942 _("can only load two consecutive registers")); 6943 /* If op 1 were present and equal to PC, this function wouldn't 6944 have been called in the first place. */ 6945 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6946 6947 inst.instruction |= inst.operands[0].reg << 12; 6948 inst.instruction |= inst.operands[2].reg << 16; 6949} 6950 6951static void 6952do_ldst (void) 6953{ 6954 inst.instruction |= inst.operands[0].reg << 12; 6955 if (!inst.operands[1].isreg) 6956 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) 6957 return; 6958 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); 6959} 6960 6961static void 6962do_ldstt (void) 6963{ 6964 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 6965 reject [Rn,...]. */ 6966 if (inst.operands[1].preind) 6967 { 6968 constraint (inst.reloc.exp.X_op != O_constant || 6969 inst.reloc.exp.X_add_number != 0, 6970 _("this instruction requires a post-indexed address")); 6971 6972 inst.operands[1].preind = 0; 6973 inst.operands[1].postind = 1; 6974 inst.operands[1].writeback = 1; 6975 } 6976 inst.instruction |= inst.operands[0].reg << 12; 6977 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); 6978} 6979 6980/* Halfword and signed-byte load/store operations. */ 6981 6982static void 6983do_ldstv4 (void) 6984{ 6985 inst.instruction |= inst.operands[0].reg << 12; 6986 if (!inst.operands[1].isreg) 6987 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) 6988 return; 6989 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); 6990} 6991 6992static void 6993do_ldsttv4 (void) 6994{ 6995 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 6996 reject [Rn,...]. */ 6997 if (inst.operands[1].preind) 6998 { 6999 constraint (inst.reloc.exp.X_op != O_constant || 7000 inst.reloc.exp.X_add_number != 0, 7001 _("this instruction requires a post-indexed address")); 7002 7003 inst.operands[1].preind = 0; 7004 inst.operands[1].postind = 1; 7005 inst.operands[1].writeback = 1; 7006 } 7007 inst.instruction |= inst.operands[0].reg << 12; 7008 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); 7009} 7010 7011/* Co-processor register load/store. 7012 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ 7013static void 7014do_lstc (void) 7015{ 7016 inst.instruction |= inst.operands[0].reg << 8; 7017 inst.instruction |= inst.operands[1].reg << 12; 7018 encode_arm_cp_address (2, TRUE, TRUE, 0); 7019} 7020 7021static void 7022do_mlas (void) 7023{ 7024 /* This restriction does not apply to mls (nor to mla in v6 or later). */ 7025 if (inst.operands[0].reg == inst.operands[1].reg 7026 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) 7027 && !(inst.instruction & 0x00400000)) 7028 as_tsktsk (_("Rd and Rm should be different in mla")); 7029 7030 inst.instruction |= inst.operands[0].reg << 16; 7031 inst.instruction |= inst.operands[1].reg; 7032 inst.instruction |= inst.operands[2].reg << 8; 7033 inst.instruction |= inst.operands[3].reg << 12; 7034} 7035 7036static void 7037do_mov (void) 7038{ 7039 inst.instruction |= inst.operands[0].reg << 12; 7040 encode_arm_shifter_operand (1); 7041} 7042 7043/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ 7044static void 7045do_mov16 (void) 7046{ 7047 bfd_vma imm; 7048 bfd_boolean top; 7049 7050 top = (inst.instruction & 0x00400000) != 0; 7051 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, 7052 _(":lower16: not allowed this instruction")); 7053 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, 7054 _(":upper16: not allowed instruction")); 7055 inst.instruction |= inst.operands[0].reg << 12; 7056 if (inst.reloc.type == BFD_RELOC_UNUSED) 7057 { 7058 imm = inst.reloc.exp.X_add_number; 7059 /* The value is in two pieces: 0:11, 16:19. */ 7060 inst.instruction |= (imm & 0x00000fff); 7061 inst.instruction |= (imm & 0x0000f000) << 4; 7062 } 7063} 7064 7065static void do_vfp_nsyn_opcode (const char *); 7066 7067static int 7068do_vfp_nsyn_mrs (void) 7069{ 7070 if (inst.operands[0].isvec) 7071 { 7072 if (inst.operands[1].reg != 1) 7073 first_error (_("operand 1 must be FPSCR")); 7074 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 7075 memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); 7076 do_vfp_nsyn_opcode ("fmstat"); 7077 } 7078 else if (inst.operands[1].isvec) 7079 do_vfp_nsyn_opcode ("fmrx"); 7080 else 7081 return FAIL; 7082 7083 return SUCCESS; 7084} 7085 7086static int 7087do_vfp_nsyn_msr (void) 7088{ 7089 if (inst.operands[0].isvec) 7090 do_vfp_nsyn_opcode ("fmxr"); 7091 else 7092 return FAIL; 7093 7094 return SUCCESS; 7095} 7096 7097static void 7098do_mrs (void) 7099{ 7100 if (do_vfp_nsyn_mrs () == SUCCESS) 7101 return; 7102 7103 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 7104 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) 7105 != (PSR_c|PSR_f), 7106 _("'CPSR' or 'SPSR' expected")); 7107 inst.instruction |= inst.operands[0].reg << 12; 7108 inst.instruction |= (inst.operands[1].imm & SPSR_BIT); 7109} 7110 7111/* Two possible forms: 7112 "{C|S}PSR_<field>, Rm", 7113 "{C|S}PSR_f, #expression". */ 7114 7115static void 7116do_msr (void) 7117{ 7118 if (do_vfp_nsyn_msr () == SUCCESS) 7119 return; 7120 7121 inst.instruction |= inst.operands[0].imm; 7122 if (inst.operands[1].isreg) 7123 inst.instruction |= inst.operands[1].reg; 7124 else 7125 { 7126 inst.instruction |= INST_IMMEDIATE; 7127 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 7128 inst.reloc.pc_rel = 0; 7129 } 7130} 7131 7132static void 7133do_mul (void) 7134{ 7135 if (!inst.operands[2].present) 7136 inst.operands[2].reg = inst.operands[0].reg; 7137 inst.instruction |= inst.operands[0].reg << 16; 7138 inst.instruction |= inst.operands[1].reg; 7139 inst.instruction |= inst.operands[2].reg << 8; 7140 7141 if (inst.operands[0].reg == inst.operands[1].reg 7142 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7143 as_tsktsk (_("Rd and Rm should be different in mul")); 7144} 7145 7146/* Long Multiply Parser 7147 UMULL RdLo, RdHi, Rm, Rs 7148 SMULL RdLo, RdHi, Rm, Rs 7149 UMLAL RdLo, RdHi, Rm, Rs 7150 SMLAL RdLo, RdHi, Rm, Rs. */ 7151 7152static void 7153do_mull (void) 7154{ 7155 inst.instruction |= inst.operands[0].reg << 12; 7156 inst.instruction |= inst.operands[1].reg << 16; 7157 inst.instruction |= inst.operands[2].reg; 7158 inst.instruction |= inst.operands[3].reg << 8; 7159 7160 /* rdhi, rdlo and rm must all be different. */ 7161 if (inst.operands[0].reg == inst.operands[1].reg 7162 || inst.operands[0].reg == inst.operands[2].reg 7163 || inst.operands[1].reg == inst.operands[2].reg) 7164 as_tsktsk (_("rdhi, rdlo and rm must all be different")); 7165} 7166 7167static void 7168do_nop (void) 7169{ 7170 if (inst.operands[0].present) 7171 { 7172 /* Architectural NOP hints are CPSR sets with no bits selected. */ 7173 inst.instruction &= 0xf0000000; 7174 inst.instruction |= 0x0320f000 + inst.operands[0].imm; 7175 } 7176} 7177 7178/* ARM V6 Pack Halfword Bottom Top instruction (argument parse). 7179 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 7180 Condition defaults to COND_ALWAYS. 7181 Error if Rd, Rn or Rm are R15. */ 7182 7183static void 7184do_pkhbt (void) 7185{ 7186 inst.instruction |= inst.operands[0].reg << 12; 7187 inst.instruction |= inst.operands[1].reg << 16; 7188 inst.instruction |= inst.operands[2].reg; 7189 if (inst.operands[3].present) 7190 encode_arm_shift (3); 7191} 7192 7193/* ARM V6 PKHTB (Argument Parse). */ 7194 7195static void 7196do_pkhtb (void) 7197{ 7198 if (!inst.operands[3].present) 7199 { 7200 /* If the shift specifier is omitted, turn the instruction 7201 into pkhbt rd, rm, rn. */ 7202 inst.instruction &= 0xfff00010; 7203 inst.instruction |= inst.operands[0].reg << 12; 7204 inst.instruction |= inst.operands[1].reg; 7205 inst.instruction |= inst.operands[2].reg << 16; 7206 } 7207 else 7208 { 7209 inst.instruction |= inst.operands[0].reg << 12; 7210 inst.instruction |= inst.operands[1].reg << 16; 7211 inst.instruction |= inst.operands[2].reg; 7212 encode_arm_shift (3); 7213 } 7214} 7215 7216/* ARMv5TE: Preload-Cache 7217 7218 PLD <addr_mode> 7219 7220 Syntactically, like LDR with B=1, W=0, L=1. */ 7221 7222static void 7223do_pld (void) 7224{ 7225 constraint (!inst.operands[0].isreg, 7226 _("'[' expected after PLD mnemonic")); 7227 constraint (inst.operands[0].postind, 7228 _("post-indexed expression used in preload instruction")); 7229 constraint (inst.operands[0].writeback, 7230 _("writeback used in preload instruction")); 7231 constraint (!inst.operands[0].preind, 7232 _("unindexed addressing used in preload instruction")); 7233 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7234} 7235 7236/* ARMv7: PLI <addr_mode> */ 7237static void 7238do_pli (void) 7239{ 7240 constraint (!inst.operands[0].isreg, 7241 _("'[' expected after PLI mnemonic")); 7242 constraint (inst.operands[0].postind, 7243 _("post-indexed expression used in preload instruction")); 7244 constraint (inst.operands[0].writeback, 7245 _("writeback used in preload instruction")); 7246 constraint (!inst.operands[0].preind, 7247 _("unindexed addressing used in preload instruction")); 7248 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7249 inst.instruction &= ~PRE_INDEX; 7250} 7251 7252static void 7253do_push_pop (void) 7254{ 7255 inst.operands[1] = inst.operands[0]; 7256 memset (&inst.operands[0], 0, sizeof inst.operands[0]); 7257 inst.operands[0].isreg = 1; 7258 inst.operands[0].writeback = 1; 7259 inst.operands[0].reg = REG_SP; 7260 do_ldmstm (); 7261} 7262 7263/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the 7264 word at the specified address and the following word 7265 respectively. 7266 Unconditionally executed. 7267 Error if Rn is R15. */ 7268 7269static void 7270do_rfe (void) 7271{ 7272 inst.instruction |= inst.operands[0].reg << 16; 7273 if (inst.operands[0].writeback) 7274 inst.instruction |= WRITE_BACK; 7275} 7276 7277/* ARM V6 ssat (argument parse). */ 7278 7279static void 7280do_ssat (void) 7281{ 7282 inst.instruction |= inst.operands[0].reg << 12; 7283 inst.instruction |= (inst.operands[1].imm - 1) << 16; 7284 inst.instruction |= inst.operands[2].reg; 7285 7286 if (inst.operands[3].present) 7287 encode_arm_shift (3); 7288} 7289 7290/* ARM V6 usat (argument parse). */ 7291 7292static void 7293do_usat (void) 7294{ 7295 inst.instruction |= inst.operands[0].reg << 12; 7296 inst.instruction |= inst.operands[1].imm << 16; 7297 inst.instruction |= inst.operands[2].reg; 7298 7299 if (inst.operands[3].present) 7300 encode_arm_shift (3); 7301} 7302 7303/* ARM V6 ssat16 (argument parse). */ 7304 7305static void 7306do_ssat16 (void) 7307{ 7308 inst.instruction |= inst.operands[0].reg << 12; 7309 inst.instruction |= ((inst.operands[1].imm - 1) << 16); 7310 inst.instruction |= inst.operands[2].reg; 7311} 7312 7313static void 7314do_usat16 (void) 7315{ 7316 inst.instruction |= inst.operands[0].reg << 12; 7317 inst.instruction |= inst.operands[1].imm << 16; 7318 inst.instruction |= inst.operands[2].reg; 7319} 7320 7321/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while 7322 preserving the other bits. 7323 7324 setend <endian_specifier>, where <endian_specifier> is either 7325 BE or LE. */ 7326 7327static void 7328do_setend (void) 7329{ 7330 if (inst.operands[0].imm) 7331 inst.instruction |= 0x200; 7332} 7333 7334static void 7335do_shift (void) 7336{ 7337 unsigned int Rm = (inst.operands[1].present 7338 ? inst.operands[1].reg 7339 : inst.operands[0].reg); 7340 7341 inst.instruction |= inst.operands[0].reg << 12; 7342 inst.instruction |= Rm; 7343 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ 7344 { 7345 inst.instruction |= inst.operands[2].reg << 8; 7346 inst.instruction |= SHIFT_BY_REG; 7347 } 7348 else 7349 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 7350} 7351 7352static void 7353do_smc (void) 7354{ 7355 inst.reloc.type = BFD_RELOC_ARM_SMC; 7356 inst.reloc.pc_rel = 0; 7357} 7358 7359static void 7360do_swi (void) 7361{ 7362 inst.reloc.type = BFD_RELOC_ARM_SWI; 7363 inst.reloc.pc_rel = 0; 7364} 7365 7366/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) 7367 SMLAxy{cond} Rd,Rm,Rs,Rn 7368 SMLAWy{cond} Rd,Rm,Rs,Rn 7369 Error if any register is R15. */ 7370 7371static void 7372do_smla (void) 7373{ 7374 inst.instruction |= inst.operands[0].reg << 16; 7375 inst.instruction |= inst.operands[1].reg; 7376 inst.instruction |= inst.operands[2].reg << 8; 7377 inst.instruction |= inst.operands[3].reg << 12; 7378} 7379 7380/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) 7381 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs 7382 Error if any register is R15. 7383 Warning if Rdlo == Rdhi. */ 7384 7385static void 7386do_smlal (void) 7387{ 7388 inst.instruction |= inst.operands[0].reg << 12; 7389 inst.instruction |= inst.operands[1].reg << 16; 7390 inst.instruction |= inst.operands[2].reg; 7391 inst.instruction |= inst.operands[3].reg << 8; 7392 7393 if (inst.operands[0].reg == inst.operands[1].reg) 7394 as_tsktsk (_("rdhi and rdlo must be different")); 7395} 7396 7397/* ARM V5E (El Segundo) signed-multiply (argument parse) 7398 SMULxy{cond} Rd,Rm,Rs 7399 Error if any register is R15. */ 7400 7401static void 7402do_smul (void) 7403{ 7404 inst.instruction |= inst.operands[0].reg << 16; 7405 inst.instruction |= inst.operands[1].reg; 7406 inst.instruction |= inst.operands[2].reg << 8; 7407} 7408 7409/* ARM V6 srs (argument parse). The variable fields in the encoding are 7410 the same for both ARM and Thumb-2. */ 7411 7412static void 7413do_srs (void) 7414{ 7415 int reg; 7416 7417 if (inst.operands[0].present) 7418 { 7419 reg = inst.operands[0].reg; 7420 constraint (reg != 13, _("SRS base register must be r13")); 7421 } 7422 else 7423 reg = 13; 7424 7425 inst.instruction |= reg << 16; 7426 inst.instruction |= inst.operands[1].imm; 7427 if (inst.operands[0].writeback || inst.operands[1].writeback) 7428 inst.instruction |= WRITE_BACK; 7429} 7430 7431/* ARM V6 strex (argument parse). */ 7432 7433static void 7434do_strex (void) 7435{ 7436 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 7437 || inst.operands[2].postind || inst.operands[2].writeback 7438 || inst.operands[2].immisreg || inst.operands[2].shifted 7439 || inst.operands[2].negative 7440 /* See comment in do_ldrex(). */ 7441 || (inst.operands[2].reg == REG_PC), 7442 BAD_ADDR_MODE); 7443 7444 constraint (inst.operands[0].reg == inst.operands[1].reg 7445 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); 7446 7447 constraint (inst.reloc.exp.X_op != O_constant 7448 || inst.reloc.exp.X_add_number != 0, 7449 _("offset must be zero in ARM encoding")); 7450 7451 inst.instruction |= inst.operands[0].reg << 12; 7452 inst.instruction |= inst.operands[1].reg; 7453 inst.instruction |= inst.operands[2].reg << 16; 7454 inst.reloc.type = BFD_RELOC_UNUSED; 7455} 7456 7457static void 7458do_strexd (void) 7459{ 7460 constraint (inst.operands[1].reg % 2 != 0, 7461 _("even register required")); 7462 constraint (inst.operands[2].present 7463 && inst.operands[2].reg != inst.operands[1].reg + 1, 7464 _("can only store two consecutive registers")); 7465 /* If op 2 were present and equal to PC, this function wouldn't 7466 have been called in the first place. */ 7467 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); 7468 7469 constraint (inst.operands[0].reg == inst.operands[1].reg 7470 || inst.operands[0].reg == inst.operands[1].reg + 1 7471 || inst.operands[0].reg == inst.operands[3].reg, 7472 BAD_OVERLAP); 7473 7474 inst.instruction |= inst.operands[0].reg << 12; 7475 inst.instruction |= inst.operands[1].reg; 7476 inst.instruction |= inst.operands[3].reg << 16; 7477} 7478 7479/* ARM V6 SXTAH extracts a 16-bit value from a register, sign 7480 extends it to 32-bits, and adds the result to a value in another 7481 register. You can specify a rotation by 0, 8, 16, or 24 bits 7482 before extracting the 16-bit value. 7483 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} 7484 Condition defaults to COND_ALWAYS. 7485 Error if any register uses R15. */ 7486 7487static void 7488do_sxtah (void) 7489{ 7490 inst.instruction |= inst.operands[0].reg << 12; 7491 inst.instruction |= inst.operands[1].reg << 16; 7492 inst.instruction |= inst.operands[2].reg; 7493 inst.instruction |= inst.operands[3].imm << 10; 7494} 7495 7496/* ARM V6 SXTH. 7497 7498 SXTH {<cond>} <Rd>, <Rm>{, <rotation>} 7499 Condition defaults to COND_ALWAYS. 7500 Error if any register uses R15. */ 7501 7502static void 7503do_sxth (void) 7504{ 7505 inst.instruction |= inst.operands[0].reg << 12; 7506 inst.instruction |= inst.operands[1].reg; 7507 inst.instruction |= inst.operands[2].imm << 10; 7508} 7509 7510/* VFP instructions. In a logical order: SP variant first, monad 7511 before dyad, arithmetic then move then load/store. */ 7512 7513static void 7514do_vfp_sp_monadic (void) 7515{ 7516 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7517 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7518} 7519 7520static void 7521do_vfp_sp_dyadic (void) 7522{ 7523 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7524 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7525 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7526} 7527 7528static void 7529do_vfp_sp_compare_z (void) 7530{ 7531 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7532} 7533 7534static void 7535do_vfp_dp_sp_cvt (void) 7536{ 7537 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7538 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7539} 7540 7541static void 7542do_vfp_sp_dp_cvt (void) 7543{ 7544 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7545 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7546} 7547 7548static void 7549do_vfp_reg_from_sp (void) 7550{ 7551 inst.instruction |= inst.operands[0].reg << 12; 7552 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7553} 7554 7555static void 7556do_vfp_reg2_from_sp2 (void) 7557{ 7558 constraint (inst.operands[2].imm != 2, 7559 _("only two consecutive VFP SP registers allowed here")); 7560 inst.instruction |= inst.operands[0].reg << 12; 7561 inst.instruction |= inst.operands[1].reg << 16; 7562 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7563} 7564 7565static void 7566do_vfp_sp_from_reg (void) 7567{ 7568 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); 7569 inst.instruction |= inst.operands[1].reg << 12; 7570} 7571 7572static void 7573do_vfp_sp2_from_reg2 (void) 7574{ 7575 constraint (inst.operands[0].imm != 2, 7576 _("only two consecutive VFP SP registers allowed here")); 7577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); 7578 inst.instruction |= inst.operands[1].reg << 12; 7579 inst.instruction |= inst.operands[2].reg << 16; 7580} 7581 7582static void 7583do_vfp_sp_ldst (void) 7584{ 7585 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7586 encode_arm_cp_address (1, FALSE, TRUE, 0); 7587} 7588 7589static void 7590do_vfp_dp_ldst (void) 7591{ 7592 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7593 encode_arm_cp_address (1, FALSE, TRUE, 0); 7594} 7595 7596 7597static void 7598vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) 7599{ 7600 if (inst.operands[0].writeback) 7601 inst.instruction |= WRITE_BACK; 7602 else 7603 constraint (ldstm_type != VFP_LDSTMIA, 7604 _("this addressing mode requires base-register writeback")); 7605 inst.instruction |= inst.operands[0].reg << 16; 7606 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); 7607 inst.instruction |= inst.operands[1].imm; 7608} 7609 7610static void 7611vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) 7612{ 7613 int count; 7614 7615 if (inst.operands[0].writeback) 7616 inst.instruction |= WRITE_BACK; 7617 else 7618 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, 7619 _("this addressing mode requires base-register writeback")); 7620 7621 inst.instruction |= inst.operands[0].reg << 16; 7622 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7623 7624 count = inst.operands[1].imm << 1; 7625 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) 7626 count += 1; 7627 7628 inst.instruction |= count; 7629} 7630 7631static void 7632do_vfp_sp_ldstmia (void) 7633{ 7634 vfp_sp_ldstm (VFP_LDSTMIA); 7635} 7636 7637static void 7638do_vfp_sp_ldstmdb (void) 7639{ 7640 vfp_sp_ldstm (VFP_LDSTMDB); 7641} 7642 7643static void 7644do_vfp_dp_ldstmia (void) 7645{ 7646 vfp_dp_ldstm (VFP_LDSTMIA); 7647} 7648 7649static void 7650do_vfp_dp_ldstmdb (void) 7651{ 7652 vfp_dp_ldstm (VFP_LDSTMDB); 7653} 7654 7655static void 7656do_vfp_xp_ldstmia (void) 7657{ 7658 vfp_dp_ldstm (VFP_LDSTMIAX); 7659} 7660 7661static void 7662do_vfp_xp_ldstmdb (void) 7663{ 7664 vfp_dp_ldstm (VFP_LDSTMDBX); 7665} 7666 7667static void 7668do_vfp_dp_rd_rm (void) 7669{ 7670 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7671 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7672} 7673 7674static void 7675do_vfp_dp_rn_rd (void) 7676{ 7677 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); 7678 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7679} 7680 7681static void 7682do_vfp_dp_rd_rn (void) 7683{ 7684 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7685 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7686} 7687 7688static void 7689do_vfp_dp_rd_rn_rm (void) 7690{ 7691 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7692 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7693 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); 7694} 7695 7696static void 7697do_vfp_dp_rd (void) 7698{ 7699 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7700} 7701 7702static void 7703do_vfp_dp_rm_rd_rn (void) 7704{ 7705 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); 7706 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7707 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); 7708} 7709 7710/* VFPv3 instructions. */ 7711static void 7712do_vfp_sp_const (void) 7713{ 7714 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7715 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7716 inst.instruction |= (inst.operands[1].imm & 0x0f); 7717} 7718 7719static void 7720do_vfp_dp_const (void) 7721{ 7722 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7723 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7724 inst.instruction |= (inst.operands[1].imm & 0x0f); 7725} 7726 7727static void 7728vfp_conv (int srcsize) 7729{ 7730 unsigned immbits = srcsize - inst.operands[1].imm; 7731 inst.instruction |= (immbits & 1) << 5; 7732 inst.instruction |= (immbits >> 1); 7733} 7734 7735static void 7736do_vfp_sp_conv_16 (void) 7737{ 7738 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7739 vfp_conv (16); 7740} 7741 7742static void 7743do_vfp_dp_conv_16 (void) 7744{ 7745 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7746 vfp_conv (16); 7747} 7748 7749static void 7750do_vfp_sp_conv_32 (void) 7751{ 7752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7753 vfp_conv (32); 7754} 7755 7756static void 7757do_vfp_dp_conv_32 (void) 7758{ 7759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7760 vfp_conv (32); 7761} 7762 7763 7764/* FPA instructions. Also in a logical order. */ 7765 7766static void 7767do_fpa_cmp (void) 7768{ 7769 inst.instruction |= inst.operands[0].reg << 16; 7770 inst.instruction |= inst.operands[1].reg; 7771} 7772 7773static void 7774do_fpa_ldmstm (void) 7775{ 7776 inst.instruction |= inst.operands[0].reg << 12; 7777 switch (inst.operands[1].imm) 7778 { 7779 case 1: inst.instruction |= CP_T_X; break; 7780 case 2: inst.instruction |= CP_T_Y; break; 7781 case 3: inst.instruction |= CP_T_Y | CP_T_X; break; 7782 case 4: break; 7783 default: abort (); 7784 } 7785 7786 if (inst.instruction & (PRE_INDEX | INDEX_UP)) 7787 { 7788 /* The instruction specified "ea" or "fd", so we can only accept 7789 [Rn]{!}. The instruction does not really support stacking or 7790 unstacking, so we have to emulate these by setting appropriate 7791 bits and offsets. */ 7792 constraint (inst.reloc.exp.X_op != O_constant 7793 || inst.reloc.exp.X_add_number != 0, 7794 _("this instruction does not support indexing")); 7795 7796 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) 7797 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; 7798 7799 if (!(inst.instruction & INDEX_UP)) 7800 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; 7801 7802 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) 7803 { 7804 inst.operands[2].preind = 0; 7805 inst.operands[2].postind = 1; 7806 } 7807 } 7808 7809 encode_arm_cp_address (2, TRUE, TRUE, 0); 7810} 7811 7812 7813/* iWMMXt instructions: strictly in alphabetical order. */ 7814 7815static void 7816do_iwmmxt_tandorc (void) 7817{ 7818 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); 7819} 7820 7821static void 7822do_iwmmxt_textrc (void) 7823{ 7824 inst.instruction |= inst.operands[0].reg << 12; 7825 inst.instruction |= inst.operands[1].imm; 7826} 7827 7828static void 7829do_iwmmxt_textrm (void) 7830{ 7831 inst.instruction |= inst.operands[0].reg << 12; 7832 inst.instruction |= inst.operands[1].reg << 16; 7833 inst.instruction |= inst.operands[2].imm; 7834} 7835 7836static void 7837do_iwmmxt_tinsr (void) 7838{ 7839 inst.instruction |= inst.operands[0].reg << 16; 7840 inst.instruction |= inst.operands[1].reg << 12; 7841 inst.instruction |= inst.operands[2].imm; 7842} 7843 7844static void 7845do_iwmmxt_tmia (void) 7846{ 7847 inst.instruction |= inst.operands[0].reg << 5; 7848 inst.instruction |= inst.operands[1].reg; 7849 inst.instruction |= inst.operands[2].reg << 12; 7850} 7851 7852static void 7853do_iwmmxt_waligni (void) 7854{ 7855 inst.instruction |= inst.operands[0].reg << 12; 7856 inst.instruction |= inst.operands[1].reg << 16; 7857 inst.instruction |= inst.operands[2].reg; 7858 inst.instruction |= inst.operands[3].imm << 20; 7859} 7860 7861static void 7862do_iwmmxt_wmerge (void) 7863{ 7864 inst.instruction |= inst.operands[0].reg << 12; 7865 inst.instruction |= inst.operands[1].reg << 16; 7866 inst.instruction |= inst.operands[2].reg; 7867 inst.instruction |= inst.operands[3].imm << 21; 7868} 7869 7870static void 7871do_iwmmxt_wmov (void) 7872{ 7873 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ 7874 inst.instruction |= inst.operands[0].reg << 12; 7875 inst.instruction |= inst.operands[1].reg << 16; 7876 inst.instruction |= inst.operands[1].reg; 7877} 7878 7879static void 7880do_iwmmxt_wldstbh (void) 7881{ 7882 int reloc; 7883 inst.instruction |= inst.operands[0].reg << 12; 7884 if (thumb_mode) 7885 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; 7886 else 7887 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; 7888 encode_arm_cp_address (1, TRUE, FALSE, reloc); 7889} 7890 7891static void 7892do_iwmmxt_wldstw (void) 7893{ 7894 /* RIWR_RIWC clears .isreg for a control register. */ 7895 if (!inst.operands[0].isreg) 7896 { 7897 constraint (inst.cond != COND_ALWAYS, BAD_COND); 7898 inst.instruction |= 0xf0000000; 7899 } 7900 7901 inst.instruction |= inst.operands[0].reg << 12; 7902 encode_arm_cp_address (1, TRUE, TRUE, 0); 7903} 7904 7905static void 7906do_iwmmxt_wldstd (void) 7907{ 7908 inst.instruction |= inst.operands[0].reg << 12; 7909 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) 7910 && inst.operands[1].immisreg) 7911 { 7912 inst.instruction &= ~0x1a000ff; 7913 inst.instruction |= (0xf << 28); 7914 if (inst.operands[1].preind) 7915 inst.instruction |= PRE_INDEX; 7916 if (!inst.operands[1].negative) 7917 inst.instruction |= INDEX_UP; 7918 if (inst.operands[1].writeback) 7919 inst.instruction |= WRITE_BACK; 7920 inst.instruction |= inst.operands[1].reg << 16; 7921 inst.instruction |= inst.reloc.exp.X_add_number << 4; 7922 inst.instruction |= inst.operands[1].imm; 7923 } 7924 else 7925 encode_arm_cp_address (1, TRUE, FALSE, 0); 7926} 7927 7928static void 7929do_iwmmxt_wshufh (void) 7930{ 7931 inst.instruction |= inst.operands[0].reg << 12; 7932 inst.instruction |= inst.operands[1].reg << 16; 7933 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); 7934 inst.instruction |= (inst.operands[2].imm & 0x0f); 7935} 7936 7937static void 7938do_iwmmxt_wzero (void) 7939{ 7940 /* WZERO reg is an alias for WANDN reg, reg, reg. */ 7941 inst.instruction |= inst.operands[0].reg; 7942 inst.instruction |= inst.operands[0].reg << 12; 7943 inst.instruction |= inst.operands[0].reg << 16; 7944} 7945 7946static void 7947do_iwmmxt_wrwrwr_or_imm5 (void) 7948{ 7949 if (inst.operands[2].isreg) 7950 do_rd_rn_rm (); 7951 else { 7952 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), 7953 _("immediate operand requires iWMMXt2")); 7954 do_rd_rn (); 7955 if (inst.operands[2].imm == 0) 7956 { 7957 switch ((inst.instruction >> 20) & 0xf) 7958 { 7959 case 4: 7960 case 5: 7961 case 6: 7962 case 7: 7963 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ 7964 inst.operands[2].imm = 16; 7965 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); 7966 break; 7967 case 8: 7968 case 9: 7969 case 10: 7970 case 11: 7971 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ 7972 inst.operands[2].imm = 32; 7973 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); 7974 break; 7975 case 12: 7976 case 13: 7977 case 14: 7978 case 15: 7979 { 7980 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ 7981 unsigned long wrn; 7982 wrn = (inst.instruction >> 16) & 0xf; 7983 inst.instruction &= 0xff0fff0f; 7984 inst.instruction |= wrn; 7985 /* Bail out here; the instruction is now assembled. */ 7986 return; 7987 } 7988 } 7989 } 7990 /* Map 32 -> 0, etc. */ 7991 inst.operands[2].imm &= 0x1f; 7992 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); 7993 } 7994} 7995 7996/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register 7997 operations first, then control, shift, and load/store. */ 7998 7999/* Insns like "foo X,Y,Z". */ 8000 8001static void 8002do_mav_triple (void) 8003{ 8004 inst.instruction |= inst.operands[0].reg << 16; 8005 inst.instruction |= inst.operands[1].reg; 8006 inst.instruction |= inst.operands[2].reg << 12; 8007} 8008 8009/* Insns like "foo W,X,Y,Z". 8010 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ 8011 8012static void 8013do_mav_quad (void) 8014{ 8015 inst.instruction |= inst.operands[0].reg << 5; 8016 inst.instruction |= inst.operands[1].reg << 12; 8017 inst.instruction |= inst.operands[2].reg << 16; 8018 inst.instruction |= inst.operands[3].reg; 8019} 8020 8021/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ 8022static void 8023do_mav_dspsc (void) 8024{ 8025 inst.instruction |= inst.operands[1].reg << 12; 8026} 8027 8028/* Maverick shift immediate instructions. 8029 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. 8030 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ 8031 8032static void 8033do_mav_shift (void) 8034{ 8035 int imm = inst.operands[2].imm; 8036 8037 inst.instruction |= inst.operands[0].reg << 12; 8038 inst.instruction |= inst.operands[1].reg << 16; 8039 8040 /* Bits 0-3 of the insn should have bits 0-3 of the immediate. 8041 Bits 5-7 of the insn should have bits 4-6 of the immediate. 8042 Bit 4 should be 0. */ 8043 imm = (imm & 0xf) | ((imm & 0x70) << 1); 8044 8045 inst.instruction |= imm; 8046} 8047 8048/* XScale instructions. Also sorted arithmetic before move. */ 8049 8050/* Xscale multiply-accumulate (argument parse) 8051 MIAcc acc0,Rm,Rs 8052 MIAPHcc acc0,Rm,Rs 8053 MIAxycc acc0,Rm,Rs. */ 8054 8055static void 8056do_xsc_mia (void) 8057{ 8058 inst.instruction |= inst.operands[1].reg; 8059 inst.instruction |= inst.operands[2].reg << 12; 8060} 8061 8062/* Xscale move-accumulator-register (argument parse) 8063 8064 MARcc acc0,RdLo,RdHi. */ 8065 8066static void 8067do_xsc_mar (void) 8068{ 8069 inst.instruction |= inst.operands[1].reg << 12; 8070 inst.instruction |= inst.operands[2].reg << 16; 8071} 8072 8073/* Xscale move-register-accumulator (argument parse) 8074 8075 MRAcc RdLo,RdHi,acc0. */ 8076 8077static void 8078do_xsc_mra (void) 8079{ 8080 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); 8081 inst.instruction |= inst.operands[0].reg << 12; 8082 inst.instruction |= inst.operands[1].reg << 16; 8083} 8084 8085/* Encoding functions relevant only to Thumb. */ 8086 8087/* inst.operands[i] is a shifted-register operand; encode 8088 it into inst.instruction in the format used by Thumb32. */ 8089 8090static void 8091encode_thumb32_shifted_operand (int i) 8092{ 8093 unsigned int value = inst.reloc.exp.X_add_number; 8094 unsigned int shift = inst.operands[i].shift_kind; 8095 8096 constraint (inst.operands[i].immisreg, 8097 _("shift by register not allowed in thumb mode")); 8098 inst.instruction |= inst.operands[i].reg; 8099 if (shift == SHIFT_RRX) 8100 inst.instruction |= SHIFT_ROR << 4; 8101 else 8102 { 8103 constraint (inst.reloc.exp.X_op != O_constant, 8104 _("expression too complex")); 8105 8106 constraint (value > 32 8107 || (value == 32 && (shift == SHIFT_LSL 8108 || shift == SHIFT_ROR)), 8109 _("shift expression is too large")); 8110 8111 if (value == 0) 8112 shift = SHIFT_LSL; 8113 else if (value == 32) 8114 value = 0; 8115 8116 inst.instruction |= shift << 4; 8117 inst.instruction |= (value & 0x1c) << 10; 8118 inst.instruction |= (value & 0x03) << 6; 8119 } 8120} 8121 8122 8123/* inst.operands[i] was set up by parse_address. Encode it into a 8124 Thumb32 format load or store instruction. Reject forms that cannot 8125 be used with such instructions. If is_t is true, reject forms that 8126 cannot be used with a T instruction; if is_d is true, reject forms 8127 that cannot be used with a D instruction. */ 8128 8129static void 8130encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) 8131{ 8132 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); 8133 8134 constraint (!inst.operands[i].isreg, 8135 _("Instruction does not support =N addresses")); 8136 8137 inst.instruction |= inst.operands[i].reg << 16; 8138 if (inst.operands[i].immisreg) 8139 { 8140 constraint (is_pc, _("cannot use register index with PC-relative addressing")); 8141 constraint (is_t || is_d, _("cannot use register index with this instruction")); 8142 constraint (inst.operands[i].negative, 8143 _("Thumb does not support negative register indexing")); 8144 constraint (inst.operands[i].postind, 8145 _("Thumb does not support register post-indexing")); 8146 constraint (inst.operands[i].writeback, 8147 _("Thumb does not support register indexing with writeback")); 8148 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, 8149 _("Thumb supports only LSL in shifted register indexing")); 8150 8151 inst.instruction |= inst.operands[i].imm; 8152 if (inst.operands[i].shifted) 8153 { 8154 constraint (inst.reloc.exp.X_op != O_constant, 8155 _("expression too complex")); 8156 constraint (inst.reloc.exp.X_add_number < 0 8157 || inst.reloc.exp.X_add_number > 3, 8158 _("shift out of range")); 8159 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8160 } 8161 inst.reloc.type = BFD_RELOC_UNUSED; 8162 } 8163 else if (inst.operands[i].preind) 8164 { 8165 constraint (is_pc && inst.operands[i].writeback, 8166 _("cannot use writeback with PC-relative addressing")); 8167 constraint (is_t && inst.operands[i].writeback, 8168 _("cannot use writeback with this instruction")); 8169 8170 if (is_d) 8171 { 8172 inst.instruction |= 0x01000000; 8173 if (inst.operands[i].writeback) 8174 inst.instruction |= 0x00200000; 8175 } 8176 else 8177 { 8178 inst.instruction |= 0x00000c00; 8179 if (inst.operands[i].writeback) 8180 inst.instruction |= 0x00000100; 8181 } 8182 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8183 } 8184 else if (inst.operands[i].postind) 8185 { 8186 assert (inst.operands[i].writeback); 8187 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); 8188 constraint (is_t, _("cannot use post-indexing with this instruction")); 8189 8190 if (is_d) 8191 inst.instruction |= 0x00200000; 8192 else 8193 inst.instruction |= 0x00000900; 8194 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8195 } 8196 else /* unindexed - only for coprocessor */ 8197 inst.error = _("instruction does not accept unindexed addressing"); 8198} 8199 8200/* Table of Thumb instructions which exist in both 16- and 32-bit 8201 encodings (the latter only in post-V6T2 cores). The index is the 8202 value used in the insns table below. When there is more than one 8203 possible 16-bit encoding for the instruction, this table always 8204 holds variant (1). 8205 Also contains several pseudo-instructions used during relaxation. */ 8206#define T16_32_TAB \ 8207 X(adc, 4140, eb400000), \ 8208 X(adcs, 4140, eb500000), \ 8209 X(add, 1c00, eb000000), \ 8210 X(adds, 1c00, eb100000), \ 8211 X(addi, 0000, f1000000), \ 8212 X(addis, 0000, f1100000), \ 8213 X(add_pc,000f, f20f0000), \ 8214 X(add_sp,000d, f10d0000), \ 8215 X(adr, 000f, f20f0000), \ 8216 X(and, 4000, ea000000), \ 8217 X(ands, 4000, ea100000), \ 8218 X(asr, 1000, fa40f000), \ 8219 X(asrs, 1000, fa50f000), \ 8220 X(b, e000, f000b000), \ 8221 X(bcond, d000, f0008000), \ 8222 X(bic, 4380, ea200000), \ 8223 X(bics, 4380, ea300000), \ 8224 X(cmn, 42c0, eb100f00), \ 8225 X(cmp, 2800, ebb00f00), \ 8226 X(cpsie, b660, f3af8400), \ 8227 X(cpsid, b670, f3af8600), \ 8228 X(cpy, 4600, ea4f0000), \ 8229 X(dec_sp,80dd, f1ad0d00), \ 8230 X(eor, 4040, ea800000), \ 8231 X(eors, 4040, ea900000), \ 8232 X(inc_sp,00dd, f10d0d00), \ 8233 X(ldmia, c800, e8900000), \ 8234 X(ldr, 6800, f8500000), \ 8235 X(ldrb, 7800, f8100000), \ 8236 X(ldrh, 8800, f8300000), \ 8237 X(ldrsb, 5600, f9100000), \ 8238 X(ldrsh, 5e00, f9300000), \ 8239 X(ldr_pc,4800, f85f0000), \ 8240 X(ldr_pc2,4800, f85f0000), \ 8241 X(ldr_sp,9800, f85d0000), \ 8242 X(lsl, 0000, fa00f000), \ 8243 X(lsls, 0000, fa10f000), \ 8244 X(lsr, 0800, fa20f000), \ 8245 X(lsrs, 0800, fa30f000), \ 8246 X(mov, 2000, ea4f0000), \ 8247 X(movs, 2000, ea5f0000), \ 8248 X(mul, 4340, fb00f000), \ 8249 X(muls, 4340, ffffffff), /* no 32b muls */ \ 8250 X(mvn, 43c0, ea6f0000), \ 8251 X(mvns, 43c0, ea7f0000), \ 8252 X(neg, 4240, f1c00000), /* rsb #0 */ \ 8253 X(negs, 4240, f1d00000), /* rsbs #0 */ \ 8254 X(orr, 4300, ea400000), \ 8255 X(orrs, 4300, ea500000), \ 8256 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ 8257 X(push, b400, e92d0000), /* stmdb sp!,... */ \ 8258 X(rev, ba00, fa90f080), \ 8259 X(rev16, ba40, fa90f090), \ 8260 X(revsh, bac0, fa90f0b0), \ 8261 X(ror, 41c0, fa60f000), \ 8262 X(rors, 41c0, fa70f000), \ 8263 X(sbc, 4180, eb600000), \ 8264 X(sbcs, 4180, eb700000), \ 8265 X(stmia, c000, e8800000), \ 8266 X(str, 6000, f8400000), \ 8267 X(strb, 7000, f8000000), \ 8268 X(strh, 8000, f8200000), \ 8269 X(str_sp,9000, f84d0000), \ 8270 X(sub, 1e00, eba00000), \ 8271 X(subs, 1e00, ebb00000), \ 8272 X(subi, 8000, f1a00000), \ 8273 X(subis, 8000, f1b00000), \ 8274 X(sxtb, b240, fa4ff080), \ 8275 X(sxth, b200, fa0ff080), \ 8276 X(tst, 4200, ea100f00), \ 8277 X(uxtb, b2c0, fa5ff080), \ 8278 X(uxth, b280, fa1ff080), \ 8279 X(nop, bf00, f3af8000), \ 8280 X(yield, bf10, f3af8001), \ 8281 X(wfe, bf20, f3af8002), \ 8282 X(wfi, bf30, f3af8003), \ 8283 X(sev, bf40, f3af9004), /* typo, 8004? */ 8284 8285/* To catch errors in encoding functions, the codes are all offset by 8286 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined 8287 as 16-bit instructions. */ 8288#define X(a,b,c) T_MNEM_##a 8289enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; 8290#undef X 8291 8292#define X(a,b,c) 0x##b 8293static const unsigned short thumb_op16[] = { T16_32_TAB }; 8294#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) 8295#undef X 8296 8297#define X(a,b,c) 0x##c 8298static const unsigned int thumb_op32[] = { T16_32_TAB }; 8299#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) 8300#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) 8301#undef X 8302#undef T16_32_TAB 8303 8304/* Thumb instruction encoders, in alphabetical order. */ 8305 8306/* ADDW or SUBW. */ 8307static void 8308do_t_add_sub_w (void) 8309{ 8310 int Rd, Rn; 8311 8312 Rd = inst.operands[0].reg; 8313 Rn = inst.operands[1].reg; 8314 8315 constraint (Rd == 15, _("PC not allowed as destination")); 8316 inst.instruction |= (Rn << 16) | (Rd << 8); 8317 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8318} 8319 8320/* Parse an add or subtract instruction. We get here with inst.instruction 8321 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ 8322 8323static void 8324do_t_add_sub (void) 8325{ 8326 int Rd, Rs, Rn; 8327 8328 Rd = inst.operands[0].reg; 8329 Rs = (inst.operands[1].present 8330 ? inst.operands[1].reg /* Rd, Rs, foo */ 8331 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8332 8333 if (unified_syntax) 8334 { 8335 bfd_boolean flags; 8336 bfd_boolean narrow; 8337 int opcode; 8338 8339 flags = (inst.instruction == T_MNEM_adds 8340 || inst.instruction == T_MNEM_subs); 8341 if (flags) 8342 narrow = (current_it_mask == 0); 8343 else 8344 narrow = (current_it_mask != 0); 8345 if (!inst.operands[2].isreg) 8346 { 8347 int add; 8348 8349 add = (inst.instruction == T_MNEM_add 8350 || inst.instruction == T_MNEM_adds); 8351 opcode = 0; 8352 if (inst.size_req != 4) 8353 { 8354 /* Attempt to use a narrow opcode, with relaxation if 8355 appropriate. */ 8356 if (Rd == REG_SP && Rs == REG_SP && !flags) 8357 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; 8358 else if (Rd <= 7 && Rs == REG_SP && add && !flags) 8359 opcode = T_MNEM_add_sp; 8360 else if (Rd <= 7 && Rs == REG_PC && add && !flags) 8361 opcode = T_MNEM_add_pc; 8362 else if (Rd <= 7 && Rs <= 7 && narrow) 8363 { 8364 if (flags) 8365 opcode = add ? T_MNEM_addis : T_MNEM_subis; 8366 else 8367 opcode = add ? T_MNEM_addi : T_MNEM_subi; 8368 } 8369 if (opcode) 8370 { 8371 inst.instruction = THUMB_OP16(opcode); 8372 inst.instruction |= (Rd << 4) | Rs; 8373 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8374 if (inst.size_req != 2) 8375 inst.relax = opcode; 8376 } 8377 else 8378 constraint (inst.size_req == 2, BAD_HIREG); 8379 } 8380 if (inst.size_req == 4 8381 || (inst.size_req != 2 && !opcode)) 8382 { 8383 if (Rd == REG_PC) 8384 { 8385 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, 8386 _("only SUBS PC, LR, #const allowed")); 8387 constraint (inst.reloc.exp.X_op != O_constant, 8388 _("expression too complex")); 8389 constraint (inst.reloc.exp.X_add_number < 0 8390 || inst.reloc.exp.X_add_number > 0xff, 8391 _("immediate value out of range")); 8392 inst.instruction = T2_SUBS_PC_LR 8393 | inst.reloc.exp.X_add_number; 8394 inst.reloc.type = BFD_RELOC_UNUSED; 8395 return; 8396 } 8397 else if (Rs == REG_PC) 8398 { 8399 /* Always use addw/subw. */ 8400 inst.instruction = add ? 0xf20f0000 : 0xf2af0000; 8401 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8402 } 8403 else 8404 { 8405 inst.instruction = THUMB_OP32 (inst.instruction); 8406 inst.instruction = (inst.instruction & 0xe1ffffff) 8407 | 0x10000000; 8408 if (flags) 8409 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8410 else 8411 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; 8412 } 8413 inst.instruction |= Rd << 8; 8414 inst.instruction |= Rs << 16; 8415 } 8416 } 8417 else 8418 { 8419 Rn = inst.operands[2].reg; 8420 /* See if we can do this with a 16-bit instruction. */ 8421 if (!inst.operands[2].shifted && inst.size_req != 4) 8422 { 8423 if (Rd > 7 || Rs > 7 || Rn > 7) 8424 narrow = FALSE; 8425 8426 if (narrow) 8427 { 8428 inst.instruction = ((inst.instruction == T_MNEM_adds 8429 || inst.instruction == T_MNEM_add) 8430 ? T_OPCODE_ADD_R3 8431 : T_OPCODE_SUB_R3); 8432 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8433 return; 8434 } 8435 8436 if (inst.instruction == T_MNEM_add) 8437 { 8438 if (Rd == Rs) 8439 { 8440 inst.instruction = T_OPCODE_ADD_HI; 8441 inst.instruction |= (Rd & 8) << 4; 8442 inst.instruction |= (Rd & 7); 8443 inst.instruction |= Rn << 3; 8444 return; 8445 } 8446 /* ... because addition is commutative! */ 8447 else if (Rd == Rn) 8448 { 8449 inst.instruction = T_OPCODE_ADD_HI; 8450 inst.instruction |= (Rd & 8) << 4; 8451 inst.instruction |= (Rd & 7); 8452 inst.instruction |= Rs << 3; 8453 return; 8454 } 8455 } 8456 } 8457 /* If we get here, it can't be done in 16 bits. */ 8458 constraint (inst.operands[2].shifted && inst.operands[2].immisreg, 8459 _("shift must be constant")); 8460 inst.instruction = THUMB_OP32 (inst.instruction); 8461 inst.instruction |= Rd << 8; 8462 inst.instruction |= Rs << 16; 8463 encode_thumb32_shifted_operand (2); 8464 } 8465 } 8466 else 8467 { 8468 constraint (inst.instruction == T_MNEM_adds 8469 || inst.instruction == T_MNEM_subs, 8470 BAD_THUMB32); 8471 8472 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ 8473 { 8474 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) 8475 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), 8476 BAD_HIREG); 8477 8478 inst.instruction = (inst.instruction == T_MNEM_add 8479 ? 0x0000 : 0x8000); 8480 inst.instruction |= (Rd << 4) | Rs; 8481 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8482 return; 8483 } 8484 8485 Rn = inst.operands[2].reg; 8486 constraint (inst.operands[2].shifted, _("unshifted register required")); 8487 8488 /* We now have Rd, Rs, and Rn set to registers. */ 8489 if (Rd > 7 || Rs > 7 || Rn > 7) 8490 { 8491 /* Can't do this for SUB. */ 8492 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); 8493 inst.instruction = T_OPCODE_ADD_HI; 8494 inst.instruction |= (Rd & 8) << 4; 8495 inst.instruction |= (Rd & 7); 8496 if (Rs == Rd) 8497 inst.instruction |= Rn << 3; 8498 else if (Rn == Rd) 8499 inst.instruction |= Rs << 3; 8500 else 8501 constraint (1, _("dest must overlap one source register")); 8502 } 8503 else 8504 { 8505 inst.instruction = (inst.instruction == T_MNEM_add 8506 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); 8507 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8508 } 8509 } 8510} 8511 8512static void 8513do_t_adr (void) 8514{ 8515 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) 8516 { 8517 /* Defer to section relaxation. */ 8518 inst.relax = inst.instruction; 8519 inst.instruction = THUMB_OP16 (inst.instruction); 8520 inst.instruction |= inst.operands[0].reg << 4; 8521 } 8522 else if (unified_syntax && inst.size_req != 2) 8523 { 8524 /* Generate a 32-bit opcode. */ 8525 inst.instruction = THUMB_OP32 (inst.instruction); 8526 inst.instruction |= inst.operands[0].reg << 8; 8527 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; 8528 inst.reloc.pc_rel = 1; 8529 } 8530 else 8531 { 8532 /* Generate a 16-bit opcode. */ 8533 inst.instruction = THUMB_OP16 (inst.instruction); 8534 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8535 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ 8536 inst.reloc.pc_rel = 1; 8537 8538 inst.instruction |= inst.operands[0].reg << 4; 8539 } 8540} 8541 8542/* Arithmetic instructions for which there is just one 16-bit 8543 instruction encoding, and it allows only two low registers. 8544 For maximal compatibility with ARM syntax, we allow three register 8545 operands even when Thumb-32 instructions are not available, as long 8546 as the first two are identical. For instance, both "sbc r0,r1" and 8547 "sbc r0,r0,r1" are allowed. */ 8548static void 8549do_t_arit3 (void) 8550{ 8551 int Rd, Rs, Rn; 8552 8553 Rd = inst.operands[0].reg; 8554 Rs = (inst.operands[1].present 8555 ? inst.operands[1].reg /* Rd, Rs, foo */ 8556 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8557 Rn = inst.operands[2].reg; 8558 8559 if (unified_syntax) 8560 { 8561 if (!inst.operands[2].isreg) 8562 { 8563 /* For an immediate, we always generate a 32-bit opcode; 8564 section relaxation will shrink it later if possible. */ 8565 inst.instruction = THUMB_OP32 (inst.instruction); 8566 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8567 inst.instruction |= Rd << 8; 8568 inst.instruction |= Rs << 16; 8569 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8570 } 8571 else 8572 { 8573 bfd_boolean narrow; 8574 8575 /* See if we can do this with a 16-bit instruction. */ 8576 if (THUMB_SETS_FLAGS (inst.instruction)) 8577 narrow = current_it_mask == 0; 8578 else 8579 narrow = current_it_mask != 0; 8580 8581 if (Rd > 7 || Rn > 7 || Rs > 7) 8582 narrow = FALSE; 8583 if (inst.operands[2].shifted) 8584 narrow = FALSE; 8585 if (inst.size_req == 4) 8586 narrow = FALSE; 8587 8588 if (narrow 8589 && Rd == Rs) 8590 { 8591 inst.instruction = THUMB_OP16 (inst.instruction); 8592 inst.instruction |= Rd; 8593 inst.instruction |= Rn << 3; 8594 return; 8595 } 8596 8597 /* If we get here, it can't be done in 16 bits. */ 8598 constraint (inst.operands[2].shifted 8599 && inst.operands[2].immisreg, 8600 _("shift must be constant")); 8601 inst.instruction = THUMB_OP32 (inst.instruction); 8602 inst.instruction |= Rd << 8; 8603 inst.instruction |= Rs << 16; 8604 encode_thumb32_shifted_operand (2); 8605 } 8606 } 8607 else 8608 { 8609 /* On its face this is a lie - the instruction does set the 8610 flags. However, the only supported mnemonic in this mode 8611 says it doesn't. */ 8612 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8613 8614 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8615 _("unshifted register required")); 8616 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8617 constraint (Rd != Rs, 8618 _("dest and source1 must be the same register")); 8619 8620 inst.instruction = THUMB_OP16 (inst.instruction); 8621 inst.instruction |= Rd; 8622 inst.instruction |= Rn << 3; 8623 } 8624} 8625 8626/* Similarly, but for instructions where the arithmetic operation is 8627 commutative, so we can allow either of them to be different from 8628 the destination operand in a 16-bit instruction. For instance, all 8629 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are 8630 accepted. */ 8631static void 8632do_t_arit3c (void) 8633{ 8634 int Rd, Rs, Rn; 8635 8636 Rd = inst.operands[0].reg; 8637 Rs = (inst.operands[1].present 8638 ? inst.operands[1].reg /* Rd, Rs, foo */ 8639 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8640 Rn = inst.operands[2].reg; 8641 8642 if (unified_syntax) 8643 { 8644 if (!inst.operands[2].isreg) 8645 { 8646 /* For an immediate, we always generate a 32-bit opcode; 8647 section relaxation will shrink it later if possible. */ 8648 inst.instruction = THUMB_OP32 (inst.instruction); 8649 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8650 inst.instruction |= Rd << 8; 8651 inst.instruction |= Rs << 16; 8652 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8653 } 8654 else 8655 { 8656 bfd_boolean narrow; 8657 8658 /* See if we can do this with a 16-bit instruction. */ 8659 if (THUMB_SETS_FLAGS (inst.instruction)) 8660 narrow = current_it_mask == 0; 8661 else 8662 narrow = current_it_mask != 0; 8663 8664 if (Rd > 7 || Rn > 7 || Rs > 7) 8665 narrow = FALSE; 8666 if (inst.operands[2].shifted) 8667 narrow = FALSE; 8668 if (inst.size_req == 4) 8669 narrow = FALSE; 8670 8671 if (narrow) 8672 { 8673 if (Rd == Rs) 8674 { 8675 inst.instruction = THUMB_OP16 (inst.instruction); 8676 inst.instruction |= Rd; 8677 inst.instruction |= Rn << 3; 8678 return; 8679 } 8680 if (Rd == Rn) 8681 { 8682 inst.instruction = THUMB_OP16 (inst.instruction); 8683 inst.instruction |= Rd; 8684 inst.instruction |= Rs << 3; 8685 return; 8686 } 8687 } 8688 8689 /* If we get here, it can't be done in 16 bits. */ 8690 constraint (inst.operands[2].shifted 8691 && inst.operands[2].immisreg, 8692 _("shift must be constant")); 8693 inst.instruction = THUMB_OP32 (inst.instruction); 8694 inst.instruction |= Rd << 8; 8695 inst.instruction |= Rs << 16; 8696 encode_thumb32_shifted_operand (2); 8697 } 8698 } 8699 else 8700 { 8701 /* On its face this is a lie - the instruction does set the 8702 flags. However, the only supported mnemonic in this mode 8703 says it doesn't. */ 8704 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8705 8706 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8707 _("unshifted register required")); 8708 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8709 8710 inst.instruction = THUMB_OP16 (inst.instruction); 8711 inst.instruction |= Rd; 8712 8713 if (Rd == Rs) 8714 inst.instruction |= Rn << 3; 8715 else if (Rd == Rn) 8716 inst.instruction |= Rs << 3; 8717 else 8718 constraint (1, _("dest must overlap one source register")); 8719 } 8720} 8721 8722static void 8723do_t_barrier (void) 8724{ 8725 if (inst.operands[0].present) 8726 { 8727 constraint ((inst.instruction & 0xf0) != 0x40 8728 && inst.operands[0].imm != 0xf, 8729 "bad barrier type"); 8730 inst.instruction |= inst.operands[0].imm; 8731 } 8732 else 8733 inst.instruction |= 0xf; 8734} 8735 8736static void 8737do_t_bfc (void) 8738{ 8739 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 8740 constraint (msb > 32, _("bit-field extends past end of register")); 8741 /* The instruction encoding stores the LSB and MSB, 8742 not the LSB and width. */ 8743 inst.instruction |= inst.operands[0].reg << 8; 8744 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; 8745 inst.instruction |= (inst.operands[1].imm & 0x03) << 6; 8746 inst.instruction |= msb - 1; 8747} 8748 8749static void 8750do_t_bfi (void) 8751{ 8752 unsigned int msb; 8753 8754 /* #0 in second position is alternative syntax for bfc, which is 8755 the same instruction but with REG_PC in the Rm field. */ 8756 if (!inst.operands[1].isreg) 8757 inst.operands[1].reg = REG_PC; 8758 8759 msb = inst.operands[2].imm + inst.operands[3].imm; 8760 constraint (msb > 32, _("bit-field extends past end of register")); 8761 /* The instruction encoding stores the LSB and MSB, 8762 not the LSB and width. */ 8763 inst.instruction |= inst.operands[0].reg << 8; 8764 inst.instruction |= inst.operands[1].reg << 16; 8765 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8766 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8767 inst.instruction |= msb - 1; 8768} 8769 8770static void 8771do_t_bfx (void) 8772{ 8773 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 8774 _("bit-field extends past end of register")); 8775 inst.instruction |= inst.operands[0].reg << 8; 8776 inst.instruction |= inst.operands[1].reg << 16; 8777 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8778 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8779 inst.instruction |= inst.operands[3].imm - 1; 8780} 8781 8782/* ARM V5 Thumb BLX (argument parse) 8783 BLX <target_addr> which is BLX(1) 8784 BLX <Rm> which is BLX(2) 8785 Unfortunately, there are two different opcodes for this mnemonic. 8786 So, the insns[].value is not used, and the code here zaps values 8787 into inst.instruction. 8788 8789 ??? How to take advantage of the additional two bits of displacement 8790 available in Thumb32 mode? Need new relocation? */ 8791 8792static void 8793do_t_blx (void) 8794{ 8795 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8796 if (inst.operands[0].isreg) 8797 /* We have a register, so this is BLX(2). */ 8798 inst.instruction |= inst.operands[0].reg << 3; 8799 else 8800 { 8801 /* No register. This must be BLX(1). */ 8802 inst.instruction = 0xf000e800; 8803#ifdef OBJ_ELF 8804 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 8805 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8806 else 8807#endif 8808 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; 8809 inst.reloc.pc_rel = 1; 8810 } 8811} 8812 8813static void 8814do_t_branch (void) 8815{ 8816 int opcode; 8817 int cond; 8818 8819 if (current_it_mask) 8820 { 8821 /* Conditional branches inside IT blocks are encoded as unconditional 8822 branches. */ 8823 cond = COND_ALWAYS; 8824 /* A branch must be the last instruction in an IT block. */ 8825 constraint (current_it_mask != 0x10, BAD_BRANCH); 8826 } 8827 else 8828 cond = inst.cond; 8829 8830 if (cond != COND_ALWAYS) 8831 opcode = T_MNEM_bcond; 8832 else 8833 opcode = inst.instruction; 8834 8835 if (unified_syntax && inst.size_req == 4) 8836 { 8837 inst.instruction = THUMB_OP32(opcode); 8838 if (cond == COND_ALWAYS) 8839 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; 8840 else 8841 { 8842 assert (cond != 0xF); 8843 inst.instruction |= cond << 22; 8844 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; 8845 } 8846 } 8847 else 8848 { 8849 inst.instruction = THUMB_OP16(opcode); 8850 if (cond == COND_ALWAYS) 8851 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; 8852 else 8853 { 8854 inst.instruction |= cond << 8; 8855 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; 8856 } 8857 /* Allow section relaxation. */ 8858 if (unified_syntax && inst.size_req != 2) 8859 inst.relax = opcode; 8860 } 8861 8862 inst.reloc.pc_rel = 1; 8863} 8864 8865static void 8866do_t_bkpt (void) 8867{ 8868 constraint (inst.cond != COND_ALWAYS, 8869 _("instruction is always unconditional")); 8870 if (inst.operands[0].present) 8871 { 8872 constraint (inst.operands[0].imm > 255, 8873 _("immediate value out of range")); 8874 inst.instruction |= inst.operands[0].imm; 8875 } 8876} 8877 8878static void 8879do_t_branch23 (void) 8880{ 8881 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8882 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8883 inst.reloc.pc_rel = 1; 8884 8885 /* If the destination of the branch is a defined symbol which does not have 8886 the THUMB_FUNC attribute, then we must be calling a function which has 8887 the (interfacearm) attribute. We look for the Thumb entry point to that 8888 function and change the branch to refer to that function instead. */ 8889 if ( inst.reloc.exp.X_op == O_symbol 8890 && inst.reloc.exp.X_add_symbol != NULL 8891 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) 8892 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) 8893 inst.reloc.exp.X_add_symbol = 8894 find_real_start (inst.reloc.exp.X_add_symbol); 8895} 8896 8897static void 8898do_t_bx (void) 8899{ 8900 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8901 inst.instruction |= inst.operands[0].reg << 3; 8902 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc 8903 should cause the alignment to be checked once it is known. This is 8904 because BX PC only works if the instruction is word aligned. */ 8905} 8906 8907static void 8908do_t_bxj (void) 8909{ 8910 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8911 if (inst.operands[0].reg == REG_PC) 8912 as_tsktsk (_("use of r15 in bxj is not really useful")); 8913 8914 inst.instruction |= inst.operands[0].reg << 16; 8915} 8916 8917static void 8918do_t_clz (void) 8919{ 8920 inst.instruction |= inst.operands[0].reg << 8; 8921 inst.instruction |= inst.operands[1].reg << 16; 8922 inst.instruction |= inst.operands[1].reg; 8923} 8924 8925static void 8926do_t_cps (void) 8927{ 8928 constraint (current_it_mask, BAD_NOT_IT); 8929 inst.instruction |= inst.operands[0].imm; 8930} 8931 8932static void 8933do_t_cpsi (void) 8934{ 8935 constraint (current_it_mask, BAD_NOT_IT); 8936 if (unified_syntax 8937 && (inst.operands[1].present || inst.size_req == 4) 8938 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) 8939 { 8940 unsigned int imod = (inst.instruction & 0x0030) >> 4; 8941 inst.instruction = 0xf3af8000; 8942 inst.instruction |= imod << 9; 8943 inst.instruction |= inst.operands[0].imm << 5; 8944 if (inst.operands[1].present) 8945 inst.instruction |= 0x100 | inst.operands[1].imm; 8946 } 8947 else 8948 { 8949 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) 8950 && (inst.operands[0].imm & 4), 8951 _("selected processor does not support 'A' form " 8952 "of this instruction")); 8953 constraint (inst.operands[1].present || inst.size_req == 4, 8954 _("Thumb does not support the 2-argument " 8955 "form of this instruction")); 8956 inst.instruction |= inst.operands[0].imm; 8957 } 8958} 8959 8960/* THUMB CPY instruction (argument parse). */ 8961 8962static void 8963do_t_cpy (void) 8964{ 8965 if (inst.size_req == 4) 8966 { 8967 inst.instruction = THUMB_OP32 (T_MNEM_mov); 8968 inst.instruction |= inst.operands[0].reg << 8; 8969 inst.instruction |= inst.operands[1].reg; 8970 } 8971 else 8972 { 8973 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 8974 inst.instruction |= (inst.operands[0].reg & 0x7); 8975 inst.instruction |= inst.operands[1].reg << 3; 8976 } 8977} 8978 8979static void 8980do_t_cbz (void) 8981{ 8982 constraint (current_it_mask, BAD_NOT_IT); 8983 constraint (inst.operands[0].reg > 7, BAD_HIREG); 8984 inst.instruction |= inst.operands[0].reg; 8985 inst.reloc.pc_rel = 1; 8986 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; 8987} 8988 8989static void 8990do_t_dbg (void) 8991{ 8992 inst.instruction |= inst.operands[0].imm; 8993} 8994 8995static void 8996do_t_div (void) 8997{ 8998 if (!inst.operands[1].present) 8999 inst.operands[1].reg = inst.operands[0].reg; 9000 inst.instruction |= inst.operands[0].reg << 8; 9001 inst.instruction |= inst.operands[1].reg << 16; 9002 inst.instruction |= inst.operands[2].reg; 9003} 9004 9005static void 9006do_t_hint (void) 9007{ 9008 if (unified_syntax && inst.size_req == 4) 9009 inst.instruction = THUMB_OP32 (inst.instruction); 9010 else 9011 inst.instruction = THUMB_OP16 (inst.instruction); 9012} 9013 9014static void 9015do_t_it (void) 9016{ 9017 unsigned int cond = inst.operands[0].imm; 9018 9019 constraint (current_it_mask, BAD_NOT_IT); 9020 current_it_mask = (inst.instruction & 0xf) | 0x10; 9021 current_cc = cond; 9022 9023 /* If the condition is a negative condition, invert the mask. */ 9024 if ((cond & 0x1) == 0x0) 9025 { 9026 unsigned int mask = inst.instruction & 0x000f; 9027 9028 if ((mask & 0x7) == 0) 9029 /* no conversion needed */; 9030 else if ((mask & 0x3) == 0) 9031 mask ^= 0x8; 9032 else if ((mask & 0x1) == 0) 9033 mask ^= 0xC; 9034 else 9035 mask ^= 0xE; 9036 9037 inst.instruction &= 0xfff0; 9038 inst.instruction |= mask; 9039 } 9040 9041 inst.instruction |= cond << 4; 9042} 9043 9044/* Helper function used for both push/pop and ldm/stm. */ 9045static void 9046encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) 9047{ 9048 bfd_boolean load; 9049 9050 load = (inst.instruction & (1 << 20)) != 0; 9051 9052 if (mask & (1 << 13)) 9053 inst.error = _("SP not allowed in register list"); 9054 if (load) 9055 { 9056 if (mask & (1 << 14) 9057 && mask & (1 << 15)) 9058 inst.error = _("LR and PC should not both be in register list"); 9059 9060 if ((mask & (1 << base)) != 0 9061 && writeback) 9062 as_warn (_("base register should not be in register list " 9063 "when written back")); 9064 } 9065 else 9066 { 9067 if (mask & (1 << 15)) 9068 inst.error = _("PC not allowed in register list"); 9069 9070 if (mask & (1 << base)) 9071 as_warn (_("value stored for r%d is UNPREDICTABLE"), base); 9072 } 9073 9074 if ((mask & (mask - 1)) == 0) 9075 { 9076 /* Single register transfers implemented as str/ldr. */ 9077 if (writeback) 9078 { 9079 if (inst.instruction & (1 << 23)) 9080 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ 9081 else 9082 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ 9083 } 9084 else 9085 { 9086 if (inst.instruction & (1 << 23)) 9087 inst.instruction = 0x00800000; /* ia -> [base] */ 9088 else 9089 inst.instruction = 0x00000c04; /* db -> [base, #-4] */ 9090 } 9091 9092 inst.instruction |= 0xf8400000; 9093 if (load) 9094 inst.instruction |= 0x00100000; 9095 9096 mask = ffs(mask) - 1; 9097 mask <<= 12; 9098 } 9099 else if (writeback) 9100 inst.instruction |= WRITE_BACK; 9101 9102 inst.instruction |= mask; 9103 inst.instruction |= base << 16; 9104} 9105 9106static void 9107do_t_ldmstm (void) 9108{ 9109 /* This really doesn't seem worth it. */ 9110 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 9111 _("expression too complex")); 9112 constraint (inst.operands[1].writeback, 9113 _("Thumb load/store multiple does not support {reglist}^")); 9114 9115 if (unified_syntax) 9116 { 9117 bfd_boolean narrow; 9118 unsigned mask; 9119 9120 narrow = FALSE; 9121 /* See if we can use a 16-bit instruction. */ 9122 if (inst.instruction < 0xffff /* not ldmdb/stmdb */ 9123 && inst.size_req != 4 9124 && !(inst.operands[1].imm & ~0xff)) 9125 { 9126 mask = 1 << inst.operands[0].reg; 9127 9128 if (inst.operands[0].reg <= 7 9129 && (inst.instruction == T_MNEM_stmia 9130 ? inst.operands[0].writeback 9131 : (inst.operands[0].writeback 9132 == !(inst.operands[1].imm & mask)))) 9133 { 9134 if (inst.instruction == T_MNEM_stmia 9135 && (inst.operands[1].imm & mask) 9136 && (inst.operands[1].imm & (mask - 1))) 9137 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9138 inst.operands[0].reg); 9139 9140 inst.instruction = THUMB_OP16 (inst.instruction); 9141 inst.instruction |= inst.operands[0].reg << 8; 9142 inst.instruction |= inst.operands[1].imm; 9143 narrow = TRUE; 9144 } 9145 else if (inst.operands[0] .reg == REG_SP 9146 && inst.operands[0].writeback) 9147 { 9148 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia 9149 ? T_MNEM_push : T_MNEM_pop); 9150 inst.instruction |= inst.operands[1].imm; 9151 narrow = TRUE; 9152 } 9153 } 9154 9155 if (!narrow) 9156 { 9157 if (inst.instruction < 0xffff) 9158 inst.instruction = THUMB_OP32 (inst.instruction); 9159 9160 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm, 9161 inst.operands[0].writeback); 9162 } 9163 } 9164 else 9165 { 9166 constraint (inst.operands[0].reg > 7 9167 || (inst.operands[1].imm & ~0xff), BAD_HIREG); 9168 constraint (inst.instruction != T_MNEM_ldmia 9169 && inst.instruction != T_MNEM_stmia, 9170 _("Thumb-2 instruction only valid in unified syntax")); 9171 if (inst.instruction == T_MNEM_stmia) 9172 { 9173 if (!inst.operands[0].writeback) 9174 as_warn (_("this instruction will write back the base register")); 9175 if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) 9176 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) 9177 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9178 inst.operands[0].reg); 9179 } 9180 else 9181 { 9182 if (!inst.operands[0].writeback 9183 && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) 9184 as_warn (_("this instruction will write back the base register")); 9185 else if (inst.operands[0].writeback 9186 && (inst.operands[1].imm & (1 << inst.operands[0].reg))) 9187 as_warn (_("this instruction will not write back the base register")); 9188 } 9189 9190 inst.instruction = THUMB_OP16 (inst.instruction); 9191 inst.instruction |= inst.operands[0].reg << 8; 9192 inst.instruction |= inst.operands[1].imm; 9193 } 9194} 9195 9196static void 9197do_t_ldrex (void) 9198{ 9199 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 9200 || inst.operands[1].postind || inst.operands[1].writeback 9201 || inst.operands[1].immisreg || inst.operands[1].shifted 9202 || inst.operands[1].negative, 9203 BAD_ADDR_MODE); 9204 9205 inst.instruction |= inst.operands[0].reg << 12; 9206 inst.instruction |= inst.operands[1].reg << 16; 9207 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 9208} 9209 9210static void 9211do_t_ldrexd (void) 9212{ 9213 if (!inst.operands[1].present) 9214 { 9215 constraint (inst.operands[0].reg == REG_LR, 9216 _("r14 not allowed as first register " 9217 "when second register is omitted")); 9218 inst.operands[1].reg = inst.operands[0].reg + 1; 9219 } 9220 constraint (inst.operands[0].reg == inst.operands[1].reg, 9221 BAD_OVERLAP); 9222 9223 inst.instruction |= inst.operands[0].reg << 12; 9224 inst.instruction |= inst.operands[1].reg << 8; 9225 inst.instruction |= inst.operands[2].reg << 16; 9226} 9227 9228static void 9229do_t_ldst (void) 9230{ 9231 unsigned long opcode; 9232 int Rn; 9233 9234 opcode = inst.instruction; 9235 if (unified_syntax) 9236 { 9237 if (!inst.operands[1].isreg) 9238 { 9239 if (opcode <= 0xffff) 9240 inst.instruction = THUMB_OP32 (opcode); 9241 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9242 return; 9243 } 9244 if (inst.operands[1].isreg 9245 && !inst.operands[1].writeback 9246 && !inst.operands[1].shifted && !inst.operands[1].postind 9247 && !inst.operands[1].negative && inst.operands[0].reg <= 7 9248 && opcode <= 0xffff 9249 && inst.size_req != 4) 9250 { 9251 /* Insn may have a 16-bit form. */ 9252 Rn = inst.operands[1].reg; 9253 if (inst.operands[1].immisreg) 9254 { 9255 inst.instruction = THUMB_OP16 (opcode); 9256 /* [Rn, Ri] */ 9257 if (Rn <= 7 && inst.operands[1].imm <= 7) 9258 goto op16; 9259 } 9260 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh 9261 && opcode != T_MNEM_ldrsb) 9262 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) 9263 || (Rn == REG_SP && opcode == T_MNEM_str)) 9264 { 9265 /* [Rn, #const] */ 9266 if (Rn > 7) 9267 { 9268 if (Rn == REG_PC) 9269 { 9270 if (inst.reloc.pc_rel) 9271 opcode = T_MNEM_ldr_pc2; 9272 else 9273 opcode = T_MNEM_ldr_pc; 9274 } 9275 else 9276 { 9277 if (opcode == T_MNEM_ldr) 9278 opcode = T_MNEM_ldr_sp; 9279 else 9280 opcode = T_MNEM_str_sp; 9281 } 9282 inst.instruction = inst.operands[0].reg << 8; 9283 } 9284 else 9285 { 9286 inst.instruction = inst.operands[0].reg; 9287 inst.instruction |= inst.operands[1].reg << 3; 9288 } 9289 inst.instruction |= THUMB_OP16 (opcode); 9290 if (inst.size_req == 2) 9291 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9292 else 9293 inst.relax = opcode; 9294 return; 9295 } 9296 } 9297 /* Definitely a 32-bit variant. */ 9298 inst.instruction = THUMB_OP32 (opcode); 9299 inst.instruction |= inst.operands[0].reg << 12; 9300 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); 9301 return; 9302 } 9303 9304 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9305 9306 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) 9307 { 9308 /* Only [Rn,Rm] is acceptable. */ 9309 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); 9310 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg 9311 || inst.operands[1].postind || inst.operands[1].shifted 9312 || inst.operands[1].negative, 9313 _("Thumb does not support this addressing mode")); 9314 inst.instruction = THUMB_OP16 (inst.instruction); 9315 goto op16; 9316 } 9317 9318 inst.instruction = THUMB_OP16 (inst.instruction); 9319 if (!inst.operands[1].isreg) 9320 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9321 return; 9322 9323 constraint (!inst.operands[1].preind 9324 || inst.operands[1].shifted 9325 || inst.operands[1].writeback, 9326 _("Thumb does not support this addressing mode")); 9327 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) 9328 { 9329 constraint (inst.instruction & 0x0600, 9330 _("byte or halfword not valid for base register")); 9331 constraint (inst.operands[1].reg == REG_PC 9332 && !(inst.instruction & THUMB_LOAD_BIT), 9333 _("r15 based store not allowed")); 9334 constraint (inst.operands[1].immisreg, 9335 _("invalid base register for register offset")); 9336 9337 if (inst.operands[1].reg == REG_PC) 9338 inst.instruction = T_OPCODE_LDR_PC; 9339 else if (inst.instruction & THUMB_LOAD_BIT) 9340 inst.instruction = T_OPCODE_LDR_SP; 9341 else 9342 inst.instruction = T_OPCODE_STR_SP; 9343 9344 inst.instruction |= inst.operands[0].reg << 8; 9345 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9346 return; 9347 } 9348 9349 constraint (inst.operands[1].reg > 7, BAD_HIREG); 9350 if (!inst.operands[1].immisreg) 9351 { 9352 /* Immediate offset. */ 9353 inst.instruction |= inst.operands[0].reg; 9354 inst.instruction |= inst.operands[1].reg << 3; 9355 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9356 return; 9357 } 9358 9359 /* Register offset. */ 9360 constraint (inst.operands[1].imm > 7, BAD_HIREG); 9361 constraint (inst.operands[1].negative, 9362 _("Thumb does not support this addressing mode")); 9363 9364 op16: 9365 switch (inst.instruction) 9366 { 9367 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; 9368 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; 9369 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; 9370 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; 9371 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; 9372 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; 9373 case 0x5600 /* ldrsb */: 9374 case 0x5e00 /* ldrsh */: break; 9375 default: abort (); 9376 } 9377 9378 inst.instruction |= inst.operands[0].reg; 9379 inst.instruction |= inst.operands[1].reg << 3; 9380 inst.instruction |= inst.operands[1].imm << 6; 9381} 9382 9383static void 9384do_t_ldstd (void) 9385{ 9386 if (!inst.operands[1].present) 9387 { 9388 inst.operands[1].reg = inst.operands[0].reg + 1; 9389 constraint (inst.operands[0].reg == REG_LR, 9390 _("r14 not allowed here")); 9391 } 9392 inst.instruction |= inst.operands[0].reg << 12; 9393 inst.instruction |= inst.operands[1].reg << 8; 9394 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); 9395 9396} 9397 9398static void 9399do_t_ldstt (void) 9400{ 9401 inst.instruction |= inst.operands[0].reg << 12; 9402 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); 9403} 9404 9405static void 9406do_t_mla (void) 9407{ 9408 inst.instruction |= inst.operands[0].reg << 8; 9409 inst.instruction |= inst.operands[1].reg << 16; 9410 inst.instruction |= inst.operands[2].reg; 9411 inst.instruction |= inst.operands[3].reg << 12; 9412} 9413 9414static void 9415do_t_mlal (void) 9416{ 9417 inst.instruction |= inst.operands[0].reg << 12; 9418 inst.instruction |= inst.operands[1].reg << 8; 9419 inst.instruction |= inst.operands[2].reg << 16; 9420 inst.instruction |= inst.operands[3].reg; 9421} 9422 9423static void 9424do_t_mov_cmp (void) 9425{ 9426 if (unified_syntax) 9427 { 9428 int r0off = (inst.instruction == T_MNEM_mov 9429 || inst.instruction == T_MNEM_movs) ? 8 : 16; 9430 unsigned long opcode; 9431 bfd_boolean narrow; 9432 bfd_boolean low_regs; 9433 9434 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); 9435 opcode = inst.instruction; 9436 if (current_it_mask) 9437 narrow = opcode != T_MNEM_movs; 9438 else 9439 narrow = opcode != T_MNEM_movs || low_regs; 9440 if (inst.size_req == 4 9441 || inst.operands[1].shifted) 9442 narrow = FALSE; 9443 9444 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ 9445 if (opcode == T_MNEM_movs && inst.operands[1].isreg 9446 && !inst.operands[1].shifted 9447 && inst.operands[0].reg == REG_PC 9448 && inst.operands[1].reg == REG_LR) 9449 { 9450 inst.instruction = T2_SUBS_PC_LR; 9451 return; 9452 } 9453 9454 if (!inst.operands[1].isreg) 9455 { 9456 /* Immediate operand. */ 9457 if (current_it_mask == 0 && opcode == T_MNEM_mov) 9458 narrow = 0; 9459 if (low_regs && narrow) 9460 { 9461 inst.instruction = THUMB_OP16 (opcode); 9462 inst.instruction |= inst.operands[0].reg << 8; 9463 if (inst.size_req == 2) 9464 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9465 else 9466 inst.relax = opcode; 9467 } 9468 else 9469 { 9470 inst.instruction = THUMB_OP32 (inst.instruction); 9471 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9472 inst.instruction |= inst.operands[0].reg << r0off; 9473 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9474 } 9475 } 9476 else if (inst.operands[1].shifted && inst.operands[1].immisreg 9477 && (inst.instruction == T_MNEM_mov 9478 || inst.instruction == T_MNEM_movs)) 9479 { 9480 /* Register shifts are encoded as separate shift instructions. */ 9481 bfd_boolean flags = (inst.instruction == T_MNEM_movs); 9482 9483 if (current_it_mask) 9484 narrow = !flags; 9485 else 9486 narrow = flags; 9487 9488 if (inst.size_req == 4) 9489 narrow = FALSE; 9490 9491 if (!low_regs || inst.operands[1].imm > 7) 9492 narrow = FALSE; 9493 9494 if (inst.operands[0].reg != inst.operands[1].reg) 9495 narrow = FALSE; 9496 9497 switch (inst.operands[1].shift_kind) 9498 { 9499 case SHIFT_LSL: 9500 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); 9501 break; 9502 case SHIFT_ASR: 9503 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); 9504 break; 9505 case SHIFT_LSR: 9506 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); 9507 break; 9508 case SHIFT_ROR: 9509 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); 9510 break; 9511 default: 9512 abort(); 9513 } 9514 9515 inst.instruction = opcode; 9516 if (narrow) 9517 { 9518 inst.instruction |= inst.operands[0].reg; 9519 inst.instruction |= inst.operands[1].imm << 3; 9520 } 9521 else 9522 { 9523 if (flags) 9524 inst.instruction |= CONDS_BIT; 9525 9526 inst.instruction |= inst.operands[0].reg << 8; 9527 inst.instruction |= inst.operands[1].reg << 16; 9528 inst.instruction |= inst.operands[1].imm; 9529 } 9530 } 9531 else if (!narrow) 9532 { 9533 /* Some mov with immediate shift have narrow variants. 9534 Register shifts are handled above. */ 9535 if (low_regs && inst.operands[1].shifted 9536 && (inst.instruction == T_MNEM_mov 9537 || inst.instruction == T_MNEM_movs)) 9538 { 9539 if (current_it_mask) 9540 narrow = (inst.instruction == T_MNEM_mov); 9541 else 9542 narrow = (inst.instruction == T_MNEM_movs); 9543 } 9544 9545 if (narrow) 9546 { 9547 switch (inst.operands[1].shift_kind) 9548 { 9549 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 9550 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 9551 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 9552 default: narrow = FALSE; break; 9553 } 9554 } 9555 9556 if (narrow) 9557 { 9558 inst.instruction |= inst.operands[0].reg; 9559 inst.instruction |= inst.operands[1].reg << 3; 9560 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 9561 } 9562 else 9563 { 9564 inst.instruction = THUMB_OP32 (inst.instruction); 9565 inst.instruction |= inst.operands[0].reg << r0off; 9566 encode_thumb32_shifted_operand (1); 9567 } 9568 } 9569 else 9570 switch (inst.instruction) 9571 { 9572 case T_MNEM_mov: 9573 inst.instruction = T_OPCODE_MOV_HR; 9574 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9575 inst.instruction |= (inst.operands[0].reg & 0x7); 9576 inst.instruction |= inst.operands[1].reg << 3; 9577 break; 9578 9579 case T_MNEM_movs: 9580 /* We know we have low registers at this point. 9581 Generate ADD Rd, Rs, #0. */ 9582 inst.instruction = T_OPCODE_ADD_I3; 9583 inst.instruction |= inst.operands[0].reg; 9584 inst.instruction |= inst.operands[1].reg << 3; 9585 break; 9586 9587 case T_MNEM_cmp: 9588 if (low_regs) 9589 { 9590 inst.instruction = T_OPCODE_CMP_LR; 9591 inst.instruction |= inst.operands[0].reg; 9592 inst.instruction |= inst.operands[1].reg << 3; 9593 } 9594 else 9595 { 9596 inst.instruction = T_OPCODE_CMP_HR; 9597 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9598 inst.instruction |= (inst.operands[0].reg & 0x7); 9599 inst.instruction |= inst.operands[1].reg << 3; 9600 } 9601 break; 9602 } 9603 return; 9604 } 9605 9606 inst.instruction = THUMB_OP16 (inst.instruction); 9607 if (inst.operands[1].isreg) 9608 { 9609 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) 9610 { 9611 /* A move of two lowregs is encoded as ADD Rd, Rs, #0 9612 since a MOV instruction produces unpredictable results. */ 9613 if (inst.instruction == T_OPCODE_MOV_I8) 9614 inst.instruction = T_OPCODE_ADD_I3; 9615 else 9616 inst.instruction = T_OPCODE_CMP_LR; 9617 9618 inst.instruction |= inst.operands[0].reg; 9619 inst.instruction |= inst.operands[1].reg << 3; 9620 } 9621 else 9622 { 9623 if (inst.instruction == T_OPCODE_MOV_I8) 9624 inst.instruction = T_OPCODE_MOV_HR; 9625 else 9626 inst.instruction = T_OPCODE_CMP_HR; 9627 do_t_cpy (); 9628 } 9629 } 9630 else 9631 { 9632 constraint (inst.operands[0].reg > 7, 9633 _("only lo regs allowed with immediate")); 9634 inst.instruction |= inst.operands[0].reg << 8; 9635 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9636 } 9637} 9638 9639static void 9640do_t_mov16 (void) 9641{ 9642 bfd_vma imm; 9643 bfd_boolean top; 9644 9645 top = (inst.instruction & 0x00800000) != 0; 9646 if (inst.reloc.type == BFD_RELOC_ARM_MOVW) 9647 { 9648 constraint (top, _(":lower16: not allowed this instruction")); 9649 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; 9650 } 9651 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) 9652 { 9653 constraint (!top, _(":upper16: not allowed this instruction")); 9654 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; 9655 } 9656 9657 inst.instruction |= inst.operands[0].reg << 8; 9658 if (inst.reloc.type == BFD_RELOC_UNUSED) 9659 { 9660 imm = inst.reloc.exp.X_add_number; 9661 inst.instruction |= (imm & 0xf000) << 4; 9662 inst.instruction |= (imm & 0x0800) << 15; 9663 inst.instruction |= (imm & 0x0700) << 4; 9664 inst.instruction |= (imm & 0x00ff); 9665 } 9666} 9667 9668static void 9669do_t_mvn_tst (void) 9670{ 9671 if (unified_syntax) 9672 { 9673 int r0off = (inst.instruction == T_MNEM_mvn 9674 || inst.instruction == T_MNEM_mvns) ? 8 : 16; 9675 bfd_boolean narrow; 9676 9677 if (inst.size_req == 4 9678 || inst.instruction > 0xffff 9679 || inst.operands[1].shifted 9680 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9681 narrow = FALSE; 9682 else if (inst.instruction == T_MNEM_cmn) 9683 narrow = TRUE; 9684 else if (THUMB_SETS_FLAGS (inst.instruction)) 9685 narrow = (current_it_mask == 0); 9686 else 9687 narrow = (current_it_mask != 0); 9688 9689 if (!inst.operands[1].isreg) 9690 { 9691 /* For an immediate, we always generate a 32-bit opcode; 9692 section relaxation will shrink it later if possible. */ 9693 if (inst.instruction < 0xffff) 9694 inst.instruction = THUMB_OP32 (inst.instruction); 9695 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9696 inst.instruction |= inst.operands[0].reg << r0off; 9697 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9698 } 9699 else 9700 { 9701 /* See if we can do this with a 16-bit instruction. */ 9702 if (narrow) 9703 { 9704 inst.instruction = THUMB_OP16 (inst.instruction); 9705 inst.instruction |= inst.operands[0].reg; 9706 inst.instruction |= inst.operands[1].reg << 3; 9707 } 9708 else 9709 { 9710 constraint (inst.operands[1].shifted 9711 && inst.operands[1].immisreg, 9712 _("shift must be constant")); 9713 if (inst.instruction < 0xffff) 9714 inst.instruction = THUMB_OP32 (inst.instruction); 9715 inst.instruction |= inst.operands[0].reg << r0off; 9716 encode_thumb32_shifted_operand (1); 9717 } 9718 } 9719 } 9720 else 9721 { 9722 constraint (inst.instruction > 0xffff 9723 || inst.instruction == T_MNEM_mvns, BAD_THUMB32); 9724 constraint (!inst.operands[1].isreg || inst.operands[1].shifted, 9725 _("unshifted register required")); 9726 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9727 BAD_HIREG); 9728 9729 inst.instruction = THUMB_OP16 (inst.instruction); 9730 inst.instruction |= inst.operands[0].reg; 9731 inst.instruction |= inst.operands[1].reg << 3; 9732 } 9733} 9734 9735static void 9736do_t_mrs (void) 9737{ 9738 int flags; 9739 9740 if (do_vfp_nsyn_mrs () == SUCCESS) 9741 return; 9742 9743 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); 9744 if (flags == 0) 9745 { 9746 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9747 _("selected processor does not support " 9748 "requested special purpose register")); 9749 } 9750 else 9751 { 9752 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9753 _("selected processor does not support " 9754 "requested special purpose register %x")); 9755 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 9756 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), 9757 _("'CPSR' or 'SPSR' expected")); 9758 } 9759 9760 inst.instruction |= inst.operands[0].reg << 8; 9761 inst.instruction |= (flags & SPSR_BIT) >> 2; 9762 inst.instruction |= inst.operands[1].imm & 0xff; 9763} 9764 9765static void 9766do_t_msr (void) 9767{ 9768 int flags; 9769 9770 if (do_vfp_nsyn_msr () == SUCCESS) 9771 return; 9772 9773 constraint (!inst.operands[1].isreg, 9774 _("Thumb encoding does not support an immediate here")); 9775 flags = inst.operands[0].imm; 9776 if (flags & ~0xff) 9777 { 9778 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9779 _("selected processor does not support " 9780 "requested special purpose register")); 9781 } 9782 else 9783 { 9784 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9785 _("selected processor does not support " 9786 "requested special purpose register")); 9787 flags |= PSR_f; 9788 } 9789 inst.instruction |= (flags & SPSR_BIT) >> 2; 9790 inst.instruction |= (flags & ~SPSR_BIT) >> 8; 9791 inst.instruction |= (flags & 0xff); 9792 inst.instruction |= inst.operands[1].reg << 16; 9793} 9794 9795static void 9796do_t_mul (void) 9797{ 9798 if (!inst.operands[2].present) 9799 inst.operands[2].reg = inst.operands[0].reg; 9800 9801 /* There is no 32-bit MULS and no 16-bit MUL. */ 9802 if (unified_syntax && inst.instruction == T_MNEM_mul) 9803 { 9804 inst.instruction = THUMB_OP32 (inst.instruction); 9805 inst.instruction |= inst.operands[0].reg << 8; 9806 inst.instruction |= inst.operands[1].reg << 16; 9807 inst.instruction |= inst.operands[2].reg << 0; 9808 } 9809 else 9810 { 9811 constraint (!unified_syntax 9812 && inst.instruction == T_MNEM_muls, BAD_THUMB32); 9813 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9814 BAD_HIREG); 9815 9816 inst.instruction = THUMB_OP16 (inst.instruction); 9817 inst.instruction |= inst.operands[0].reg; 9818 9819 if (inst.operands[0].reg == inst.operands[1].reg) 9820 inst.instruction |= inst.operands[2].reg << 3; 9821 else if (inst.operands[0].reg == inst.operands[2].reg) 9822 inst.instruction |= inst.operands[1].reg << 3; 9823 else 9824 constraint (1, _("dest must overlap one source register")); 9825 } 9826} 9827 9828static void 9829do_t_mull (void) 9830{ 9831 inst.instruction |= inst.operands[0].reg << 12; 9832 inst.instruction |= inst.operands[1].reg << 8; 9833 inst.instruction |= inst.operands[2].reg << 16; 9834 inst.instruction |= inst.operands[3].reg; 9835 9836 if (inst.operands[0].reg == inst.operands[1].reg) 9837 as_tsktsk (_("rdhi and rdlo must be different")); 9838} 9839 9840static void 9841do_t_nop (void) 9842{ 9843 if (unified_syntax) 9844 { 9845 if (inst.size_req == 4 || inst.operands[0].imm > 15) 9846 { 9847 inst.instruction = THUMB_OP32 (inst.instruction); 9848 inst.instruction |= inst.operands[0].imm; 9849 } 9850 else 9851 { 9852 inst.instruction = THUMB_OP16 (inst.instruction); 9853 inst.instruction |= inst.operands[0].imm << 4; 9854 } 9855 } 9856 else 9857 { 9858 constraint (inst.operands[0].present, 9859 _("Thumb does not support NOP with hints")); 9860 inst.instruction = 0x46c0; 9861 } 9862} 9863 9864static void 9865do_t_neg (void) 9866{ 9867 if (unified_syntax) 9868 { 9869 bfd_boolean narrow; 9870 9871 if (THUMB_SETS_FLAGS (inst.instruction)) 9872 narrow = (current_it_mask == 0); 9873 else 9874 narrow = (current_it_mask != 0); 9875 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9876 narrow = FALSE; 9877 if (inst.size_req == 4) 9878 narrow = FALSE; 9879 9880 if (!narrow) 9881 { 9882 inst.instruction = THUMB_OP32 (inst.instruction); 9883 inst.instruction |= inst.operands[0].reg << 8; 9884 inst.instruction |= inst.operands[1].reg << 16; 9885 } 9886 else 9887 { 9888 inst.instruction = THUMB_OP16 (inst.instruction); 9889 inst.instruction |= inst.operands[0].reg; 9890 inst.instruction |= inst.operands[1].reg << 3; 9891 } 9892 } 9893 else 9894 { 9895 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9896 BAD_HIREG); 9897 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 9898 9899 inst.instruction = THUMB_OP16 (inst.instruction); 9900 inst.instruction |= inst.operands[0].reg; 9901 inst.instruction |= inst.operands[1].reg << 3; 9902 } 9903} 9904 9905static void 9906do_t_pkhbt (void) 9907{ 9908 inst.instruction |= inst.operands[0].reg << 8; 9909 inst.instruction |= inst.operands[1].reg << 16; 9910 inst.instruction |= inst.operands[2].reg; 9911 if (inst.operands[3].present) 9912 { 9913 unsigned int val = inst.reloc.exp.X_add_number; 9914 constraint (inst.reloc.exp.X_op != O_constant, 9915 _("expression too complex")); 9916 inst.instruction |= (val & 0x1c) << 10; 9917 inst.instruction |= (val & 0x03) << 6; 9918 } 9919} 9920 9921static void 9922do_t_pkhtb (void) 9923{ 9924 if (!inst.operands[3].present) 9925 inst.instruction &= ~0x00000020; 9926 do_t_pkhbt (); 9927} 9928 9929static void 9930do_t_pld (void) 9931{ 9932 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); 9933} 9934 9935static void 9936do_t_push_pop (void) 9937{ 9938 unsigned mask; 9939 9940 constraint (inst.operands[0].writeback, 9941 _("push/pop do not support {reglist}^")); 9942 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 9943 _("expression too complex")); 9944 9945 mask = inst.operands[0].imm; 9946 if ((mask & ~0xff) == 0) 9947 inst.instruction = THUMB_OP16 (inst.instruction) | mask; 9948 else if ((inst.instruction == T_MNEM_push 9949 && (mask & ~0xff) == 1 << REG_LR) 9950 || (inst.instruction == T_MNEM_pop 9951 && (mask & ~0xff) == 1 << REG_PC)) 9952 { 9953 inst.instruction = THUMB_OP16 (inst.instruction); 9954 inst.instruction |= THUMB_PP_PC_LR; 9955 inst.instruction |= mask & 0xff; 9956 } 9957 else if (unified_syntax) 9958 { 9959 inst.instruction = THUMB_OP32 (inst.instruction); 9960 encode_thumb2_ldmstm(13, mask, TRUE); 9961 } 9962 else 9963 { 9964 inst.error = _("invalid register list to push/pop instruction"); 9965 return; 9966 } 9967} 9968 9969static void 9970do_t_rbit (void) 9971{ 9972 inst.instruction |= inst.operands[0].reg << 8; 9973 inst.instruction |= inst.operands[1].reg << 16; 9974} 9975 9976static void 9977do_t_rev (void) 9978{ 9979 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 9980 && inst.size_req != 4) 9981 { 9982 inst.instruction = THUMB_OP16 (inst.instruction); 9983 inst.instruction |= inst.operands[0].reg; 9984 inst.instruction |= inst.operands[1].reg << 3; 9985 } 9986 else if (unified_syntax) 9987 { 9988 inst.instruction = THUMB_OP32 (inst.instruction); 9989 inst.instruction |= inst.operands[0].reg << 8; 9990 inst.instruction |= inst.operands[1].reg << 16; 9991 inst.instruction |= inst.operands[1].reg; 9992 } 9993 else 9994 inst.error = BAD_HIREG; 9995} 9996 9997static void 9998do_t_rsb (void) 9999{ 10000 int Rd, Rs; 10001 10002 Rd = inst.operands[0].reg; 10003 Rs = (inst.operands[1].present 10004 ? inst.operands[1].reg /* Rd, Rs, foo */ 10005 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 10006 10007 inst.instruction |= Rd << 8; 10008 inst.instruction |= Rs << 16; 10009 if (!inst.operands[2].isreg) 10010 { 10011 bfd_boolean narrow; 10012 10013 if ((inst.instruction & 0x00100000) != 0) 10014 narrow = (current_it_mask == 0); 10015 else 10016 narrow = (current_it_mask != 0); 10017 10018 if (Rd > 7 || Rs > 7) 10019 narrow = FALSE; 10020 10021 if (inst.size_req == 4 || !unified_syntax) 10022 narrow = FALSE; 10023 10024 if (inst.reloc.exp.X_op != O_constant 10025 || inst.reloc.exp.X_add_number != 0) 10026 narrow = FALSE; 10027 10028 /* Turn rsb #0 into 16-bit neg. We should probably do this via 10029 relaxation, but it doesn't seem worth the hassle. */ 10030 if (narrow) 10031 { 10032 inst.reloc.type = BFD_RELOC_UNUSED; 10033 inst.instruction = THUMB_OP16 (T_MNEM_negs); 10034 inst.instruction |= Rs << 3; 10035 inst.instruction |= Rd; 10036 } 10037 else 10038 { 10039 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 10040 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 10041 } 10042 } 10043 else 10044 encode_thumb32_shifted_operand (2); 10045} 10046 10047static void 10048do_t_setend (void) 10049{ 10050 constraint (current_it_mask, BAD_NOT_IT); 10051 if (inst.operands[0].imm) 10052 inst.instruction |= 0x8; 10053} 10054 10055static void 10056do_t_shift (void) 10057{ 10058 if (!inst.operands[1].present) 10059 inst.operands[1].reg = inst.operands[0].reg; 10060 10061 if (unified_syntax) 10062 { 10063 bfd_boolean narrow; 10064 int shift_kind; 10065 10066 switch (inst.instruction) 10067 { 10068 case T_MNEM_asr: 10069 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; 10070 case T_MNEM_lsl: 10071 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; 10072 case T_MNEM_lsr: 10073 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; 10074 case T_MNEM_ror: 10075 case T_MNEM_rors: shift_kind = SHIFT_ROR; break; 10076 default: abort (); 10077 } 10078 10079 if (THUMB_SETS_FLAGS (inst.instruction)) 10080 narrow = (current_it_mask == 0); 10081 else 10082 narrow = (current_it_mask != 0); 10083 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 10084 narrow = FALSE; 10085 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) 10086 narrow = FALSE; 10087 if (inst.operands[2].isreg 10088 && (inst.operands[1].reg != inst.operands[0].reg 10089 || inst.operands[2].reg > 7)) 10090 narrow = FALSE; 10091 if (inst.size_req == 4) 10092 narrow = FALSE; 10093 10094 if (!narrow) 10095 { 10096 if (inst.operands[2].isreg) 10097 { 10098 inst.instruction = THUMB_OP32 (inst.instruction); 10099 inst.instruction |= inst.operands[0].reg << 8; 10100 inst.instruction |= inst.operands[1].reg << 16; 10101 inst.instruction |= inst.operands[2].reg; 10102 } 10103 else 10104 { 10105 inst.operands[1].shifted = 1; 10106 inst.operands[1].shift_kind = shift_kind; 10107 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) 10108 ? T_MNEM_movs : T_MNEM_mov); 10109 inst.instruction |= inst.operands[0].reg << 8; 10110 encode_thumb32_shifted_operand (1); 10111 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ 10112 inst.reloc.type = BFD_RELOC_UNUSED; 10113 } 10114 } 10115 else 10116 { 10117 if (inst.operands[2].isreg) 10118 { 10119 switch (shift_kind) 10120 { 10121 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; 10122 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; 10123 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; 10124 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; 10125 default: abort (); 10126 } 10127 10128 inst.instruction |= inst.operands[0].reg; 10129 inst.instruction |= inst.operands[2].reg << 3; 10130 } 10131 else 10132 { 10133 switch (shift_kind) 10134 { 10135 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 10136 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 10137 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 10138 default: abort (); 10139 } 10140 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10141 inst.instruction |= inst.operands[0].reg; 10142 inst.instruction |= inst.operands[1].reg << 3; 10143 } 10144 } 10145 } 10146 else 10147 { 10148 constraint (inst.operands[0].reg > 7 10149 || inst.operands[1].reg > 7, BAD_HIREG); 10150 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 10151 10152 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ 10153 { 10154 constraint (inst.operands[2].reg > 7, BAD_HIREG); 10155 constraint (inst.operands[0].reg != inst.operands[1].reg, 10156 _("source1 and dest must be same register")); 10157 10158 switch (inst.instruction) 10159 { 10160 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; 10161 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; 10162 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; 10163 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; 10164 default: abort (); 10165 } 10166 10167 inst.instruction |= inst.operands[0].reg; 10168 inst.instruction |= inst.operands[2].reg << 3; 10169 } 10170 else 10171 { 10172 switch (inst.instruction) 10173 { 10174 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; 10175 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; 10176 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; 10177 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; 10178 default: abort (); 10179 } 10180 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10181 inst.instruction |= inst.operands[0].reg; 10182 inst.instruction |= inst.operands[1].reg << 3; 10183 } 10184 } 10185} 10186 10187static void 10188do_t_simd (void) 10189{ 10190 inst.instruction |= inst.operands[0].reg << 8; 10191 inst.instruction |= inst.operands[1].reg << 16; 10192 inst.instruction |= inst.operands[2].reg; 10193} 10194 10195static void 10196do_t_smc (void) 10197{ 10198 unsigned int value = inst.reloc.exp.X_add_number; 10199 constraint (inst.reloc.exp.X_op != O_constant, 10200 _("expression too complex")); 10201 inst.reloc.type = BFD_RELOC_UNUSED; 10202 inst.instruction |= (value & 0xf000) >> 12; 10203 inst.instruction |= (value & 0x0ff0); 10204 inst.instruction |= (value & 0x000f) << 16; 10205} 10206 10207static void 10208do_t_ssat (void) 10209{ 10210 inst.instruction |= inst.operands[0].reg << 8; 10211 inst.instruction |= inst.operands[1].imm - 1; 10212 inst.instruction |= inst.operands[2].reg << 16; 10213 10214 if (inst.operands[3].present) 10215 { 10216 constraint (inst.reloc.exp.X_op != O_constant, 10217 _("expression too complex")); 10218 10219 if (inst.reloc.exp.X_add_number != 0) 10220 { 10221 if (inst.operands[3].shift_kind == SHIFT_ASR) 10222 inst.instruction |= 0x00200000; /* sh bit */ 10223 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10224 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10225 } 10226 inst.reloc.type = BFD_RELOC_UNUSED; 10227 } 10228} 10229 10230static void 10231do_t_ssat16 (void) 10232{ 10233 inst.instruction |= inst.operands[0].reg << 8; 10234 inst.instruction |= inst.operands[1].imm - 1; 10235 inst.instruction |= inst.operands[2].reg << 16; 10236} 10237 10238static void 10239do_t_strex (void) 10240{ 10241 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 10242 || inst.operands[2].postind || inst.operands[2].writeback 10243 || inst.operands[2].immisreg || inst.operands[2].shifted 10244 || inst.operands[2].negative, 10245 BAD_ADDR_MODE); 10246 10247 inst.instruction |= inst.operands[0].reg << 8; 10248 inst.instruction |= inst.operands[1].reg << 12; 10249 inst.instruction |= inst.operands[2].reg << 16; 10250 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 10251} 10252 10253static void 10254do_t_strexd (void) 10255{ 10256 if (!inst.operands[2].present) 10257 inst.operands[2].reg = inst.operands[1].reg + 1; 10258 10259 constraint (inst.operands[0].reg == inst.operands[1].reg 10260 || inst.operands[0].reg == inst.operands[2].reg 10261 || inst.operands[0].reg == inst.operands[3].reg 10262 || inst.operands[1].reg == inst.operands[2].reg, 10263 BAD_OVERLAP); 10264 10265 inst.instruction |= inst.operands[0].reg; 10266 inst.instruction |= inst.operands[1].reg << 12; 10267 inst.instruction |= inst.operands[2].reg << 8; 10268 inst.instruction |= inst.operands[3].reg << 16; 10269} 10270 10271static void 10272do_t_sxtah (void) 10273{ 10274 inst.instruction |= inst.operands[0].reg << 8; 10275 inst.instruction |= inst.operands[1].reg << 16; 10276 inst.instruction |= inst.operands[2].reg; 10277 inst.instruction |= inst.operands[3].imm << 4; 10278} 10279 10280static void 10281do_t_sxth (void) 10282{ 10283 if (inst.instruction <= 0xffff && inst.size_req != 4 10284 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10285 && (!inst.operands[2].present || inst.operands[2].imm == 0)) 10286 { 10287 inst.instruction = THUMB_OP16 (inst.instruction); 10288 inst.instruction |= inst.operands[0].reg; 10289 inst.instruction |= inst.operands[1].reg << 3; 10290 } 10291 else if (unified_syntax) 10292 { 10293 if (inst.instruction <= 0xffff) 10294 inst.instruction = THUMB_OP32 (inst.instruction); 10295 inst.instruction |= inst.operands[0].reg << 8; 10296 inst.instruction |= inst.operands[1].reg; 10297 inst.instruction |= inst.operands[2].imm << 4; 10298 } 10299 else 10300 { 10301 constraint (inst.operands[2].present && inst.operands[2].imm != 0, 10302 _("Thumb encoding does not support rotation")); 10303 constraint (1, BAD_HIREG); 10304 } 10305} 10306 10307static void 10308do_t_swi (void) 10309{ 10310 inst.reloc.type = BFD_RELOC_ARM_SWI; 10311} 10312 10313static void 10314do_t_tb (void) 10315{ 10316 int half; 10317 10318 half = (inst.instruction & 0x10) != 0; 10319 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 10320 constraint (inst.operands[0].immisreg, 10321 _("instruction requires register index")); 10322 constraint (inst.operands[0].imm == 15, 10323 _("PC is not a valid index register")); 10324 constraint (!half && inst.operands[0].shifted, 10325 _("instruction does not allow shifted index")); 10326 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; 10327} 10328 10329static void 10330do_t_usat (void) 10331{ 10332 inst.instruction |= inst.operands[0].reg << 8; 10333 inst.instruction |= inst.operands[1].imm; 10334 inst.instruction |= inst.operands[2].reg << 16; 10335 10336 if (inst.operands[3].present) 10337 { 10338 constraint (inst.reloc.exp.X_op != O_constant, 10339 _("expression too complex")); 10340 if (inst.reloc.exp.X_add_number != 0) 10341 { 10342 if (inst.operands[3].shift_kind == SHIFT_ASR) 10343 inst.instruction |= 0x00200000; /* sh bit */ 10344 10345 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10346 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10347 } 10348 inst.reloc.type = BFD_RELOC_UNUSED; 10349 } 10350} 10351 10352static void 10353do_t_usat16 (void) 10354{ 10355 inst.instruction |= inst.operands[0].reg << 8; 10356 inst.instruction |= inst.operands[1].imm; 10357 inst.instruction |= inst.operands[2].reg << 16; 10358} 10359 10360/* Neon instruction encoder helpers. */ 10361 10362/* Encodings for the different types for various Neon opcodes. */ 10363 10364/* An "invalid" code for the following tables. */ 10365#define N_INV -1u 10366 10367struct neon_tab_entry 10368{ 10369 unsigned integer; 10370 unsigned float_or_poly; 10371 unsigned scalar_or_imm; 10372}; 10373 10374/* Map overloaded Neon opcodes to their respective encodings. */ 10375#define NEON_ENC_TAB \ 10376 X(vabd, 0x0000700, 0x1200d00, N_INV), \ 10377 X(vmax, 0x0000600, 0x0000f00, N_INV), \ 10378 X(vmin, 0x0000610, 0x0200f00, N_INV), \ 10379 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ 10380 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ 10381 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ 10382 X(vadd, 0x0000800, 0x0000d00, N_INV), \ 10383 X(vsub, 0x1000800, 0x0200d00, N_INV), \ 10384 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ 10385 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ 10386 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ 10387 /* Register variants of the following two instructions are encoded as 10388 vcge / vcgt with the operands reversed. */ \ 10389 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ 10390 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ 10391 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ 10392 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ 10393 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ 10394 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ 10395 X(vmlal, 0x0800800, N_INV, 0x0800240), \ 10396 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ 10397 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ 10398 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ 10399 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ 10400 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ 10401 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ 10402 X(vshl, 0x0000400, N_INV, 0x0800510), \ 10403 X(vqshl, 0x0000410, N_INV, 0x0800710), \ 10404 X(vand, 0x0000110, N_INV, 0x0800030), \ 10405 X(vbic, 0x0100110, N_INV, 0x0800030), \ 10406 X(veor, 0x1000110, N_INV, N_INV), \ 10407 X(vorn, 0x0300110, N_INV, 0x0800010), \ 10408 X(vorr, 0x0200110, N_INV, 0x0800010), \ 10409 X(vmvn, 0x1b00580, N_INV, 0x0800030), \ 10410 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ 10411 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ 10412 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ 10413 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ 10414 X(vst1, 0x0000000, 0x0800000, N_INV), \ 10415 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ 10416 X(vst2, 0x0000100, 0x0800100, N_INV), \ 10417 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ 10418 X(vst3, 0x0000200, 0x0800200, N_INV), \ 10419 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ 10420 X(vst4, 0x0000300, 0x0800300, N_INV), \ 10421 X(vmovn, 0x1b20200, N_INV, N_INV), \ 10422 X(vtrn, 0x1b20080, N_INV, N_INV), \ 10423 X(vqmovn, 0x1b20200, N_INV, N_INV), \ 10424 X(vqmovun, 0x1b20240, N_INV, N_INV), \ 10425 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ 10426 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ 10427 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ 10428 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ 10429 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ 10430 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ 10431 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) 10432 10433enum neon_opc 10434{ 10435#define X(OPC,I,F,S) N_MNEM_##OPC 10436NEON_ENC_TAB 10437#undef X 10438}; 10439 10440static const struct neon_tab_entry neon_enc_tab[] = 10441{ 10442#define X(OPC,I,F,S) { (I), (F), (S) } 10443NEON_ENC_TAB 10444#undef X 10445}; 10446 10447#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10448#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10449#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10450#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10451#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10452#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10453#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10454#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10455#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10456#define NEON_ENC_SINGLE(X) \ 10457 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) 10458#define NEON_ENC_DOUBLE(X) \ 10459 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) 10460 10461/* Define shapes for instruction operands. The following mnemonic characters 10462 are used in this table: 10463 10464 F - VFP S<n> register 10465 D - Neon D<n> register 10466 Q - Neon Q<n> register 10467 I - Immediate 10468 S - Scalar 10469 R - ARM register 10470 L - D<n> register list 10471 10472 This table is used to generate various data: 10473 - enumerations of the form NS_DDR to be used as arguments to 10474 neon_select_shape. 10475 - a table classifying shapes into single, double, quad, mixed. 10476 - a table used to drive neon_select_shape. 10477*/ 10478 10479#define NEON_SHAPE_DEF \ 10480 X(3, (D, D, D), DOUBLE), \ 10481 X(3, (Q, Q, Q), QUAD), \ 10482 X(3, (D, D, I), DOUBLE), \ 10483 X(3, (Q, Q, I), QUAD), \ 10484 X(3, (D, D, S), DOUBLE), \ 10485 X(3, (Q, Q, S), QUAD), \ 10486 X(2, (D, D), DOUBLE), \ 10487 X(2, (Q, Q), QUAD), \ 10488 X(2, (D, S), DOUBLE), \ 10489 X(2, (Q, S), QUAD), \ 10490 X(2, (D, R), DOUBLE), \ 10491 X(2, (Q, R), QUAD), \ 10492 X(2, (D, I), DOUBLE), \ 10493 X(2, (Q, I), QUAD), \ 10494 X(3, (D, L, D), DOUBLE), \ 10495 X(2, (D, Q), MIXED), \ 10496 X(2, (Q, D), MIXED), \ 10497 X(3, (D, Q, I), MIXED), \ 10498 X(3, (Q, D, I), MIXED), \ 10499 X(3, (Q, D, D), MIXED), \ 10500 X(3, (D, Q, Q), MIXED), \ 10501 X(3, (Q, Q, D), MIXED), \ 10502 X(3, (Q, D, S), MIXED), \ 10503 X(3, (D, Q, S), MIXED), \ 10504 X(4, (D, D, D, I), DOUBLE), \ 10505 X(4, (Q, Q, Q, I), QUAD), \ 10506 X(2, (F, F), SINGLE), \ 10507 X(3, (F, F, F), SINGLE), \ 10508 X(2, (F, I), SINGLE), \ 10509 X(2, (F, D), MIXED), \ 10510 X(2, (D, F), MIXED), \ 10511 X(3, (F, F, I), MIXED), \ 10512 X(4, (R, R, F, F), SINGLE), \ 10513 X(4, (F, F, R, R), SINGLE), \ 10514 X(3, (D, R, R), DOUBLE), \ 10515 X(3, (R, R, D), DOUBLE), \ 10516 X(2, (S, R), SINGLE), \ 10517 X(2, (R, S), SINGLE), \ 10518 X(2, (F, R), SINGLE), \ 10519 X(2, (R, F), SINGLE) 10520 10521#define S2(A,B) NS_##A##B 10522#define S3(A,B,C) NS_##A##B##C 10523#define S4(A,B,C,D) NS_##A##B##C##D 10524 10525#define X(N, L, C) S##N L 10526 10527enum neon_shape 10528{ 10529 NEON_SHAPE_DEF, 10530 NS_NULL 10531}; 10532 10533#undef X 10534#undef S2 10535#undef S3 10536#undef S4 10537 10538enum neon_shape_class 10539{ 10540 SC_SINGLE, 10541 SC_DOUBLE, 10542 SC_QUAD, 10543 SC_MIXED 10544}; 10545 10546#define X(N, L, C) SC_##C 10547 10548static enum neon_shape_class neon_shape_class[] = 10549{ 10550 NEON_SHAPE_DEF 10551}; 10552 10553#undef X 10554 10555enum neon_shape_el 10556{ 10557 SE_F, 10558 SE_D, 10559 SE_Q, 10560 SE_I, 10561 SE_S, 10562 SE_R, 10563 SE_L 10564}; 10565 10566/* Register widths of above. */ 10567static unsigned neon_shape_el_size[] = 10568{ 10569 32, 10570 64, 10571 128, 10572 0, 10573 32, 10574 32, 10575 0 10576}; 10577 10578struct neon_shape_info 10579{ 10580 unsigned els; 10581 enum neon_shape_el el[NEON_MAX_TYPE_ELS]; 10582}; 10583 10584#define S2(A,B) { SE_##A, SE_##B } 10585#define S3(A,B,C) { SE_##A, SE_##B, SE_##C } 10586#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } 10587 10588#define X(N, L, C) { N, S##N L } 10589 10590static struct neon_shape_info neon_shape_tab[] = 10591{ 10592 NEON_SHAPE_DEF 10593}; 10594 10595#undef X 10596#undef S2 10597#undef S3 10598#undef S4 10599 10600/* Bit masks used in type checking given instructions. 10601 'N_EQK' means the type must be the same as (or based on in some way) the key 10602 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is 10603 set, various other bits can be set as well in order to modify the meaning of 10604 the type constraint. */ 10605 10606enum neon_type_mask 10607{ 10608 N_S8 = 0x000001, 10609 N_S16 = 0x000002, 10610 N_S32 = 0x000004, 10611 N_S64 = 0x000008, 10612 N_U8 = 0x000010, 10613 N_U16 = 0x000020, 10614 N_U32 = 0x000040, 10615 N_U64 = 0x000080, 10616 N_I8 = 0x000100, 10617 N_I16 = 0x000200, 10618 N_I32 = 0x000400, 10619 N_I64 = 0x000800, 10620 N_8 = 0x001000, 10621 N_16 = 0x002000, 10622 N_32 = 0x004000, 10623 N_64 = 0x008000, 10624 N_P8 = 0x010000, 10625 N_P16 = 0x020000, 10626 N_F32 = 0x040000, 10627 N_F64 = 0x080000, 10628 N_KEY = 0x100000, /* key element (main type specifier). */ 10629 N_EQK = 0x200000, /* given operand has the same type & size as the key. */ 10630 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */ 10631 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */ 10632 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */ 10633 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */ 10634 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */ 10635 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */ 10636 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */ 10637 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */ 10638 N_UTYP = 0, 10639 N_MAX_NONSPECIAL = N_F64 10640}; 10641 10642#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) 10643 10644#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) 10645#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) 10646#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) 10647#define N_SUF_32 (N_SU_32 | N_F32) 10648#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) 10649#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) 10650 10651/* Pass this as the first type argument to neon_check_type to ignore types 10652 altogether. */ 10653#define N_IGNORE_TYPE (N_KEY | N_EQK) 10654 10655/* Select a "shape" for the current instruction (describing register types or 10656 sizes) from a list of alternatives. Return NS_NULL if the current instruction 10657 doesn't fit. For non-polymorphic shapes, checking is usually done as a 10658 function of operand parsing, so this function doesn't need to be called. 10659 Shapes should be listed in order of decreasing length. */ 10660 10661static enum neon_shape 10662neon_select_shape (enum neon_shape shape, ...) 10663{ 10664 va_list ap; 10665 enum neon_shape first_shape = shape; 10666 10667 /* Fix missing optional operands. FIXME: we don't know at this point how 10668 many arguments we should have, so this makes the assumption that we have 10669 > 1. This is true of all current Neon opcodes, I think, but may not be 10670 true in the future. */ 10671 if (!inst.operands[1].present) 10672 inst.operands[1] = inst.operands[0]; 10673 10674 va_start (ap, shape); 10675 10676 for (; shape != NS_NULL; shape = va_arg (ap, int)) 10677 { 10678 unsigned j; 10679 int matches = 1; 10680 10681 for (j = 0; j < neon_shape_tab[shape].els; j++) 10682 { 10683 if (!inst.operands[j].present) 10684 { 10685 matches = 0; 10686 break; 10687 } 10688 10689 switch (neon_shape_tab[shape].el[j]) 10690 { 10691 case SE_F: 10692 if (!(inst.operands[j].isreg 10693 && inst.operands[j].isvec 10694 && inst.operands[j].issingle 10695 && !inst.operands[j].isquad)) 10696 matches = 0; 10697 break; 10698 10699 case SE_D: 10700 if (!(inst.operands[j].isreg 10701 && inst.operands[j].isvec 10702 && !inst.operands[j].isquad 10703 && !inst.operands[j].issingle)) 10704 matches = 0; 10705 break; 10706 10707 case SE_R: 10708 if (!(inst.operands[j].isreg 10709 && !inst.operands[j].isvec)) 10710 matches = 0; 10711 break; 10712 10713 case SE_Q: 10714 if (!(inst.operands[j].isreg 10715 && inst.operands[j].isvec 10716 && inst.operands[j].isquad 10717 && !inst.operands[j].issingle)) 10718 matches = 0; 10719 break; 10720 10721 case SE_I: 10722 if (!(!inst.operands[j].isreg 10723 && !inst.operands[j].isscalar)) 10724 matches = 0; 10725 break; 10726 10727 case SE_S: 10728 if (!(!inst.operands[j].isreg 10729 && inst.operands[j].isscalar)) 10730 matches = 0; 10731 break; 10732 10733 case SE_L: 10734 break; 10735 } 10736 } 10737 if (matches) 10738 break; 10739 } 10740 10741 va_end (ap); 10742 10743 if (shape == NS_NULL && first_shape != NS_NULL) 10744 first_error (_("invalid instruction shape")); 10745 10746 return shape; 10747} 10748 10749/* True if SHAPE is predominantly a quadword operation (most of the time, this 10750 means the Q bit should be set). */ 10751 10752static int 10753neon_quad (enum neon_shape shape) 10754{ 10755 return neon_shape_class[shape] == SC_QUAD; 10756} 10757 10758static void 10759neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, 10760 unsigned *g_size) 10761{ 10762 /* Allow modification to be made to types which are constrained to be 10763 based on the key element, based on bits set alongside N_EQK. */ 10764 if ((typebits & N_EQK) != 0) 10765 { 10766 if ((typebits & N_HLF) != 0) 10767 *g_size /= 2; 10768 else if ((typebits & N_DBL) != 0) 10769 *g_size *= 2; 10770 if ((typebits & N_SGN) != 0) 10771 *g_type = NT_signed; 10772 else if ((typebits & N_UNS) != 0) 10773 *g_type = NT_unsigned; 10774 else if ((typebits & N_INT) != 0) 10775 *g_type = NT_integer; 10776 else if ((typebits & N_FLT) != 0) 10777 *g_type = NT_float; 10778 else if ((typebits & N_SIZ) != 0) 10779 *g_type = NT_untyped; 10780 } 10781} 10782 10783/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" 10784 operand type, i.e. the single type specified in a Neon instruction when it 10785 is the only one given. */ 10786 10787static struct neon_type_el 10788neon_type_promote (struct neon_type_el *key, unsigned thisarg) 10789{ 10790 struct neon_type_el dest = *key; 10791 10792 assert ((thisarg & N_EQK) != 0); 10793 10794 neon_modify_type_size (thisarg, &dest.type, &dest.size); 10795 10796 return dest; 10797} 10798 10799/* Convert Neon type and size into compact bitmask representation. */ 10800 10801static enum neon_type_mask 10802type_chk_of_el_type (enum neon_el_type type, unsigned size) 10803{ 10804 switch (type) 10805 { 10806 case NT_untyped: 10807 switch (size) 10808 { 10809 case 8: return N_8; 10810 case 16: return N_16; 10811 case 32: return N_32; 10812 case 64: return N_64; 10813 default: ; 10814 } 10815 break; 10816 10817 case NT_integer: 10818 switch (size) 10819 { 10820 case 8: return N_I8; 10821 case 16: return N_I16; 10822 case 32: return N_I32; 10823 case 64: return N_I64; 10824 default: ; 10825 } 10826 break; 10827 10828 case NT_float: 10829 switch (size) 10830 { 10831 case 32: return N_F32; 10832 case 64: return N_F64; 10833 default: ; 10834 } 10835 break; 10836 10837 case NT_poly: 10838 switch (size) 10839 { 10840 case 8: return N_P8; 10841 case 16: return N_P16; 10842 default: ; 10843 } 10844 break; 10845 10846 case NT_signed: 10847 switch (size) 10848 { 10849 case 8: return N_S8; 10850 case 16: return N_S16; 10851 case 32: return N_S32; 10852 case 64: return N_S64; 10853 default: ; 10854 } 10855 break; 10856 10857 case NT_unsigned: 10858 switch (size) 10859 { 10860 case 8: return N_U8; 10861 case 16: return N_U16; 10862 case 32: return N_U32; 10863 case 64: return N_U64; 10864 default: ; 10865 } 10866 break; 10867 10868 default: ; 10869 } 10870 10871 return N_UTYP; 10872} 10873 10874/* Convert compact Neon bitmask type representation to a type and size. Only 10875 handles the case where a single bit is set in the mask. */ 10876 10877static int 10878el_type_of_type_chk (enum neon_el_type *type, unsigned *size, 10879 enum neon_type_mask mask) 10880{ 10881 if ((mask & N_EQK) != 0) 10882 return FAIL; 10883 10884 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) 10885 *size = 8; 10886 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) 10887 *size = 16; 10888 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) 10889 *size = 32; 10890 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) 10891 *size = 64; 10892 else 10893 return FAIL; 10894 10895 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) 10896 *type = NT_signed; 10897 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) 10898 *type = NT_unsigned; 10899 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) 10900 *type = NT_integer; 10901 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) 10902 *type = NT_untyped; 10903 else if ((mask & (N_P8 | N_P16)) != 0) 10904 *type = NT_poly; 10905 else if ((mask & (N_F32 | N_F64)) != 0) 10906 *type = NT_float; 10907 else 10908 return FAIL; 10909 10910 return SUCCESS; 10911} 10912 10913/* Modify a bitmask of allowed types. This is only needed for type 10914 relaxation. */ 10915 10916static unsigned 10917modify_types_allowed (unsigned allowed, unsigned mods) 10918{ 10919 unsigned size; 10920 enum neon_el_type type; 10921 unsigned destmask; 10922 int i; 10923 10924 destmask = 0; 10925 10926 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) 10927 { 10928 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) 10929 { 10930 neon_modify_type_size (mods, &type, &size); 10931 destmask |= type_chk_of_el_type (type, size); 10932 } 10933 } 10934 10935 return destmask; 10936} 10937 10938/* Check type and return type classification. 10939 The manual states (paraphrase): If one datatype is given, it indicates the 10940 type given in: 10941 - the second operand, if there is one 10942 - the operand, if there is no second operand 10943 - the result, if there are no operands. 10944 This isn't quite good enough though, so we use a concept of a "key" datatype 10945 which is set on a per-instruction basis, which is the one which matters when 10946 only one data type is written. 10947 Note: this function has side-effects (e.g. filling in missing operands). All 10948 Neon instructions should call it before performing bit encoding. */ 10949 10950static struct neon_type_el 10951neon_check_type (unsigned els, enum neon_shape ns, ...) 10952{ 10953 va_list ap; 10954 unsigned i, pass, key_el = 0; 10955 unsigned types[NEON_MAX_TYPE_ELS]; 10956 enum neon_el_type k_type = NT_invtype; 10957 unsigned k_size = -1u; 10958 struct neon_type_el badtype = {NT_invtype, -1}; 10959 unsigned key_allowed = 0; 10960 10961 /* Optional registers in Neon instructions are always (not) in operand 1. 10962 Fill in the missing operand here, if it was omitted. */ 10963 if (els > 1 && !inst.operands[1].present) 10964 inst.operands[1] = inst.operands[0]; 10965 10966 /* Suck up all the varargs. */ 10967 va_start (ap, ns); 10968 for (i = 0; i < els; i++) 10969 { 10970 unsigned thisarg = va_arg (ap, unsigned); 10971 if (thisarg == N_IGNORE_TYPE) 10972 { 10973 va_end (ap); 10974 return badtype; 10975 } 10976 types[i] = thisarg; 10977 if ((thisarg & N_KEY) != 0) 10978 key_el = i; 10979 } 10980 va_end (ap); 10981 10982 if (inst.vectype.elems > 0) 10983 for (i = 0; i < els; i++) 10984 if (inst.operands[i].vectype.type != NT_invtype) 10985 { 10986 first_error (_("types specified in both the mnemonic and operands")); 10987 return badtype; 10988 } 10989 10990 /* Duplicate inst.vectype elements here as necessary. 10991 FIXME: No idea if this is exactly the same as the ARM assembler, 10992 particularly when an insn takes one register and one non-register 10993 operand. */ 10994 if (inst.vectype.elems == 1 && els > 1) 10995 { 10996 unsigned j; 10997 inst.vectype.elems = els; 10998 inst.vectype.el[key_el] = inst.vectype.el[0]; 10999 for (j = 0; j < els; j++) 11000 if (j != key_el) 11001 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11002 types[j]); 11003 } 11004 else if (inst.vectype.elems == 0 && els > 0) 11005 { 11006 unsigned j; 11007 /* No types were given after the mnemonic, so look for types specified 11008 after each operand. We allow some flexibility here; as long as the 11009 "key" operand has a type, we can infer the others. */ 11010 for (j = 0; j < els; j++) 11011 if (inst.operands[j].vectype.type != NT_invtype) 11012 inst.vectype.el[j] = inst.operands[j].vectype; 11013 11014 if (inst.operands[key_el].vectype.type != NT_invtype) 11015 { 11016 for (j = 0; j < els; j++) 11017 if (inst.operands[j].vectype.type == NT_invtype) 11018 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11019 types[j]); 11020 } 11021 else 11022 { 11023 first_error (_("operand types can't be inferred")); 11024 return badtype; 11025 } 11026 } 11027 else if (inst.vectype.elems != els) 11028 { 11029 first_error (_("type specifier has the wrong number of parts")); 11030 return badtype; 11031 } 11032 11033 for (pass = 0; pass < 2; pass++) 11034 { 11035 for (i = 0; i < els; i++) 11036 { 11037 unsigned thisarg = types[i]; 11038 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) 11039 ? modify_types_allowed (key_allowed, thisarg) : thisarg; 11040 enum neon_el_type g_type = inst.vectype.el[i].type; 11041 unsigned g_size = inst.vectype.el[i].size; 11042 11043 /* Decay more-specific signed & unsigned types to sign-insensitive 11044 integer types if sign-specific variants are unavailable. */ 11045 if ((g_type == NT_signed || g_type == NT_unsigned) 11046 && (types_allowed & N_SU_ALL) == 0) 11047 g_type = NT_integer; 11048 11049 /* If only untyped args are allowed, decay any more specific types to 11050 them. Some instructions only care about signs for some element 11051 sizes, so handle that properly. */ 11052 if ((g_size == 8 && (types_allowed & N_8) != 0) 11053 || (g_size == 16 && (types_allowed & N_16) != 0) 11054 || (g_size == 32 && (types_allowed & N_32) != 0) 11055 || (g_size == 64 && (types_allowed & N_64) != 0)) 11056 g_type = NT_untyped; 11057 11058 if (pass == 0) 11059 { 11060 if ((thisarg & N_KEY) != 0) 11061 { 11062 k_type = g_type; 11063 k_size = g_size; 11064 key_allowed = thisarg & ~N_KEY; 11065 } 11066 } 11067 else 11068 { 11069 if ((thisarg & N_VFP) != 0) 11070 { 11071 enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; 11072 unsigned regwidth = neon_shape_el_size[regshape], match; 11073 11074 /* In VFP mode, operands must match register widths. If we 11075 have a key operand, use its width, else use the width of 11076 the current operand. */ 11077 if (k_size != -1u) 11078 match = k_size; 11079 else 11080 match = g_size; 11081 11082 if (regwidth != match) 11083 { 11084 first_error (_("operand size must match register width")); 11085 return badtype; 11086 } 11087 } 11088 11089 if ((thisarg & N_EQK) == 0) 11090 { 11091 unsigned given_type = type_chk_of_el_type (g_type, g_size); 11092 11093 if ((given_type & types_allowed) == 0) 11094 { 11095 first_error (_("bad type in Neon instruction")); 11096 return badtype; 11097 } 11098 } 11099 else 11100 { 11101 enum neon_el_type mod_k_type = k_type; 11102 unsigned mod_k_size = k_size; 11103 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); 11104 if (g_type != mod_k_type || g_size != mod_k_size) 11105 { 11106 first_error (_("inconsistent types in Neon instruction")); 11107 return badtype; 11108 } 11109 } 11110 } 11111 } 11112 } 11113 11114 return inst.vectype.el[key_el]; 11115} 11116 11117/* Neon-style VFP instruction forwarding. */ 11118 11119/* Thumb VFP instructions have 0xE in the condition field. */ 11120 11121static void 11122do_vfp_cond_or_thumb (void) 11123{ 11124 if (thumb_mode) 11125 inst.instruction |= 0xe0000000; 11126 else 11127 inst.instruction |= inst.cond << 28; 11128} 11129 11130/* Look up and encode a simple mnemonic, for use as a helper function for the 11131 Neon-style VFP syntax. This avoids duplication of bits of the insns table, 11132 etc. It is assumed that operand parsing has already been done, and that the 11133 operands are in the form expected by the given opcode (this isn't necessarily 11134 the same as the form in which they were parsed, hence some massaging must 11135 take place before this function is called). 11136 Checks current arch version against that in the looked-up opcode. */ 11137 11138static void 11139do_vfp_nsyn_opcode (const char *opname) 11140{ 11141 const struct asm_opcode *opcode; 11142 11143 opcode = hash_find (arm_ops_hsh, opname); 11144 11145 if (!opcode) 11146 abort (); 11147 11148 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, 11149 thumb_mode ? *opcode->tvariant : *opcode->avariant), 11150 _(BAD_FPU)); 11151 11152 if (thumb_mode) 11153 { 11154 inst.instruction = opcode->tvalue; 11155 opcode->tencode (); 11156 } 11157 else 11158 { 11159 inst.instruction = (inst.cond << 28) | opcode->avalue; 11160 opcode->aencode (); 11161 } 11162} 11163 11164static void 11165do_vfp_nsyn_add_sub (enum neon_shape rs) 11166{ 11167 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; 11168 11169 if (rs == NS_FFF) 11170 { 11171 if (is_add) 11172 do_vfp_nsyn_opcode ("fadds"); 11173 else 11174 do_vfp_nsyn_opcode ("fsubs"); 11175 } 11176 else 11177 { 11178 if (is_add) 11179 do_vfp_nsyn_opcode ("faddd"); 11180 else 11181 do_vfp_nsyn_opcode ("fsubd"); 11182 } 11183} 11184 11185/* Check operand types to see if this is a VFP instruction, and if so call 11186 PFN (). */ 11187 11188static int 11189try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) 11190{ 11191 enum neon_shape rs; 11192 struct neon_type_el et; 11193 11194 switch (args) 11195 { 11196 case 2: 11197 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11198 et = neon_check_type (2, rs, 11199 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11200 break; 11201 11202 case 3: 11203 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11204 et = neon_check_type (3, rs, 11205 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11206 break; 11207 11208 default: 11209 abort (); 11210 } 11211 11212 if (et.type != NT_invtype) 11213 { 11214 pfn (rs); 11215 return SUCCESS; 11216 } 11217 else 11218 inst.error = NULL; 11219 11220 return FAIL; 11221} 11222 11223static void 11224do_vfp_nsyn_mla_mls (enum neon_shape rs) 11225{ 11226 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; 11227 11228 if (rs == NS_FFF) 11229 { 11230 if (is_mla) 11231 do_vfp_nsyn_opcode ("fmacs"); 11232 else 11233 do_vfp_nsyn_opcode ("fmscs"); 11234 } 11235 else 11236 { 11237 if (is_mla) 11238 do_vfp_nsyn_opcode ("fmacd"); 11239 else 11240 do_vfp_nsyn_opcode ("fmscd"); 11241 } 11242} 11243 11244static void 11245do_vfp_nsyn_mul (enum neon_shape rs) 11246{ 11247 if (rs == NS_FFF) 11248 do_vfp_nsyn_opcode ("fmuls"); 11249 else 11250 do_vfp_nsyn_opcode ("fmuld"); 11251} 11252 11253static void 11254do_vfp_nsyn_abs_neg (enum neon_shape rs) 11255{ 11256 int is_neg = (inst.instruction & 0x80) != 0; 11257 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); 11258 11259 if (rs == NS_FF) 11260 { 11261 if (is_neg) 11262 do_vfp_nsyn_opcode ("fnegs"); 11263 else 11264 do_vfp_nsyn_opcode ("fabss"); 11265 } 11266 else 11267 { 11268 if (is_neg) 11269 do_vfp_nsyn_opcode ("fnegd"); 11270 else 11271 do_vfp_nsyn_opcode ("fabsd"); 11272 } 11273} 11274 11275/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision 11276 insns belong to Neon, and are handled elsewhere. */ 11277 11278static void 11279do_vfp_nsyn_ldm_stm (int is_dbmode) 11280{ 11281 int is_ldm = (inst.instruction & (1 << 20)) != 0; 11282 if (is_ldm) 11283 { 11284 if (is_dbmode) 11285 do_vfp_nsyn_opcode ("fldmdbs"); 11286 else 11287 do_vfp_nsyn_opcode ("fldmias"); 11288 } 11289 else 11290 { 11291 if (is_dbmode) 11292 do_vfp_nsyn_opcode ("fstmdbs"); 11293 else 11294 do_vfp_nsyn_opcode ("fstmias"); 11295 } 11296} 11297 11298static void 11299do_vfp_nsyn_sqrt (void) 11300{ 11301 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11302 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11303 11304 if (rs == NS_FF) 11305 do_vfp_nsyn_opcode ("fsqrts"); 11306 else 11307 do_vfp_nsyn_opcode ("fsqrtd"); 11308} 11309 11310static void 11311do_vfp_nsyn_div (void) 11312{ 11313 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11314 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11315 N_F32 | N_F64 | N_KEY | N_VFP); 11316 11317 if (rs == NS_FFF) 11318 do_vfp_nsyn_opcode ("fdivs"); 11319 else 11320 do_vfp_nsyn_opcode ("fdivd"); 11321} 11322 11323static void 11324do_vfp_nsyn_nmul (void) 11325{ 11326 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11327 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11328 N_F32 | N_F64 | N_KEY | N_VFP); 11329 11330 if (rs == NS_FFF) 11331 { 11332 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11333 do_vfp_sp_dyadic (); 11334 } 11335 else 11336 { 11337 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11338 do_vfp_dp_rd_rn_rm (); 11339 } 11340 do_vfp_cond_or_thumb (); 11341} 11342 11343static void 11344do_vfp_nsyn_cmp (void) 11345{ 11346 if (inst.operands[1].isreg) 11347 { 11348 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11349 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11350 11351 if (rs == NS_FF) 11352 { 11353 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11354 do_vfp_sp_monadic (); 11355 } 11356 else 11357 { 11358 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11359 do_vfp_dp_rd_rm (); 11360 } 11361 } 11362 else 11363 { 11364 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); 11365 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); 11366 11367 switch (inst.instruction & 0x0fffffff) 11368 { 11369 case N_MNEM_vcmp: 11370 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; 11371 break; 11372 case N_MNEM_vcmpe: 11373 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; 11374 break; 11375 default: 11376 abort (); 11377 } 11378 11379 if (rs == NS_FI) 11380 { 11381 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11382 do_vfp_sp_compare_z (); 11383 } 11384 else 11385 { 11386 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11387 do_vfp_dp_rd (); 11388 } 11389 } 11390 do_vfp_cond_or_thumb (); 11391} 11392 11393static void 11394nsyn_insert_sp (void) 11395{ 11396 inst.operands[1] = inst.operands[0]; 11397 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 11398 inst.operands[0].reg = 13; 11399 inst.operands[0].isreg = 1; 11400 inst.operands[0].writeback = 1; 11401 inst.operands[0].present = 1; 11402} 11403 11404static void 11405do_vfp_nsyn_push (void) 11406{ 11407 nsyn_insert_sp (); 11408 if (inst.operands[1].issingle) 11409 do_vfp_nsyn_opcode ("fstmdbs"); 11410 else 11411 do_vfp_nsyn_opcode ("fstmdbd"); 11412} 11413 11414static void 11415do_vfp_nsyn_pop (void) 11416{ 11417 nsyn_insert_sp (); 11418 if (inst.operands[1].issingle) 11419 do_vfp_nsyn_opcode ("fldmias"); 11420 else 11421 do_vfp_nsyn_opcode ("fldmiad"); 11422} 11423 11424/* Fix up Neon data-processing instructions, ORing in the correct bits for 11425 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ 11426 11427static unsigned 11428neon_dp_fixup (unsigned i) 11429{ 11430 if (thumb_mode) 11431 { 11432 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ 11433 if (i & (1 << 24)) 11434 i |= 1 << 28; 11435 11436 i &= ~(1 << 24); 11437 11438 i |= 0xef000000; 11439 } 11440 else 11441 i |= 0xf2000000; 11442 11443 return i; 11444} 11445 11446/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 11447 (0, 1, 2, 3). */ 11448 11449static unsigned 11450neon_logbits (unsigned x) 11451{ 11452 return ffs (x) - 4; 11453} 11454 11455#define LOW4(R) ((R) & 0xf) 11456#define HI1(R) (((R) >> 4) & 1) 11457 11458/* Encode insns with bit pattern: 11459 11460 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| 11461 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | 11462 11463 SIZE is passed in bits. -1 means size field isn't changed, in case it has a 11464 different meaning for some instruction. */ 11465 11466static void 11467neon_three_same (int isquad, int ubit, int size) 11468{ 11469 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11470 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11471 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 11472 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 11473 inst.instruction |= LOW4 (inst.operands[2].reg); 11474 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 11475 inst.instruction |= (isquad != 0) << 6; 11476 inst.instruction |= (ubit != 0) << 24; 11477 if (size != -1) 11478 inst.instruction |= neon_logbits (size) << 20; 11479 11480 inst.instruction = neon_dp_fixup (inst.instruction); 11481} 11482 11483/* Encode instructions of the form: 11484 11485 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| 11486 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | 11487 11488 Don't write size if SIZE == -1. */ 11489 11490static void 11491neon_two_same (int qbit, int ubit, int size) 11492{ 11493 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11494 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11495 inst.instruction |= LOW4 (inst.operands[1].reg); 11496 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11497 inst.instruction |= (qbit != 0) << 6; 11498 inst.instruction |= (ubit != 0) << 24; 11499 11500 if (size != -1) 11501 inst.instruction |= neon_logbits (size) << 18; 11502 11503 inst.instruction = neon_dp_fixup (inst.instruction); 11504} 11505 11506/* Neon instruction encoders, in approximate order of appearance. */ 11507 11508static void 11509do_neon_dyadic_i_su (void) 11510{ 11511 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11512 struct neon_type_el et = neon_check_type (3, rs, 11513 N_EQK, N_EQK, N_SU_32 | N_KEY); 11514 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11515} 11516 11517static void 11518do_neon_dyadic_i64_su (void) 11519{ 11520 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11521 struct neon_type_el et = neon_check_type (3, rs, 11522 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11523 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11524} 11525 11526static void 11527neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, 11528 unsigned immbits) 11529{ 11530 unsigned size = et.size >> 3; 11531 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11532 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11533 inst.instruction |= LOW4 (inst.operands[1].reg); 11534 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11535 inst.instruction |= (isquad != 0) << 6; 11536 inst.instruction |= immbits << 16; 11537 inst.instruction |= (size >> 3) << 7; 11538 inst.instruction |= (size & 0x7) << 19; 11539 if (write_ubit) 11540 inst.instruction |= (uval != 0) << 24; 11541 11542 inst.instruction = neon_dp_fixup (inst.instruction); 11543} 11544 11545static void 11546do_neon_shl_imm (void) 11547{ 11548 if (!inst.operands[2].isreg) 11549 { 11550 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11551 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); 11552 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11553 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); 11554 } 11555 else 11556 { 11557 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11558 struct neon_type_el et = neon_check_type (3, rs, 11559 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11560 unsigned int tmp; 11561 11562 /* VSHL/VQSHL 3-register variants have syntax such as: 11563 vshl.xx Dd, Dm, Dn 11564 whereas other 3-register operations encoded by neon_three_same have 11565 syntax like: 11566 vadd.xx Dd, Dn, Dm 11567 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg 11568 here. */ 11569 tmp = inst.operands[2].reg; 11570 inst.operands[2].reg = inst.operands[1].reg; 11571 inst.operands[1].reg = tmp; 11572 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11573 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11574 } 11575} 11576 11577static void 11578do_neon_qshl_imm (void) 11579{ 11580 if (!inst.operands[2].isreg) 11581 { 11582 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11583 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 11584 11585 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11586 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 11587 inst.operands[2].imm); 11588 } 11589 else 11590 { 11591 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11592 struct neon_type_el et = neon_check_type (3, rs, 11593 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11594 unsigned int tmp; 11595 11596 /* See note in do_neon_shl_imm. */ 11597 tmp = inst.operands[2].reg; 11598 inst.operands[2].reg = inst.operands[1].reg; 11599 inst.operands[1].reg = tmp; 11600 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11601 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11602 } 11603} 11604 11605static void 11606do_neon_rshl (void) 11607{ 11608 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11609 struct neon_type_el et = neon_check_type (3, rs, 11610 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11611 unsigned int tmp; 11612 11613 tmp = inst.operands[2].reg; 11614 inst.operands[2].reg = inst.operands[1].reg; 11615 inst.operands[1].reg = tmp; 11616 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11617} 11618 11619static int 11620neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) 11621{ 11622 /* Handle .I8 pseudo-instructions. */ 11623 if (size == 8) 11624 { 11625 /* Unfortunately, this will make everything apart from zero out-of-range. 11626 FIXME is this the intended semantics? There doesn't seem much point in 11627 accepting .I8 if so. */ 11628 immediate |= immediate << 8; 11629 size = 16; 11630 } 11631 11632 if (size >= 32) 11633 { 11634 if (immediate == (immediate & 0x000000ff)) 11635 { 11636 *immbits = immediate; 11637 return 0x1; 11638 } 11639 else if (immediate == (immediate & 0x0000ff00)) 11640 { 11641 *immbits = immediate >> 8; 11642 return 0x3; 11643 } 11644 else if (immediate == (immediate & 0x00ff0000)) 11645 { 11646 *immbits = immediate >> 16; 11647 return 0x5; 11648 } 11649 else if (immediate == (immediate & 0xff000000)) 11650 { 11651 *immbits = immediate >> 24; 11652 return 0x7; 11653 } 11654 if ((immediate & 0xffff) != (immediate >> 16)) 11655 goto bad_immediate; 11656 immediate &= 0xffff; 11657 } 11658 11659 if (immediate == (immediate & 0x000000ff)) 11660 { 11661 *immbits = immediate; 11662 return 0x9; 11663 } 11664 else if (immediate == (immediate & 0x0000ff00)) 11665 { 11666 *immbits = immediate >> 8; 11667 return 0xb; 11668 } 11669 11670 bad_immediate: 11671 first_error (_("immediate value out of range")); 11672 return FAIL; 11673} 11674 11675/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits 11676 A, B, C, D. */ 11677 11678static int 11679neon_bits_same_in_bytes (unsigned imm) 11680{ 11681 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) 11682 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) 11683 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) 11684 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); 11685} 11686 11687/* For immediate of above form, return 0bABCD. */ 11688 11689static unsigned 11690neon_squash_bits (unsigned imm) 11691{ 11692 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) 11693 | ((imm & 0x01000000) >> 21); 11694} 11695 11696/* Compress quarter-float representation to 0b...000 abcdefgh. */ 11697 11698static unsigned 11699neon_qfloat_bits (unsigned imm) 11700{ 11701 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); 11702} 11703 11704/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into 11705 the instruction. *OP is passed as the initial value of the op field, and 11706 may be set to a different value depending on the constant (i.e. 11707 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not 11708 MVN). If the immediate looks like a repeated parttern then also 11709 try smaller element sizes. */ 11710 11711static int 11712neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, 11713 unsigned *immbits, int *op, int size, 11714 enum neon_el_type type) 11715{ 11716 /* Only permit float immediates (including 0.0/-0.0) if the operand type is 11717 float. */ 11718 if (type == NT_float && !float_p) 11719 return FAIL; 11720 11721 if (type == NT_float && is_quarter_float (immlo) && immhi == 0) 11722 { 11723 if (size != 32 || *op == 1) 11724 return FAIL; 11725 *immbits = neon_qfloat_bits (immlo); 11726 return 0xf; 11727 } 11728 11729 if (size == 64) 11730 { 11731 if (neon_bits_same_in_bytes (immhi) 11732 && neon_bits_same_in_bytes (immlo)) 11733 { 11734 if (*op == 1) 11735 return FAIL; 11736 *immbits = (neon_squash_bits (immhi) << 4) 11737 | neon_squash_bits (immlo); 11738 *op = 1; 11739 return 0xe; 11740 } 11741 11742 if (immhi != immlo) 11743 return FAIL; 11744 } 11745 11746 if (size >= 32) 11747 { 11748 if (immlo == (immlo & 0x000000ff)) 11749 { 11750 *immbits = immlo; 11751 return 0x0; 11752 } 11753 else if (immlo == (immlo & 0x0000ff00)) 11754 { 11755 *immbits = immlo >> 8; 11756 return 0x2; 11757 } 11758 else if (immlo == (immlo & 0x00ff0000)) 11759 { 11760 *immbits = immlo >> 16; 11761 return 0x4; 11762 } 11763 else if (immlo == (immlo & 0xff000000)) 11764 { 11765 *immbits = immlo >> 24; 11766 return 0x6; 11767 } 11768 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) 11769 { 11770 *immbits = (immlo >> 8) & 0xff; 11771 return 0xc; 11772 } 11773 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) 11774 { 11775 *immbits = (immlo >> 16) & 0xff; 11776 return 0xd; 11777 } 11778 11779 if ((immlo & 0xffff) != (immlo >> 16)) 11780 return FAIL; 11781 immlo &= 0xffff; 11782 } 11783 11784 if (size >= 16) 11785 { 11786 if (immlo == (immlo & 0x000000ff)) 11787 { 11788 *immbits = immlo; 11789 return 0x8; 11790 } 11791 else if (immlo == (immlo & 0x0000ff00)) 11792 { 11793 *immbits = immlo >> 8; 11794 return 0xa; 11795 } 11796 11797 if ((immlo & 0xff) != (immlo >> 8)) 11798 return FAIL; 11799 immlo &= 0xff; 11800 } 11801 11802 if (immlo == (immlo & 0x000000ff)) 11803 { 11804 /* Don't allow MVN with 8-bit immediate. */ 11805 if (*op == 1) 11806 return FAIL; 11807 *immbits = immlo; 11808 return 0xe; 11809 } 11810 11811 return FAIL; 11812} 11813 11814/* Write immediate bits [7:0] to the following locations: 11815 11816 |28/24|23 19|18 16|15 4|3 0| 11817 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| 11818 11819 This function is used by VMOV/VMVN/VORR/VBIC. */ 11820 11821static void 11822neon_write_immbits (unsigned immbits) 11823{ 11824 inst.instruction |= immbits & 0xf; 11825 inst.instruction |= ((immbits >> 4) & 0x7) << 16; 11826 inst.instruction |= ((immbits >> 7) & 0x1) << 24; 11827} 11828 11829/* Invert low-order SIZE bits of XHI:XLO. */ 11830 11831static void 11832neon_invert_size (unsigned *xlo, unsigned *xhi, int size) 11833{ 11834 unsigned immlo = xlo ? *xlo : 0; 11835 unsigned immhi = xhi ? *xhi : 0; 11836 11837 switch (size) 11838 { 11839 case 8: 11840 immlo = (~immlo) & 0xff; 11841 break; 11842 11843 case 16: 11844 immlo = (~immlo) & 0xffff; 11845 break; 11846 11847 case 64: 11848 immhi = (~immhi) & 0xffffffff; 11849 /* fall through. */ 11850 11851 case 32: 11852 immlo = (~immlo) & 0xffffffff; 11853 break; 11854 11855 default: 11856 abort (); 11857 } 11858 11859 if (xlo) 11860 *xlo = immlo; 11861 11862 if (xhi) 11863 *xhi = immhi; 11864} 11865 11866static void 11867do_neon_logic (void) 11868{ 11869 if (inst.operands[2].present && inst.operands[2].isreg) 11870 { 11871 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11872 neon_check_type (3, rs, N_IGNORE_TYPE); 11873 /* U bit and size field were set as part of the bitmask. */ 11874 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11875 neon_three_same (neon_quad (rs), 0, -1); 11876 } 11877 else 11878 { 11879 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 11880 struct neon_type_el et = neon_check_type (2, rs, 11881 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 11882 enum neon_opc opcode = inst.instruction & 0x0fffffff; 11883 unsigned immbits; 11884 int cmode; 11885 11886 if (et.type == NT_invtype) 11887 return; 11888 11889 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11890 11891 immbits = inst.operands[1].imm; 11892 if (et.size == 64) 11893 { 11894 /* .i64 is a pseudo-op, so the immediate must be a repeating 11895 pattern. */ 11896 if (immbits != (inst.operands[1].regisimm ? 11897 inst.operands[1].reg : 0)) 11898 { 11899 /* Set immbits to an invalid constant. */ 11900 immbits = 0xdeadbeef; 11901 } 11902 } 11903 11904 switch (opcode) 11905 { 11906 case N_MNEM_vbic: 11907 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11908 break; 11909 11910 case N_MNEM_vorr: 11911 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11912 break; 11913 11914 case N_MNEM_vand: 11915 /* Pseudo-instruction for VBIC. */ 11916 neon_invert_size (&immbits, 0, et.size); 11917 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11918 break; 11919 11920 case N_MNEM_vorn: 11921 /* Pseudo-instruction for VORR. */ 11922 neon_invert_size (&immbits, 0, et.size); 11923 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11924 break; 11925 11926 default: 11927 abort (); 11928 } 11929 11930 if (cmode == FAIL) 11931 return; 11932 11933 inst.instruction |= neon_quad (rs) << 6; 11934 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11935 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11936 inst.instruction |= cmode << 8; 11937 neon_write_immbits (immbits); 11938 11939 inst.instruction = neon_dp_fixup (inst.instruction); 11940 } 11941} 11942 11943static void 11944do_neon_bitfield (void) 11945{ 11946 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11947 neon_check_type (3, rs, N_IGNORE_TYPE); 11948 neon_three_same (neon_quad (rs), 0, -1); 11949} 11950 11951static void 11952neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, 11953 unsigned destbits) 11954{ 11955 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11956 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, 11957 types | N_KEY); 11958 if (et.type == NT_float) 11959 { 11960 inst.instruction = NEON_ENC_FLOAT (inst.instruction); 11961 neon_three_same (neon_quad (rs), 0, -1); 11962 } 11963 else 11964 { 11965 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11966 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); 11967 } 11968} 11969 11970static void 11971do_neon_dyadic_if_su (void) 11972{ 11973 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 11974} 11975 11976static void 11977do_neon_dyadic_if_su_d (void) 11978{ 11979 /* This version only allow D registers, but that constraint is enforced during 11980 operand parsing so we don't need to do anything extra here. */ 11981 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 11982} 11983 11984static void 11985do_neon_dyadic_if_i_d (void) 11986{ 11987 /* The "untyped" case can't happen. Do this to stop the "U" bit being 11988 affected if we specify unsigned args. */ 11989 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 11990} 11991 11992enum vfp_or_neon_is_neon_bits 11993{ 11994 NEON_CHECK_CC = 1, 11995 NEON_CHECK_ARCH = 2 11996}; 11997 11998/* Call this function if an instruction which may have belonged to the VFP or 11999 Neon instruction sets, but turned out to be a Neon instruction (due to the 12000 operand types involved, etc.). We have to check and/or fix-up a couple of 12001 things: 12002 12003 - Make sure the user hasn't attempted to make a Neon instruction 12004 conditional. 12005 - Alter the value in the condition code field if necessary. 12006 - Make sure that the arch supports Neon instructions. 12007 12008 Which of these operations take place depends on bits from enum 12009 vfp_or_neon_is_neon_bits. 12010 12011 WARNING: This function has side effects! If NEON_CHECK_CC is used and the 12012 current instruction's condition is COND_ALWAYS, the condition field is 12013 changed to inst.uncond_value. This is necessary because instructions shared 12014 between VFP and Neon may be conditional for the VFP variants only, and the 12015 unconditional Neon version must have, e.g., 0xF in the condition field. */ 12016 12017static int 12018vfp_or_neon_is_neon (unsigned check) 12019{ 12020 /* Conditions are always legal in Thumb mode (IT blocks). */ 12021 if (!thumb_mode && (check & NEON_CHECK_CC)) 12022 { 12023 if (inst.cond != COND_ALWAYS) 12024 { 12025 first_error (_(BAD_COND)); 12026 return FAIL; 12027 } 12028 if (inst.uncond_value != -1) 12029 inst.instruction |= inst.uncond_value << 28; 12030 } 12031 12032 if ((check & NEON_CHECK_ARCH) 12033 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) 12034 { 12035 first_error (_(BAD_FPU)); 12036 return FAIL; 12037 } 12038 12039 return SUCCESS; 12040} 12041 12042static void 12043do_neon_addsub_if_i (void) 12044{ 12045 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) 12046 return; 12047 12048 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12049 return; 12050 12051 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12052 affected if we specify unsigned args. */ 12053 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); 12054} 12055 12056/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the 12057 result to be: 12058 V<op> A,B (A is operand 0, B is operand 2) 12059 to mean: 12060 V<op> A,B,A 12061 not: 12062 V<op> A,B,B 12063 so handle that case specially. */ 12064 12065static void 12066neon_exchange_operands (void) 12067{ 12068 void *scratch = alloca (sizeof (inst.operands[0])); 12069 if (inst.operands[1].present) 12070 { 12071 /* Swap operands[1] and operands[2]. */ 12072 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); 12073 inst.operands[1] = inst.operands[2]; 12074 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); 12075 } 12076 else 12077 { 12078 inst.operands[1] = inst.operands[2]; 12079 inst.operands[2] = inst.operands[0]; 12080 } 12081} 12082 12083static void 12084neon_compare (unsigned regtypes, unsigned immtypes, int invert) 12085{ 12086 if (inst.operands[2].isreg) 12087 { 12088 if (invert) 12089 neon_exchange_operands (); 12090 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); 12091 } 12092 else 12093 { 12094 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12095 struct neon_type_el et = neon_check_type (2, rs, 12096 N_EQK | N_SIZ, immtypes | N_KEY); 12097 12098 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12099 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12100 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12101 inst.instruction |= LOW4 (inst.operands[1].reg); 12102 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12103 inst.instruction |= neon_quad (rs) << 6; 12104 inst.instruction |= (et.type == NT_float) << 10; 12105 inst.instruction |= neon_logbits (et.size) << 18; 12106 12107 inst.instruction = neon_dp_fixup (inst.instruction); 12108 } 12109} 12110 12111static void 12112do_neon_cmp (void) 12113{ 12114 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); 12115} 12116 12117static void 12118do_neon_cmp_inv (void) 12119{ 12120 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); 12121} 12122 12123static void 12124do_neon_ceq (void) 12125{ 12126 neon_compare (N_IF_32, N_IF_32, FALSE); 12127} 12128 12129/* For multiply instructions, we have the possibility of 16-bit or 32-bit 12130 scalars, which are encoded in 5 bits, M : Rm. 12131 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in 12132 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the 12133 index in M. */ 12134 12135static unsigned 12136neon_scalar_for_mul (unsigned scalar, unsigned elsize) 12137{ 12138 unsigned regno = NEON_SCALAR_REG (scalar); 12139 unsigned elno = NEON_SCALAR_INDEX (scalar); 12140 12141 switch (elsize) 12142 { 12143 case 16: 12144 if (regno > 7 || elno > 3) 12145 goto bad_scalar; 12146 return regno | (elno << 3); 12147 12148 case 32: 12149 if (regno > 15 || elno > 1) 12150 goto bad_scalar; 12151 return regno | (elno << 4); 12152 12153 default: 12154 bad_scalar: 12155 first_error (_("scalar out of range for multiply instruction")); 12156 } 12157 12158 return 0; 12159} 12160 12161/* Encode multiply / multiply-accumulate scalar instructions. */ 12162 12163static void 12164neon_mul_mac (struct neon_type_el et, int ubit) 12165{ 12166 unsigned scalar; 12167 12168 /* Give a more helpful error message if we have an invalid type. */ 12169 if (et.type == NT_invtype) 12170 return; 12171 12172 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); 12173 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12174 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12175 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12176 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12177 inst.instruction |= LOW4 (scalar); 12178 inst.instruction |= HI1 (scalar) << 5; 12179 inst.instruction |= (et.type == NT_float) << 8; 12180 inst.instruction |= neon_logbits (et.size) << 20; 12181 inst.instruction |= (ubit != 0) << 24; 12182 12183 inst.instruction = neon_dp_fixup (inst.instruction); 12184} 12185 12186static void 12187do_neon_mac_maybe_scalar (void) 12188{ 12189 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) 12190 return; 12191 12192 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12193 return; 12194 12195 if (inst.operands[2].isscalar) 12196 { 12197 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12198 struct neon_type_el et = neon_check_type (3, rs, 12199 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); 12200 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12201 neon_mul_mac (et, neon_quad (rs)); 12202 } 12203 else 12204 { 12205 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12206 affected if we specify unsigned args. */ 12207 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12208 } 12209} 12210 12211static void 12212do_neon_tst (void) 12213{ 12214 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12215 struct neon_type_el et = neon_check_type (3, rs, 12216 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); 12217 neon_three_same (neon_quad (rs), 0, et.size); 12218} 12219 12220/* VMUL with 3 registers allows the P8 type. The scalar version supports the 12221 same types as the MAC equivalents. The polynomial type for this instruction 12222 is encoded the same as the integer type. */ 12223 12224static void 12225do_neon_mul (void) 12226{ 12227 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) 12228 return; 12229 12230 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12231 return; 12232 12233 if (inst.operands[2].isscalar) 12234 do_neon_mac_maybe_scalar (); 12235 else 12236 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); 12237} 12238 12239static void 12240do_neon_qdmulh (void) 12241{ 12242 if (inst.operands[2].isscalar) 12243 { 12244 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12245 struct neon_type_el et = neon_check_type (3, rs, 12246 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12247 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12248 neon_mul_mac (et, neon_quad (rs)); 12249 } 12250 else 12251 { 12252 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12253 struct neon_type_el et = neon_check_type (3, rs, 12254 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12255 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12256 /* The U bit (rounding) comes from bit mask. */ 12257 neon_three_same (neon_quad (rs), 0, et.size); 12258 } 12259} 12260 12261static void 12262do_neon_fcmp_absolute (void) 12263{ 12264 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12265 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12266 /* Size field comes from bit mask. */ 12267 neon_three_same (neon_quad (rs), 1, -1); 12268} 12269 12270static void 12271do_neon_fcmp_absolute_inv (void) 12272{ 12273 neon_exchange_operands (); 12274 do_neon_fcmp_absolute (); 12275} 12276 12277static void 12278do_neon_step (void) 12279{ 12280 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12281 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12282 neon_three_same (neon_quad (rs), 0, -1); 12283} 12284 12285static void 12286do_neon_abs_neg (void) 12287{ 12288 enum neon_shape rs; 12289 struct neon_type_el et; 12290 12291 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) 12292 return; 12293 12294 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12295 return; 12296 12297 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12298 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); 12299 12300 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12301 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12302 inst.instruction |= LOW4 (inst.operands[1].reg); 12303 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12304 inst.instruction |= neon_quad (rs) << 6; 12305 inst.instruction |= (et.type == NT_float) << 10; 12306 inst.instruction |= neon_logbits (et.size) << 18; 12307 12308 inst.instruction = neon_dp_fixup (inst.instruction); 12309} 12310 12311static void 12312do_neon_sli (void) 12313{ 12314 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12315 struct neon_type_el et = neon_check_type (2, rs, 12316 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12317 int imm = inst.operands[2].imm; 12318 constraint (imm < 0 || (unsigned)imm >= et.size, 12319 _("immediate out of range for insert")); 12320 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12321} 12322 12323static void 12324do_neon_sri (void) 12325{ 12326 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12327 struct neon_type_el et = neon_check_type (2, rs, 12328 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12329 int imm = inst.operands[2].imm; 12330 constraint (imm < 1 || (unsigned)imm > et.size, 12331 _("immediate out of range for insert")); 12332 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); 12333} 12334 12335static void 12336do_neon_qshlu_imm (void) 12337{ 12338 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12339 struct neon_type_el et = neon_check_type (2, rs, 12340 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); 12341 int imm = inst.operands[2].imm; 12342 constraint (imm < 0 || (unsigned)imm >= et.size, 12343 _("immediate out of range for shift")); 12344 /* Only encodes the 'U present' variant of the instruction. 12345 In this case, signed types have OP (bit 8) set to 0. 12346 Unsigned types have OP set to 1. */ 12347 inst.instruction |= (et.type == NT_unsigned) << 8; 12348 /* The rest of the bits are the same as other immediate shifts. */ 12349 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12350} 12351 12352static void 12353do_neon_qmovn (void) 12354{ 12355 struct neon_type_el et = neon_check_type (2, NS_DQ, 12356 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12357 /* Saturating move where operands can be signed or unsigned, and the 12358 destination has the same signedness. */ 12359 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12360 if (et.type == NT_unsigned) 12361 inst.instruction |= 0xc0; 12362 else 12363 inst.instruction |= 0x80; 12364 neon_two_same (0, 1, et.size / 2); 12365} 12366 12367static void 12368do_neon_qmovun (void) 12369{ 12370 struct neon_type_el et = neon_check_type (2, NS_DQ, 12371 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12372 /* Saturating move with unsigned results. Operands must be signed. */ 12373 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12374 neon_two_same (0, 1, et.size / 2); 12375} 12376 12377static void 12378do_neon_rshift_sat_narrow (void) 12379{ 12380 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12381 or unsigned. If operands are unsigned, results must also be unsigned. */ 12382 struct neon_type_el et = neon_check_type (2, NS_DQI, 12383 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12384 int imm = inst.operands[2].imm; 12385 /* This gets the bounds check, size encoding and immediate bits calculation 12386 right. */ 12387 et.size /= 2; 12388 12389 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for 12390 VQMOVN.I<size> <Dd>, <Qm>. */ 12391 if (imm == 0) 12392 { 12393 inst.operands[2].present = 0; 12394 inst.instruction = N_MNEM_vqmovn; 12395 do_neon_qmovn (); 12396 return; 12397 } 12398 12399 constraint (imm < 1 || (unsigned)imm > et.size, 12400 _("immediate out of range")); 12401 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); 12402} 12403 12404static void 12405do_neon_rshift_sat_narrow_u (void) 12406{ 12407 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12408 or unsigned. If operands are unsigned, results must also be unsigned. */ 12409 struct neon_type_el et = neon_check_type (2, NS_DQI, 12410 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12411 int imm = inst.operands[2].imm; 12412 /* This gets the bounds check, size encoding and immediate bits calculation 12413 right. */ 12414 et.size /= 2; 12415 12416 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for 12417 VQMOVUN.I<size> <Dd>, <Qm>. */ 12418 if (imm == 0) 12419 { 12420 inst.operands[2].present = 0; 12421 inst.instruction = N_MNEM_vqmovun; 12422 do_neon_qmovun (); 12423 return; 12424 } 12425 12426 constraint (imm < 1 || (unsigned)imm > et.size, 12427 _("immediate out of range")); 12428 /* FIXME: The manual is kind of unclear about what value U should have in 12429 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it 12430 must be 1. */ 12431 neon_imm_shift (TRUE, 1, 0, et, et.size - imm); 12432} 12433 12434static void 12435do_neon_movn (void) 12436{ 12437 struct neon_type_el et = neon_check_type (2, NS_DQ, 12438 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12439 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12440 neon_two_same (0, 1, et.size / 2); 12441} 12442 12443static void 12444do_neon_rshift_narrow (void) 12445{ 12446 struct neon_type_el et = neon_check_type (2, NS_DQI, 12447 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12448 int imm = inst.operands[2].imm; 12449 /* This gets the bounds check, size encoding and immediate bits calculation 12450 right. */ 12451 et.size /= 2; 12452 12453 /* If immediate is zero then we are a pseudo-instruction for 12454 VMOVN.I<size> <Dd>, <Qm> */ 12455 if (imm == 0) 12456 { 12457 inst.operands[2].present = 0; 12458 inst.instruction = N_MNEM_vmovn; 12459 do_neon_movn (); 12460 return; 12461 } 12462 12463 constraint (imm < 1 || (unsigned)imm > et.size, 12464 _("immediate out of range for narrowing operation")); 12465 neon_imm_shift (FALSE, 0, 0, et, et.size - imm); 12466} 12467 12468static void 12469do_neon_shll (void) 12470{ 12471 /* FIXME: Type checking when lengthening. */ 12472 struct neon_type_el et = neon_check_type (2, NS_QDI, 12473 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); 12474 unsigned imm = inst.operands[2].imm; 12475 12476 if (imm == et.size) 12477 { 12478 /* Maximum shift variant. */ 12479 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12480 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12481 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12482 inst.instruction |= LOW4 (inst.operands[1].reg); 12483 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12484 inst.instruction |= neon_logbits (et.size) << 18; 12485 12486 inst.instruction = neon_dp_fixup (inst.instruction); 12487 } 12488 else 12489 { 12490 /* A more-specific type check for non-max versions. */ 12491 et = neon_check_type (2, NS_QDI, 12492 N_EQK | N_DBL, N_SU_32 | N_KEY); 12493 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12494 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); 12495 } 12496} 12497 12498/* Check the various types for the VCVT instruction, and return which version 12499 the current instruction is. */ 12500 12501static int 12502neon_cvt_flavour (enum neon_shape rs) 12503{ 12504#define CVT_VAR(C,X,Y) \ 12505 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ 12506 if (et.type != NT_invtype) \ 12507 { \ 12508 inst.error = NULL; \ 12509 return (C); \ 12510 } 12511 struct neon_type_el et; 12512 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF 12513 || rs == NS_FF) ? N_VFP : 0; 12514 /* The instruction versions which take an immediate take one register 12515 argument, which is extended to the width of the full register. Thus the 12516 "source" and "destination" registers must have the same width. Hack that 12517 here by making the size equal to the key (wider, in this case) operand. */ 12518 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; 12519 12520 CVT_VAR (0, N_S32, N_F32); 12521 CVT_VAR (1, N_U32, N_F32); 12522 CVT_VAR (2, N_F32, N_S32); 12523 CVT_VAR (3, N_F32, N_U32); 12524 12525 whole_reg = N_VFP; 12526 12527 /* VFP instructions. */ 12528 CVT_VAR (4, N_F32, N_F64); 12529 CVT_VAR (5, N_F64, N_F32); 12530 CVT_VAR (6, N_S32, N_F64 | key); 12531 CVT_VAR (7, N_U32, N_F64 | key); 12532 CVT_VAR (8, N_F64 | key, N_S32); 12533 CVT_VAR (9, N_F64 | key, N_U32); 12534 /* VFP instructions with bitshift. */ 12535 CVT_VAR (10, N_F32 | key, N_S16); 12536 CVT_VAR (11, N_F32 | key, N_U16); 12537 CVT_VAR (12, N_F64 | key, N_S16); 12538 CVT_VAR (13, N_F64 | key, N_U16); 12539 CVT_VAR (14, N_S16, N_F32 | key); 12540 CVT_VAR (15, N_U16, N_F32 | key); 12541 CVT_VAR (16, N_S16, N_F64 | key); 12542 CVT_VAR (17, N_U16, N_F64 | key); 12543 12544 return -1; 12545#undef CVT_VAR 12546} 12547 12548/* Neon-syntax VFP conversions. */ 12549 12550static void 12551do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) 12552{ 12553 const char *opname = 0; 12554 12555 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) 12556 { 12557 /* Conversions with immediate bitshift. */ 12558 const char *enc[] = 12559 { 12560 "ftosls", 12561 "ftouls", 12562 "fsltos", 12563 "fultos", 12564 NULL, 12565 NULL, 12566 "ftosld", 12567 "ftould", 12568 "fsltod", 12569 "fultod", 12570 "fshtos", 12571 "fuhtos", 12572 "fshtod", 12573 "fuhtod", 12574 "ftoshs", 12575 "ftouhs", 12576 "ftoshd", 12577 "ftouhd" 12578 }; 12579 12580 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12581 { 12582 opname = enc[flavour]; 12583 constraint (inst.operands[0].reg != inst.operands[1].reg, 12584 _("operands 0 and 1 must be the same register")); 12585 inst.operands[1] = inst.operands[2]; 12586 memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); 12587 } 12588 } 12589 else 12590 { 12591 /* Conversions without bitshift. */ 12592 const char *enc[] = 12593 { 12594 "ftosis", 12595 "ftouis", 12596 "fsitos", 12597 "fuitos", 12598 "fcvtsd", 12599 "fcvtds", 12600 "ftosid", 12601 "ftouid", 12602 "fsitod", 12603 "fuitod" 12604 }; 12605 12606 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12607 opname = enc[flavour]; 12608 } 12609 12610 if (opname) 12611 do_vfp_nsyn_opcode (opname); 12612} 12613 12614static void 12615do_vfp_nsyn_cvtz (void) 12616{ 12617 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); 12618 int flavour = neon_cvt_flavour (rs); 12619 const char *enc[] = 12620 { 12621 "ftosizs", 12622 "ftouizs", 12623 NULL, 12624 NULL, 12625 NULL, 12626 NULL, 12627 "ftosizd", 12628 "ftouizd" 12629 }; 12630 12631 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) 12632 do_vfp_nsyn_opcode (enc[flavour]); 12633} 12634 12635static void 12636do_neon_cvt (void) 12637{ 12638 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, 12639 NS_FD, NS_DF, NS_FF, NS_NULL); 12640 int flavour = neon_cvt_flavour (rs); 12641 12642 /* VFP rather than Neon conversions. */ 12643 if (flavour >= 4) 12644 { 12645 do_vfp_nsyn_cvt (rs, flavour); 12646 return; 12647 } 12648 12649 switch (rs) 12650 { 12651 case NS_DDI: 12652 case NS_QQI: 12653 { 12654 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12655 return; 12656 12657 /* Fixed-point conversion with #0 immediate is encoded as an 12658 integer conversion. */ 12659 if (inst.operands[2].present && inst.operands[2].imm == 0) 12660 goto int_encode; 12661 unsigned immbits = 32 - inst.operands[2].imm; 12662 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; 12663 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12664 if (flavour != -1) 12665 inst.instruction |= enctab[flavour]; 12666 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12667 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12668 inst.instruction |= LOW4 (inst.operands[1].reg); 12669 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12670 inst.instruction |= neon_quad (rs) << 6; 12671 inst.instruction |= 1 << 21; 12672 inst.instruction |= immbits << 16; 12673 12674 inst.instruction = neon_dp_fixup (inst.instruction); 12675 } 12676 break; 12677 12678 case NS_DD: 12679 case NS_QQ: 12680 int_encode: 12681 { 12682 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; 12683 12684 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12685 12686 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12687 return; 12688 12689 if (flavour != -1) 12690 inst.instruction |= enctab[flavour]; 12691 12692 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12693 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12694 inst.instruction |= LOW4 (inst.operands[1].reg); 12695 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12696 inst.instruction |= neon_quad (rs) << 6; 12697 inst.instruction |= 2 << 18; 12698 12699 inst.instruction = neon_dp_fixup (inst.instruction); 12700 } 12701 break; 12702 12703 default: 12704 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ 12705 do_vfp_nsyn_cvt (rs, flavour); 12706 } 12707} 12708 12709static void 12710neon_move_immediate (void) 12711{ 12712 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 12713 struct neon_type_el et = neon_check_type (2, rs, 12714 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 12715 unsigned immlo, immhi = 0, immbits; 12716 int op, cmode, float_p; 12717 12718 constraint (et.type == NT_invtype, 12719 _("operand size must be specified for immediate VMOV")); 12720 12721 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ 12722 op = (inst.instruction & (1 << 5)) != 0; 12723 12724 immlo = inst.operands[1].imm; 12725 if (inst.operands[1].regisimm) 12726 immhi = inst.operands[1].reg; 12727 12728 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, 12729 _("immediate has bits set outside the operand size")); 12730 12731 float_p = inst.operands[1].immisfloat; 12732 12733 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, 12734 et.size, et.type)) == FAIL) 12735 { 12736 /* Invert relevant bits only. */ 12737 neon_invert_size (&immlo, &immhi, et.size); 12738 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable 12739 with one or the other; those cases are caught by 12740 neon_cmode_for_move_imm. */ 12741 op = !op; 12742 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, 12743 &op, et.size, et.type)) == FAIL) 12744 { 12745 first_error (_("immediate out of range")); 12746 return; 12747 } 12748 } 12749 12750 inst.instruction &= ~(1 << 5); 12751 inst.instruction |= op << 5; 12752 12753 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12754 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12755 inst.instruction |= neon_quad (rs) << 6; 12756 inst.instruction |= cmode << 8; 12757 12758 neon_write_immbits (immbits); 12759} 12760 12761static void 12762do_neon_mvn (void) 12763{ 12764 if (inst.operands[1].isreg) 12765 { 12766 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12767 12768 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12769 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12770 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12771 inst.instruction |= LOW4 (inst.operands[1].reg); 12772 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12773 inst.instruction |= neon_quad (rs) << 6; 12774 } 12775 else 12776 { 12777 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12778 neon_move_immediate (); 12779 } 12780 12781 inst.instruction = neon_dp_fixup (inst.instruction); 12782} 12783 12784/* Encode instructions of form: 12785 12786 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| 12787 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | 12788 12789*/ 12790 12791static void 12792neon_mixed_length (struct neon_type_el et, unsigned size) 12793{ 12794 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12795 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12796 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12797 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12798 inst.instruction |= LOW4 (inst.operands[2].reg); 12799 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12800 inst.instruction |= (et.type == NT_unsigned) << 24; 12801 inst.instruction |= neon_logbits (size) << 20; 12802 12803 inst.instruction = neon_dp_fixup (inst.instruction); 12804} 12805 12806static void 12807do_neon_dyadic_long (void) 12808{ 12809 /* FIXME: Type checking for lengthening op. */ 12810 struct neon_type_el et = neon_check_type (3, NS_QDD, 12811 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); 12812 neon_mixed_length (et, et.size); 12813} 12814 12815static void 12816do_neon_abal (void) 12817{ 12818 struct neon_type_el et = neon_check_type (3, NS_QDD, 12819 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); 12820 neon_mixed_length (et, et.size); 12821} 12822 12823static void 12824neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) 12825{ 12826 if (inst.operands[2].isscalar) 12827 { 12828 struct neon_type_el et = neon_check_type (3, NS_QDS, 12829 N_EQK | N_DBL, N_EQK, regtypes | N_KEY); 12830 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12831 neon_mul_mac (et, et.type == NT_unsigned); 12832 } 12833 else 12834 { 12835 struct neon_type_el et = neon_check_type (3, NS_QDD, 12836 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); 12837 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12838 neon_mixed_length (et, et.size); 12839 } 12840} 12841 12842static void 12843do_neon_mac_maybe_scalar_long (void) 12844{ 12845 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); 12846} 12847 12848static void 12849do_neon_dyadic_wide (void) 12850{ 12851 struct neon_type_el et = neon_check_type (3, NS_QQD, 12852 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); 12853 neon_mixed_length (et, et.size); 12854} 12855 12856static void 12857do_neon_dyadic_narrow (void) 12858{ 12859 struct neon_type_el et = neon_check_type (3, NS_QDD, 12860 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); 12861 /* Operand sign is unimportant, and the U bit is part of the opcode, 12862 so force the operand type to integer. */ 12863 et.type = NT_integer; 12864 neon_mixed_length (et, et.size / 2); 12865} 12866 12867static void 12868do_neon_mul_sat_scalar_long (void) 12869{ 12870 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); 12871} 12872 12873static void 12874do_neon_vmull (void) 12875{ 12876 if (inst.operands[2].isscalar) 12877 do_neon_mac_maybe_scalar_long (); 12878 else 12879 { 12880 struct neon_type_el et = neon_check_type (3, NS_QDD, 12881 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); 12882 if (et.type == NT_poly) 12883 inst.instruction = NEON_ENC_POLY (inst.instruction); 12884 else 12885 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12886 /* For polynomial encoding, size field must be 0b00 and the U bit must be 12887 zero. Should be OK as-is. */ 12888 neon_mixed_length (et, et.size); 12889 } 12890} 12891 12892static void 12893do_neon_ext (void) 12894{ 12895 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); 12896 struct neon_type_el et = neon_check_type (3, rs, 12897 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12898 unsigned imm = (inst.operands[3].imm * et.size) / 8; 12899 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range")); 12900 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12901 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12902 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12903 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12904 inst.instruction |= LOW4 (inst.operands[2].reg); 12905 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12906 inst.instruction |= neon_quad (rs) << 6; 12907 inst.instruction |= imm << 8; 12908 12909 inst.instruction = neon_dp_fixup (inst.instruction); 12910} 12911 12912static void 12913do_neon_rev (void) 12914{ 12915 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12916 struct neon_type_el et = neon_check_type (2, rs, 12917 N_EQK, N_8 | N_16 | N_32 | N_KEY); 12918 unsigned op = (inst.instruction >> 7) & 3; 12919 /* N (width of reversed regions) is encoded as part of the bitmask. We 12920 extract it here to check the elements to be reversed are smaller. 12921 Otherwise we'd get a reserved instruction. */ 12922 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; 12923 assert (elsize != 0); 12924 constraint (et.size >= elsize, 12925 _("elements must be smaller than reversal region")); 12926 neon_two_same (neon_quad (rs), 1, et.size); 12927} 12928 12929static void 12930do_neon_dup (void) 12931{ 12932 if (inst.operands[1].isscalar) 12933 { 12934 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); 12935 struct neon_type_el et = neon_check_type (2, rs, 12936 N_EQK, N_8 | N_16 | N_32 | N_KEY); 12937 unsigned sizebits = et.size >> 3; 12938 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); 12939 int logsize = neon_logbits (et.size); 12940 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; 12941 12942 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) 12943 return; 12944 12945 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12946 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12947 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12948 inst.instruction |= LOW4 (dm); 12949 inst.instruction |= HI1 (dm) << 5; 12950 inst.instruction |= neon_quad (rs) << 6; 12951 inst.instruction |= x << 17; 12952 inst.instruction |= sizebits << 16; 12953 12954 inst.instruction = neon_dp_fixup (inst.instruction); 12955 } 12956 else 12957 { 12958 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); 12959 struct neon_type_el et = neon_check_type (2, rs, 12960 N_8 | N_16 | N_32 | N_KEY, N_EQK); 12961 /* Duplicate ARM register to lanes of vector. */ 12962 inst.instruction = NEON_ENC_ARMREG (inst.instruction); 12963 switch (et.size) 12964 { 12965 case 8: inst.instruction |= 0x400000; break; 12966 case 16: inst.instruction |= 0x000020; break; 12967 case 32: inst.instruction |= 0x000000; break; 12968 default: break; 12969 } 12970 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 12971 inst.instruction |= LOW4 (inst.operands[0].reg) << 16; 12972 inst.instruction |= HI1 (inst.operands[0].reg) << 7; 12973 inst.instruction |= neon_quad (rs) << 21; 12974 /* The encoding for this instruction is identical for the ARM and Thumb 12975 variants, except for the condition field. */ 12976 do_vfp_cond_or_thumb (); 12977 } 12978} 12979 12980/* VMOV has particularly many variations. It can be one of: 12981 0. VMOV<c><q> <Qd>, <Qm> 12982 1. VMOV<c><q> <Dd>, <Dm> 12983 (Register operations, which are VORR with Rm = Rn.) 12984 2. VMOV<c><q>.<dt> <Qd>, #<imm> 12985 3. VMOV<c><q>.<dt> <Dd>, #<imm> 12986 (Immediate loads.) 12987 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> 12988 (ARM register to scalar.) 12989 5. VMOV<c><q> <Dm>, <Rd>, <Rn> 12990 (Two ARM registers to vector.) 12991 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> 12992 (Scalar to ARM register.) 12993 7. VMOV<c><q> <Rd>, <Rn>, <Dm> 12994 (Vector to two ARM registers.) 12995 8. VMOV.F32 <Sd>, <Sm> 12996 9. VMOV.F64 <Dd>, <Dm> 12997 (VFP register moves.) 12998 10. VMOV.F32 <Sd>, #imm 12999 11. VMOV.F64 <Dd>, #imm 13000 (VFP float immediate load.) 13001 12. VMOV <Rd>, <Sm> 13002 (VFP single to ARM reg.) 13003 13. VMOV <Sd>, <Rm> 13004 (ARM reg to VFP single.) 13005 14. VMOV <Rd>, <Re>, <Sn>, <Sm> 13006 (Two ARM regs to two VFP singles.) 13007 15. VMOV <Sd>, <Se>, <Rn>, <Rm> 13008 (Two VFP singles to two ARM regs.) 13009 13010 These cases can be disambiguated using neon_select_shape, except cases 1/9 13011 and 3/11 which depend on the operand type too. 13012 13013 All the encoded bits are hardcoded by this function. 13014 13015 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). 13016 Cases 5, 7 may be used with VFPv2 and above. 13017 13018 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you 13019 can specify a type where it doesn't make sense to, and is ignored). 13020*/ 13021 13022static void 13023do_neon_mov (void) 13024{ 13025 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, 13026 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, 13027 NS_NULL); 13028 struct neon_type_el et; 13029 const char *ldconst = 0; 13030 13031 switch (rs) 13032 { 13033 case NS_DD: /* case 1/9. */ 13034 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13035 /* It is not an error here if no type is given. */ 13036 inst.error = NULL; 13037 if (et.type == NT_float && et.size == 64) 13038 { 13039 do_vfp_nsyn_opcode ("fcpyd"); 13040 break; 13041 } 13042 /* fall through. */ 13043 13044 case NS_QQ: /* case 0/1. */ 13045 { 13046 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13047 return; 13048 /* The architecture manual I have doesn't explicitly state which 13049 value the U bit should have for register->register moves, but 13050 the equivalent VORR instruction has U = 0, so do that. */ 13051 inst.instruction = 0x0200110; 13052 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13053 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13054 inst.instruction |= LOW4 (inst.operands[1].reg); 13055 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13056 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13057 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13058 inst.instruction |= neon_quad (rs) << 6; 13059 13060 inst.instruction = neon_dp_fixup (inst.instruction); 13061 } 13062 break; 13063 13064 case NS_DI: /* case 3/11. */ 13065 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13066 inst.error = NULL; 13067 if (et.type == NT_float && et.size == 64) 13068 { 13069 /* case 11 (fconstd). */ 13070 ldconst = "fconstd"; 13071 goto encode_fconstd; 13072 } 13073 /* fall through. */ 13074 13075 case NS_QI: /* case 2/3. */ 13076 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13077 return; 13078 inst.instruction = 0x0800010; 13079 neon_move_immediate (); 13080 inst.instruction = neon_dp_fixup (inst.instruction); 13081 break; 13082 13083 case NS_SR: /* case 4. */ 13084 { 13085 unsigned bcdebits = 0; 13086 struct neon_type_el et = neon_check_type (2, NS_NULL, 13087 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13088 int logsize = neon_logbits (et.size); 13089 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); 13090 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); 13091 13092 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13093 _(BAD_FPU)); 13094 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13095 && et.size != 32, _(BAD_FPU)); 13096 constraint (et.type == NT_invtype, _("bad type for scalar")); 13097 constraint (x >= 64 / et.size, _("scalar index out of range")); 13098 13099 switch (et.size) 13100 { 13101 case 8: bcdebits = 0x8; break; 13102 case 16: bcdebits = 0x1; break; 13103 case 32: bcdebits = 0x0; break; 13104 default: ; 13105 } 13106 13107 bcdebits |= x << logsize; 13108 13109 inst.instruction = 0xe000b10; 13110 do_vfp_cond_or_thumb (); 13111 inst.instruction |= LOW4 (dn) << 16; 13112 inst.instruction |= HI1 (dn) << 7; 13113 inst.instruction |= inst.operands[1].reg << 12; 13114 inst.instruction |= (bcdebits & 3) << 5; 13115 inst.instruction |= (bcdebits >> 2) << 21; 13116 } 13117 break; 13118 13119 case NS_DRR: /* case 5 (fmdrr). */ 13120 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13121 _(BAD_FPU)); 13122 13123 inst.instruction = 0xc400b10; 13124 do_vfp_cond_or_thumb (); 13125 inst.instruction |= LOW4 (inst.operands[0].reg); 13126 inst.instruction |= HI1 (inst.operands[0].reg) << 5; 13127 inst.instruction |= inst.operands[1].reg << 12; 13128 inst.instruction |= inst.operands[2].reg << 16; 13129 break; 13130 13131 case NS_RS: /* case 6. */ 13132 { 13133 struct neon_type_el et = neon_check_type (2, NS_NULL, 13134 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); 13135 unsigned logsize = neon_logbits (et.size); 13136 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); 13137 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); 13138 unsigned abcdebits = 0; 13139 13140 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13141 _(BAD_FPU)); 13142 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13143 && et.size != 32, _(BAD_FPU)); 13144 constraint (et.type == NT_invtype, _("bad type for scalar")); 13145 constraint (x >= 64 / et.size, _("scalar index out of range")); 13146 13147 switch (et.size) 13148 { 13149 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; 13150 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; 13151 case 32: abcdebits = 0x00; break; 13152 default: ; 13153 } 13154 13155 abcdebits |= x << logsize; 13156 inst.instruction = 0xe100b10; 13157 do_vfp_cond_or_thumb (); 13158 inst.instruction |= LOW4 (dn) << 16; 13159 inst.instruction |= HI1 (dn) << 7; 13160 inst.instruction |= inst.operands[0].reg << 12; 13161 inst.instruction |= (abcdebits & 3) << 5; 13162 inst.instruction |= (abcdebits >> 2) << 21; 13163 } 13164 break; 13165 13166 case NS_RRD: /* case 7 (fmrrd). */ 13167 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13168 _(BAD_FPU)); 13169 13170 inst.instruction = 0xc500b10; 13171 do_vfp_cond_or_thumb (); 13172 inst.instruction |= inst.operands[0].reg << 12; 13173 inst.instruction |= inst.operands[1].reg << 16; 13174 inst.instruction |= LOW4 (inst.operands[2].reg); 13175 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13176 break; 13177 13178 case NS_FF: /* case 8 (fcpys). */ 13179 do_vfp_nsyn_opcode ("fcpys"); 13180 break; 13181 13182 case NS_FI: /* case 10 (fconsts). */ 13183 ldconst = "fconsts"; 13184 encode_fconstd: 13185 if (is_quarter_float (inst.operands[1].imm)) 13186 { 13187 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); 13188 do_vfp_nsyn_opcode (ldconst); 13189 } 13190 else 13191 first_error (_("immediate out of range")); 13192 break; 13193 13194 case NS_RF: /* case 12 (fmrs). */ 13195 do_vfp_nsyn_opcode ("fmrs"); 13196 break; 13197 13198 case NS_FR: /* case 13 (fmsr). */ 13199 do_vfp_nsyn_opcode ("fmsr"); 13200 break; 13201 13202 /* The encoders for the fmrrs and fmsrr instructions expect three operands 13203 (one of which is a list), but we have parsed four. Do some fiddling to 13204 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 13205 expect. */ 13206 case NS_RRFF: /* case 14 (fmrrs). */ 13207 constraint (inst.operands[3].reg != inst.operands[2].reg + 1, 13208 _("VFP registers must be adjacent")); 13209 inst.operands[2].imm = 2; 13210 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13211 do_vfp_nsyn_opcode ("fmrrs"); 13212 break; 13213 13214 case NS_FFRR: /* case 15 (fmsrr). */ 13215 constraint (inst.operands[1].reg != inst.operands[0].reg + 1, 13216 _("VFP registers must be adjacent")); 13217 inst.operands[1] = inst.operands[2]; 13218 inst.operands[2] = inst.operands[3]; 13219 inst.operands[0].imm = 2; 13220 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13221 do_vfp_nsyn_opcode ("fmsrr"); 13222 break; 13223 13224 default: 13225 abort (); 13226 } 13227} 13228 13229static void 13230do_neon_rshift_round_imm (void) 13231{ 13232 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13233 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 13234 int imm = inst.operands[2].imm; 13235 13236 /* imm == 0 case is encoded as VMOV for V{R}SHR. */ 13237 if (imm == 0) 13238 { 13239 inst.operands[2].present = 0; 13240 do_neon_mov (); 13241 return; 13242 } 13243 13244 constraint (imm < 1 || (unsigned)imm > et.size, 13245 _("immediate out of range for shift")); 13246 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 13247 et.size - imm); 13248} 13249 13250static void 13251do_neon_movl (void) 13252{ 13253 struct neon_type_el et = neon_check_type (2, NS_QD, 13254 N_EQK | N_DBL, N_SU_32 | N_KEY); 13255 unsigned sizebits = et.size >> 3; 13256 inst.instruction |= sizebits << 19; 13257 neon_two_same (0, et.type == NT_unsigned, -1); 13258} 13259 13260static void 13261do_neon_trn (void) 13262{ 13263 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13264 struct neon_type_el et = neon_check_type (2, rs, 13265 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13266 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 13267 neon_two_same (neon_quad (rs), 1, et.size); 13268} 13269 13270static void 13271do_neon_zip_uzp (void) 13272{ 13273 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13274 struct neon_type_el et = neon_check_type (2, rs, 13275 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13276 if (rs == NS_DD && et.size == 32) 13277 { 13278 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ 13279 inst.instruction = N_MNEM_vtrn; 13280 do_neon_trn (); 13281 return; 13282 } 13283 neon_two_same (neon_quad (rs), 1, et.size); 13284} 13285 13286static void 13287do_neon_sat_abs_neg (void) 13288{ 13289 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13290 struct neon_type_el et = neon_check_type (2, rs, 13291 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13292 neon_two_same (neon_quad (rs), 1, et.size); 13293} 13294 13295static void 13296do_neon_pair_long (void) 13297{ 13298 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13299 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); 13300 /* Unsigned is encoded in OP field (bit 7) for these instruction. */ 13301 inst.instruction |= (et.type == NT_unsigned) << 7; 13302 neon_two_same (neon_quad (rs), 1, et.size); 13303} 13304 13305static void 13306do_neon_recip_est (void) 13307{ 13308 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13309 struct neon_type_el et = neon_check_type (2, rs, 13310 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); 13311 inst.instruction |= (et.type == NT_float) << 8; 13312 neon_two_same (neon_quad (rs), 1, et.size); 13313} 13314 13315static void 13316do_neon_cls (void) 13317{ 13318 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13319 struct neon_type_el et = neon_check_type (2, rs, 13320 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13321 neon_two_same (neon_quad (rs), 1, et.size); 13322} 13323 13324static void 13325do_neon_clz (void) 13326{ 13327 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13328 struct neon_type_el et = neon_check_type (2, rs, 13329 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); 13330 neon_two_same (neon_quad (rs), 1, et.size); 13331} 13332 13333static void 13334do_neon_cnt (void) 13335{ 13336 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13337 struct neon_type_el et = neon_check_type (2, rs, 13338 N_EQK | N_INT, N_8 | N_KEY); 13339 neon_two_same (neon_quad (rs), 1, et.size); 13340} 13341 13342static void 13343do_neon_swp (void) 13344{ 13345 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13346 neon_two_same (neon_quad (rs), 1, -1); 13347} 13348 13349static void 13350do_neon_tbl_tbx (void) 13351{ 13352 unsigned listlenbits; 13353 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); 13354 13355 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) 13356 { 13357 first_error (_("bad list length for table lookup")); 13358 return; 13359 } 13360 13361 listlenbits = inst.operands[1].imm - 1; 13362 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13363 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13364 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13365 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13366 inst.instruction |= LOW4 (inst.operands[2].reg); 13367 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13368 inst.instruction |= listlenbits << 8; 13369 13370 inst.instruction = neon_dp_fixup (inst.instruction); 13371} 13372 13373static void 13374do_neon_ldm_stm (void) 13375{ 13376 /* P, U and L bits are part of bitmask. */ 13377 int is_dbmode = (inst.instruction & (1 << 24)) != 0; 13378 unsigned offsetbits = inst.operands[1].imm * 2; 13379 13380 if (inst.operands[1].issingle) 13381 { 13382 do_vfp_nsyn_ldm_stm (is_dbmode); 13383 return; 13384 } 13385 13386 constraint (is_dbmode && !inst.operands[0].writeback, 13387 _("writeback (!) must be used for VLDMDB and VSTMDB")); 13388 13389 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, 13390 _("register list must contain at least 1 and at most 16 " 13391 "registers")); 13392 13393 inst.instruction |= inst.operands[0].reg << 16; 13394 inst.instruction |= inst.operands[0].writeback << 21; 13395 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13396 inst.instruction |= HI1 (inst.operands[1].reg) << 22; 13397 13398 inst.instruction |= offsetbits; 13399 13400 do_vfp_cond_or_thumb (); 13401} 13402 13403static void 13404do_neon_ldr_str (void) 13405{ 13406 int is_ldr = (inst.instruction & (1 << 20)) != 0; 13407 13408 if (inst.operands[0].issingle) 13409 { 13410 if (is_ldr) 13411 do_vfp_nsyn_opcode ("flds"); 13412 else 13413 do_vfp_nsyn_opcode ("fsts"); 13414 } 13415 else 13416 { 13417 if (is_ldr) 13418 do_vfp_nsyn_opcode ("fldd"); 13419 else 13420 do_vfp_nsyn_opcode ("fstd"); 13421 } 13422} 13423 13424/* "interleave" version also handles non-interleaving register VLD1/VST1 13425 instructions. */ 13426 13427static void 13428do_neon_ld_st_interleave (void) 13429{ 13430 struct neon_type_el et = neon_check_type (1, NS_NULL, 13431 N_8 | N_16 | N_32 | N_64); 13432 unsigned alignbits = 0; 13433 unsigned idx; 13434 /* The bits in this table go: 13435 0: register stride of one (0) or two (1) 13436 1,2: register list length, minus one (1, 2, 3, 4). 13437 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). 13438 We use -1 for invalid entries. */ 13439 const int typetable[] = 13440 { 13441 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ 13442 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ 13443 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ 13444 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ 13445 }; 13446 int typebits; 13447 13448 if (et.type == NT_invtype) 13449 return; 13450 13451 if (inst.operands[1].immisalign) 13452 switch (inst.operands[1].imm >> 8) 13453 { 13454 case 64: alignbits = 1; break; 13455 case 128: 13456 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13457 goto bad_alignment; 13458 alignbits = 2; 13459 break; 13460 case 256: 13461 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13462 goto bad_alignment; 13463 alignbits = 3; 13464 break; 13465 default: 13466 bad_alignment: 13467 first_error (_("bad alignment")); 13468 return; 13469 } 13470 13471 inst.instruction |= alignbits << 4; 13472 inst.instruction |= neon_logbits (et.size) << 6; 13473 13474 /* Bits [4:6] of the immediate in a list specifier encode register stride 13475 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of 13476 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look 13477 up the right value for "type" in a table based on this value and the given 13478 list style, then stick it back. */ 13479 idx = ((inst.operands[0].imm >> 4) & 7) 13480 | (((inst.instruction >> 8) & 3) << 3); 13481 13482 typebits = typetable[idx]; 13483 13484 constraint (typebits == -1, _("bad list type for instruction")); 13485 13486 inst.instruction &= ~0xf00; 13487 inst.instruction |= typebits << 8; 13488} 13489 13490/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. 13491 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 13492 otherwise. The variable arguments are a list of pairs of legal (size, align) 13493 values, terminated with -1. */ 13494 13495static int 13496neon_alignment_bit (int size, int align, int *do_align, ...) 13497{ 13498 va_list ap; 13499 int result = FAIL, thissize, thisalign; 13500 13501 if (!inst.operands[1].immisalign) 13502 { 13503 *do_align = 0; 13504 return SUCCESS; 13505 } 13506 13507 va_start (ap, do_align); 13508 13509 do 13510 { 13511 thissize = va_arg (ap, int); 13512 if (thissize == -1) 13513 break; 13514 thisalign = va_arg (ap, int); 13515 13516 if (size == thissize && align == thisalign) 13517 result = SUCCESS; 13518 } 13519 while (result != SUCCESS); 13520 13521 va_end (ap); 13522 13523 if (result == SUCCESS) 13524 *do_align = 1; 13525 else 13526 first_error (_("unsupported alignment for instruction")); 13527 13528 return result; 13529} 13530 13531static void 13532do_neon_ld_st_lane (void) 13533{ 13534 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13535 int align_good, do_align = 0; 13536 int logsize = neon_logbits (et.size); 13537 int align = inst.operands[1].imm >> 8; 13538 int n = (inst.instruction >> 8) & 3; 13539 int max_el = 64 / et.size; 13540 13541 if (et.type == NT_invtype) 13542 return; 13543 13544 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, 13545 _("bad list length")); 13546 constraint (NEON_LANE (inst.operands[0].imm) >= max_el, 13547 _("scalar index out of range")); 13548 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 13549 && et.size == 8, 13550 _("stride of 2 unavailable when element size is 8")); 13551 13552 switch (n) 13553 { 13554 case 0: /* VLD1 / VST1. */ 13555 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, 13556 32, 32, -1); 13557 if (align_good == FAIL) 13558 return; 13559 if (do_align) 13560 { 13561 unsigned alignbits = 0; 13562 switch (et.size) 13563 { 13564 case 16: alignbits = 0x1; break; 13565 case 32: alignbits = 0x3; break; 13566 default: ; 13567 } 13568 inst.instruction |= alignbits << 4; 13569 } 13570 break; 13571 13572 case 1: /* VLD2 / VST2. */ 13573 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, 13574 32, 64, -1); 13575 if (align_good == FAIL) 13576 return; 13577 if (do_align) 13578 inst.instruction |= 1 << 4; 13579 break; 13580 13581 case 2: /* VLD3 / VST3. */ 13582 constraint (inst.operands[1].immisalign, 13583 _("can't use alignment with this instruction")); 13584 break; 13585 13586 case 3: /* VLD4 / VST4. */ 13587 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13588 16, 64, 32, 64, 32, 128, -1); 13589 if (align_good == FAIL) 13590 return; 13591 if (do_align) 13592 { 13593 unsigned alignbits = 0; 13594 switch (et.size) 13595 { 13596 case 8: alignbits = 0x1; break; 13597 case 16: alignbits = 0x1; break; 13598 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; 13599 default: ; 13600 } 13601 inst.instruction |= alignbits << 4; 13602 } 13603 break; 13604 13605 default: ; 13606 } 13607 13608 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ 13609 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13610 inst.instruction |= 1 << (4 + logsize); 13611 13612 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); 13613 inst.instruction |= logsize << 10; 13614} 13615 13616/* Encode single n-element structure to all lanes VLD<n> instructions. */ 13617 13618static void 13619do_neon_ld_dup (void) 13620{ 13621 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13622 int align_good, do_align = 0; 13623 13624 if (et.type == NT_invtype) 13625 return; 13626 13627 switch ((inst.instruction >> 8) & 3) 13628 { 13629 case 0: /* VLD1. */ 13630 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); 13631 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13632 &do_align, 16, 16, 32, 32, -1); 13633 if (align_good == FAIL) 13634 return; 13635 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) 13636 { 13637 case 1: break; 13638 case 2: inst.instruction |= 1 << 5; break; 13639 default: first_error (_("bad list length")); return; 13640 } 13641 inst.instruction |= neon_logbits (et.size) << 6; 13642 break; 13643 13644 case 1: /* VLD2. */ 13645 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13646 &do_align, 8, 16, 16, 32, 32, 64, -1); 13647 if (align_good == FAIL) 13648 return; 13649 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, 13650 _("bad list length")); 13651 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13652 inst.instruction |= 1 << 5; 13653 inst.instruction |= neon_logbits (et.size) << 6; 13654 break; 13655 13656 case 2: /* VLD3. */ 13657 constraint (inst.operands[1].immisalign, 13658 _("can't use alignment with this instruction")); 13659 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, 13660 _("bad list length")); 13661 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13662 inst.instruction |= 1 << 5; 13663 inst.instruction |= neon_logbits (et.size) << 6; 13664 break; 13665 13666 case 3: /* VLD4. */ 13667 { 13668 int align = inst.operands[1].imm >> 8; 13669 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13670 16, 64, 32, 64, 32, 128, -1); 13671 if (align_good == FAIL) 13672 return; 13673 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, 13674 _("bad list length")); 13675 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13676 inst.instruction |= 1 << 5; 13677 if (et.size == 32 && align == 128) 13678 inst.instruction |= 0x3 << 6; 13679 else 13680 inst.instruction |= neon_logbits (et.size) << 6; 13681 } 13682 break; 13683 13684 default: ; 13685 } 13686 13687 inst.instruction |= do_align << 4; 13688} 13689 13690/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those 13691 apart from bits [11:4]. */ 13692 13693static void 13694do_neon_ldx_stx (void) 13695{ 13696 switch (NEON_LANE (inst.operands[0].imm)) 13697 { 13698 case NEON_INTERLEAVE_LANES: 13699 inst.instruction = NEON_ENC_INTERLV (inst.instruction); 13700 do_neon_ld_st_interleave (); 13701 break; 13702 13703 case NEON_ALL_LANES: 13704 inst.instruction = NEON_ENC_DUP (inst.instruction); 13705 do_neon_ld_dup (); 13706 break; 13707 13708 default: 13709 inst.instruction = NEON_ENC_LANE (inst.instruction); 13710 do_neon_ld_st_lane (); 13711 } 13712 13713 /* L bit comes from bit mask. */ 13714 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13715 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13716 inst.instruction |= inst.operands[1].reg << 16; 13717 13718 if (inst.operands[1].postind) 13719 { 13720 int postreg = inst.operands[1].imm & 0xf; 13721 constraint (!inst.operands[1].immisreg, 13722 _("post-index must be a register")); 13723 constraint (postreg == 0xd || postreg == 0xf, 13724 _("bad register for post-index")); 13725 inst.instruction |= postreg; 13726 } 13727 else if (inst.operands[1].writeback) 13728 { 13729 inst.instruction |= 0xd; 13730 } 13731 else 13732 inst.instruction |= 0xf; 13733 13734 if (thumb_mode) 13735 inst.instruction |= 0xf9000000; 13736 else 13737 inst.instruction |= 0xf4000000; 13738} 13739 13740 13741/* Overall per-instruction processing. */ 13742 13743/* We need to be able to fix up arbitrary expressions in some statements. 13744 This is so that we can handle symbols that are an arbitrary distance from 13745 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), 13746 which returns part of an address in a form which will be valid for 13747 a data instruction. We do this by pushing the expression into a symbol 13748 in the expr_section, and creating a fix for that. */ 13749 13750static void 13751fix_new_arm (fragS * frag, 13752 int where, 13753 short int size, 13754 expressionS * exp, 13755 int pc_rel, 13756 int reloc) 13757{ 13758 fixS * new_fix; 13759 13760 switch (exp->X_op) 13761 { 13762 case O_constant: 13763 case O_symbol: 13764 case O_add: 13765 case O_subtract: 13766 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); 13767 break; 13768 13769 default: 13770 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, 13771 pc_rel, reloc); 13772 break; 13773 } 13774 13775 /* Mark whether the fix is to a THUMB instruction, or an ARM 13776 instruction. */ 13777 new_fix->tc_fix_data = thumb_mode; 13778} 13779 13780/* Create a frg for an instruction requiring relaxation. */ 13781static void 13782output_relax_insn (void) 13783{ 13784 char * to; 13785 symbolS *sym; 13786 int offset; 13787 13788 /* The size of the instruction is unknown, so tie the debug info to the 13789 start of the instruction. */ 13790 dwarf2_emit_insn (0); 13791 13792 switch (inst.reloc.exp.X_op) 13793 { 13794 case O_symbol: 13795 sym = inst.reloc.exp.X_add_symbol; 13796 offset = inst.reloc.exp.X_add_number; 13797 break; 13798 case O_constant: 13799 sym = NULL; 13800 offset = inst.reloc.exp.X_add_number; 13801 break; 13802 default: 13803 sym = make_expr_symbol (&inst.reloc.exp); 13804 offset = 0; 13805 break; 13806 } 13807 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, 13808 inst.relax, sym, offset, NULL/*offset, opcode*/); 13809 md_number_to_chars (to, inst.instruction, THUMB_SIZE); 13810} 13811 13812/* Write a 32-bit thumb instruction to buf. */ 13813static void 13814put_thumb32_insn (char * buf, unsigned long insn) 13815{ 13816 md_number_to_chars (buf, insn >> 16, THUMB_SIZE); 13817 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); 13818} 13819 13820static void 13821output_inst (const char * str) 13822{ 13823 char * to = NULL; 13824 13825 if (inst.error) 13826 { 13827 as_bad ("%s -- `%s'", inst.error, str); 13828 return; 13829 } 13830 if (inst.relax) { 13831 output_relax_insn(); 13832 return; 13833 } 13834 if (inst.size == 0) 13835 return; 13836 13837 to = frag_more (inst.size); 13838 13839 if (thumb_mode && (inst.size > THUMB_SIZE)) 13840 { 13841 assert (inst.size == (2 * THUMB_SIZE)); 13842 put_thumb32_insn (to, inst.instruction); 13843 } 13844 else if (inst.size > INSN_SIZE) 13845 { 13846 assert (inst.size == (2 * INSN_SIZE)); 13847 md_number_to_chars (to, inst.instruction, INSN_SIZE); 13848 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); 13849 } 13850 else 13851 md_number_to_chars (to, inst.instruction, inst.size); 13852 13853 if (inst.reloc.type != BFD_RELOC_UNUSED) 13854 fix_new_arm (frag_now, to - frag_now->fr_literal, 13855 inst.size, & inst.reloc.exp, inst.reloc.pc_rel, 13856 inst.reloc.type); 13857 13858 dwarf2_emit_insn (inst.size); 13859} 13860 13861/* Tag values used in struct asm_opcode's tag field. */ 13862enum opcode_tag 13863{ 13864 OT_unconditional, /* Instruction cannot be conditionalized. 13865 The ARM condition field is still 0xE. */ 13866 OT_unconditionalF, /* Instruction cannot be conditionalized 13867 and carries 0xF in its ARM condition field. */ 13868 OT_csuffix, /* Instruction takes a conditional suffix. */ 13869 OT_csuffixF, /* Some forms of the instruction take a conditional 13870 suffix, others place 0xF where the condition field 13871 would be. */ 13872 OT_cinfix3, /* Instruction takes a conditional infix, 13873 beginning at character index 3. (In 13874 unified mode, it becomes a suffix.) */ 13875 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for 13876 tsts, cmps, cmns, and teqs. */ 13877 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at 13878 character index 3, even in unified mode. Used for 13879 legacy instructions where suffix and infix forms 13880 may be ambiguous. */ 13881 OT_csuf_or_in3, /* Instruction takes either a conditional 13882 suffix or an infix at character index 3. */ 13883 OT_odd_infix_unc, /* This is the unconditional variant of an 13884 instruction that takes a conditional infix 13885 at an unusual position. In unified mode, 13886 this variant will accept a suffix. */ 13887 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 13888 are the conditional variants of instructions that 13889 take conditional infixes in unusual positions. 13890 The infix appears at character index 13891 (tag - OT_odd_infix_0). These are not accepted 13892 in unified mode. */ 13893}; 13894 13895/* Subroutine of md_assemble, responsible for looking up the primary 13896 opcode from the mnemonic the user wrote. STR points to the 13897 beginning of the mnemonic. 13898 13899 This is not simply a hash table lookup, because of conditional 13900 variants. Most instructions have conditional variants, which are 13901 expressed with a _conditional affix_ to the mnemonic. If we were 13902 to encode each conditional variant as a literal string in the opcode 13903 table, it would have approximately 20,000 entries. 13904 13905 Most mnemonics take this affix as a suffix, and in unified syntax, 13906 'most' is upgraded to 'all'. However, in the divided syntax, some 13907 instructions take the affix as an infix, notably the s-variants of 13908 the arithmetic instructions. Of those instructions, all but six 13909 have the infix appear after the third character of the mnemonic. 13910 13911 Accordingly, the algorithm for looking up primary opcodes given 13912 an identifier is: 13913 13914 1. Look up the identifier in the opcode table. 13915 If we find a match, go to step U. 13916 13917 2. Look up the last two characters of the identifier in the 13918 conditions table. If we find a match, look up the first N-2 13919 characters of the identifier in the opcode table. If we 13920 find a match, go to step CE. 13921 13922 3. Look up the fourth and fifth characters of the identifier in 13923 the conditions table. If we find a match, extract those 13924 characters from the identifier, and look up the remaining 13925 characters in the opcode table. If we find a match, go 13926 to step CM. 13927 13928 4. Fail. 13929 13930 U. Examine the tag field of the opcode structure, in case this is 13931 one of the six instructions with its conditional infix in an 13932 unusual place. If it is, the tag tells us where to find the 13933 infix; look it up in the conditions table and set inst.cond 13934 accordingly. Otherwise, this is an unconditional instruction. 13935 Again set inst.cond accordingly. Return the opcode structure. 13936 13937 CE. Examine the tag field to make sure this is an instruction that 13938 should receive a conditional suffix. If it is not, fail. 13939 Otherwise, set inst.cond from the suffix we already looked up, 13940 and return the opcode structure. 13941 13942 CM. Examine the tag field to make sure this is an instruction that 13943 should receive a conditional infix after the third character. 13944 If it is not, fail. Otherwise, undo the edits to the current 13945 line of input and proceed as for case CE. */ 13946 13947static const struct asm_opcode * 13948opcode_lookup (char **str) 13949{ 13950 char *end, *base; 13951 char *affix; 13952 const struct asm_opcode *opcode; 13953 const struct asm_cond *cond; 13954 char save[2]; 13955 bfd_boolean neon_supported; 13956 13957 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1); 13958 13959 /* Scan up to the end of the mnemonic, which must end in white space, 13960 '.' (in unified mode, or for Neon instructions), or end of string. */ 13961 for (base = end = *str; *end != '\0'; end++) 13962 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.')) 13963 break; 13964 13965 if (end == base) 13966 return 0; 13967 13968 /* Handle a possible width suffix and/or Neon type suffix. */ 13969 if (end[0] == '.') 13970 { 13971 int offset = 2; 13972 13973 /* The .w and .n suffixes are only valid if the unified syntax is in 13974 use. */ 13975 if (unified_syntax && end[1] == 'w') 13976 inst.size_req = 4; 13977 else if (unified_syntax && end[1] == 'n') 13978 inst.size_req = 2; 13979 else 13980 offset = 0; 13981 13982 inst.vectype.elems = 0; 13983 13984 *str = end + offset; 13985 13986 if (end[offset] == '.') 13987 { 13988 /* See if we have a Neon type suffix (possible in either unified or 13989 non-unified ARM syntax mode). */ 13990 if (parse_neon_type (&inst.vectype, str) == FAIL) 13991 return 0; 13992 } 13993 else if (end[offset] != '\0' && end[offset] != ' ') 13994 return 0; 13995 } 13996 else 13997 *str = end; 13998 13999 /* Look for unaffixed or special-case affixed mnemonic. */ 14000 opcode = hash_find_n (arm_ops_hsh, base, end - base); 14001 if (opcode) 14002 { 14003 /* step U */ 14004 if (opcode->tag < OT_odd_infix_0) 14005 { 14006 inst.cond = COND_ALWAYS; 14007 return opcode; 14008 } 14009 14010 if (unified_syntax) 14011 as_warn (_("conditional infixes are deprecated in unified syntax")); 14012 affix = base + (opcode->tag - OT_odd_infix_0); 14013 cond = hash_find_n (arm_cond_hsh, affix, 2); 14014 assert (cond); 14015 14016 inst.cond = cond->value; 14017 return opcode; 14018 } 14019 14020 /* Cannot have a conditional suffix on a mnemonic of less than two 14021 characters. */ 14022 if (end - base < 3) 14023 return 0; 14024 14025 /* Look for suffixed mnemonic. */ 14026 affix = end - 2; 14027 cond = hash_find_n (arm_cond_hsh, affix, 2); 14028 opcode = hash_find_n (arm_ops_hsh, base, affix - base); 14029 if (opcode && cond) 14030 { 14031 /* step CE */ 14032 switch (opcode->tag) 14033 { 14034 case OT_cinfix3_legacy: 14035 /* Ignore conditional suffixes matched on infix only mnemonics. */ 14036 break; 14037 14038 case OT_cinfix3: 14039 case OT_cinfix3_deprecated: 14040 case OT_odd_infix_unc: 14041 if (!unified_syntax) 14042 return 0; 14043 /* else fall through */ 14044 14045 case OT_csuffix: 14046 case OT_csuffixF: 14047 case OT_csuf_or_in3: 14048 inst.cond = cond->value; 14049 return opcode; 14050 14051 case OT_unconditional: 14052 case OT_unconditionalF: 14053 if (thumb_mode) 14054 { 14055 inst.cond = cond->value; 14056 } 14057 else 14058 { 14059 /* delayed diagnostic */ 14060 inst.error = BAD_COND; 14061 inst.cond = COND_ALWAYS; 14062 } 14063 return opcode; 14064 14065 default: 14066 return 0; 14067 } 14068 } 14069 14070 /* Cannot have a usual-position infix on a mnemonic of less than 14071 six characters (five would be a suffix). */ 14072 if (end - base < 6) 14073 return 0; 14074 14075 /* Look for infixed mnemonic in the usual position. */ 14076 affix = base + 3; 14077 cond = hash_find_n (arm_cond_hsh, affix, 2); 14078 if (!cond) 14079 return 0; 14080 14081 memcpy (save, affix, 2); 14082 memmove (affix, affix + 2, (end - affix) - 2); 14083 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); 14084 memmove (affix + 2, affix, (end - affix) - 2); 14085 memcpy (affix, save, 2); 14086 14087 if (opcode 14088 && (opcode->tag == OT_cinfix3 14089 || opcode->tag == OT_cinfix3_deprecated 14090 || opcode->tag == OT_csuf_or_in3 14091 || opcode->tag == OT_cinfix3_legacy)) 14092 { 14093 /* step CM */ 14094 if (unified_syntax 14095 && (opcode->tag == OT_cinfix3 14096 || opcode->tag == OT_cinfix3_deprecated)) 14097 as_warn (_("conditional infixes are deprecated in unified syntax")); 14098 14099 inst.cond = cond->value; 14100 return opcode; 14101 } 14102 14103 return 0; 14104} 14105 14106void 14107md_assemble (char *str) 14108{ 14109 char *p = str; 14110 const struct asm_opcode * opcode; 14111 14112 /* Align the previous label if needed. */ 14113 if (last_label_seen != NULL) 14114 { 14115 symbol_set_frag (last_label_seen, frag_now); 14116 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); 14117 S_SET_SEGMENT (last_label_seen, now_seg); 14118 } 14119 14120 memset (&inst, '\0', sizeof (inst)); 14121 inst.reloc.type = BFD_RELOC_UNUSED; 14122 14123 opcode = opcode_lookup (&p); 14124 if (!opcode) 14125 { 14126 /* It wasn't an instruction, but it might be a register alias of 14127 the form alias .req reg, or a Neon .dn/.qn directive. */ 14128 if (!create_register_alias (str, p) 14129 && !create_neon_reg_alias (str, p)) 14130 as_bad (_("bad instruction `%s'"), str); 14131 14132 return; 14133 } 14134 14135 if (opcode->tag == OT_cinfix3_deprecated) 14136 as_warn (_("s suffix on comparison instruction is deprecated")); 14137 14138 /* The value which unconditional instructions should have in place of the 14139 condition field. */ 14140 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; 14141 14142 if (thumb_mode) 14143 { 14144 arm_feature_set variant; 14145 14146 variant = cpu_variant; 14147 /* Only allow coprocessor instructions on Thumb-2 capable devices. */ 14148 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) 14149 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); 14150 /* Check that this instruction is supported for this CPU. */ 14151 if (!opcode->tvariant 14152 || (thumb_mode == 1 14153 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) 14154 { 14155 as_bad (_("selected processor does not support `%s'"), str); 14156 return; 14157 } 14158 if (inst.cond != COND_ALWAYS && !unified_syntax 14159 && opcode->tencode != do_t_branch) 14160 { 14161 as_bad (_("Thumb does not support conditional execution")); 14162 return; 14163 } 14164 14165 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req) 14166 { 14167 /* Implicit require narrow instructions on Thumb-1. This avoids 14168 relaxation accidentally introducing Thumb-2 instructions. */ 14169 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23) 14170 inst.size_req = 2; 14171 } 14172 14173 /* Check conditional suffixes. */ 14174 if (current_it_mask) 14175 { 14176 int cond; 14177 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; 14178 current_it_mask <<= 1; 14179 current_it_mask &= 0x1f; 14180 /* The BKPT instruction is unconditional even in an IT block. */ 14181 if (!inst.error 14182 && cond != inst.cond && opcode->tencode != do_t_bkpt) 14183 { 14184 as_bad (_("incorrect condition in IT block")); 14185 return; 14186 } 14187 } 14188 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) 14189 { 14190 as_bad (_("thumb conditional instrunction not in IT block")); 14191 return; 14192 } 14193 14194 mapping_state (MAP_THUMB); 14195 inst.instruction = opcode->tvalue; 14196 14197 if (!parse_operands (p, opcode->operands)) 14198 opcode->tencode (); 14199 14200 /* Clear current_it_mask at the end of an IT block. */ 14201 if (current_it_mask == 0x10) 14202 current_it_mask = 0; 14203 14204 if (!(inst.error || inst.relax)) 14205 { 14206 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); 14207 inst.size = (inst.instruction > 0xffff ? 4 : 2); 14208 if (inst.size_req && inst.size_req != inst.size) 14209 { 14210 as_bad (_("cannot honor width suffix -- `%s'"), str); 14211 return; 14212 } 14213 } 14214 14215 /* Something has gone badly wrong if we try to relax a fixed size 14216 instruction. */ 14217 assert (inst.size_req == 0 || !inst.relax); 14218 14219 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14220 *opcode->tvariant); 14221 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly 14222 set those bits when Thumb-2 32-bit instructions are seen. ie. 14223 anything other than bl/blx. 14224 This is overly pessimistic for relaxable instructions. */ 14225 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) 14226 || inst.relax) 14227 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14228 arm_ext_v6t2); 14229 } 14230 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 14231 { 14232 /* Check that this instruction is supported for this CPU. */ 14233 if (!opcode->avariant || 14234 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) 14235 { 14236 as_bad (_("selected processor does not support `%s'"), str); 14237 return; 14238 } 14239 if (inst.size_req) 14240 { 14241 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); 14242 return; 14243 } 14244 14245 mapping_state (MAP_ARM); 14246 inst.instruction = opcode->avalue; 14247 if (opcode->tag == OT_unconditionalF) 14248 inst.instruction |= 0xF << 28; 14249 else 14250 inst.instruction |= inst.cond << 28; 14251 inst.size = INSN_SIZE; 14252 if (!parse_operands (p, opcode->operands)) 14253 opcode->aencode (); 14254 /* Arm mode bx is marked as both v4T and v5 because it's still required 14255 on a hypothetical non-thumb v5 core. */ 14256 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) 14257 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) 14258 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); 14259 else 14260 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 14261 *opcode->avariant); 14262 } 14263 else 14264 { 14265 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " 14266 "-- `%s'"), str); 14267 return; 14268 } 14269 output_inst (str); 14270} 14271 14272/* Various frobbings of labels and their addresses. */ 14273 14274void 14275arm_start_line_hook (void) 14276{ 14277 last_label_seen = NULL; 14278} 14279 14280void 14281arm_frob_label (symbolS * sym) 14282{ 14283 last_label_seen = sym; 14284 14285 ARM_SET_THUMB (sym, thumb_mode); 14286 14287#if defined OBJ_COFF || defined OBJ_ELF 14288 ARM_SET_INTERWORK (sym, support_interwork); 14289#endif 14290 14291 /* Note - do not allow local symbols (.Lxxx) to be labeled 14292 as Thumb functions. This is because these labels, whilst 14293 they exist inside Thumb code, are not the entry points for 14294 possible ARM->Thumb calls. Also, these labels can be used 14295 as part of a computed goto or switch statement. eg gcc 14296 can generate code that looks like this: 14297 14298 ldr r2, [pc, .Laaa] 14299 lsl r3, r3, #2 14300 ldr r2, [r3, r2] 14301 mov pc, r2 14302 14303 .Lbbb: .word .Lxxx 14304 .Lccc: .word .Lyyy 14305 ..etc... 14306 .Laaa: .word Lbbb 14307 14308 The first instruction loads the address of the jump table. 14309 The second instruction converts a table index into a byte offset. 14310 The third instruction gets the jump address out of the table. 14311 The fourth instruction performs the jump. 14312 14313 If the address stored at .Laaa is that of a symbol which has the 14314 Thumb_Func bit set, then the linker will arrange for this address 14315 to have the bottom bit set, which in turn would mean that the 14316 address computation performed by the third instruction would end 14317 up with the bottom bit set. Since the ARM is capable of unaligned 14318 word loads, the instruction would then load the incorrect address 14319 out of the jump table, and chaos would ensue. */ 14320 if (label_is_thumb_function_name 14321 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') 14322 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) 14323 { 14324 /* When the address of a Thumb function is taken the bottom 14325 bit of that address should be set. This will allow 14326 interworking between Arm and Thumb functions to work 14327 correctly. */ 14328 14329 THUMB_SET_FUNC (sym, 1); 14330 14331 label_is_thumb_function_name = FALSE; 14332 } 14333 14334 dwarf2_emit_label (sym); 14335} 14336 14337int 14338arm_data_in_code (void) 14339{ 14340 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) 14341 { 14342 *input_line_pointer = '/'; 14343 input_line_pointer += 5; 14344 *input_line_pointer = 0; 14345 return 1; 14346 } 14347 14348 return 0; 14349} 14350 14351char * 14352arm_canonicalize_symbol_name (char * name) 14353{ 14354 int len; 14355 14356 if (thumb_mode && (len = strlen (name)) > 5 14357 && streq (name + len - 5, "/data")) 14358 *(name + len - 5) = 0; 14359 14360 return name; 14361} 14362 14363/* Table of all register names defined by default. The user can 14364 define additional names with .req. Note that all register names 14365 should appear in both upper and lowercase variants. Some registers 14366 also have mixed-case names. */ 14367 14368#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } 14369#define REGNUM(p,n,t) REGDEF(p##n, n, t) 14370#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) 14371#define REGSET(p,t) \ 14372 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ 14373 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ 14374 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ 14375 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) 14376#define REGSETH(p,t) \ 14377 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ 14378 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ 14379 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ 14380 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) 14381#define REGSET2(p,t) \ 14382 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ 14383 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ 14384 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ 14385 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) 14386 14387static const struct reg_entry reg_names[] = 14388{ 14389 /* ARM integer registers. */ 14390 REGSET(r, RN), REGSET(R, RN), 14391 14392 /* ATPCS synonyms. */ 14393 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), 14394 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), 14395 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), 14396 14397 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), 14398 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), 14399 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), 14400 14401 /* Well-known aliases. */ 14402 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), 14403 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), 14404 14405 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), 14406 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), 14407 14408 /* Coprocessor numbers. */ 14409 REGSET(p, CP), REGSET(P, CP), 14410 14411 /* Coprocessor register numbers. The "cr" variants are for backward 14412 compatibility. */ 14413 REGSET(c, CN), REGSET(C, CN), 14414 REGSET(cr, CN), REGSET(CR, CN), 14415 14416 /* FPA registers. */ 14417 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), 14418 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), 14419 14420 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), 14421 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), 14422 14423 /* VFP SP registers. */ 14424 REGSET(s,VFS), REGSET(S,VFS), 14425 REGSETH(s,VFS), REGSETH(S,VFS), 14426 14427 /* VFP DP Registers. */ 14428 REGSET(d,VFD), REGSET(D,VFD), 14429 /* Extra Neon DP registers. */ 14430 REGSETH(d,VFD), REGSETH(D,VFD), 14431 14432 /* Neon QP registers. */ 14433 REGSET2(q,NQ), REGSET2(Q,NQ), 14434 14435 /* VFP control registers. */ 14436 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), 14437 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), 14438 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), 14439 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), 14440 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), 14441 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), 14442 14443 /* Maverick DSP coprocessor registers. */ 14444 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), 14445 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), 14446 14447 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), 14448 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), 14449 REGDEF(dspsc,0,DSPSC), 14450 14451 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), 14452 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), 14453 REGDEF(DSPSC,0,DSPSC), 14454 14455 /* iWMMXt data registers - p0, c0-15. */ 14456 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), 14457 14458 /* iWMMXt control registers - p1, c0-3. */ 14459 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), 14460 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), 14461 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), 14462 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), 14463 14464 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ 14465 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), 14466 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), 14467 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), 14468 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), 14469 14470 /* XScale accumulator registers. */ 14471 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), 14472}; 14473#undef REGDEF 14474#undef REGNUM 14475#undef REGSET 14476 14477/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled 14478 within psr_required_here. */ 14479static const struct asm_psr psrs[] = 14480{ 14481 /* Backward compatibility notation. Note that "all" is no longer 14482 truly all possible PSR bits. */ 14483 {"all", PSR_c | PSR_f}, 14484 {"flg", PSR_f}, 14485 {"ctl", PSR_c}, 14486 14487 /* Individual flags. */ 14488 {"f", PSR_f}, 14489 {"c", PSR_c}, 14490 {"x", PSR_x}, 14491 {"s", PSR_s}, 14492 /* Combinations of flags. */ 14493 {"fs", PSR_f | PSR_s}, 14494 {"fx", PSR_f | PSR_x}, 14495 {"fc", PSR_f | PSR_c}, 14496 {"sf", PSR_s | PSR_f}, 14497 {"sx", PSR_s | PSR_x}, 14498 {"sc", PSR_s | PSR_c}, 14499 {"xf", PSR_x | PSR_f}, 14500 {"xs", PSR_x | PSR_s}, 14501 {"xc", PSR_x | PSR_c}, 14502 {"cf", PSR_c | PSR_f}, 14503 {"cs", PSR_c | PSR_s}, 14504 {"cx", PSR_c | PSR_x}, 14505 {"fsx", PSR_f | PSR_s | PSR_x}, 14506 {"fsc", PSR_f | PSR_s | PSR_c}, 14507 {"fxs", PSR_f | PSR_x | PSR_s}, 14508 {"fxc", PSR_f | PSR_x | PSR_c}, 14509 {"fcs", PSR_f | PSR_c | PSR_s}, 14510 {"fcx", PSR_f | PSR_c | PSR_x}, 14511 {"sfx", PSR_s | PSR_f | PSR_x}, 14512 {"sfc", PSR_s | PSR_f | PSR_c}, 14513 {"sxf", PSR_s | PSR_x | PSR_f}, 14514 {"sxc", PSR_s | PSR_x | PSR_c}, 14515 {"scf", PSR_s | PSR_c | PSR_f}, 14516 {"scx", PSR_s | PSR_c | PSR_x}, 14517 {"xfs", PSR_x | PSR_f | PSR_s}, 14518 {"xfc", PSR_x | PSR_f | PSR_c}, 14519 {"xsf", PSR_x | PSR_s | PSR_f}, 14520 {"xsc", PSR_x | PSR_s | PSR_c}, 14521 {"xcf", PSR_x | PSR_c | PSR_f}, 14522 {"xcs", PSR_x | PSR_c | PSR_s}, 14523 {"cfs", PSR_c | PSR_f | PSR_s}, 14524 {"cfx", PSR_c | PSR_f | PSR_x}, 14525 {"csf", PSR_c | PSR_s | PSR_f}, 14526 {"csx", PSR_c | PSR_s | PSR_x}, 14527 {"cxf", PSR_c | PSR_x | PSR_f}, 14528 {"cxs", PSR_c | PSR_x | PSR_s}, 14529 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, 14530 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, 14531 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, 14532 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, 14533 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, 14534 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, 14535 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, 14536 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, 14537 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, 14538 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, 14539 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, 14540 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, 14541 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, 14542 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, 14543 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, 14544 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, 14545 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, 14546 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, 14547 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, 14548 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, 14549 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, 14550 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, 14551 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, 14552 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, 14553}; 14554 14555/* Table of V7M psr names. */ 14556static const struct asm_psr v7m_psrs[] = 14557{ 14558 {"apsr", 0 }, {"APSR", 0 }, 14559 {"iapsr", 1 }, {"IAPSR", 1 }, 14560 {"eapsr", 2 }, {"EAPSR", 2 }, 14561 {"psr", 3 }, {"PSR", 3 }, 14562 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, 14563 {"ipsr", 5 }, {"IPSR", 5 }, 14564 {"epsr", 6 }, {"EPSR", 6 }, 14565 {"iepsr", 7 }, {"IEPSR", 7 }, 14566 {"msp", 8 }, {"MSP", 8 }, 14567 {"psp", 9 }, {"PSP", 9 }, 14568 {"primask", 16}, {"PRIMASK", 16}, 14569 {"basepri", 17}, {"BASEPRI", 17}, 14570 {"basepri_max", 18}, {"BASEPRI_MAX", 18}, 14571 {"faultmask", 19}, {"FAULTMASK", 19}, 14572 {"control", 20}, {"CONTROL", 20} 14573}; 14574 14575/* Table of all shift-in-operand names. */ 14576static const struct asm_shift_name shift_names [] = 14577{ 14578 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, 14579 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, 14580 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, 14581 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, 14582 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, 14583 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } 14584}; 14585 14586/* Table of all explicit relocation names. */ 14587#ifdef OBJ_ELF 14588static struct reloc_entry reloc_names[] = 14589{ 14590 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, 14591 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, 14592 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, 14593 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, 14594 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, 14595 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, 14596 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, 14597 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, 14598 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, 14599 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, 14600 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} 14601}; 14602#endif 14603 14604/* Table of all conditional affixes. 0xF is not defined as a condition code. */ 14605static const struct asm_cond conds[] = 14606{ 14607 {"eq", 0x0}, 14608 {"ne", 0x1}, 14609 {"cs", 0x2}, {"hs", 0x2}, 14610 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, 14611 {"mi", 0x4}, 14612 {"pl", 0x5}, 14613 {"vs", 0x6}, 14614 {"vc", 0x7}, 14615 {"hi", 0x8}, 14616 {"ls", 0x9}, 14617 {"ge", 0xa}, 14618 {"lt", 0xb}, 14619 {"gt", 0xc}, 14620 {"le", 0xd}, 14621 {"al", 0xe} 14622}; 14623 14624static struct asm_barrier_opt barrier_opt_names[] = 14625{ 14626 { "sy", 0xf }, 14627 { "un", 0x7 }, 14628 { "st", 0xe }, 14629 { "unst", 0x6 } 14630}; 14631 14632/* Table of ARM-format instructions. */ 14633 14634/* Macros for gluing together operand strings. N.B. In all cases 14635 other than OPS0, the trailing OP_stop comes from default 14636 zero-initialization of the unspecified elements of the array. */ 14637#define OPS0() { OP_stop, } 14638#define OPS1(a) { OP_##a, } 14639#define OPS2(a,b) { OP_##a,OP_##b, } 14640#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } 14641#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } 14642#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } 14643#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } 14644 14645/* These macros abstract out the exact format of the mnemonic table and 14646 save some repeated characters. */ 14647 14648/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ 14649#define TxCE(mnem, op, top, nops, ops, ae, te) \ 14650 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ 14651 THUMB_VARIANT, do_##ae, do_##te } 14652 14653/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for 14654 a T_MNEM_xyz enumerator. */ 14655#define TCE(mnem, aop, top, nops, ops, ae, te) \ 14656 TxCE(mnem, aop, 0x##top, nops, ops, ae, te) 14657#define tCE(mnem, aop, top, nops, ops, ae, te) \ 14658 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14659 14660/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional 14661 infix after the third character. */ 14662#define TxC3(mnem, op, top, nops, ops, ae, te) \ 14663 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ 14664 THUMB_VARIANT, do_##ae, do_##te } 14665#define TxC3w(mnem, op, top, nops, ops, ae, te) \ 14666 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ 14667 THUMB_VARIANT, do_##ae, do_##te } 14668#define TC3(mnem, aop, top, nops, ops, ae, te) \ 14669 TxC3(mnem, aop, 0x##top, nops, ops, ae, te) 14670#define TC3w(mnem, aop, top, nops, ops, ae, te) \ 14671 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te) 14672#define tC3(mnem, aop, top, nops, ops, ae, te) \ 14673 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14674#define tC3w(mnem, aop, top, nops, ops, ae, te) \ 14675 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14676 14677/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to 14678 appear in the condition table. */ 14679#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ 14680 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14681 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } 14682 14683#define TxCM(m1, m2, op, top, nops, ops, ae, te) \ 14684 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ 14685 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ 14686 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ 14687 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ 14688 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ 14689 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ 14690 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ 14691 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ 14692 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ 14693 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ 14694 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ 14695 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ 14696 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ 14697 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ 14698 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ 14699 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ 14700 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ 14701 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ 14702 TxCM_(m1, al, m2, op, top, nops, ops, ae, te) 14703 14704#define TCM(m1,m2, aop, top, nops, ops, ae, te) \ 14705 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) 14706#define tCM(m1,m2, aop, top, nops, ops, ae, te) \ 14707 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) 14708 14709/* Mnemonic that cannot be conditionalized. The ARM condition-code 14710 field is still 0xE. Many of the Thumb variants can be executed 14711 conditionally, so this is checked separately. */ 14712#define TUE(mnem, op, top, nops, ops, ae, te) \ 14713 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ 14714 THUMB_VARIANT, do_##ae, do_##te } 14715 14716/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM 14717 condition code field. */ 14718#define TUF(mnem, op, top, nops, ops, ae, te) \ 14719 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ 14720 THUMB_VARIANT, do_##ae, do_##te } 14721 14722/* ARM-only variants of all the above. */ 14723#define CE(mnem, op, nops, ops, ae) \ 14724 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14725 14726#define C3(mnem, op, nops, ops, ae) \ 14727 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14728 14729/* Legacy mnemonics that always have conditional infix after the third 14730 character. */ 14731#define CL(mnem, op, nops, ops, ae) \ 14732 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14733 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14734 14735/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ 14736#define cCE(mnem, op, nops, ops, ae) \ 14737 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14738 14739/* Legacy coprocessor instructions where conditional infix and conditional 14740 suffix are ambiguous. For consistency this includes all FPA instructions, 14741 not just the potentially ambiguous ones. */ 14742#define cCL(mnem, op, nops, ops, ae) \ 14743 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14744 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14745 14746/* Coprocessor, takes either a suffix or a position-3 infix 14747 (for an FPA corner case). */ 14748#define C3E(mnem, op, nops, ops, ae) \ 14749 { #mnem, OPS##nops ops, OT_csuf_or_in3, \ 14750 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14751 14752#define xCM_(m1, m2, m3, op, nops, ops, ae) \ 14753 { #m1 #m2 #m3, OPS##nops ops, \ 14754 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14755 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14756 14757#define CM(m1, m2, op, nops, ops, ae) \ 14758 xCM_(m1, , m2, op, nops, ops, ae), \ 14759 xCM_(m1, eq, m2, op, nops, ops, ae), \ 14760 xCM_(m1, ne, m2, op, nops, ops, ae), \ 14761 xCM_(m1, cs, m2, op, nops, ops, ae), \ 14762 xCM_(m1, hs, m2, op, nops, ops, ae), \ 14763 xCM_(m1, cc, m2, op, nops, ops, ae), \ 14764 xCM_(m1, ul, m2, op, nops, ops, ae), \ 14765 xCM_(m1, lo, m2, op, nops, ops, ae), \ 14766 xCM_(m1, mi, m2, op, nops, ops, ae), \ 14767 xCM_(m1, pl, m2, op, nops, ops, ae), \ 14768 xCM_(m1, vs, m2, op, nops, ops, ae), \ 14769 xCM_(m1, vc, m2, op, nops, ops, ae), \ 14770 xCM_(m1, hi, m2, op, nops, ops, ae), \ 14771 xCM_(m1, ls, m2, op, nops, ops, ae), \ 14772 xCM_(m1, ge, m2, op, nops, ops, ae), \ 14773 xCM_(m1, lt, m2, op, nops, ops, ae), \ 14774 xCM_(m1, gt, m2, op, nops, ops, ae), \ 14775 xCM_(m1, le, m2, op, nops, ops, ae), \ 14776 xCM_(m1, al, m2, op, nops, ops, ae) 14777 14778#define UE(mnem, op, nops, ops, ae) \ 14779 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14780 14781#define UF(mnem, op, nops, ops, ae) \ 14782 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14783 14784/* Neon data-processing. ARM versions are unconditional with cond=0xf. 14785 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we 14786 use the same encoding function for each. */ 14787#define NUF(mnem, op, nops, ops, enc) \ 14788 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ 14789 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14790 14791/* Neon data processing, version which indirects through neon_enc_tab for 14792 the various overloaded versions of opcodes. */ 14793#define nUF(mnem, op, nops, ops, enc) \ 14794 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ 14795 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14796 14797/* Neon insn with conditional suffix for the ARM version, non-overloaded 14798 version. */ 14799#define NCE_tag(mnem, op, nops, ops, enc, tag) \ 14800 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ 14801 THUMB_VARIANT, do_##enc, do_##enc } 14802 14803#define NCE(mnem, op, nops, ops, enc) \ 14804 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14805 14806#define NCEF(mnem, op, nops, ops, enc) \ 14807 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14808 14809/* Neon insn with conditional suffix for the ARM version, overloaded types. */ 14810#define nCE_tag(mnem, op, nops, ops, enc, tag) \ 14811 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ 14812 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14813 14814#define nCE(mnem, op, nops, ops, enc) \ 14815 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14816 14817#define nCEF(mnem, op, nops, ops, enc) \ 14818 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14819 14820#define do_0 0 14821 14822/* Thumb-only, unconditional. */ 14823#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) 14824 14825static const struct asm_opcode insns[] = 14826{ 14827#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ 14828#define THUMB_VARIANT &arm_ext_v4t 14829 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), 14830 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), 14831 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), 14832 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), 14833 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), 14834 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), 14835 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), 14836 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), 14837 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), 14838 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), 14839 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), 14840 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), 14841 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), 14842 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), 14843 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), 14844 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), 14845 14846 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism 14847 for setting PSR flag bits. They are obsolete in V6 and do not 14848 have Thumb equivalents. */ 14849 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14850 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14851 CL(tstp, 110f000, 2, (RR, SH), cmp), 14852 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14853 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14854 CL(cmpp, 150f000, 2, (RR, SH), cmp), 14855 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14856 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14857 CL(cmnp, 170f000, 2, (RR, SH), cmp), 14858 14859 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), 14860 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), 14861 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), 14862 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), 14863 14864 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), 14865 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14866 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), 14867 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14868 14869 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14870 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14871 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14872 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14873 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14874 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14875 14876 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), 14877 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), 14878 tCE(b, a000000, b, 1, (EXPr), branch, t_branch), 14879 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), 14880 14881 /* Pseudo ops. */ 14882 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), 14883 C3(adrl, 28f0000, 2, (RR, EXP), adrl), 14884 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), 14885 14886 /* Thumb-compatibility pseudo ops. */ 14887 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), 14888 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), 14889 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), 14890 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), 14891 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), 14892 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), 14893 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), 14894 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), 14895 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), 14896 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), 14897 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), 14898 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), 14899 14900 /* These may simplify to neg. */ 14901 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), 14902 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), 14903 14904#undef THUMB_VARIANT 14905#define THUMB_VARIANT &arm_ext_v6 14906 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), 14907 14908 /* V1 instructions with no Thumb analogue prior to V6T2. */ 14909#undef THUMB_VARIANT 14910#define THUMB_VARIANT &arm_ext_v6t2 14911 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 14912 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 14913 CL(teqp, 130f000, 2, (RR, SH), cmp), 14914 14915 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), 14916 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), 14917 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), 14918 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), 14919 14920 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14921 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14922 14923 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14924 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14925 14926 /* V1 instructions with no Thumb analogue at all. */ 14927 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), 14928 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), 14929 14930 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), 14931 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), 14932 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), 14933 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), 14934 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), 14935 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), 14936 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), 14937 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), 14938 14939#undef ARM_VARIANT 14940#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ 14941#undef THUMB_VARIANT 14942#define THUMB_VARIANT &arm_ext_v4t 14943 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 14944 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 14945 14946#undef THUMB_VARIANT 14947#define THUMB_VARIANT &arm_ext_v6t2 14948 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 14949 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), 14950 14951 /* Generic coprocessor instructions. */ 14952 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 14953 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 14954 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 14955 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 14956 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 14957 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 14958 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 14959 14960#undef ARM_VARIANT 14961#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ 14962 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 14963 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 14964 14965#undef ARM_VARIANT 14966#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ 14967 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), 14968 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), 14969 14970#undef ARM_VARIANT 14971#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ 14972 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 14973 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 14974 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 14975 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 14976 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 14977 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 14978 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 14979 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 14980 14981#undef ARM_VARIANT 14982#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ 14983#undef THUMB_VARIANT 14984#define THUMB_VARIANT &arm_ext_v4t 14985 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 14986 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 14987 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 14988 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 14989 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 14990 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 14991 14992#undef ARM_VARIANT 14993#define ARM_VARIANT &arm_ext_v4t_5 14994 /* ARM Architecture 4T. */ 14995 /* Note: bx (and blx) are required on V5, even if the processor does 14996 not support Thumb. */ 14997 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), 14998 14999#undef ARM_VARIANT 15000#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ 15001#undef THUMB_VARIANT 15002#define THUMB_VARIANT &arm_ext_v5t 15003 /* Note: blx has 2 variants; the .value coded here is for 15004 BLX(2). Only this variant has conditional execution. */ 15005 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), 15006 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), 15007 15008#undef THUMB_VARIANT 15009#define THUMB_VARIANT &arm_ext_v6t2 15010 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), 15011 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15012 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15013 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15014 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15015 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15016 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15017 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15018 15019#undef ARM_VARIANT 15020#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ 15021 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15022 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15023 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15024 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15025 15026 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15027 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15028 15029 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15030 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15031 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15032 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15033 15034 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15035 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15036 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15037 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15038 15039 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15040 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15041 15042 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15043 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15044 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15045 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15046 15047#undef ARM_VARIANT 15048#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ 15049 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), 15050 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15051 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15052 15053 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15054 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15055 15056#undef ARM_VARIANT 15057#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ 15058 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), 15059 15060#undef ARM_VARIANT 15061#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ 15062#undef THUMB_VARIANT 15063#define THUMB_VARIANT &arm_ext_v6 15064 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), 15065 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), 15066 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15067 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15068 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15069 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15070 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15071 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15072 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15073 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), 15074 15075#undef THUMB_VARIANT 15076#define THUMB_VARIANT &arm_ext_v6t2 15077 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), 15078 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), 15079 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15080 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15081 15082 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), 15083 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), 15084 15085/* ARM V6 not included in V7M (eg. integer SIMD). */ 15086#undef THUMB_VARIANT 15087#define THUMB_VARIANT &arm_ext_v6_notm 15088 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), 15089 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), 15090 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), 15091 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15092 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15093 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15094 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15095 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15096 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15097 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15098 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15099 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15100 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15101 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15102 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15103 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15104 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15105 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15106 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15107 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15108 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15109 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15110 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15111 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15112 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15113 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15114 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15115 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15116 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15117 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15118 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15119 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15120 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15121 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15122 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15123 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15124 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15125 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15126 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15127 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15128 UF(rfeib, 9900a00, 1, (RRw), rfe), 15129 UF(rfeda, 8100a00, 1, (RRw), rfe), 15130 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15131 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15132 UF(rfefa, 9900a00, 1, (RRw), rfe), 15133 UF(rfeea, 8100a00, 1, (RRw), rfe), 15134 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15135 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15136 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15137 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15138 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15139 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15140 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15141 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15142 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15143 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15144 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15145 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15146 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15147 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15148 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15149 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15150 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15151 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15152 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15153 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15154 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15155 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15156 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15157 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15158 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15159 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15160 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15161 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15162 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), 15163 UF(srsib, 9c00500, 2, (oRRw, I31w), srs), 15164 UF(srsda, 8400500, 2, (oRRw, I31w), srs), 15165 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs), 15166 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), 15167 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), 15168 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15169 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15170 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), 15171 15172#undef ARM_VARIANT 15173#define ARM_VARIANT &arm_ext_v6k 15174#undef THUMB_VARIANT 15175#define THUMB_VARIANT &arm_ext_v6k 15176 tCE(yield, 320f001, yield, 0, (), noargs, t_hint), 15177 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), 15178 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), 15179 tCE(sev, 320f004, sev, 0, (), noargs, t_hint), 15180 15181#undef THUMB_VARIANT 15182#define THUMB_VARIANT &arm_ext_v6_notm 15183 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), 15184 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), 15185 15186#undef THUMB_VARIANT 15187#define THUMB_VARIANT &arm_ext_v6t2 15188 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15189 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15190 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15191 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15192 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), 15193 15194#undef ARM_VARIANT 15195#define ARM_VARIANT &arm_ext_v6z 15196 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), 15197 15198#undef ARM_VARIANT 15199#define ARM_VARIANT &arm_ext_v6t2 15200 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), 15201 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), 15202 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15203 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15204 15205 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15206 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), 15207 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), 15208 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), 15209 15210 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15211 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15212 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15213 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15214 15215 UT(cbnz, b900, 2, (RR, EXP), t_cbz), 15216 UT(cbz, b100, 2, (RR, EXP), t_cbz), 15217 /* ARM does not really have an IT instruction, so always allow it. */ 15218#undef ARM_VARIANT 15219#define ARM_VARIANT &arm_ext_v1 15220 TUE(it, 0, bf08, 1, (COND), it, t_it), 15221 TUE(itt, 0, bf0c, 1, (COND), it, t_it), 15222 TUE(ite, 0, bf04, 1, (COND), it, t_it), 15223 TUE(ittt, 0, bf0e, 1, (COND), it, t_it), 15224 TUE(itet, 0, bf06, 1, (COND), it, t_it), 15225 TUE(itte, 0, bf0a, 1, (COND), it, t_it), 15226 TUE(itee, 0, bf02, 1, (COND), it, t_it), 15227 TUE(itttt, 0, bf0f, 1, (COND), it, t_it), 15228 TUE(itett, 0, bf07, 1, (COND), it, t_it), 15229 TUE(ittet, 0, bf0b, 1, (COND), it, t_it), 15230 TUE(iteet, 0, bf03, 1, (COND), it, t_it), 15231 TUE(ittte, 0, bf0d, 1, (COND), it, t_it), 15232 TUE(itete, 0, bf05, 1, (COND), it, t_it), 15233 TUE(ittee, 0, bf09, 1, (COND), it, t_it), 15234 TUE(iteee, 0, bf01, 1, (COND), it, t_it), 15235 15236 /* Thumb2 only instructions. */ 15237#undef ARM_VARIANT 15238#define ARM_VARIANT NULL 15239 15240 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15241 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15242 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), 15243 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), 15244 15245 /* Thumb-2 hardware division instructions (R and M profiles only). */ 15246#undef THUMB_VARIANT 15247#define THUMB_VARIANT &arm_ext_div 15248 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), 15249 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), 15250 15251 /* ARM V7 instructions. */ 15252#undef ARM_VARIANT 15253#define ARM_VARIANT &arm_ext_v7 15254#undef THUMB_VARIANT 15255#define THUMB_VARIANT &arm_ext_v7 15256 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), 15257 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), 15258 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), 15259 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), 15260 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), 15261 15262#undef ARM_VARIANT 15263#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ 15264 cCE(wfs, e200110, 1, (RR), rd), 15265 cCE(rfs, e300110, 1, (RR), rd), 15266 cCE(wfc, e400110, 1, (RR), rd), 15267 cCE(rfc, e500110, 1, (RR), rd), 15268 15269 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), 15270 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), 15271 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), 15272 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), 15273 15274 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), 15275 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), 15276 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), 15277 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), 15278 15279 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), 15280 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), 15281 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), 15282 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), 15283 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), 15284 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), 15285 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), 15286 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), 15287 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), 15288 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), 15289 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), 15290 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), 15291 15292 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), 15293 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), 15294 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), 15295 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), 15296 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), 15297 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), 15298 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), 15299 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), 15300 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), 15301 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), 15302 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), 15303 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), 15304 15305 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), 15306 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), 15307 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), 15308 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), 15309 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), 15310 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), 15311 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), 15312 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), 15313 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), 15314 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), 15315 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), 15316 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), 15317 15318 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), 15319 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), 15320 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), 15321 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), 15322 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), 15323 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), 15324 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), 15325 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), 15326 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), 15327 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), 15328 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), 15329 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), 15330 15331 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), 15332 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), 15333 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), 15334 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), 15335 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), 15336 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), 15337 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), 15338 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), 15339 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), 15340 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), 15341 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), 15342 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), 15343 15344 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), 15345 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), 15346 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), 15347 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), 15348 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), 15349 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), 15350 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), 15351 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), 15352 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), 15353 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), 15354 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), 15355 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), 15356 15357 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), 15358 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), 15359 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), 15360 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), 15361 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), 15362 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), 15363 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), 15364 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), 15365 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), 15366 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), 15367 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), 15368 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), 15369 15370 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), 15371 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), 15372 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), 15373 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), 15374 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), 15375 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), 15376 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), 15377 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), 15378 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), 15379 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), 15380 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), 15381 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), 15382 15383 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), 15384 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), 15385 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), 15386 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), 15387 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), 15388 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), 15389 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), 15390 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), 15391 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), 15392 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), 15393 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), 15394 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), 15395 15396 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), 15397 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), 15398 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), 15399 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), 15400 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), 15401 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), 15402 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), 15403 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), 15404 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), 15405 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), 15406 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), 15407 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), 15408 15409 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), 15410 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), 15411 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), 15412 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), 15413 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), 15414 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), 15415 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), 15416 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), 15417 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), 15418 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), 15419 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), 15420 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), 15421 15422 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), 15423 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), 15424 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), 15425 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), 15426 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), 15427 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), 15428 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), 15429 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), 15430 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), 15431 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), 15432 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), 15433 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), 15434 15435 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), 15436 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), 15437 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), 15438 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), 15439 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), 15440 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), 15441 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), 15442 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), 15443 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), 15444 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), 15445 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), 15446 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), 15447 15448 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), 15449 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), 15450 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), 15451 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), 15452 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), 15453 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), 15454 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), 15455 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), 15456 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), 15457 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), 15458 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), 15459 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), 15460 15461 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), 15462 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), 15463 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), 15464 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), 15465 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), 15466 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), 15467 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), 15468 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), 15469 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), 15470 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), 15471 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), 15472 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), 15473 15474 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), 15475 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), 15476 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), 15477 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), 15478 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), 15479 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), 15480 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), 15481 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), 15482 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), 15483 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), 15484 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), 15485 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), 15486 15487 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), 15488 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), 15489 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), 15490 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), 15491 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), 15492 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15493 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15494 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15495 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), 15496 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), 15497 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), 15498 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), 15499 15500 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), 15501 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), 15502 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), 15503 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), 15504 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), 15505 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15506 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15507 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15508 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), 15509 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), 15510 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), 15511 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), 15512 15513 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), 15514 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), 15515 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), 15516 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), 15517 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), 15518 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15519 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15520 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15521 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), 15522 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), 15523 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), 15524 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), 15525 15526 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), 15527 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), 15528 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), 15529 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), 15530 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), 15531 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15532 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15533 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15534 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), 15535 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), 15536 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), 15537 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), 15538 15539 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), 15540 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), 15541 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), 15542 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), 15543 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), 15544 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15545 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15546 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15547 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), 15548 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), 15549 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), 15550 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), 15551 15552 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), 15553 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), 15554 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), 15555 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), 15556 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), 15557 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15558 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15559 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15560 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), 15561 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), 15562 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), 15563 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), 15564 15565 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), 15566 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), 15567 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), 15568 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), 15569 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), 15570 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15571 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15572 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15573 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), 15574 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), 15575 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), 15576 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), 15577 15578 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), 15579 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), 15580 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), 15581 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), 15582 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), 15583 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15584 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15585 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15586 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), 15587 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), 15588 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), 15589 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), 15590 15591 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), 15592 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), 15593 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), 15594 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), 15595 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), 15596 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15597 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15598 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15599 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), 15600 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), 15601 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), 15602 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), 15603 15604 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), 15605 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), 15606 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), 15607 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), 15608 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), 15609 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15610 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15611 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15612 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), 15613 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), 15614 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), 15615 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), 15616 15617 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15618 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15619 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15620 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15621 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15622 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15623 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15624 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15625 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15626 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15627 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15628 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15629 15630 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15631 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15632 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15633 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15634 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15635 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15636 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15637 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15638 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15639 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15640 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15641 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15642 15643 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15644 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15645 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15646 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15647 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15648 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15649 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15650 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15651 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15652 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15653 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15654 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15655 15656 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), 15657 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), 15658 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), 15659 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), 15660 15661 cCL(flts, e000110, 2, (RF, RR), rn_rd), 15662 cCL(fltsp, e000130, 2, (RF, RR), rn_rd), 15663 cCL(fltsm, e000150, 2, (RF, RR), rn_rd), 15664 cCL(fltsz, e000170, 2, (RF, RR), rn_rd), 15665 cCL(fltd, e000190, 2, (RF, RR), rn_rd), 15666 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), 15667 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), 15668 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), 15669 cCL(flte, e080110, 2, (RF, RR), rn_rd), 15670 cCL(fltep, e080130, 2, (RF, RR), rn_rd), 15671 cCL(fltem, e080150, 2, (RF, RR), rn_rd), 15672 cCL(fltez, e080170, 2, (RF, RR), rn_rd), 15673 15674 /* The implementation of the FIX instruction is broken on some 15675 assemblers, in that it accepts a precision specifier as well as a 15676 rounding specifier, despite the fact that this is meaningless. 15677 To be more compatible, we accept it as well, though of course it 15678 does not set any bits. */ 15679 cCE(fix, e100110, 2, (RR, RF), rd_rm), 15680 cCL(fixp, e100130, 2, (RR, RF), rd_rm), 15681 cCL(fixm, e100150, 2, (RR, RF), rd_rm), 15682 cCL(fixz, e100170, 2, (RR, RF), rd_rm), 15683 cCL(fixsp, e100130, 2, (RR, RF), rd_rm), 15684 cCL(fixsm, e100150, 2, (RR, RF), rd_rm), 15685 cCL(fixsz, e100170, 2, (RR, RF), rd_rm), 15686 cCL(fixdp, e100130, 2, (RR, RF), rd_rm), 15687 cCL(fixdm, e100150, 2, (RR, RF), rd_rm), 15688 cCL(fixdz, e100170, 2, (RR, RF), rd_rm), 15689 cCL(fixep, e100130, 2, (RR, RF), rd_rm), 15690 cCL(fixem, e100150, 2, (RR, RF), rd_rm), 15691 cCL(fixez, e100170, 2, (RR, RF), rd_rm), 15692 15693 /* Instructions that were new with the real FPA, call them V2. */ 15694#undef ARM_VARIANT 15695#define ARM_VARIANT &fpu_fpa_ext_v2 15696 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15697 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15698 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15699 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15700 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15701 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15702 15703#undef ARM_VARIANT 15704#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ 15705 /* Moves and type conversions. */ 15706 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), 15707 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), 15708 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), 15709 cCE(fmstat, ef1fa10, 0, (), noargs), 15710 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), 15711 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), 15712 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), 15713 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15714 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), 15715 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15716 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), 15717 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), 15718 15719 /* Memory operations. */ 15720 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15721 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15722 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15723 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15724 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15725 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15726 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15727 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15728 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15729 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15730 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15731 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15732 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15733 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15734 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15735 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15736 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15737 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15738 15739 /* Monadic operations. */ 15740 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), 15741 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), 15742 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), 15743 15744 /* Dyadic operations. */ 15745 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15746 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15747 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15748 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15749 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15750 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15751 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15752 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15753 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15754 15755 /* Comparisons. */ 15756 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), 15757 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), 15758 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), 15759 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), 15760 15761#undef ARM_VARIANT 15762#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ 15763 /* Moves and type conversions. */ 15764 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15765 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15766 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15767 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), 15768 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), 15769 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), 15770 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), 15771 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15772 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), 15773 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15774 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15775 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15776 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15777 15778 /* Memory operations. */ 15779 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15780 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15781 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15782 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15783 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15784 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15785 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15786 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15787 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15788 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15789 15790 /* Monadic operations. */ 15791 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15792 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15793 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15794 15795 /* Dyadic operations. */ 15796 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15797 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15798 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15799 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15800 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15801 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15802 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15803 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15804 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15805 15806 /* Comparisons. */ 15807 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15808 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), 15809 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15810 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), 15811 15812#undef ARM_VARIANT 15813#define ARM_VARIANT &fpu_vfp_ext_v2 15814 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), 15815 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), 15816 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), 15817 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), 15818 15819/* Instructions which may belong to either the Neon or VFP instruction sets. 15820 Individual encoder functions perform additional architecture checks. */ 15821#undef ARM_VARIANT 15822#define ARM_VARIANT &fpu_vfp_ext_v1xd 15823#undef THUMB_VARIANT 15824#define THUMB_VARIANT &fpu_vfp_ext_v1xd 15825 /* These mnemonics are unique to VFP. */ 15826 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), 15827 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), 15828 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15829 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15830 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15831 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15832 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15833 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), 15834 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), 15835 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), 15836 15837 /* Mnemonics shared by Neon and VFP. */ 15838 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), 15839 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15840 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15841 15842 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15843 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15844 15845 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15846 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15847 15848 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15849 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15850 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15851 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15852 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15853 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15854 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15855 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15856 15857 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), 15858 15859 /* NOTE: All VMOV encoding is special-cased! */ 15860 NCE(vmov, 0, 1, (VMOV), neon_mov), 15861 NCE(vmovq, 0, 1, (VMOV), neon_mov), 15862 15863#undef THUMB_VARIANT 15864#define THUMB_VARIANT &fpu_neon_ext_v1 15865#undef ARM_VARIANT 15866#define ARM_VARIANT &fpu_neon_ext_v1 15867 /* Data processing with three registers of the same length. */ 15868 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ 15869 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), 15870 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), 15871 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15872 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15873 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15874 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15875 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15876 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15877 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ 15878 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15879 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15880 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15881 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15882 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15883 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15884 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15885 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15886 /* If not immediate, fall back to neon_dyadic_i64_su. 15887 shl_imm should accept I8 I16 I32 I64, 15888 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ 15889 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), 15890 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), 15891 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), 15892 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), 15893 /* Logic ops, types optional & ignored. */ 15894 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), 15895 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), 15896 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), 15897 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), 15898 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), 15899 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), 15900 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), 15901 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), 15902 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), 15903 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), 15904 /* Bitfield ops, untyped. */ 15905 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15906 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15907 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15908 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15909 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15910 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15911 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ 15912 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15913 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15914 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15915 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15916 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15917 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15918 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall 15919 back to neon_dyadic_if_su. */ 15920 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 15921 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 15922 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 15923 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 15924 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 15925 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 15926 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 15927 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 15928 /* Comparison. Type I8 I16 I32 F32. */ 15929 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), 15930 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), 15931 /* As above, D registers only. */ 15932 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 15933 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 15934 /* Int and float variants, signedness unimportant. */ 15935 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 15936 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 15937 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), 15938 /* Add/sub take types I8 I16 I32 I64 F32. */ 15939 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 15940 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 15941 /* vtst takes sizes 8, 16, 32. */ 15942 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), 15943 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), 15944 /* VMUL takes I8 I16 I32 F32 P8. */ 15945 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), 15946 /* VQD{R}MULH takes S16 S32. */ 15947 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 15948 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 15949 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 15950 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 15951 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 15952 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 15953 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 15954 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 15955 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 15956 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 15957 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 15958 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 15959 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 15960 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), 15961 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 15962 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), 15963 15964 /* Two address, int/float. Types S8 S16 S32 F32. */ 15965 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), 15966 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), 15967 15968 /* Data processing with two registers and a shift amount. */ 15969 /* Right shifts, and variants with rounding. 15970 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ 15971 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 15972 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 15973 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 15974 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 15975 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 15976 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 15977 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 15978 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 15979 /* Shift and insert. Sizes accepted 8 16 32 64. */ 15980 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), 15981 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), 15982 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), 15983 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), 15984 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ 15985 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), 15986 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), 15987 /* Right shift immediate, saturating & narrowing, with rounding variants. 15988 Types accepted S16 S32 S64 U16 U32 U64. */ 15989 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 15990 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 15991 /* As above, unsigned. Types accepted S16 S32 S64. */ 15992 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 15993 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 15994 /* Right shift narrowing. Types accepted I16 I32 I64. */ 15995 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), 15996 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), 15997 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ 15998 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), 15999 /* CVT with optional immediate for fixed-point variant. */ 16000 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), 16001 16002 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), 16003 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), 16004 16005 /* Data processing, three registers of different lengths. */ 16006 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ 16007 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), 16008 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), 16009 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), 16010 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), 16011 /* If not scalar, fall back to neon_dyadic_long. 16012 Vector types as above, scalar types S16 S32 U16 U32. */ 16013 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16014 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16015 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ 16016 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16017 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16018 /* Dyadic, narrowing insns. Types I16 I32 I64. */ 16019 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16020 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16021 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16022 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16023 /* Saturating doubling multiplies. Types S16 S32. */ 16024 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16025 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16026 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16027 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types 16028 S16 S32 U16 U32. */ 16029 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), 16030 16031 /* Extract. Size 8. */ 16032 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), 16033 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), 16034 16035 /* Two registers, miscellaneous. */ 16036 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ 16037 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), 16038 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), 16039 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), 16040 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), 16041 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), 16042 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), 16043 /* Vector replicate. Sizes 8 16 32. */ 16044 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), 16045 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), 16046 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ 16047 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), 16048 /* VMOVN. Types I16 I32 I64. */ 16049 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), 16050 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ 16051 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), 16052 /* VQMOVUN. Types S16 S32 S64. */ 16053 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), 16054 /* VZIP / VUZP. Sizes 8 16 32. */ 16055 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), 16056 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), 16057 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), 16058 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), 16059 /* VQABS / VQNEG. Types S8 S16 S32. */ 16060 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16061 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), 16062 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16063 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), 16064 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ 16065 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), 16066 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), 16067 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), 16068 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), 16069 /* Reciprocal estimates. Types U32 F32. */ 16070 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), 16071 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), 16072 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), 16073 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), 16074 /* VCLS. Types S8 S16 S32. */ 16075 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), 16076 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), 16077 /* VCLZ. Types I8 I16 I32. */ 16078 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), 16079 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), 16080 /* VCNT. Size 8. */ 16081 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), 16082 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), 16083 /* Two address, untyped. */ 16084 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), 16085 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), 16086 /* VTRN. Sizes 8 16 32. */ 16087 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), 16088 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), 16089 16090 /* Table lookup. Size 8. */ 16091 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16092 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16093 16094#undef THUMB_VARIANT 16095#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext 16096#undef ARM_VARIANT 16097#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext 16098 /* Neon element/structure load/store. */ 16099 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16100 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16101 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16102 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16103 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16104 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16105 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16106 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16107 16108#undef THUMB_VARIANT 16109#define THUMB_VARIANT &fpu_vfp_ext_v3 16110#undef ARM_VARIANT 16111#define ARM_VARIANT &fpu_vfp_ext_v3 16112 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), 16113 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), 16114 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16115 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16116 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16117 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16118 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16119 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16120 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16121 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16122 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16123 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16124 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16125 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16126 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16127 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16128 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16129 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16130 16131#undef THUMB_VARIANT 16132#undef ARM_VARIANT 16133#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ 16134 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16135 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16136 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16137 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16138 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16139 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16140 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), 16141 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), 16142 16143#undef ARM_VARIANT 16144#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ 16145 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), 16146 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), 16147 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), 16148 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), 16149 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), 16150 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), 16151 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), 16152 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), 16153 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), 16154 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16155 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16156 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16157 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16158 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16159 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16160 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16161 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16162 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16163 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), 16164 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), 16165 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16166 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16167 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16168 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16169 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16170 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16171 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), 16172 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), 16173 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), 16174 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), 16175 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), 16176 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), 16177 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), 16178 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), 16179 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), 16180 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), 16181 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), 16182 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16183 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16184 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16185 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16186 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16187 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16188 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16189 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16190 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16191 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), 16192 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16193 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16194 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16195 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16196 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16197 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16198 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16199 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16200 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16201 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16202 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16203 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16204 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16205 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16206 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16207 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16208 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16209 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16210 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16211 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16212 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16213 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16214 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16215 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16216 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16217 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16218 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16219 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16220 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16221 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16222 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16223 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16224 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16225 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16226 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16227 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16228 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16229 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16230 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16231 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16232 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16233 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), 16234 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16235 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16236 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16237 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16238 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16239 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16240 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16241 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16242 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16243 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16244 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16245 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16246 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16247 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16248 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16249 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16250 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16251 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16252 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16253 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16254 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16255 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), 16256 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16257 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16258 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16259 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16260 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16261 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16262 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16263 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16264 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16265 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16266 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16267 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16268 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16269 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16270 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16271 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16272 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16273 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16274 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16275 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16276 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16277 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16278 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16279 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16280 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16281 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16282 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16283 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16284 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16285 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16286 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16287 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), 16288 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), 16289 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), 16290 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), 16291 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), 16292 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), 16293 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16294 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16295 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16296 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), 16297 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), 16298 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), 16299 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), 16300 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), 16301 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), 16302 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16303 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16304 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16305 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16306 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), 16307 16308#undef ARM_VARIANT 16309#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ 16310 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc), 16311 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc), 16312 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc), 16313 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn), 16314 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn), 16315 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn), 16316 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16317 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16318 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16319 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16320 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16321 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16322 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16323 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16324 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16325 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16326 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16327 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16328 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16329 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16330 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), 16331 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16332 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16333 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16334 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16335 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16336 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16337 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16338 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16339 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16340 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16341 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16342 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16343 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16344 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16345 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16346 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16347 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16348 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16349 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16350 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16351 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16352 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16353 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16354 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16355 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16356 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16357 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16358 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16359 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16360 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16361 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16362 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16363 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16364 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16365 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16366 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16367 16368#undef ARM_VARIANT 16369#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ 16370 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16371 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16372 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16373 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16374 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16375 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16376 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16377 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16378 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), 16379 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), 16380 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), 16381 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), 16382 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), 16383 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), 16384 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), 16385 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), 16386 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), 16387 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), 16388 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), 16389 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), 16390 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), 16391 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), 16392 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), 16393 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), 16394 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), 16395 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), 16396 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), 16397 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), 16398 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), 16399 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), 16400 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), 16401 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), 16402 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), 16403 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), 16404 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), 16405 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), 16406 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), 16407 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), 16408 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), 16409 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), 16410 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), 16411 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), 16412 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), 16413 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), 16414 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), 16415 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), 16416 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), 16417 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), 16418 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), 16419 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), 16420 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), 16421 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), 16422 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), 16423 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), 16424 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), 16425 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), 16426 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), 16427 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), 16428 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), 16429 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), 16430 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), 16431 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), 16432 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), 16433 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), 16434 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16435 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16436 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16437 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16438 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16439 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16440 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16441 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16442 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16443 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16444 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16445 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16446}; 16447#undef ARM_VARIANT 16448#undef THUMB_VARIANT 16449#undef TCE 16450#undef TCM 16451#undef TUE 16452#undef TUF 16453#undef TCC 16454#undef cCE 16455#undef cCL 16456#undef C3E 16457#undef CE 16458#undef CM 16459#undef UE 16460#undef UF 16461#undef UT 16462#undef NUF 16463#undef nUF 16464#undef NCE 16465#undef nCE 16466#undef OPS0 16467#undef OPS1 16468#undef OPS2 16469#undef OPS3 16470#undef OPS4 16471#undef OPS5 16472#undef OPS6 16473#undef do_0 16474 16475/* MD interface: bits in the object file. */ 16476 16477/* Turn an integer of n bytes (in val) into a stream of bytes appropriate 16478 for use in the a.out file, and stores them in the array pointed to by buf. 16479 This knows about the endian-ness of the target machine and does 16480 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) 16481 2 (short) and 4 (long) Floating numbers are put out as a series of 16482 LITTLENUMS (shorts, here at least). */ 16483 16484void 16485md_number_to_chars (char * buf, valueT val, int n) 16486{ 16487 if (target_big_endian) 16488 number_to_chars_bigendian (buf, val, n); 16489 else 16490 number_to_chars_littleendian (buf, val, n); 16491} 16492 16493static valueT 16494md_chars_to_number (char * buf, int n) 16495{ 16496 valueT result = 0; 16497 unsigned char * where = (unsigned char *) buf; 16498 16499 if (target_big_endian) 16500 { 16501 while (n--) 16502 { 16503 result <<= 8; 16504 result |= (*where++ & 255); 16505 } 16506 } 16507 else 16508 { 16509 while (n--) 16510 { 16511 result <<= 8; 16512 result |= (where[n] & 255); 16513 } 16514 } 16515 16516 return result; 16517} 16518 16519/* MD interface: Sections. */ 16520 16521/* Estimate the size of a frag before relaxing. Assume everything fits in 16522 2 bytes. */ 16523 16524int 16525md_estimate_size_before_relax (fragS * fragp, 16526 segT segtype ATTRIBUTE_UNUSED) 16527{ 16528 fragp->fr_var = 2; 16529 return 2; 16530} 16531 16532/* Convert a machine dependent frag. */ 16533 16534void 16535md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) 16536{ 16537 unsigned long insn; 16538 unsigned long old_op; 16539 char *buf; 16540 expressionS exp; 16541 fixS *fixp; 16542 int reloc_type; 16543 int pc_rel; 16544 int opcode; 16545 16546 buf = fragp->fr_literal + fragp->fr_fix; 16547 16548 old_op = bfd_get_16(abfd, buf); 16549 if (fragp->fr_symbol) { 16550 exp.X_op = O_symbol; 16551 exp.X_add_symbol = fragp->fr_symbol; 16552 } else { 16553 exp.X_op = O_constant; 16554 } 16555 exp.X_add_number = fragp->fr_offset; 16556 opcode = fragp->fr_subtype; 16557 switch (opcode) 16558 { 16559 case T_MNEM_ldr_pc: 16560 case T_MNEM_ldr_pc2: 16561 case T_MNEM_ldr_sp: 16562 case T_MNEM_str_sp: 16563 case T_MNEM_ldr: 16564 case T_MNEM_ldrb: 16565 case T_MNEM_ldrh: 16566 case T_MNEM_str: 16567 case T_MNEM_strb: 16568 case T_MNEM_strh: 16569 if (fragp->fr_var == 4) 16570 { 16571 insn = THUMB_OP32(opcode); 16572 if ((old_op >> 12) == 4 || (old_op >> 12) == 9) 16573 { 16574 insn |= (old_op & 0x700) << 4; 16575 } 16576 else 16577 { 16578 insn |= (old_op & 7) << 12; 16579 insn |= (old_op & 0x38) << 13; 16580 } 16581 insn |= 0x00000c00; 16582 put_thumb32_insn (buf, insn); 16583 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; 16584 } 16585 else 16586 { 16587 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; 16588 } 16589 pc_rel = (opcode == T_MNEM_ldr_pc2); 16590 break; 16591 case T_MNEM_adr: 16592 if (fragp->fr_var == 4) 16593 { 16594 insn = THUMB_OP32 (opcode); 16595 insn |= (old_op & 0xf0) << 4; 16596 put_thumb32_insn (buf, insn); 16597 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; 16598 } 16599 else 16600 { 16601 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16602 exp.X_add_number -= 4; 16603 } 16604 pc_rel = 1; 16605 break; 16606 case T_MNEM_mov: 16607 case T_MNEM_movs: 16608 case T_MNEM_cmp: 16609 case T_MNEM_cmn: 16610 if (fragp->fr_var == 4) 16611 { 16612 int r0off = (opcode == T_MNEM_mov 16613 || opcode == T_MNEM_movs) ? 0 : 8; 16614 insn = THUMB_OP32 (opcode); 16615 insn = (insn & 0xe1ffffff) | 0x10000000; 16616 insn |= (old_op & 0x700) << r0off; 16617 put_thumb32_insn (buf, insn); 16618 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16619 } 16620 else 16621 { 16622 reloc_type = BFD_RELOC_ARM_THUMB_IMM; 16623 } 16624 pc_rel = 0; 16625 break; 16626 case T_MNEM_b: 16627 if (fragp->fr_var == 4) 16628 { 16629 insn = THUMB_OP32(opcode); 16630 put_thumb32_insn (buf, insn); 16631 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; 16632 } 16633 else 16634 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; 16635 pc_rel = 1; 16636 break; 16637 case T_MNEM_bcond: 16638 if (fragp->fr_var == 4) 16639 { 16640 insn = THUMB_OP32(opcode); 16641 insn |= (old_op & 0xf00) << 14; 16642 put_thumb32_insn (buf, insn); 16643 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; 16644 } 16645 else 16646 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; 16647 pc_rel = 1; 16648 break; 16649 case T_MNEM_add_sp: 16650 case T_MNEM_add_pc: 16651 case T_MNEM_inc_sp: 16652 case T_MNEM_dec_sp: 16653 if (fragp->fr_var == 4) 16654 { 16655 /* ??? Choose between add and addw. */ 16656 insn = THUMB_OP32 (opcode); 16657 insn |= (old_op & 0xf0) << 4; 16658 put_thumb32_insn (buf, insn); 16659 if (opcode == T_MNEM_add_pc) 16660 reloc_type = BFD_RELOC_ARM_T32_IMM12; 16661 else 16662 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16663 } 16664 else 16665 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16666 pc_rel = 0; 16667 break; 16668 16669 case T_MNEM_addi: 16670 case T_MNEM_addis: 16671 case T_MNEM_subi: 16672 case T_MNEM_subis: 16673 if (fragp->fr_var == 4) 16674 { 16675 insn = THUMB_OP32 (opcode); 16676 insn |= (old_op & 0xf0) << 4; 16677 insn |= (old_op & 0xf) << 16; 16678 put_thumb32_insn (buf, insn); 16679 if (insn & (1 << 20)) 16680 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16681 else 16682 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16683 } 16684 else 16685 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16686 pc_rel = 0; 16687 break; 16688 default: 16689 abort(); 16690 } 16691 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, 16692 reloc_type); 16693 fixp->fx_file = fragp->fr_file; 16694 fixp->fx_line = fragp->fr_line; 16695 fragp->fr_fix += fragp->fr_var; 16696} 16697 16698/* Return the size of a relaxable immediate operand instruction. 16699 SHIFT and SIZE specify the form of the allowable immediate. */ 16700static int 16701relax_immediate (fragS *fragp, int size, int shift) 16702{ 16703 offsetT offset; 16704 offsetT mask; 16705 offsetT low; 16706 16707 /* ??? Should be able to do better than this. */ 16708 if (fragp->fr_symbol) 16709 return 4; 16710 16711 low = (1 << shift) - 1; 16712 mask = (1 << (shift + size)) - (1 << shift); 16713 offset = fragp->fr_offset; 16714 /* Force misaligned offsets to 32-bit variant. */ 16715 if (offset & low) 16716 return 4; 16717 if (offset & ~mask) 16718 return 4; 16719 return 2; 16720} 16721 16722/* Get the address of a symbol during relaxation. */ 16723static addressT 16724relaxed_symbol_addr(fragS *fragp, long stretch) 16725{ 16726 fragS *sym_frag; 16727 addressT addr; 16728 symbolS *sym; 16729 16730 sym = fragp->fr_symbol; 16731 sym_frag = symbol_get_frag (sym); 16732 know (S_GET_SEGMENT (sym) != absolute_section 16733 || sym_frag == &zero_address_frag); 16734 addr = S_GET_VALUE (sym) + fragp->fr_offset; 16735 16736 /* If frag has yet to be reached on this pass, assume it will 16737 move by STRETCH just as we did. If this is not so, it will 16738 be because some frag between grows, and that will force 16739 another pass. */ 16740 16741 if (stretch != 0 16742 && sym_frag->relax_marker != fragp->relax_marker) 16743 addr += stretch; 16744 16745 return addr; 16746} 16747 16748/* Return the size of a relaxable adr pseudo-instruction or PC-relative 16749 load. */ 16750static int 16751relax_adr (fragS *fragp, asection *sec, long stretch) 16752{ 16753 addressT addr; 16754 offsetT val; 16755 16756 /* Assume worst case for symbols not known to be in the same section. */ 16757 if (!S_IS_DEFINED(fragp->fr_symbol) 16758 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16759 return 4; 16760 16761 val = relaxed_symbol_addr(fragp, stretch); 16762 addr = fragp->fr_address + fragp->fr_fix; 16763 addr = (addr + 4) & ~3; 16764 /* Force misaligned targets to 32-bit variant. */ 16765 if (val & 3) 16766 return 4; 16767 val -= addr; 16768 if (val < 0 || val > 1020) 16769 return 4; 16770 return 2; 16771} 16772 16773/* Return the size of a relaxable add/sub immediate instruction. */ 16774static int 16775relax_addsub (fragS *fragp, asection *sec) 16776{ 16777 char *buf; 16778 int op; 16779 16780 buf = fragp->fr_literal + fragp->fr_fix; 16781 op = bfd_get_16(sec->owner, buf); 16782 if ((op & 0xf) == ((op >> 4) & 0xf)) 16783 return relax_immediate (fragp, 8, 0); 16784 else 16785 return relax_immediate (fragp, 3, 0); 16786} 16787 16788 16789/* Return the size of a relaxable branch instruction. BITS is the 16790 size of the offset field in the narrow instruction. */ 16791 16792static int 16793relax_branch (fragS *fragp, asection *sec, int bits, long stretch) 16794{ 16795 addressT addr; 16796 offsetT val; 16797 offsetT limit; 16798 16799 /* Assume worst case for symbols not known to be in the same section. */ 16800 if (!S_IS_DEFINED(fragp->fr_symbol) 16801 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16802 return 4; 16803 16804 val = relaxed_symbol_addr(fragp, stretch); 16805 addr = fragp->fr_address + fragp->fr_fix + 4; 16806 val -= addr; 16807 16808 /* Offset is a signed value *2 */ 16809 limit = 1 << bits; 16810 if (val >= limit || val < -limit) 16811 return 4; 16812 return 2; 16813} 16814 16815 16816/* Relax a machine dependent frag. This returns the amount by which 16817 the current size of the frag should change. */ 16818 16819int 16820arm_relax_frag (asection *sec, fragS *fragp, long stretch) 16821{ 16822 int oldsize; 16823 int newsize; 16824 16825 oldsize = fragp->fr_var; 16826 switch (fragp->fr_subtype) 16827 { 16828 case T_MNEM_ldr_pc2: 16829 newsize = relax_adr(fragp, sec, stretch); 16830 break; 16831 case T_MNEM_ldr_pc: 16832 case T_MNEM_ldr_sp: 16833 case T_MNEM_str_sp: 16834 newsize = relax_immediate(fragp, 8, 2); 16835 break; 16836 case T_MNEM_ldr: 16837 case T_MNEM_str: 16838 newsize = relax_immediate(fragp, 5, 2); 16839 break; 16840 case T_MNEM_ldrh: 16841 case T_MNEM_strh: 16842 newsize = relax_immediate(fragp, 5, 1); 16843 break; 16844 case T_MNEM_ldrb: 16845 case T_MNEM_strb: 16846 newsize = relax_immediate(fragp, 5, 0); 16847 break; 16848 case T_MNEM_adr: 16849 newsize = relax_adr(fragp, sec, stretch); 16850 break; 16851 case T_MNEM_mov: 16852 case T_MNEM_movs: 16853 case T_MNEM_cmp: 16854 case T_MNEM_cmn: 16855 newsize = relax_immediate(fragp, 8, 0); 16856 break; 16857 case T_MNEM_b: 16858 newsize = relax_branch(fragp, sec, 11, stretch); 16859 break; 16860 case T_MNEM_bcond: 16861 newsize = relax_branch(fragp, sec, 8, stretch); 16862 break; 16863 case T_MNEM_add_sp: 16864 case T_MNEM_add_pc: 16865 newsize = relax_immediate (fragp, 8, 2); 16866 break; 16867 case T_MNEM_inc_sp: 16868 case T_MNEM_dec_sp: 16869 newsize = relax_immediate (fragp, 7, 2); 16870 break; 16871 case T_MNEM_addi: 16872 case T_MNEM_addis: 16873 case T_MNEM_subi: 16874 case T_MNEM_subis: 16875 newsize = relax_addsub (fragp, sec); 16876 break; 16877 default: 16878 abort(); 16879 } 16880 16881 fragp->fr_var = newsize; 16882 /* Freeze wide instructions that are at or before the same location as 16883 in the previous pass. This avoids infinite loops. 16884 Don't freeze them unconditionally because targets may be artificialy 16885 misaligned by the expansion of preceeding frags. */ 16886 if (stretch <= 0 && newsize > 2) 16887 { 16888 md_convert_frag (sec->owner, sec, fragp); 16889 frag_wane(fragp); 16890 } 16891 16892 return newsize - oldsize; 16893} 16894 16895/* Round up a section size to the appropriate boundary. */ 16896 16897valueT 16898md_section_align (segT segment ATTRIBUTE_UNUSED, 16899 valueT size) 16900{ 16901#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 16902 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 16903 { 16904 /* For a.out, force the section size to be aligned. If we don't do 16905 this, BFD will align it for us, but it will not write out the 16906 final bytes of the section. This may be a bug in BFD, but it is 16907 easier to fix it here since that is how the other a.out targets 16908 work. */ 16909 int align; 16910 16911 align = bfd_get_section_alignment (stdoutput, segment); 16912 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 16913 } 16914#endif 16915 16916 return size; 16917} 16918 16919/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 16920 of an rs_align_code fragment. */ 16921 16922void 16923arm_handle_align (fragS * fragP) 16924{ 16925 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; 16926 static char const thumb_noop[2] = { 0xc0, 0x46 }; 16927 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; 16928 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; 16929 16930 int bytes, fix, noop_size; 16931 char * p; 16932 const char * noop; 16933 16934 if (fragP->fr_type != rs_align_code) 16935 return; 16936 16937 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 16938 p = fragP->fr_literal + fragP->fr_fix; 16939 fix = 0; 16940 16941 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) 16942 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; 16943 16944 if (fragP->tc_frag_data) 16945 { 16946 if (target_big_endian) 16947 noop = thumb_bigend_noop; 16948 else 16949 noop = thumb_noop; 16950 noop_size = sizeof (thumb_noop); 16951 } 16952 else 16953 { 16954 if (target_big_endian) 16955 noop = arm_bigend_noop; 16956 else 16957 noop = arm_noop; 16958 noop_size = sizeof (arm_noop); 16959 } 16960 16961 if (bytes & (noop_size - 1)) 16962 { 16963 fix = bytes & (noop_size - 1); 16964 memset (p, 0, fix); 16965 p += fix; 16966 bytes -= fix; 16967 } 16968 16969 while (bytes >= noop_size) 16970 { 16971 memcpy (p, noop, noop_size); 16972 p += noop_size; 16973 bytes -= noop_size; 16974 fix += noop_size; 16975 } 16976 16977 fragP->fr_fix += fix; 16978 fragP->fr_var = noop_size; 16979} 16980 16981/* Called from md_do_align. Used to create an alignment 16982 frag in a code section. */ 16983 16984void 16985arm_frag_align_code (int n, int max) 16986{ 16987 char * p; 16988 16989 /* We assume that there will never be a requirement 16990 to support alignments greater than 32 bytes. */ 16991 if (max > MAX_MEM_FOR_RS_ALIGN_CODE) 16992 as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); 16993 16994 p = frag_var (rs_align_code, 16995 MAX_MEM_FOR_RS_ALIGN_CODE, 16996 1, 16997 (relax_substateT) max, 16998 (symbolS *) NULL, 16999 (offsetT) n, 17000 (char *) NULL); 17001 *p = 0; 17002} 17003 17004/* Perform target specific initialisation of a frag. */ 17005 17006void 17007arm_init_frag (fragS * fragP) 17008{ 17009 /* Record whether this frag is in an ARM or a THUMB area. */ 17010 fragP->tc_frag_data = thumb_mode; 17011} 17012 17013#ifdef OBJ_ELF 17014/* When we change sections we need to issue a new mapping symbol. */ 17015 17016void 17017arm_elf_change_section (void) 17018{ 17019 flagword flags; 17020 segment_info_type *seginfo; 17021 17022 /* Link an unlinked unwind index table section to the .text section. */ 17023 if (elf_section_type (now_seg) == SHT_ARM_EXIDX 17024 && elf_linked_to_section (now_seg) == NULL) 17025 elf_linked_to_section (now_seg) = text_section; 17026 17027 if (!SEG_NORMAL (now_seg)) 17028 return; 17029 17030 flags = bfd_get_section_flags (stdoutput, now_seg); 17031 17032 /* We can ignore sections that only contain debug info. */ 17033 if ((flags & SEC_ALLOC) == 0) 17034 return; 17035 17036 seginfo = seg_info (now_seg); 17037 mapstate = seginfo->tc_segment_info_data.mapstate; 17038 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; 17039} 17040 17041int 17042arm_elf_section_type (const char * str, size_t len) 17043{ 17044 if (len == 5 && strncmp (str, "exidx", 5) == 0) 17045 return SHT_ARM_EXIDX; 17046 17047 return -1; 17048} 17049 17050/* Code to deal with unwinding tables. */ 17051 17052static void add_unwind_adjustsp (offsetT); 17053 17054/* Cenerate and deferred unwind frame offset. */ 17055 17056static void 17057flush_pending_unwind (void) 17058{ 17059 offsetT offset; 17060 17061 offset = unwind.pending_offset; 17062 unwind.pending_offset = 0; 17063 if (offset != 0) 17064 add_unwind_adjustsp (offset); 17065} 17066 17067/* Add an opcode to this list for this function. Two-byte opcodes should 17068 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse 17069 order. */ 17070 17071static void 17072add_unwind_opcode (valueT op, int length) 17073{ 17074 /* Add any deferred stack adjustment. */ 17075 if (unwind.pending_offset) 17076 flush_pending_unwind (); 17077 17078 unwind.sp_restored = 0; 17079 17080 if (unwind.opcode_count + length > unwind.opcode_alloc) 17081 { 17082 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; 17083 if (unwind.opcodes) 17084 unwind.opcodes = xrealloc (unwind.opcodes, 17085 unwind.opcode_alloc); 17086 else 17087 unwind.opcodes = xmalloc (unwind.opcode_alloc); 17088 } 17089 while (length > 0) 17090 { 17091 length--; 17092 unwind.opcodes[unwind.opcode_count] = op & 0xff; 17093 op >>= 8; 17094 unwind.opcode_count++; 17095 } 17096} 17097 17098/* Add unwind opcodes to adjust the stack pointer. */ 17099 17100static void 17101add_unwind_adjustsp (offsetT offset) 17102{ 17103 valueT op; 17104 17105 if (offset > 0x200) 17106 { 17107 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ 17108 char bytes[5]; 17109 int n; 17110 valueT o; 17111 17112 /* Long form: 0xb2, uleb128. */ 17113 /* This might not fit in a word so add the individual bytes, 17114 remembering the list is built in reverse order. */ 17115 o = (valueT) ((offset - 0x204) >> 2); 17116 if (o == 0) 17117 add_unwind_opcode (0, 1); 17118 17119 /* Calculate the uleb128 encoding of the offset. */ 17120 n = 0; 17121 while (o) 17122 { 17123 bytes[n] = o & 0x7f; 17124 o >>= 7; 17125 if (o) 17126 bytes[n] |= 0x80; 17127 n++; 17128 } 17129 /* Add the insn. */ 17130 for (; n; n--) 17131 add_unwind_opcode (bytes[n - 1], 1); 17132 add_unwind_opcode (0xb2, 1); 17133 } 17134 else if (offset > 0x100) 17135 { 17136 /* Two short opcodes. */ 17137 add_unwind_opcode (0x3f, 1); 17138 op = (offset - 0x104) >> 2; 17139 add_unwind_opcode (op, 1); 17140 } 17141 else if (offset > 0) 17142 { 17143 /* Short opcode. */ 17144 op = (offset - 4) >> 2; 17145 add_unwind_opcode (op, 1); 17146 } 17147 else if (offset < 0) 17148 { 17149 offset = -offset; 17150 while (offset > 0x100) 17151 { 17152 add_unwind_opcode (0x7f, 1); 17153 offset -= 0x100; 17154 } 17155 op = ((offset - 4) >> 2) | 0x40; 17156 add_unwind_opcode (op, 1); 17157 } 17158} 17159 17160/* Finish the list of unwind opcodes for this function. */ 17161static void 17162finish_unwind_opcodes (void) 17163{ 17164 valueT op; 17165 17166 if (unwind.fp_used) 17167 { 17168 /* Adjust sp as necessary. */ 17169 unwind.pending_offset += unwind.fp_offset - unwind.frame_size; 17170 flush_pending_unwind (); 17171 17172 /* After restoring sp from the frame pointer. */ 17173 op = 0x90 | unwind.fp_reg; 17174 add_unwind_opcode (op, 1); 17175 } 17176 else 17177 flush_pending_unwind (); 17178} 17179 17180 17181/* Start an exception table entry. If idx is nonzero this is an index table 17182 entry. */ 17183 17184static void 17185start_unwind_section (const segT text_seg, int idx) 17186{ 17187 const char * text_name; 17188 const char * prefix; 17189 const char * prefix_once; 17190 const char * group_name; 17191 size_t prefix_len; 17192 size_t text_len; 17193 char * sec_name; 17194 size_t sec_name_len; 17195 int type; 17196 int flags; 17197 int linkonce; 17198 17199 if (idx) 17200 { 17201 prefix = ELF_STRING_ARM_unwind; 17202 prefix_once = ELF_STRING_ARM_unwind_once; 17203 type = SHT_ARM_EXIDX; 17204 } 17205 else 17206 { 17207 prefix = ELF_STRING_ARM_unwind_info; 17208 prefix_once = ELF_STRING_ARM_unwind_info_once; 17209 type = SHT_PROGBITS; 17210 } 17211 17212 text_name = segment_name (text_seg); 17213 if (streq (text_name, ".text")) 17214 text_name = ""; 17215 17216 if (strncmp (text_name, ".gnu.linkonce.t.", 17217 strlen (".gnu.linkonce.t.")) == 0) 17218 { 17219 prefix = prefix_once; 17220 text_name += strlen (".gnu.linkonce.t."); 17221 } 17222 17223 prefix_len = strlen (prefix); 17224 text_len = strlen (text_name); 17225 sec_name_len = prefix_len + text_len; 17226 sec_name = xmalloc (sec_name_len + 1); 17227 memcpy (sec_name, prefix, prefix_len); 17228 memcpy (sec_name + prefix_len, text_name, text_len); 17229 sec_name[prefix_len + text_len] = '\0'; 17230 17231 flags = SHF_ALLOC; 17232 linkonce = 0; 17233 group_name = 0; 17234 17235 /* Handle COMDAT group. */ 17236 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) 17237 { 17238 group_name = elf_group_name (text_seg); 17239 if (group_name == NULL) 17240 { 17241 as_bad ("Group section `%s' has no group signature", 17242 segment_name (text_seg)); 17243 ignore_rest_of_line (); 17244 return; 17245 } 17246 flags |= SHF_GROUP; 17247 linkonce = 1; 17248 } 17249 17250 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); 17251 17252 /* Set the setion link for index tables. */ 17253 if (idx) 17254 elf_linked_to_section (now_seg) = text_seg; 17255} 17256 17257 17258/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional 17259 personality routine data. Returns zero, or the index table value for 17260 and inline entry. */ 17261 17262static valueT 17263create_unwind_entry (int have_data) 17264{ 17265 int size; 17266 addressT where; 17267 char *ptr; 17268 /* The current word of data. */ 17269 valueT data; 17270 /* The number of bytes left in this word. */ 17271 int n; 17272 17273 finish_unwind_opcodes (); 17274 17275 /* Remember the current text section. */ 17276 unwind.saved_seg = now_seg; 17277 unwind.saved_subseg = now_subseg; 17278 17279 start_unwind_section (now_seg, 0); 17280 17281 if (unwind.personality_routine == NULL) 17282 { 17283 if (unwind.personality_index == -2) 17284 { 17285 if (have_data) 17286 as_bad (_("handerdata in cantunwind frame")); 17287 return 1; /* EXIDX_CANTUNWIND. */ 17288 } 17289 17290 /* Use a default personality routine if none is specified. */ 17291 if (unwind.personality_index == -1) 17292 { 17293 if (unwind.opcode_count > 3) 17294 unwind.personality_index = 1; 17295 else 17296 unwind.personality_index = 0; 17297 } 17298 17299 /* Space for the personality routine entry. */ 17300 if (unwind.personality_index == 0) 17301 { 17302 if (unwind.opcode_count > 3) 17303 as_bad (_("too many unwind opcodes for personality routine 0")); 17304 17305 if (!have_data) 17306 { 17307 /* All the data is inline in the index table. */ 17308 data = 0x80; 17309 n = 3; 17310 while (unwind.opcode_count > 0) 17311 { 17312 unwind.opcode_count--; 17313 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17314 n--; 17315 } 17316 17317 /* Pad with "finish" opcodes. */ 17318 while (n--) 17319 data = (data << 8) | 0xb0; 17320 17321 return data; 17322 } 17323 size = 0; 17324 } 17325 else 17326 /* We get two opcodes "free" in the first word. */ 17327 size = unwind.opcode_count - 2; 17328 } 17329 else 17330 /* An extra byte is required for the opcode count. */ 17331 size = unwind.opcode_count + 1; 17332 17333 size = (size + 3) >> 2; 17334 if (size > 0xff) 17335 as_bad (_("too many unwind opcodes")); 17336 17337 frag_align (2, 0, 0); 17338 record_alignment (now_seg, 2); 17339 unwind.table_entry = expr_build_dot (); 17340 17341 /* Allocate the table entry. */ 17342 ptr = frag_more ((size << 2) + 4); 17343 where = frag_now_fix () - ((size << 2) + 4); 17344 17345 switch (unwind.personality_index) 17346 { 17347 case -1: 17348 /* ??? Should this be a PLT generating relocation? */ 17349 /* Custom personality routine. */ 17350 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, 17351 BFD_RELOC_ARM_PREL31); 17352 17353 where += 4; 17354 ptr += 4; 17355 17356 /* Set the first byte to the number of additional words. */ 17357 data = size - 1; 17358 n = 3; 17359 break; 17360 17361 /* ABI defined personality routines. */ 17362 case 0: 17363 /* Three opcodes bytes are packed into the first word. */ 17364 data = 0x80; 17365 n = 3; 17366 break; 17367 17368 case 1: 17369 case 2: 17370 /* The size and first two opcode bytes go in the first word. */ 17371 data = ((0x80 + unwind.personality_index) << 8) | size; 17372 n = 2; 17373 break; 17374 17375 default: 17376 /* Should never happen. */ 17377 abort (); 17378 } 17379 17380 /* Pack the opcodes into words (MSB first), reversing the list at the same 17381 time. */ 17382 while (unwind.opcode_count > 0) 17383 { 17384 if (n == 0) 17385 { 17386 md_number_to_chars (ptr, data, 4); 17387 ptr += 4; 17388 n = 4; 17389 data = 0; 17390 } 17391 unwind.opcode_count--; 17392 n--; 17393 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17394 } 17395 17396 /* Finish off the last word. */ 17397 if (n < 4) 17398 { 17399 /* Pad with "finish" opcodes. */ 17400 while (n--) 17401 data = (data << 8) | 0xb0; 17402 17403 md_number_to_chars (ptr, data, 4); 17404 } 17405 17406 if (!have_data) 17407 { 17408 /* Add an empty descriptor if there is no user-specified data. */ 17409 ptr = frag_more (4); 17410 md_number_to_chars (ptr, 0, 4); 17411 } 17412 17413 return 0; 17414} 17415 17416 17417/* Initialize the DWARF-2 unwind information for this procedure. */ 17418 17419void 17420tc_arm_frame_initial_instructions (void) 17421{ 17422 cfi_add_CFA_def_cfa (REG_SP, 0); 17423} 17424#endif /* OBJ_ELF */ 17425 17426/* Convert REGNAME to a DWARF-2 register number. */ 17427 17428int 17429tc_arm_regname_to_dw2regnum (char *regname) 17430{ 17431 int reg = arm_reg_parse (®name, REG_TYPE_RN); 17432 17433 if (reg == FAIL) 17434 return -1; 17435 17436 return reg; 17437} 17438 17439#ifdef TE_PE 17440void 17441tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 17442{ 17443 expressionS expr; 17444 17445 expr.X_op = O_secrel; 17446 expr.X_add_symbol = symbol; 17447 expr.X_add_number = 0; 17448 emit_expr (&expr, size); 17449} 17450#endif 17451 17452/* MD interface: Symbol and relocation handling. */ 17453 17454/* Return the address within the segment that a PC-relative fixup is 17455 relative to. For ARM, PC-relative fixups applied to instructions 17456 are generally relative to the location of the fixup plus 8 bytes. 17457 Thumb branches are offset by 4, and Thumb loads relative to PC 17458 require special handling. */ 17459 17460long 17461md_pcrel_from_section (fixS * fixP, segT seg) 17462{ 17463 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; 17464 17465 /* If this is pc-relative and we are going to emit a relocation 17466 then we just want to put out any pipeline compensation that the linker 17467 will need. Otherwise we want to use the calculated base. 17468 For WinCE we skip the bias for externals as well, since this 17469 is how the MS ARM-CE assembler behaves and we want to be compatible. */ 17470 if (fixP->fx_pcrel 17471 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) 17472 || (arm_force_relocation (fixP) 17473#ifdef TE_WINCE 17474 && !S_IS_EXTERNAL (fixP->fx_addsy) 17475#endif 17476 ))) 17477 base = 0; 17478 17479 switch (fixP->fx_r_type) 17480 { 17481 /* PC relative addressing on the Thumb is slightly odd as the 17482 bottom two bits of the PC are forced to zero for the 17483 calculation. This happens *after* application of the 17484 pipeline offset. However, Thumb adrl already adjusts for 17485 this, so we need not do it again. */ 17486 case BFD_RELOC_ARM_THUMB_ADD: 17487 return base & ~3; 17488 17489 case BFD_RELOC_ARM_THUMB_OFFSET: 17490 case BFD_RELOC_ARM_T32_OFFSET_IMM: 17491 case BFD_RELOC_ARM_T32_ADD_PC12: 17492 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 17493 return (base + 4) & ~3; 17494 17495 /* Thumb branches are simply offset by +4. */ 17496 case BFD_RELOC_THUMB_PCREL_BRANCH7: 17497 case BFD_RELOC_THUMB_PCREL_BRANCH9: 17498 case BFD_RELOC_THUMB_PCREL_BRANCH12: 17499 case BFD_RELOC_THUMB_PCREL_BRANCH20: 17500 case BFD_RELOC_THUMB_PCREL_BRANCH23: 17501 case BFD_RELOC_THUMB_PCREL_BRANCH25: 17502 case BFD_RELOC_THUMB_PCREL_BLX: 17503 return base + 4; 17504 17505 /* ARM mode branches are offset by +8. However, the Windows CE 17506 loader expects the relocation not to take this into account. */ 17507 case BFD_RELOC_ARM_PCREL_BRANCH: 17508 case BFD_RELOC_ARM_PCREL_CALL: 17509 case BFD_RELOC_ARM_PCREL_JUMP: 17510 case BFD_RELOC_ARM_PCREL_BLX: 17511 case BFD_RELOC_ARM_PLT32: 17512#ifdef TE_WINCE 17513 /* When handling fixups immediately, because we have already 17514 discovered the value of a symbol, or the address of the frag involved 17515 we must account for the offset by +8, as the OS loader will never see the reloc. 17516 see fixup_segment() in write.c 17517 The S_IS_EXTERNAL test handles the case of global symbols. 17518 Those need the calculated base, not just the pipe compensation the linker will need. */ 17519 if (fixP->fx_pcrel 17520 && fixP->fx_addsy != NULL 17521 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 17522 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) 17523 return base + 8; 17524 return base; 17525#else 17526 return base + 8; 17527#endif 17528 17529 /* ARM mode loads relative to PC are also offset by +8. Unlike 17530 branches, the Windows CE loader *does* expect the relocation 17531 to take this into account. */ 17532 case BFD_RELOC_ARM_OFFSET_IMM: 17533 case BFD_RELOC_ARM_OFFSET_IMM8: 17534 case BFD_RELOC_ARM_HWLITERAL: 17535 case BFD_RELOC_ARM_LITERAL: 17536 case BFD_RELOC_ARM_CP_OFF_IMM: 17537 return base + 8; 17538 17539 17540 /* Other PC-relative relocations are un-offset. */ 17541 default: 17542 return base; 17543 } 17544} 17545 17546/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. 17547 Otherwise we have no need to default values of symbols. */ 17548 17549symbolS * 17550md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 17551{ 17552#ifdef OBJ_ELF 17553 if (name[0] == '_' && name[1] == 'G' 17554 && streq (name, GLOBAL_OFFSET_TABLE_NAME)) 17555 { 17556 if (!GOT_symbol) 17557 { 17558 if (symbol_find (name)) 17559 as_bad ("GOT already in the symbol table"); 17560 17561 GOT_symbol = symbol_new (name, undefined_section, 17562 (valueT) 0, & zero_address_frag); 17563 } 17564 17565 return GOT_symbol; 17566 } 17567#endif 17568 17569 return 0; 17570} 17571 17572/* Subroutine of md_apply_fix. Check to see if an immediate can be 17573 computed as two separate immediate values, added together. We 17574 already know that this value cannot be computed by just one ARM 17575 instruction. */ 17576 17577static unsigned int 17578validate_immediate_twopart (unsigned int val, 17579 unsigned int * highpart) 17580{ 17581 unsigned int a; 17582 unsigned int i; 17583 17584 for (i = 0; i < 32; i += 2) 17585 if (((a = rotate_left (val, i)) & 0xff) != 0) 17586 { 17587 if (a & 0xff00) 17588 { 17589 if (a & ~ 0xffff) 17590 continue; 17591 * highpart = (a >> 8) | ((i + 24) << 7); 17592 } 17593 else if (a & 0xff0000) 17594 { 17595 if (a & 0xff000000) 17596 continue; 17597 * highpart = (a >> 16) | ((i + 16) << 7); 17598 } 17599 else 17600 { 17601 assert (a & 0xff000000); 17602 * highpart = (a >> 24) | ((i + 8) << 7); 17603 } 17604 17605 return (a & 0xff) | (i << 7); 17606 } 17607 17608 return FAIL; 17609} 17610 17611static int 17612validate_offset_imm (unsigned int val, int hwse) 17613{ 17614 if ((hwse && val > 255) || val > 4095) 17615 return FAIL; 17616 return val; 17617} 17618 17619/* Subroutine of md_apply_fix. Do those data_ops which can take a 17620 negative immediate constant by altering the instruction. A bit of 17621 a hack really. 17622 MOV <-> MVN 17623 AND <-> BIC 17624 ADC <-> SBC 17625 by inverting the second operand, and 17626 ADD <-> SUB 17627 CMP <-> CMN 17628 by negating the second operand. */ 17629 17630static int 17631negate_data_op (unsigned long * instruction, 17632 unsigned long value) 17633{ 17634 int op, new_inst; 17635 unsigned long negated, inverted; 17636 17637 negated = encode_arm_immediate (-value); 17638 inverted = encode_arm_immediate (~value); 17639 17640 op = (*instruction >> DATA_OP_SHIFT) & 0xf; 17641 switch (op) 17642 { 17643 /* First negates. */ 17644 case OPCODE_SUB: /* ADD <-> SUB */ 17645 new_inst = OPCODE_ADD; 17646 value = negated; 17647 break; 17648 17649 case OPCODE_ADD: 17650 new_inst = OPCODE_SUB; 17651 value = negated; 17652 break; 17653 17654 case OPCODE_CMP: /* CMP <-> CMN */ 17655 new_inst = OPCODE_CMN; 17656 value = negated; 17657 break; 17658 17659 case OPCODE_CMN: 17660 new_inst = OPCODE_CMP; 17661 value = negated; 17662 break; 17663 17664 /* Now Inverted ops. */ 17665 case OPCODE_MOV: /* MOV <-> MVN */ 17666 new_inst = OPCODE_MVN; 17667 value = inverted; 17668 break; 17669 17670 case OPCODE_MVN: 17671 new_inst = OPCODE_MOV; 17672 value = inverted; 17673 break; 17674 17675 case OPCODE_AND: /* AND <-> BIC */ 17676 new_inst = OPCODE_BIC; 17677 value = inverted; 17678 break; 17679 17680 case OPCODE_BIC: 17681 new_inst = OPCODE_AND; 17682 value = inverted; 17683 break; 17684 17685 case OPCODE_ADC: /* ADC <-> SBC */ 17686 new_inst = OPCODE_SBC; 17687 value = inverted; 17688 break; 17689 17690 case OPCODE_SBC: 17691 new_inst = OPCODE_ADC; 17692 value = inverted; 17693 break; 17694 17695 /* We cannot do anything. */ 17696 default: 17697 return FAIL; 17698 } 17699 17700 if (value == (unsigned) FAIL) 17701 return FAIL; 17702 17703 *instruction &= OPCODE_MASK; 17704 *instruction |= new_inst << DATA_OP_SHIFT; 17705 return value; 17706} 17707 17708/* Like negate_data_op, but for Thumb-2. */ 17709 17710static unsigned int 17711thumb32_negate_data_op (offsetT *instruction, unsigned int value) 17712{ 17713 int op, new_inst; 17714 int rd; 17715 unsigned int negated, inverted; 17716 17717 negated = encode_thumb32_immediate (-value); 17718 inverted = encode_thumb32_immediate (~value); 17719 17720 rd = (*instruction >> 8) & 0xf; 17721 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; 17722 switch (op) 17723 { 17724 /* ADD <-> SUB. Includes CMP <-> CMN. */ 17725 case T2_OPCODE_SUB: 17726 new_inst = T2_OPCODE_ADD; 17727 value = negated; 17728 break; 17729 17730 case T2_OPCODE_ADD: 17731 new_inst = T2_OPCODE_SUB; 17732 value = negated; 17733 break; 17734 17735 /* ORR <-> ORN. Includes MOV <-> MVN. */ 17736 case T2_OPCODE_ORR: 17737 new_inst = T2_OPCODE_ORN; 17738 value = inverted; 17739 break; 17740 17741 case T2_OPCODE_ORN: 17742 new_inst = T2_OPCODE_ORR; 17743 value = inverted; 17744 break; 17745 17746 /* AND <-> BIC. TST has no inverted equivalent. */ 17747 case T2_OPCODE_AND: 17748 new_inst = T2_OPCODE_BIC; 17749 if (rd == 15) 17750 value = FAIL; 17751 else 17752 value = inverted; 17753 break; 17754 17755 case T2_OPCODE_BIC: 17756 new_inst = T2_OPCODE_AND; 17757 value = inverted; 17758 break; 17759 17760 /* ADC <-> SBC */ 17761 case T2_OPCODE_ADC: 17762 new_inst = T2_OPCODE_SBC; 17763 value = inverted; 17764 break; 17765 17766 case T2_OPCODE_SBC: 17767 new_inst = T2_OPCODE_ADC; 17768 value = inverted; 17769 break; 17770 17771 /* We cannot do anything. */ 17772 default: 17773 return FAIL; 17774 } 17775 17776 if (value == (unsigned int)FAIL) 17777 return FAIL; 17778 17779 *instruction &= T2_OPCODE_MASK; 17780 *instruction |= new_inst << T2_DATA_OP_SHIFT; 17781 return value; 17782} 17783 17784/* Read a 32-bit thumb instruction from buf. */ 17785static unsigned long 17786get_thumb32_insn (char * buf) 17787{ 17788 unsigned long insn; 17789 insn = md_chars_to_number (buf, THUMB_SIZE) << 16; 17790 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 17791 17792 return insn; 17793} 17794 17795 17796/* We usually want to set the low bit on the address of thumb function 17797 symbols. In particular .word foo - . should have the low bit set. 17798 Generic code tries to fold the difference of two symbols to 17799 a constant. Prevent this and force a relocation when the first symbols 17800 is a thumb function. */ 17801int 17802arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) 17803{ 17804 if (op == O_subtract 17805 && l->X_op == O_symbol 17806 && r->X_op == O_symbol 17807 && THUMB_IS_FUNC (l->X_add_symbol)) 17808 { 17809 l->X_op = O_subtract; 17810 l->X_op_symbol = r->X_add_symbol; 17811 l->X_add_number -= r->X_add_number; 17812 return 1; 17813 } 17814 /* Process as normal. */ 17815 return 0; 17816} 17817 17818void 17819md_apply_fix (fixS * fixP, 17820 valueT * valP, 17821 segT seg) 17822{ 17823 offsetT value = * valP; 17824 offsetT newval; 17825 unsigned int newimm; 17826 unsigned long temp; 17827 int sign; 17828 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; 17829 17830 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); 17831 17832 /* Note whether this will delete the relocation. */ 17833 17834 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 17835 fixP->fx_done = 1; 17836 17837 /* On a 64-bit host, silently truncate 'value' to 32 bits for 17838 consistency with the behavior on 32-bit hosts. Remember value 17839 for emit_reloc. */ 17840 value &= 0xffffffff; 17841 value ^= 0x80000000; 17842 value -= 0x80000000; 17843 17844 *valP = value; 17845 fixP->fx_addnumber = value; 17846 17847 /* Same treatment for fixP->fx_offset. */ 17848 fixP->fx_offset &= 0xffffffff; 17849 fixP->fx_offset ^= 0x80000000; 17850 fixP->fx_offset -= 0x80000000; 17851 17852 switch (fixP->fx_r_type) 17853 { 17854 case BFD_RELOC_NONE: 17855 /* This will need to go in the object file. */ 17856 fixP->fx_done = 0; 17857 break; 17858 17859 case BFD_RELOC_ARM_IMMEDIATE: 17860 /* We claim that this fixup has been processed here, 17861 even if in fact we generate an error because we do 17862 not have a reloc for it, so tc_gen_reloc will reject it. */ 17863 fixP->fx_done = 1; 17864 17865 if (fixP->fx_addsy 17866 && ! S_IS_DEFINED (fixP->fx_addsy)) 17867 { 17868 as_bad_where (fixP->fx_file, fixP->fx_line, 17869 _("undefined symbol %s used as an immediate value"), 17870 S_GET_NAME (fixP->fx_addsy)); 17871 break; 17872 } 17873 17874 newimm = encode_arm_immediate (value); 17875 temp = md_chars_to_number (buf, INSN_SIZE); 17876 17877 /* If the instruction will fail, see if we can fix things up by 17878 changing the opcode. */ 17879 if (newimm == (unsigned int) FAIL 17880 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) 17881 { 17882 as_bad_where (fixP->fx_file, fixP->fx_line, 17883 _("invalid constant (%lx) after fixup"), 17884 (unsigned long) value); 17885 break; 17886 } 17887 17888 newimm |= (temp & 0xfffff000); 17889 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 17890 break; 17891 17892 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 17893 { 17894 unsigned int highpart = 0; 17895 unsigned int newinsn = 0xe1a00000; /* nop. */ 17896 17897 newimm = encode_arm_immediate (value); 17898 temp = md_chars_to_number (buf, INSN_SIZE); 17899 17900 /* If the instruction will fail, see if we can fix things up by 17901 changing the opcode. */ 17902 if (newimm == (unsigned int) FAIL 17903 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) 17904 { 17905 /* No ? OK - try using two ADD instructions to generate 17906 the value. */ 17907 newimm = validate_immediate_twopart (value, & highpart); 17908 17909 /* Yes - then make sure that the second instruction is 17910 also an add. */ 17911 if (newimm != (unsigned int) FAIL) 17912 newinsn = temp; 17913 /* Still No ? Try using a negated value. */ 17914 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) 17915 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; 17916 /* Otherwise - give up. */ 17917 else 17918 { 17919 as_bad_where (fixP->fx_file, fixP->fx_line, 17920 _("unable to compute ADRL instructions for PC offset of 0x%lx"), 17921 (long) value); 17922 break; 17923 } 17924 17925 /* Replace the first operand in the 2nd instruction (which 17926 is the PC) with the destination register. We have 17927 already added in the PC in the first instruction and we 17928 do not want to do it again. */ 17929 newinsn &= ~ 0xf0000; 17930 newinsn |= ((newinsn & 0x0f000) << 4); 17931 } 17932 17933 newimm |= (temp & 0xfffff000); 17934 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 17935 17936 highpart |= (newinsn & 0xfffff000); 17937 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); 17938 } 17939 break; 17940 17941 case BFD_RELOC_ARM_OFFSET_IMM: 17942 if (!fixP->fx_done && seg->use_rela_p) 17943 value = 0; 17944 17945 case BFD_RELOC_ARM_LITERAL: 17946 sign = value >= 0; 17947 17948 if (value < 0) 17949 value = - value; 17950 17951 if (validate_offset_imm (value, 0) == FAIL) 17952 { 17953 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) 17954 as_bad_where (fixP->fx_file, fixP->fx_line, 17955 _("invalid literal constant: pool needs to be closer")); 17956 else 17957 as_bad_where (fixP->fx_file, fixP->fx_line, 17958 _("bad immediate value for offset (%ld)"), 17959 (long) value); 17960 break; 17961 } 17962 17963 newval = md_chars_to_number (buf, INSN_SIZE); 17964 newval &= 0xff7ff000; 17965 newval |= value | (sign ? INDEX_UP : 0); 17966 md_number_to_chars (buf, newval, INSN_SIZE); 17967 break; 17968 17969 case BFD_RELOC_ARM_OFFSET_IMM8: 17970 case BFD_RELOC_ARM_HWLITERAL: 17971 sign = value >= 0; 17972 17973 if (value < 0) 17974 value = - value; 17975 17976 if (validate_offset_imm (value, 1) == FAIL) 17977 { 17978 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) 17979 as_bad_where (fixP->fx_file, fixP->fx_line, 17980 _("invalid literal constant: pool needs to be closer")); 17981 else 17982 as_bad (_("bad immediate value for 8-bit offset (%ld)"), 17983 (long) value); 17984 break; 17985 } 17986 17987 newval = md_chars_to_number (buf, INSN_SIZE); 17988 newval &= 0xff7ff0f0; 17989 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); 17990 md_number_to_chars (buf, newval, INSN_SIZE); 17991 break; 17992 17993 case BFD_RELOC_ARM_T32_OFFSET_U8: 17994 if (value < 0 || value > 1020 || value % 4 != 0) 17995 as_bad_where (fixP->fx_file, fixP->fx_line, 17996 _("bad immediate value for offset (%ld)"), (long) value); 17997 value /= 4; 17998 17999 newval = md_chars_to_number (buf+2, THUMB_SIZE); 18000 newval |= value; 18001 md_number_to_chars (buf+2, newval, THUMB_SIZE); 18002 break; 18003 18004 case BFD_RELOC_ARM_T32_OFFSET_IMM: 18005 /* This is a complicated relocation used for all varieties of Thumb32 18006 load/store instruction with immediate offset: 18007 18008 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, 18009 *4, optional writeback(W) 18010 (doubleword load/store) 18011 18012 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel 18013 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit 18014 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) 18015 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit 18016 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit 18017 18018 Uppercase letters indicate bits that are already encoded at 18019 this point. Lowercase letters are our problem. For the 18020 second block of instructions, the secondary opcode nybble 18021 (bits 8..11) is present, and bit 23 is zero, even if this is 18022 a PC-relative operation. */ 18023 newval = md_chars_to_number (buf, THUMB_SIZE); 18024 newval <<= 16; 18025 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); 18026 18027 if ((newval & 0xf0000000) == 0xe0000000) 18028 { 18029 /* Doubleword load/store: 8-bit offset, scaled by 4. */ 18030 if (value >= 0) 18031 newval |= (1 << 23); 18032 else 18033 value = -value; 18034 if (value % 4 != 0) 18035 { 18036 as_bad_where (fixP->fx_file, fixP->fx_line, 18037 _("offset not a multiple of 4")); 18038 break; 18039 } 18040 value /= 4; 18041 if (value > 0xff) 18042 { 18043 as_bad_where (fixP->fx_file, fixP->fx_line, 18044 _("offset out of range")); 18045 break; 18046 } 18047 newval &= ~0xff; 18048 } 18049 else if ((newval & 0x000f0000) == 0x000f0000) 18050 { 18051 /* PC-relative, 12-bit offset. */ 18052 if (value >= 0) 18053 newval |= (1 << 23); 18054 else 18055 value = -value; 18056 if (value > 0xfff) 18057 { 18058 as_bad_where (fixP->fx_file, fixP->fx_line, 18059 _("offset out of range")); 18060 break; 18061 } 18062 newval &= ~0xfff; 18063 } 18064 else if ((newval & 0x00000100) == 0x00000100) 18065 { 18066 /* Writeback: 8-bit, +/- offset. */ 18067 if (value >= 0) 18068 newval |= (1 << 9); 18069 else 18070 value = -value; 18071 if (value > 0xff) 18072 { 18073 as_bad_where (fixP->fx_file, fixP->fx_line, 18074 _("offset out of range")); 18075 break; 18076 } 18077 newval &= ~0xff; 18078 } 18079 else if ((newval & 0x00000f00) == 0x00000e00) 18080 { 18081 /* T-instruction: positive 8-bit offset. */ 18082 if (value < 0 || value > 0xff) 18083 { 18084 as_bad_where (fixP->fx_file, fixP->fx_line, 18085 _("offset out of range")); 18086 break; 18087 } 18088 newval &= ~0xff; 18089 newval |= value; 18090 } 18091 else 18092 { 18093 /* Positive 12-bit or negative 8-bit offset. */ 18094 int limit; 18095 if (value >= 0) 18096 { 18097 newval |= (1 << 23); 18098 limit = 0xfff; 18099 } 18100 else 18101 { 18102 value = -value; 18103 limit = 0xff; 18104 } 18105 if (value > limit) 18106 { 18107 as_bad_where (fixP->fx_file, fixP->fx_line, 18108 _("offset out of range")); 18109 break; 18110 } 18111 newval &= ~limit; 18112 } 18113 18114 newval |= value; 18115 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); 18116 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); 18117 break; 18118 18119 case BFD_RELOC_ARM_SHIFT_IMM: 18120 newval = md_chars_to_number (buf, INSN_SIZE); 18121 if (((unsigned long) value) > 32 18122 || (value == 32 18123 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) 18124 { 18125 as_bad_where (fixP->fx_file, fixP->fx_line, 18126 _("shift expression is too large")); 18127 break; 18128 } 18129 18130 if (value == 0) 18131 /* Shifts of zero must be done as lsl. */ 18132 newval &= ~0x60; 18133 else if (value == 32) 18134 value = 0; 18135 newval &= 0xfffff07f; 18136 newval |= (value & 0x1f) << 7; 18137 md_number_to_chars (buf, newval, INSN_SIZE); 18138 break; 18139 18140 case BFD_RELOC_ARM_T32_IMMEDIATE: 18141 case BFD_RELOC_ARM_T32_ADD_IMM: 18142 case BFD_RELOC_ARM_T32_IMM12: 18143 case BFD_RELOC_ARM_T32_ADD_PC12: 18144 /* We claim that this fixup has been processed here, 18145 even if in fact we generate an error because we do 18146 not have a reloc for it, so tc_gen_reloc will reject it. */ 18147 fixP->fx_done = 1; 18148 18149 if (fixP->fx_addsy 18150 && ! S_IS_DEFINED (fixP->fx_addsy)) 18151 { 18152 as_bad_where (fixP->fx_file, fixP->fx_line, 18153 _("undefined symbol %s used as an immediate value"), 18154 S_GET_NAME (fixP->fx_addsy)); 18155 break; 18156 } 18157 18158 newval = md_chars_to_number (buf, THUMB_SIZE); 18159 newval <<= 16; 18160 newval |= md_chars_to_number (buf+2, THUMB_SIZE); 18161 18162 newimm = FAIL; 18163 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 18164 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18165 { 18166 newimm = encode_thumb32_immediate (value); 18167 if (newimm == (unsigned int) FAIL) 18168 newimm = thumb32_negate_data_op (&newval, value); 18169 } 18170 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE 18171 && newimm == (unsigned int) FAIL) 18172 { 18173 /* Turn add/sum into addw/subw. */ 18174 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18175 newval = (newval & 0xfeffffff) | 0x02000000; 18176 18177 /* 12 bit immediate for addw/subw. */ 18178 if (value < 0) 18179 { 18180 value = -value; 18181 newval ^= 0x00a00000; 18182 } 18183 if (value > 0xfff) 18184 newimm = (unsigned int) FAIL; 18185 else 18186 newimm = value; 18187 } 18188 18189 if (newimm == (unsigned int)FAIL) 18190 { 18191 as_bad_where (fixP->fx_file, fixP->fx_line, 18192 _("invalid constant (%lx) after fixup"), 18193 (unsigned long) value); 18194 break; 18195 } 18196 18197 newval |= (newimm & 0x800) << 15; 18198 newval |= (newimm & 0x700) << 4; 18199 newval |= (newimm & 0x0ff); 18200 18201 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); 18202 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); 18203 break; 18204 18205 case BFD_RELOC_ARM_SMC: 18206 if (((unsigned long) value) > 0xffff) 18207 as_bad_where (fixP->fx_file, fixP->fx_line, 18208 _("invalid smc expression")); 18209 newval = md_chars_to_number (buf, INSN_SIZE); 18210 newval |= (value & 0xf) | ((value & 0xfff0) << 4); 18211 md_number_to_chars (buf, newval, INSN_SIZE); 18212 break; 18213 18214 case BFD_RELOC_ARM_SWI: 18215 if (fixP->tc_fix_data != 0) 18216 { 18217 if (((unsigned long) value) > 0xff) 18218 as_bad_where (fixP->fx_file, fixP->fx_line, 18219 _("invalid swi expression")); 18220 newval = md_chars_to_number (buf, THUMB_SIZE); 18221 newval |= value; 18222 md_number_to_chars (buf, newval, THUMB_SIZE); 18223 } 18224 else 18225 { 18226 if (((unsigned long) value) > 0x00ffffff) 18227 as_bad_where (fixP->fx_file, fixP->fx_line, 18228 _("invalid swi expression")); 18229 newval = md_chars_to_number (buf, INSN_SIZE); 18230 newval |= value; 18231 md_number_to_chars (buf, newval, INSN_SIZE); 18232 } 18233 break; 18234 18235 case BFD_RELOC_ARM_MULTI: 18236 if (((unsigned long) value) > 0xffff) 18237 as_bad_where (fixP->fx_file, fixP->fx_line, 18238 _("invalid expression in load/store multiple")); 18239 newval = value | md_chars_to_number (buf, INSN_SIZE); 18240 md_number_to_chars (buf, newval, INSN_SIZE); 18241 break; 18242 18243#ifdef OBJ_ELF 18244 case BFD_RELOC_ARM_PCREL_CALL: 18245 newval = md_chars_to_number (buf, INSN_SIZE); 18246 if ((newval & 0xf0000000) == 0xf0000000) 18247 temp = 1; 18248 else 18249 temp = 3; 18250 goto arm_branch_common; 18251 18252 case BFD_RELOC_ARM_PCREL_JUMP: 18253 case BFD_RELOC_ARM_PLT32: 18254#endif 18255 case BFD_RELOC_ARM_PCREL_BRANCH: 18256 temp = 3; 18257 goto arm_branch_common; 18258 18259 case BFD_RELOC_ARM_PCREL_BLX: 18260 temp = 1; 18261 arm_branch_common: 18262 /* We are going to store value (shifted right by two) in the 18263 instruction, in a 24 bit, signed field. Bits 26 through 32 either 18264 all clear or all set and bit 0 must be clear. For B/BL bit 1 must 18265 also be be clear. */ 18266 if (value & temp) 18267 as_bad_where (fixP->fx_file, fixP->fx_line, 18268 _("misaligned branch destination")); 18269 if ((value & (offsetT)0xfe000000) != (offsetT)0 18270 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) 18271 as_bad_where (fixP->fx_file, fixP->fx_line, 18272 _("branch out of range")); 18273 18274 if (fixP->fx_done || !seg->use_rela_p) 18275 { 18276 newval = md_chars_to_number (buf, INSN_SIZE); 18277 newval |= (value >> 2) & 0x00ffffff; 18278 /* Set the H bit on BLX instructions. */ 18279 if (temp == 1) 18280 { 18281 if (value & 2) 18282 newval |= 0x01000000; 18283 else 18284 newval &= ~0x01000000; 18285 } 18286 md_number_to_chars (buf, newval, INSN_SIZE); 18287 } 18288 break; 18289 18290 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ 18291 /* CBZ can only branch forward. */ 18292 18293 /* Attempts to use CBZ to branch to the next instruction 18294 (which, strictly speaking, are prohibited) will be turned into 18295 no-ops. 18296 18297 FIXME: It may be better to remove the instruction completely and 18298 perform relaxation. */ 18299 if (value == -2) 18300 { 18301 newval = md_chars_to_number (buf, THUMB_SIZE); 18302 newval = 0xbf00; /* NOP encoding T1 */ 18303 md_number_to_chars (buf, newval, THUMB_SIZE); 18304 } 18305 else 18306 { 18307 if (value & ~0x7e) 18308 as_bad_where (fixP->fx_file, fixP->fx_line, 18309 _("branch out of range")); 18310 18311 if (fixP->fx_done || !seg->use_rela_p) 18312 { 18313 newval = md_chars_to_number (buf, THUMB_SIZE); 18314 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); 18315 md_number_to_chars (buf, newval, THUMB_SIZE); 18316 } 18317 } 18318 break; 18319 18320 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ 18321 if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) 18322 as_bad_where (fixP->fx_file, fixP->fx_line, 18323 _("branch out of range")); 18324 18325 if (fixP->fx_done || !seg->use_rela_p) 18326 { 18327 newval = md_chars_to_number (buf, THUMB_SIZE); 18328 newval |= (value & 0x1ff) >> 1; 18329 md_number_to_chars (buf, newval, THUMB_SIZE); 18330 } 18331 break; 18332 18333 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ 18334 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) 18335 as_bad_where (fixP->fx_file, fixP->fx_line, 18336 _("branch out of range")); 18337 18338 if (fixP->fx_done || !seg->use_rela_p) 18339 { 18340 newval = md_chars_to_number (buf, THUMB_SIZE); 18341 newval |= (value & 0xfff) >> 1; 18342 md_number_to_chars (buf, newval, THUMB_SIZE); 18343 } 18344 break; 18345 18346 case BFD_RELOC_THUMB_PCREL_BRANCH20: 18347 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) 18348 as_bad_where (fixP->fx_file, fixP->fx_line, 18349 _("conditional branch out of range")); 18350 18351 if (fixP->fx_done || !seg->use_rela_p) 18352 { 18353 offsetT newval2; 18354 addressT S, J1, J2, lo, hi; 18355 18356 S = (value & 0x00100000) >> 20; 18357 J2 = (value & 0x00080000) >> 19; 18358 J1 = (value & 0x00040000) >> 18; 18359 hi = (value & 0x0003f000) >> 12; 18360 lo = (value & 0x00000ffe) >> 1; 18361 18362 newval = md_chars_to_number (buf, THUMB_SIZE); 18363 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18364 newval |= (S << 10) | hi; 18365 newval2 |= (J1 << 13) | (J2 << 11) | lo; 18366 md_number_to_chars (buf, newval, THUMB_SIZE); 18367 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18368 } 18369 break; 18370 18371 case BFD_RELOC_THUMB_PCREL_BLX: 18372 case BFD_RELOC_THUMB_PCREL_BRANCH23: 18373 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) 18374 as_bad_where (fixP->fx_file, fixP->fx_line, 18375 _("branch out of range")); 18376 18377 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) 18378 /* For a BLX instruction, make sure that the relocation is rounded up 18379 to a word boundary. This follows the semantics of the instruction 18380 which specifies that bit 1 of the target address will come from bit 18381 1 of the base address. */ 18382 value = (value + 1) & ~ 1; 18383 18384 if (fixP->fx_done || !seg->use_rela_p) 18385 { 18386 offsetT newval2; 18387 18388 newval = md_chars_to_number (buf, THUMB_SIZE); 18389 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18390 newval |= (value & 0x7fffff) >> 12; 18391 newval2 |= (value & 0xfff) >> 1; 18392 md_number_to_chars (buf, newval, THUMB_SIZE); 18393 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18394 } 18395 break; 18396 18397 case BFD_RELOC_THUMB_PCREL_BRANCH25: 18398 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) 18399 as_bad_where (fixP->fx_file, fixP->fx_line, 18400 _("branch out of range")); 18401 18402 if (fixP->fx_done || !seg->use_rela_p) 18403 { 18404 offsetT newval2; 18405 addressT S, I1, I2, lo, hi; 18406 18407 S = (value & 0x01000000) >> 24; 18408 I1 = (value & 0x00800000) >> 23; 18409 I2 = (value & 0x00400000) >> 22; 18410 hi = (value & 0x003ff000) >> 12; 18411 lo = (value & 0x00000ffe) >> 1; 18412 18413 I1 = !(I1 ^ S); 18414 I2 = !(I2 ^ S); 18415 18416 newval = md_chars_to_number (buf, THUMB_SIZE); 18417 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18418 newval |= (S << 10) | hi; 18419 newval2 |= (I1 << 13) | (I2 << 11) | lo; 18420 md_number_to_chars (buf, newval, THUMB_SIZE); 18421 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18422 } 18423 break; 18424 18425 case BFD_RELOC_8: 18426 if (fixP->fx_done || !seg->use_rela_p) 18427 md_number_to_chars (buf, value, 1); 18428 break; 18429 18430 case BFD_RELOC_16: 18431 if (fixP->fx_done || !seg->use_rela_p) 18432 md_number_to_chars (buf, value, 2); 18433 break; 18434 18435#ifdef OBJ_ELF 18436 case BFD_RELOC_ARM_TLS_GD32: 18437 case BFD_RELOC_ARM_TLS_LE32: 18438 case BFD_RELOC_ARM_TLS_IE32: 18439 case BFD_RELOC_ARM_TLS_LDM32: 18440 case BFD_RELOC_ARM_TLS_LDO32: 18441 S_SET_THREAD_LOCAL (fixP->fx_addsy); 18442 /* fall through */ 18443 18444 case BFD_RELOC_ARM_GOT32: 18445 case BFD_RELOC_ARM_GOTOFF: 18446 case BFD_RELOC_ARM_TARGET2: 18447 if (fixP->fx_done || !seg->use_rela_p) 18448 md_number_to_chars (buf, 0, 4); 18449 break; 18450#endif 18451 18452 case BFD_RELOC_RVA: 18453 case BFD_RELOC_32: 18454 case BFD_RELOC_ARM_TARGET1: 18455 case BFD_RELOC_ARM_ROSEGREL32: 18456 case BFD_RELOC_ARM_SBREL32: 18457 case BFD_RELOC_32_PCREL: 18458#ifdef TE_PE 18459 case BFD_RELOC_32_SECREL: 18460#endif 18461 if (fixP->fx_done || !seg->use_rela_p) 18462#ifdef TE_WINCE 18463 /* For WinCE we only do this for pcrel fixups. */ 18464 if (fixP->fx_done || fixP->fx_pcrel) 18465#endif 18466 md_number_to_chars (buf, value, 4); 18467 break; 18468 18469#ifdef OBJ_ELF 18470 case BFD_RELOC_ARM_PREL31: 18471 if (fixP->fx_done || !seg->use_rela_p) 18472 { 18473 newval = md_chars_to_number (buf, 4) & 0x80000000; 18474 if ((value ^ (value >> 1)) & 0x40000000) 18475 { 18476 as_bad_where (fixP->fx_file, fixP->fx_line, 18477 _("rel31 relocation overflow")); 18478 } 18479 newval |= value & 0x7fffffff; 18480 md_number_to_chars (buf, newval, 4); 18481 } 18482 break; 18483#endif 18484 18485 case BFD_RELOC_ARM_CP_OFF_IMM: 18486 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 18487 if (value < -1023 || value > 1023 || (value & 3)) 18488 as_bad_where (fixP->fx_file, fixP->fx_line, 18489 _("co-processor offset out of range")); 18490 cp_off_common: 18491 sign = value >= 0; 18492 if (value < 0) 18493 value = -value; 18494 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18495 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18496 newval = md_chars_to_number (buf, INSN_SIZE); 18497 else 18498 newval = get_thumb32_insn (buf); 18499 newval &= 0xff7fff00; 18500 newval |= (value >> 2) | (sign ? INDEX_UP : 0); 18501 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18502 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18503 md_number_to_chars (buf, newval, INSN_SIZE); 18504 else 18505 put_thumb32_insn (buf, newval); 18506 break; 18507 18508 case BFD_RELOC_ARM_CP_OFF_IMM_S2: 18509 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: 18510 if (value < -255 || value > 255) 18511 as_bad_where (fixP->fx_file, fixP->fx_line, 18512 _("co-processor offset out of range")); 18513 value *= 4; 18514 goto cp_off_common; 18515 18516 case BFD_RELOC_ARM_THUMB_OFFSET: 18517 newval = md_chars_to_number (buf, THUMB_SIZE); 18518 /* Exactly what ranges, and where the offset is inserted depends 18519 on the type of instruction, we can establish this from the 18520 top 4 bits. */ 18521 switch (newval >> 12) 18522 { 18523 case 4: /* PC load. */ 18524 /* Thumb PC loads are somewhat odd, bit 1 of the PC is 18525 forced to zero for these loads; md_pcrel_from has already 18526 compensated for this. */ 18527 if (value & 3) 18528 as_bad_where (fixP->fx_file, fixP->fx_line, 18529 _("invalid offset, target not word aligned (0x%08lX)"), 18530 (((unsigned long) fixP->fx_frag->fr_address 18531 + (unsigned long) fixP->fx_where) & ~3) 18532 + (unsigned long) value); 18533 18534 if (value & ~0x3fc) 18535 as_bad_where (fixP->fx_file, fixP->fx_line, 18536 _("invalid offset, value too big (0x%08lX)"), 18537 (long) value); 18538 18539 newval |= value >> 2; 18540 break; 18541 18542 case 9: /* SP load/store. */ 18543 if (value & ~0x3fc) 18544 as_bad_where (fixP->fx_file, fixP->fx_line, 18545 _("invalid offset, value too big (0x%08lX)"), 18546 (long) value); 18547 newval |= value >> 2; 18548 break; 18549 18550 case 6: /* Word load/store. */ 18551 if (value & ~0x7c) 18552 as_bad_where (fixP->fx_file, fixP->fx_line, 18553 _("invalid offset, value too big (0x%08lX)"), 18554 (long) value); 18555 newval |= value << 4; /* 6 - 2. */ 18556 break; 18557 18558 case 7: /* Byte load/store. */ 18559 if (value & ~0x1f) 18560 as_bad_where (fixP->fx_file, fixP->fx_line, 18561 _("invalid offset, value too big (0x%08lX)"), 18562 (long) value); 18563 newval |= value << 6; 18564 break; 18565 18566 case 8: /* Halfword load/store. */ 18567 if (value & ~0x3e) 18568 as_bad_where (fixP->fx_file, fixP->fx_line, 18569 _("invalid offset, value too big (0x%08lX)"), 18570 (long) value); 18571 newval |= value << 5; /* 6 - 1. */ 18572 break; 18573 18574 default: 18575 as_bad_where (fixP->fx_file, fixP->fx_line, 18576 "Unable to process relocation for thumb opcode: %lx", 18577 (unsigned long) newval); 18578 break; 18579 } 18580 md_number_to_chars (buf, newval, THUMB_SIZE); 18581 break; 18582 18583 case BFD_RELOC_ARM_THUMB_ADD: 18584 /* This is a complicated relocation, since we use it for all of 18585 the following immediate relocations: 18586 18587 3bit ADD/SUB 18588 8bit ADD/SUB 18589 9bit ADD/SUB SP word-aligned 18590 10bit ADD PC/SP word-aligned 18591 18592 The type of instruction being processed is encoded in the 18593 instruction field: 18594 18595 0x8000 SUB 18596 0x00F0 Rd 18597 0x000F Rs 18598 */ 18599 newval = md_chars_to_number (buf, THUMB_SIZE); 18600 { 18601 int rd = (newval >> 4) & 0xf; 18602 int rs = newval & 0xf; 18603 int subtract = !!(newval & 0x8000); 18604 18605 /* Check for HI regs, only very restricted cases allowed: 18606 Adjusting SP, and using PC or SP to get an address. */ 18607 if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) 18608 || (rs > 7 && rs != REG_SP && rs != REG_PC)) 18609 as_bad_where (fixP->fx_file, fixP->fx_line, 18610 _("invalid Hi register with immediate")); 18611 18612 /* If value is negative, choose the opposite instruction. */ 18613 if (value < 0) 18614 { 18615 value = -value; 18616 subtract = !subtract; 18617 if (value < 0) 18618 as_bad_where (fixP->fx_file, fixP->fx_line, 18619 _("immediate value out of range")); 18620 } 18621 18622 if (rd == REG_SP) 18623 { 18624 if (value & ~0x1fc) 18625 as_bad_where (fixP->fx_file, fixP->fx_line, 18626 _("invalid immediate for stack address calculation")); 18627 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; 18628 newval |= value >> 2; 18629 } 18630 else if (rs == REG_PC || rs == REG_SP) 18631 { 18632 if (subtract || value & ~0x3fc) 18633 as_bad_where (fixP->fx_file, fixP->fx_line, 18634 _("invalid immediate for address calculation (value = 0x%08lX)"), 18635 (unsigned long) value); 18636 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); 18637 newval |= rd << 8; 18638 newval |= value >> 2; 18639 } 18640 else if (rs == rd) 18641 { 18642 if (value & ~0xff) 18643 as_bad_where (fixP->fx_file, fixP->fx_line, 18644 _("immediate value out of range")); 18645 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; 18646 newval |= (rd << 8) | value; 18647 } 18648 else 18649 { 18650 if (value & ~0x7) 18651 as_bad_where (fixP->fx_file, fixP->fx_line, 18652 _("immediate value out of range")); 18653 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; 18654 newval |= rd | (rs << 3) | (value << 6); 18655 } 18656 } 18657 md_number_to_chars (buf, newval, THUMB_SIZE); 18658 break; 18659 18660 case BFD_RELOC_ARM_THUMB_IMM: 18661 newval = md_chars_to_number (buf, THUMB_SIZE); 18662 if (value < 0 || value > 255) 18663 as_bad_where (fixP->fx_file, fixP->fx_line, 18664 _("invalid immediate: %ld is too large"), 18665 (long) value); 18666 newval |= value; 18667 md_number_to_chars (buf, newval, THUMB_SIZE); 18668 break; 18669 18670 case BFD_RELOC_ARM_THUMB_SHIFT: 18671 /* 5bit shift value (0..32). LSL cannot take 32. */ 18672 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; 18673 temp = newval & 0xf800; 18674 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) 18675 as_bad_where (fixP->fx_file, fixP->fx_line, 18676 _("invalid shift value: %ld"), (long) value); 18677 /* Shifts of zero must be encoded as LSL. */ 18678 if (value == 0) 18679 newval = (newval & 0x003f) | T_OPCODE_LSL_I; 18680 /* Shifts of 32 are encoded as zero. */ 18681 else if (value == 32) 18682 value = 0; 18683 newval |= value << 6; 18684 md_number_to_chars (buf, newval, THUMB_SIZE); 18685 break; 18686 18687 case BFD_RELOC_VTABLE_INHERIT: 18688 case BFD_RELOC_VTABLE_ENTRY: 18689 fixP->fx_done = 0; 18690 return; 18691 18692 case BFD_RELOC_ARM_MOVW: 18693 case BFD_RELOC_ARM_MOVT: 18694 case BFD_RELOC_ARM_THUMB_MOVW: 18695 case BFD_RELOC_ARM_THUMB_MOVT: 18696 if (fixP->fx_done || !seg->use_rela_p) 18697 { 18698 /* REL format relocations are limited to a 16-bit addend. */ 18699 if (!fixP->fx_done) 18700 { 18701 if (value < -0x1000 || value > 0xffff) 18702 as_bad_where (fixP->fx_file, fixP->fx_line, 18703 _("offset too big")); 18704 } 18705 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT 18706 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18707 { 18708 value >>= 16; 18709 } 18710 18711 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 18712 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18713 { 18714 newval = get_thumb32_insn (buf); 18715 newval &= 0xfbf08f00; 18716 newval |= (value & 0xf000) << 4; 18717 newval |= (value & 0x0800) << 15; 18718 newval |= (value & 0x0700) << 4; 18719 newval |= (value & 0x00ff); 18720 put_thumb32_insn (buf, newval); 18721 } 18722 else 18723 { 18724 newval = md_chars_to_number (buf, 4); 18725 newval &= 0xfff0f000; 18726 newval |= value & 0x0fff; 18727 newval |= (value & 0xf000) << 4; 18728 md_number_to_chars (buf, newval, 4); 18729 } 18730 } 18731 return; 18732 18733 case BFD_RELOC_ARM_ALU_PC_G0_NC: 18734 case BFD_RELOC_ARM_ALU_PC_G0: 18735 case BFD_RELOC_ARM_ALU_PC_G1_NC: 18736 case BFD_RELOC_ARM_ALU_PC_G1: 18737 case BFD_RELOC_ARM_ALU_PC_G2: 18738 case BFD_RELOC_ARM_ALU_SB_G0_NC: 18739 case BFD_RELOC_ARM_ALU_SB_G0: 18740 case BFD_RELOC_ARM_ALU_SB_G1_NC: 18741 case BFD_RELOC_ARM_ALU_SB_G1: 18742 case BFD_RELOC_ARM_ALU_SB_G2: 18743 assert (!fixP->fx_done); 18744 if (!seg->use_rela_p) 18745 { 18746 bfd_vma insn; 18747 bfd_vma encoded_addend; 18748 bfd_vma addend_abs = abs (value); 18749 18750 /* Check that the absolute value of the addend can be 18751 expressed as an 8-bit constant plus a rotation. */ 18752 encoded_addend = encode_arm_immediate (addend_abs); 18753 if (encoded_addend == (unsigned int) FAIL) 18754 as_bad_where (fixP->fx_file, fixP->fx_line, 18755 _("the offset 0x%08lX is not representable"), 18756 (unsigned long) addend_abs); 18757 18758 /* Extract the instruction. */ 18759 insn = md_chars_to_number (buf, INSN_SIZE); 18760 18761 /* If the addend is positive, use an ADD instruction. 18762 Otherwise use a SUB. Take care not to destroy the S bit. */ 18763 insn &= 0xff1fffff; 18764 if (value < 0) 18765 insn |= 1 << 22; 18766 else 18767 insn |= 1 << 23; 18768 18769 /* Place the encoded addend into the first 12 bits of the 18770 instruction. */ 18771 insn &= 0xfffff000; 18772 insn |= encoded_addend; 18773 18774 /* Update the instruction. */ 18775 md_number_to_chars (buf, insn, INSN_SIZE); 18776 } 18777 break; 18778 18779 case BFD_RELOC_ARM_LDR_PC_G0: 18780 case BFD_RELOC_ARM_LDR_PC_G1: 18781 case BFD_RELOC_ARM_LDR_PC_G2: 18782 case BFD_RELOC_ARM_LDR_SB_G0: 18783 case BFD_RELOC_ARM_LDR_SB_G1: 18784 case BFD_RELOC_ARM_LDR_SB_G2: 18785 assert (!fixP->fx_done); 18786 if (!seg->use_rela_p) 18787 { 18788 bfd_vma insn; 18789 bfd_vma addend_abs = abs (value); 18790 18791 /* Check that the absolute value of the addend can be 18792 encoded in 12 bits. */ 18793 if (addend_abs >= 0x1000) 18794 as_bad_where (fixP->fx_file, fixP->fx_line, 18795 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), 18796 (unsigned long) addend_abs); 18797 18798 /* Extract the instruction. */ 18799 insn = md_chars_to_number (buf, INSN_SIZE); 18800 18801 /* If the addend is negative, clear bit 23 of the instruction. 18802 Otherwise set it. */ 18803 if (value < 0) 18804 insn &= ~(1 << 23); 18805 else 18806 insn |= 1 << 23; 18807 18808 /* Place the absolute value of the addend into the first 12 bits 18809 of the instruction. */ 18810 insn &= 0xfffff000; 18811 insn |= addend_abs; 18812 18813 /* Update the instruction. */ 18814 md_number_to_chars (buf, insn, INSN_SIZE); 18815 } 18816 break; 18817 18818 case BFD_RELOC_ARM_LDRS_PC_G0: 18819 case BFD_RELOC_ARM_LDRS_PC_G1: 18820 case BFD_RELOC_ARM_LDRS_PC_G2: 18821 case BFD_RELOC_ARM_LDRS_SB_G0: 18822 case BFD_RELOC_ARM_LDRS_SB_G1: 18823 case BFD_RELOC_ARM_LDRS_SB_G2: 18824 assert (!fixP->fx_done); 18825 if (!seg->use_rela_p) 18826 { 18827 bfd_vma insn; 18828 bfd_vma addend_abs = abs (value); 18829 18830 /* Check that the absolute value of the addend can be 18831 encoded in 8 bits. */ 18832 if (addend_abs >= 0x100) 18833 as_bad_where (fixP->fx_file, fixP->fx_line, 18834 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), 18835 (unsigned long) addend_abs); 18836 18837 /* Extract the instruction. */ 18838 insn = md_chars_to_number (buf, INSN_SIZE); 18839 18840 /* If the addend is negative, clear bit 23 of the instruction. 18841 Otherwise set it. */ 18842 if (value < 0) 18843 insn &= ~(1 << 23); 18844 else 18845 insn |= 1 << 23; 18846 18847 /* Place the first four bits of the absolute value of the addend 18848 into the first 4 bits of the instruction, and the remaining 18849 four into bits 8 .. 11. */ 18850 insn &= 0xfffff0f0; 18851 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); 18852 18853 /* Update the instruction. */ 18854 md_number_to_chars (buf, insn, INSN_SIZE); 18855 } 18856 break; 18857 18858 case BFD_RELOC_ARM_LDC_PC_G0: 18859 case BFD_RELOC_ARM_LDC_PC_G1: 18860 case BFD_RELOC_ARM_LDC_PC_G2: 18861 case BFD_RELOC_ARM_LDC_SB_G0: 18862 case BFD_RELOC_ARM_LDC_SB_G1: 18863 case BFD_RELOC_ARM_LDC_SB_G2: 18864 assert (!fixP->fx_done); 18865 if (!seg->use_rela_p) 18866 { 18867 bfd_vma insn; 18868 bfd_vma addend_abs = abs (value); 18869 18870 /* Check that the absolute value of the addend is a multiple of 18871 four and, when divided by four, fits in 8 bits. */ 18872 if (addend_abs & 0x3) 18873 as_bad_where (fixP->fx_file, fixP->fx_line, 18874 _("bad offset 0x%08lX (must be word-aligned)"), 18875 (unsigned long) addend_abs); 18876 18877 if ((addend_abs >> 2) > 0xff) 18878 as_bad_where (fixP->fx_file, fixP->fx_line, 18879 _("bad offset 0x%08lX (must be an 8-bit number of words)"), 18880 (unsigned long) addend_abs); 18881 18882 /* Extract the instruction. */ 18883 insn = md_chars_to_number (buf, INSN_SIZE); 18884 18885 /* If the addend is negative, clear bit 23 of the instruction. 18886 Otherwise set it. */ 18887 if (value < 0) 18888 insn &= ~(1 << 23); 18889 else 18890 insn |= 1 << 23; 18891 18892 /* Place the addend (divided by four) into the first eight 18893 bits of the instruction. */ 18894 insn &= 0xfffffff0; 18895 insn |= addend_abs >> 2; 18896 18897 /* Update the instruction. */ 18898 md_number_to_chars (buf, insn, INSN_SIZE); 18899 } 18900 break; 18901 18902 case BFD_RELOC_UNUSED: 18903 default: 18904 as_bad_where (fixP->fx_file, fixP->fx_line, 18905 _("bad relocation fixup type (%d)"), fixP->fx_r_type); 18906 } 18907} 18908 18909/* Translate internal representation of relocation info to BFD target 18910 format. */ 18911 18912arelent * 18913tc_gen_reloc (asection *section, fixS *fixp) 18914{ 18915 arelent * reloc; 18916 bfd_reloc_code_real_type code; 18917 18918 reloc = xmalloc (sizeof (arelent)); 18919 18920 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 18921 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 18922 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 18923 18924 if (fixp->fx_pcrel) 18925 { 18926 if (section->use_rela_p) 18927 fixp->fx_offset -= md_pcrel_from_section (fixp, section); 18928 else 18929 fixp->fx_offset = reloc->address; 18930 } 18931 reloc->addend = fixp->fx_offset; 18932 18933 switch (fixp->fx_r_type) 18934 { 18935 case BFD_RELOC_8: 18936 if (fixp->fx_pcrel) 18937 { 18938 code = BFD_RELOC_8_PCREL; 18939 break; 18940 } 18941 18942 case BFD_RELOC_16: 18943 if (fixp->fx_pcrel) 18944 { 18945 code = BFD_RELOC_16_PCREL; 18946 break; 18947 } 18948 18949 case BFD_RELOC_32: 18950 if (fixp->fx_pcrel) 18951 { 18952 code = BFD_RELOC_32_PCREL; 18953 break; 18954 } 18955 18956 case BFD_RELOC_ARM_MOVW: 18957 if (fixp->fx_pcrel) 18958 { 18959 code = BFD_RELOC_ARM_MOVW_PCREL; 18960 break; 18961 } 18962 18963 case BFD_RELOC_ARM_MOVT: 18964 if (fixp->fx_pcrel) 18965 { 18966 code = BFD_RELOC_ARM_MOVT_PCREL; 18967 break; 18968 } 18969 18970 case BFD_RELOC_ARM_THUMB_MOVW: 18971 if (fixp->fx_pcrel) 18972 { 18973 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; 18974 break; 18975 } 18976 18977 case BFD_RELOC_ARM_THUMB_MOVT: 18978 if (fixp->fx_pcrel) 18979 { 18980 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; 18981 break; 18982 } 18983 18984 case BFD_RELOC_NONE: 18985 case BFD_RELOC_ARM_PCREL_BRANCH: 18986 case BFD_RELOC_ARM_PCREL_BLX: 18987 case BFD_RELOC_RVA: 18988 case BFD_RELOC_THUMB_PCREL_BRANCH7: 18989 case BFD_RELOC_THUMB_PCREL_BRANCH9: 18990 case BFD_RELOC_THUMB_PCREL_BRANCH12: 18991 case BFD_RELOC_THUMB_PCREL_BRANCH20: 18992 case BFD_RELOC_THUMB_PCREL_BRANCH23: 18993 case BFD_RELOC_THUMB_PCREL_BRANCH25: 18994 case BFD_RELOC_THUMB_PCREL_BLX: 18995 case BFD_RELOC_VTABLE_ENTRY: 18996 case BFD_RELOC_VTABLE_INHERIT: 18997#ifdef TE_PE 18998 case BFD_RELOC_32_SECREL: 18999#endif 19000 code = fixp->fx_r_type; 19001 break; 19002 19003 case BFD_RELOC_ARM_LITERAL: 19004 case BFD_RELOC_ARM_HWLITERAL: 19005 /* If this is called then the a literal has 19006 been referenced across a section boundary. */ 19007 as_bad_where (fixp->fx_file, fixp->fx_line, 19008 _("literal referenced across section boundary")); 19009 return NULL; 19010 19011#ifdef OBJ_ELF 19012 case BFD_RELOC_ARM_GOT32: 19013 case BFD_RELOC_ARM_GOTOFF: 19014 case BFD_RELOC_ARM_PLT32: 19015 case BFD_RELOC_ARM_TARGET1: 19016 case BFD_RELOC_ARM_ROSEGREL32: 19017 case BFD_RELOC_ARM_SBREL32: 19018 case BFD_RELOC_ARM_PREL31: 19019 case BFD_RELOC_ARM_TARGET2: 19020 case BFD_RELOC_ARM_TLS_LE32: 19021 case BFD_RELOC_ARM_TLS_LDO32: 19022 case BFD_RELOC_ARM_PCREL_CALL: 19023 case BFD_RELOC_ARM_PCREL_JUMP: 19024 case BFD_RELOC_ARM_ALU_PC_G0_NC: 19025 case BFD_RELOC_ARM_ALU_PC_G0: 19026 case BFD_RELOC_ARM_ALU_PC_G1_NC: 19027 case BFD_RELOC_ARM_ALU_PC_G1: 19028 case BFD_RELOC_ARM_ALU_PC_G2: 19029 case BFD_RELOC_ARM_LDR_PC_G0: 19030 case BFD_RELOC_ARM_LDR_PC_G1: 19031 case BFD_RELOC_ARM_LDR_PC_G2: 19032 case BFD_RELOC_ARM_LDRS_PC_G0: 19033 case BFD_RELOC_ARM_LDRS_PC_G1: 19034 case BFD_RELOC_ARM_LDRS_PC_G2: 19035 case BFD_RELOC_ARM_LDC_PC_G0: 19036 case BFD_RELOC_ARM_LDC_PC_G1: 19037 case BFD_RELOC_ARM_LDC_PC_G2: 19038 case BFD_RELOC_ARM_ALU_SB_G0_NC: 19039 case BFD_RELOC_ARM_ALU_SB_G0: 19040 case BFD_RELOC_ARM_ALU_SB_G1_NC: 19041 case BFD_RELOC_ARM_ALU_SB_G1: 19042 case BFD_RELOC_ARM_ALU_SB_G2: 19043 case BFD_RELOC_ARM_LDR_SB_G0: 19044 case BFD_RELOC_ARM_LDR_SB_G1: 19045 case BFD_RELOC_ARM_LDR_SB_G2: 19046 case BFD_RELOC_ARM_LDRS_SB_G0: 19047 case BFD_RELOC_ARM_LDRS_SB_G1: 19048 case BFD_RELOC_ARM_LDRS_SB_G2: 19049 case BFD_RELOC_ARM_LDC_SB_G0: 19050 case BFD_RELOC_ARM_LDC_SB_G1: 19051 case BFD_RELOC_ARM_LDC_SB_G2: 19052 code = fixp->fx_r_type; 19053 break; 19054 19055 case BFD_RELOC_ARM_TLS_GD32: 19056 case BFD_RELOC_ARM_TLS_IE32: 19057 case BFD_RELOC_ARM_TLS_LDM32: 19058 /* BFD will include the symbol's address in the addend. 19059 But we don't want that, so subtract it out again here. */ 19060 if (!S_IS_COMMON (fixp->fx_addsy)) 19061 reloc->addend -= (*reloc->sym_ptr_ptr)->value; 19062 code = fixp->fx_r_type; 19063 break; 19064#endif 19065 19066 case BFD_RELOC_ARM_IMMEDIATE: 19067 as_bad_where (fixp->fx_file, fixp->fx_line, 19068 _("internal relocation (type: IMMEDIATE) not fixed up")); 19069 return NULL; 19070 19071 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 19072 as_bad_where (fixp->fx_file, fixp->fx_line, 19073 _("ADRL used for a symbol not defined in the same file")); 19074 return NULL; 19075 19076 case BFD_RELOC_ARM_OFFSET_IMM: 19077 if (section->use_rela_p) 19078 { 19079 code = fixp->fx_r_type; 19080 break; 19081 } 19082 19083 if (fixp->fx_addsy != NULL 19084 && !S_IS_DEFINED (fixp->fx_addsy) 19085 && S_IS_LOCAL (fixp->fx_addsy)) 19086 { 19087 as_bad_where (fixp->fx_file, fixp->fx_line, 19088 _("undefined local label `%s'"), 19089 S_GET_NAME (fixp->fx_addsy)); 19090 return NULL; 19091 } 19092 19093 as_bad_where (fixp->fx_file, fixp->fx_line, 19094 _("internal_relocation (type: OFFSET_IMM) not fixed up")); 19095 return NULL; 19096 19097 default: 19098 { 19099 char * type; 19100 19101 switch (fixp->fx_r_type) 19102 { 19103 case BFD_RELOC_NONE: type = "NONE"; break; 19104 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; 19105 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; 19106 case BFD_RELOC_ARM_SMC: type = "SMC"; break; 19107 case BFD_RELOC_ARM_SWI: type = "SWI"; break; 19108 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; 19109 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; 19110 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; 19111 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; 19112 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; 19113 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; 19114 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; 19115 default: type = _("<unknown>"); break; 19116 } 19117 as_bad_where (fixp->fx_file, fixp->fx_line, 19118 _("cannot represent %s relocation in this object file format"), 19119 type); 19120 return NULL; 19121 } 19122 } 19123 19124#ifdef OBJ_ELF 19125 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) 19126 && GOT_symbol 19127 && fixp->fx_addsy == GOT_symbol) 19128 { 19129 code = BFD_RELOC_ARM_GOTPC; 19130 reloc->addend = fixp->fx_offset = reloc->address; 19131 } 19132#endif 19133 19134 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 19135 19136 if (reloc->howto == NULL) 19137 { 19138 as_bad_where (fixp->fx_file, fixp->fx_line, 19139 _("cannot represent %s relocation in this object file format"), 19140 bfd_get_reloc_code_name (code)); 19141 return NULL; 19142 } 19143 19144 /* HACK: Since arm ELF uses Rel instead of Rela, encode the 19145 vtable entry to be used in the relocation's section offset. */ 19146 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19147 reloc->address = fixp->fx_offset; 19148 19149 return reloc; 19150} 19151 19152/* This fix_new is called by cons via TC_CONS_FIX_NEW. */ 19153 19154void 19155cons_fix_new_arm (fragS * frag, 19156 int where, 19157 int size, 19158 expressionS * exp) 19159{ 19160 bfd_reloc_code_real_type type; 19161 int pcrel = 0; 19162 19163 /* Pick a reloc. 19164 FIXME: @@ Should look at CPU word size. */ 19165 switch (size) 19166 { 19167 case 1: 19168 type = BFD_RELOC_8; 19169 break; 19170 case 2: 19171 type = BFD_RELOC_16; 19172 break; 19173 case 4: 19174 default: 19175 type = BFD_RELOC_32; 19176 break; 19177 case 8: 19178 type = BFD_RELOC_64; 19179 break; 19180 } 19181 19182#ifdef TE_PE 19183 if (exp->X_op == O_secrel) 19184 { 19185 exp->X_op = O_symbol; 19186 type = BFD_RELOC_32_SECREL; 19187 } 19188#endif 19189 19190 fix_new_exp (frag, where, (int) size, exp, pcrel, type); 19191} 19192 19193#if defined OBJ_COFF || defined OBJ_ELF 19194void 19195arm_validate_fix (fixS * fixP) 19196{ 19197 /* If the destination of the branch is a defined symbol which does not have 19198 the THUMB_FUNC attribute, then we must be calling a function which has 19199 the (interfacearm) attribute. We look for the Thumb entry point to that 19200 function and change the branch to refer to that function instead. */ 19201 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 19202 && fixP->fx_addsy != NULL 19203 && S_IS_DEFINED (fixP->fx_addsy) 19204 && ! THUMB_IS_FUNC (fixP->fx_addsy)) 19205 { 19206 fixP->fx_addsy = find_real_start (fixP->fx_addsy); 19207 } 19208} 19209#endif 19210 19211int 19212arm_force_relocation (struct fix * fixp) 19213{ 19214#if defined (OBJ_COFF) && defined (TE_PE) 19215 if (fixp->fx_r_type == BFD_RELOC_RVA) 19216 return 1; 19217#endif 19218 19219 /* Resolve these relocations even if the symbol is extern or weak. */ 19220 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE 19221 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM 19222 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE 19223 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM 19224 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 19225 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 19226 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) 19227 return 0; 19228 19229 /* Always leave these relocations for the linker. */ 19230 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19231 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19232 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19233 return 1; 19234 19235 /* Always generate relocations against function symbols. */ 19236 if (fixp->fx_r_type == BFD_RELOC_32 19237 && fixp->fx_addsy 19238 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) 19239 return 1; 19240 19241 return generic_force_reloc (fixp); 19242} 19243 19244#if defined (OBJ_ELF) || defined (OBJ_COFF) 19245/* Relocations against function names must be left unadjusted, 19246 so that the linker can use this information to generate interworking 19247 stubs. The MIPS version of this function 19248 also prevents relocations that are mips-16 specific, but I do not 19249 know why it does this. 19250 19251 FIXME: 19252 There is one other problem that ought to be addressed here, but 19253 which currently is not: Taking the address of a label (rather 19254 than a function) and then later jumping to that address. Such 19255 addresses also ought to have their bottom bit set (assuming that 19256 they reside in Thumb code), but at the moment they will not. */ 19257 19258bfd_boolean 19259arm_fix_adjustable (fixS * fixP) 19260{ 19261 if (fixP->fx_addsy == NULL) 19262 return 1; 19263 19264 /* Preserve relocations against symbols with function type. */ 19265 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) 19266 return 0; 19267 19268 if (THUMB_IS_FUNC (fixP->fx_addsy) 19269 && fixP->fx_subsy == NULL) 19270 return 0; 19271 19272 /* We need the symbol name for the VTABLE entries. */ 19273 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 19274 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19275 return 0; 19276 19277 /* Don't allow symbols to be discarded on GOT related relocs. */ 19278 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 19279 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 19280 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF 19281 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 19282 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 19283 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 19284 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 19285 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 19286 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) 19287 return 0; 19288 19289 /* Similarly for group relocations. */ 19290 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19291 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19292 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19293 return 0; 19294 19295 return 1; 19296} 19297#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ 19298 19299#ifdef OBJ_ELF 19300 19301const char * 19302elf32_arm_target_format (void) 19303{ 19304#ifdef TE_SYMBIAN 19305 return (target_big_endian 19306 ? "elf32-bigarm-symbian" 19307 : "elf32-littlearm-symbian"); 19308#elif defined (TE_VXWORKS) 19309 return (target_big_endian 19310 ? "elf32-bigarm-vxworks" 19311 : "elf32-littlearm-vxworks"); 19312#else 19313 if (target_big_endian) 19314 return "elf32-bigarm"; 19315 else 19316 return "elf32-littlearm"; 19317#endif 19318} 19319 19320void 19321armelf_frob_symbol (symbolS * symp, 19322 int * puntp) 19323{ 19324 elf_frob_symbol (symp, puntp); 19325} 19326#endif 19327 19328/* MD interface: Finalization. */ 19329 19330/* A good place to do this, although this was probably not intended 19331 for this kind of use. We need to dump the literal pool before 19332 references are made to a null symbol pointer. */ 19333 19334void 19335arm_cleanup (void) 19336{ 19337 literal_pool * pool; 19338 19339 for (pool = list_of_pools; pool; pool = pool->next) 19340 { 19341 /* Put it at the end of the relevent section. */ 19342 subseg_set (pool->section, pool->sub_section); 19343#ifdef OBJ_ELF 19344 arm_elf_change_section (); 19345#endif 19346 s_ltorg (0); 19347 } 19348} 19349 19350/* Adjust the symbol table. This marks Thumb symbols as distinct from 19351 ARM ones. */ 19352 19353void 19354arm_adjust_symtab (void) 19355{ 19356#ifdef OBJ_COFF 19357 symbolS * sym; 19358 19359 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19360 { 19361 if (ARM_IS_THUMB (sym)) 19362 { 19363 if (THUMB_IS_FUNC (sym)) 19364 { 19365 /* Mark the symbol as a Thumb function. */ 19366 if ( S_GET_STORAGE_CLASS (sym) == C_STAT 19367 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ 19368 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); 19369 19370 else if (S_GET_STORAGE_CLASS (sym) == C_EXT) 19371 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); 19372 else 19373 as_bad (_("%s: unexpected function type: %d"), 19374 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); 19375 } 19376 else switch (S_GET_STORAGE_CLASS (sym)) 19377 { 19378 case C_EXT: 19379 S_SET_STORAGE_CLASS (sym, C_THUMBEXT); 19380 break; 19381 case C_STAT: 19382 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); 19383 break; 19384 case C_LABEL: 19385 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); 19386 break; 19387 default: 19388 /* Do nothing. */ 19389 break; 19390 } 19391 } 19392 19393 if (ARM_IS_INTERWORK (sym)) 19394 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; 19395 } 19396#endif 19397#ifdef OBJ_ELF 19398 symbolS * sym; 19399 char bind; 19400 19401 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19402 { 19403 if (ARM_IS_THUMB (sym)) 19404 { 19405 elf_symbol_type * elf_sym; 19406 19407 elf_sym = elf_symbol (symbol_get_bfdsym (sym)); 19408 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); 19409 19410 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, 19411 BFD_ARM_SPECIAL_SYM_TYPE_ANY)) 19412 { 19413 /* If it's a .thumb_func, declare it as so, 19414 otherwise tag label as .code 16. */ 19415 if (THUMB_IS_FUNC (sym)) 19416 elf_sym->internal_elf_sym.st_info = 19417 ELF_ST_INFO (bind, STT_ARM_TFUNC); 19418 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 19419 elf_sym->internal_elf_sym.st_info = 19420 ELF_ST_INFO (bind, STT_ARM_16BIT); 19421 } 19422 } 19423 } 19424#endif 19425} 19426 19427/* MD interface: Initialization. */ 19428 19429static void 19430set_constant_flonums (void) 19431{ 19432 int i; 19433 19434 for (i = 0; i < NUM_FLOAT_VALS; i++) 19435 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) 19436 abort (); 19437} 19438 19439/* Auto-select Thumb mode if it's the only available instruction set for the 19440 given architecture. */ 19441 19442static void 19443autoselect_thumb_from_cpu_variant (void) 19444{ 19445 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 19446 opcode_select (16); 19447} 19448 19449void 19450md_begin (void) 19451{ 19452 unsigned mach; 19453 unsigned int i; 19454 19455 if ( (arm_ops_hsh = hash_new ()) == NULL 19456 || (arm_cond_hsh = hash_new ()) == NULL 19457 || (arm_shift_hsh = hash_new ()) == NULL 19458 || (arm_psr_hsh = hash_new ()) == NULL 19459 || (arm_v7m_psr_hsh = hash_new ()) == NULL 19460 || (arm_reg_hsh = hash_new ()) == NULL 19461 || (arm_reloc_hsh = hash_new ()) == NULL 19462 || (arm_barrier_opt_hsh = hash_new ()) == NULL) 19463 as_fatal (_("virtual memory exhausted")); 19464 19465 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) 19466 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); 19467 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) 19468 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); 19469 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) 19470 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); 19471 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) 19472 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); 19473 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) 19474 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i)); 19475 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) 19476 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); 19477 for (i = 0; 19478 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); 19479 i++) 19480 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, 19481 (PTR) (barrier_opt_names + i)); 19482#ifdef OBJ_ELF 19483 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) 19484 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); 19485#endif 19486 19487 set_constant_flonums (); 19488 19489 /* Set the cpu variant based on the command-line options. We prefer 19490 -mcpu= over -march= if both are set (as for GCC); and we prefer 19491 -mfpu= over any other way of setting the floating point unit. 19492 Use of legacy options with new options are faulted. */ 19493 if (legacy_cpu) 19494 { 19495 if (mcpu_cpu_opt || march_cpu_opt) 19496 as_bad (_("use of old and new-style options to set CPU type")); 19497 19498 mcpu_cpu_opt = legacy_cpu; 19499 } 19500 else if (!mcpu_cpu_opt) 19501 mcpu_cpu_opt = march_cpu_opt; 19502 19503 if (legacy_fpu) 19504 { 19505 if (mfpu_opt) 19506 as_bad (_("use of old and new-style options to set FPU type")); 19507 19508 mfpu_opt = legacy_fpu; 19509 } 19510 else if (!mfpu_opt) 19511 { 19512#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) 19513 /* Some environments specify a default FPU. If they don't, infer it 19514 from the processor. */ 19515 if (mcpu_fpu_opt) 19516 mfpu_opt = mcpu_fpu_opt; 19517 else 19518 mfpu_opt = march_fpu_opt; 19519#else 19520 mfpu_opt = &fpu_default; 19521#endif 19522 } 19523 19524 if (!mfpu_opt) 19525 { 19526 if (mcpu_cpu_opt != NULL) 19527 mfpu_opt = &fpu_default; 19528 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) 19529 mfpu_opt = &fpu_arch_vfp_v2; 19530 else 19531 mfpu_opt = &fpu_arch_fpa; 19532 } 19533 19534#ifdef CPU_DEFAULT 19535 if (!mcpu_cpu_opt) 19536 { 19537 mcpu_cpu_opt = &cpu_default; 19538 selected_cpu = cpu_default; 19539 } 19540#else 19541 if (mcpu_cpu_opt) 19542 selected_cpu = *mcpu_cpu_opt; 19543 else 19544 mcpu_cpu_opt = &arm_arch_any; 19545#endif 19546 19547 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 19548 19549 autoselect_thumb_from_cpu_variant (); 19550 19551 arm_arch_used = thumb_arch_used = arm_arch_none; 19552 19553#if defined OBJ_COFF || defined OBJ_ELF 19554 { 19555 unsigned int flags = 0; 19556 19557#if defined OBJ_ELF 19558 flags = meabi_flags; 19559 19560 switch (meabi_flags) 19561 { 19562 case EF_ARM_EABI_UNKNOWN: 19563#endif 19564 /* Set the flags in the private structure. */ 19565 if (uses_apcs_26) flags |= F_APCS26; 19566 if (support_interwork) flags |= F_INTERWORK; 19567 if (uses_apcs_float) flags |= F_APCS_FLOAT; 19568 if (pic_code) flags |= F_PIC; 19569 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) 19570 flags |= F_SOFT_FLOAT; 19571 19572 switch (mfloat_abi_opt) 19573 { 19574 case ARM_FLOAT_ABI_SOFT: 19575 case ARM_FLOAT_ABI_SOFTFP: 19576 flags |= F_SOFT_FLOAT; 19577 break; 19578 19579 case ARM_FLOAT_ABI_HARD: 19580 if (flags & F_SOFT_FLOAT) 19581 as_bad (_("hard-float conflicts with specified fpu")); 19582 break; 19583 } 19584 19585 /* Using pure-endian doubles (even if soft-float). */ 19586 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 19587 flags |= F_VFP_FLOAT; 19588 19589#if defined OBJ_ELF 19590 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) 19591 flags |= EF_ARM_MAVERICK_FLOAT; 19592 break; 19593 19594 case EF_ARM_EABI_VER4: 19595 case EF_ARM_EABI_VER5: 19596 /* No additional flags to set. */ 19597 break; 19598 19599 default: 19600 abort (); 19601 } 19602#endif 19603 bfd_set_private_flags (stdoutput, flags); 19604 19605 /* We have run out flags in the COFF header to encode the 19606 status of ATPCS support, so instead we create a dummy, 19607 empty, debug section called .arm.atpcs. */ 19608 if (atpcs) 19609 { 19610 asection * sec; 19611 19612 sec = bfd_make_section (stdoutput, ".arm.atpcs"); 19613 19614 if (sec != NULL) 19615 { 19616 bfd_set_section_flags 19617 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); 19618 bfd_set_section_size (stdoutput, sec, 0); 19619 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); 19620 } 19621 } 19622 } 19623#endif 19624 19625 /* Record the CPU type as well. */ 19626 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) 19627 mach = bfd_mach_arm_iWMMXt2; 19628 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) 19629 mach = bfd_mach_arm_iWMMXt; 19630 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) 19631 mach = bfd_mach_arm_XScale; 19632 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) 19633 mach = bfd_mach_arm_ep9312; 19634 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) 19635 mach = bfd_mach_arm_5TE; 19636 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) 19637 { 19638 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19639 mach = bfd_mach_arm_5T; 19640 else 19641 mach = bfd_mach_arm_5; 19642 } 19643 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) 19644 { 19645 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19646 mach = bfd_mach_arm_4T; 19647 else 19648 mach = bfd_mach_arm_4; 19649 } 19650 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) 19651 mach = bfd_mach_arm_3M; 19652 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) 19653 mach = bfd_mach_arm_3; 19654 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) 19655 mach = bfd_mach_arm_2a; 19656 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) 19657 mach = bfd_mach_arm_2; 19658 else 19659 mach = bfd_mach_arm_unknown; 19660 19661 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); 19662} 19663 19664/* Command line processing. */ 19665 19666/* md_parse_option 19667 Invocation line includes a switch not recognized by the base assembler. 19668 See if it's a processor-specific option. 19669 19670 This routine is somewhat complicated by the need for backwards 19671 compatibility (since older releases of gcc can't be changed). 19672 The new options try to make the interface as compatible as 19673 possible with GCC. 19674 19675 New options (supported) are: 19676 19677 -mcpu=<cpu name> Assemble for selected processor 19678 -march=<architecture name> Assemble for selected architecture 19679 -mfpu=<fpu architecture> Assemble for selected FPU. 19680 -EB/-mbig-endian Big-endian 19681 -EL/-mlittle-endian Little-endian 19682 -k Generate PIC code 19683 -mthumb Start in Thumb mode 19684 -mthumb-interwork Code supports ARM/Thumb interworking 19685 19686 For now we will also provide support for: 19687 19688 -mapcs-32 32-bit Program counter 19689 -mapcs-26 26-bit Program counter 19690 -macps-float Floats passed in FP registers 19691 -mapcs-reentrant Reentrant code 19692 -matpcs 19693 (sometime these will probably be replaced with -mapcs=<list of options> 19694 and -matpcs=<list of options>) 19695 19696 The remaining options are only supported for back-wards compatibility. 19697 Cpu variants, the arm part is optional: 19698 -m[arm]1 Currently not supported. 19699 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor 19700 -m[arm]3 Arm 3 processor 19701 -m[arm]6[xx], Arm 6 processors 19702 -m[arm]7[xx][t][[d]m] Arm 7 processors 19703 -m[arm]8[10] Arm 8 processors 19704 -m[arm]9[20][tdmi] Arm 9 processors 19705 -mstrongarm[110[0]] StrongARM processors 19706 -mxscale XScale processors 19707 -m[arm]v[2345[t[e]]] Arm architectures 19708 -mall All (except the ARM1) 19709 FP variants: 19710 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions 19711 -mfpe-old (No float load/store multiples) 19712 -mvfpxd VFP Single precision 19713 -mvfp All VFP 19714 -mno-fpu Disable all floating point instructions 19715 19716 The following CPU names are recognized: 19717 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, 19718 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, 19719 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, 19720 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, 19721 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, 19722 arm10t arm10e, arm1020t, arm1020e, arm10200e, 19723 strongarm, strongarm110, strongarm1100, strongarm1110, xscale. 19724 19725 */ 19726 19727const char * md_shortopts = "m:k"; 19728 19729#ifdef ARM_BI_ENDIAN 19730#define OPTION_EB (OPTION_MD_BASE + 0) 19731#define OPTION_EL (OPTION_MD_BASE + 1) 19732#else 19733#if TARGET_BYTES_BIG_ENDIAN 19734#define OPTION_EB (OPTION_MD_BASE + 0) 19735#else 19736#define OPTION_EL (OPTION_MD_BASE + 1) 19737#endif 19738#endif 19739 19740struct option md_longopts[] = 19741{ 19742#ifdef OPTION_EB 19743 {"EB", no_argument, NULL, OPTION_EB}, 19744#endif 19745#ifdef OPTION_EL 19746 {"EL", no_argument, NULL, OPTION_EL}, 19747#endif 19748 {NULL, no_argument, NULL, 0} 19749}; 19750 19751size_t md_longopts_size = sizeof (md_longopts); 19752 19753struct arm_option_table 19754{ 19755 char *option; /* Option name to match. */ 19756 char *help; /* Help information. */ 19757 int *var; /* Variable to change. */ 19758 int value; /* What to change it to. */ 19759 char *deprecated; /* If non-null, print this message. */ 19760}; 19761 19762struct arm_option_table arm_opts[] = 19763{ 19764 {"k", N_("generate PIC code"), &pic_code, 1, NULL}, 19765 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, 19766 {"mthumb-interwork", N_("support ARM/Thumb interworking"), 19767 &support_interwork, 1, NULL}, 19768 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, 19769 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, 19770 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, 19771 1, NULL}, 19772 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, 19773 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, 19774 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, 19775 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, 19776 NULL}, 19777 19778 /* These are recognized by the assembler, but have no affect on code. */ 19779 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, 19780 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, 19781 {NULL, NULL, NULL, 0, NULL} 19782}; 19783 19784struct arm_legacy_option_table 19785{ 19786 char *option; /* Option name to match. */ 19787 const arm_feature_set **var; /* Variable to change. */ 19788 const arm_feature_set value; /* What to change it to. */ 19789 char *deprecated; /* If non-null, print this message. */ 19790}; 19791 19792const struct arm_legacy_option_table arm_legacy_opts[] = 19793{ 19794 /* DON'T add any new processors to this list -- we want the whole list 19795 to go away... Add them to the processors table instead. */ 19796 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19797 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19798 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19799 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19800 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19801 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19802 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19803 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19804 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19805 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19806 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19807 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19808 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19809 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19810 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19811 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19812 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19813 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19814 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19815 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19816 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19817 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19818 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19819 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19820 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19821 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19822 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19823 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19824 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19825 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19826 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19827 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19828 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19829 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19830 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19831 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19832 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19833 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19834 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19835 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19836 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19837 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19838 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19839 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19840 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19841 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19842 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19843 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19844 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19845 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19846 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19847 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19848 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19849 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19850 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19851 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19852 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19853 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19854 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19855 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19856 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19857 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19858 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19859 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19860 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19861 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19862 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19863 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19864 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, 19865 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, 19866 N_("use -mcpu=strongarm110")}, 19867 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, 19868 N_("use -mcpu=strongarm1100")}, 19869 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, 19870 N_("use -mcpu=strongarm1110")}, 19871 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, 19872 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, 19873 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, 19874 19875 /* Architecture variants -- don't add any more to this list either. */ 19876 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19877 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19878 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19879 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19880 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 19881 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 19882 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 19883 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 19884 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 19885 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 19886 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 19887 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 19888 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 19889 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 19890 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 19891 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 19892 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 19893 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 19894 19895 /* Floating point variants -- don't add any more to this list either. */ 19896 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, 19897 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, 19898 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, 19899 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, 19900 N_("use either -mfpu=softfpa or -mfpu=softvfp")}, 19901 19902 {NULL, NULL, ARM_ARCH_NONE, NULL} 19903}; 19904 19905struct arm_cpu_option_table 19906{ 19907 char *name; 19908 const arm_feature_set value; 19909 /* For some CPUs we assume an FPU unless the user explicitly sets 19910 -mfpu=... */ 19911 const arm_feature_set default_fpu; 19912 /* The canonical name of the CPU, or NULL to use NAME converted to upper 19913 case. */ 19914 const char *canonical_name; 19915}; 19916 19917/* This list should, at a minimum, contain all the cpu names 19918 recognized by GCC. */ 19919static const struct arm_cpu_option_table arm_cpus[] = 19920{ 19921 {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, 19922 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, 19923 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, 19924 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 19925 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 19926 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19927 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19928 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19929 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19930 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19931 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19932 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 19933 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19934 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 19935 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19936 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 19937 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19938 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19939 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19940 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19941 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19942 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19943 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19944 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19945 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19946 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19947 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19948 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 19949 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19950 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19951 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19952 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 19953 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 19954 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 19955 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 19956 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 19957 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 19958 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 19959 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19960 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, 19961 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19962 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19963 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19964 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 19965 /* For V5 or later processors we default to using VFP; but the user 19966 should really set the FPU type explicitly. */ 19967 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 19968 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 19969 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 19970 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 19971 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 19972 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 19973 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, 19974 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 19975 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 19976 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, 19977 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 19978 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 19979 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 19980 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 19981 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 19982 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, 19983 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 19984 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 19985 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 19986 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, 19987 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 19988 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, 19989 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, 19990 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, 19991 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, 19992 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, 19993 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, 19994 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, 19995 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, 19996 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, 19997 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, 19998 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 19999 | FPU_NEON_EXT_V1), 20000 NULL}, 20001 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, 20002 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, 20003 /* ??? XSCALE is really an architecture. */ 20004 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20005 /* ??? iwmmxt is not a processor. */ 20006 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, 20007 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, 20008 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20009 /* Maverick */ 20010 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, 20011 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} 20012}; 20013 20014struct arm_arch_option_table 20015{ 20016 char *name; 20017 const arm_feature_set value; 20018 const arm_feature_set default_fpu; 20019}; 20020 20021/* This list should, at a minimum, contain all the architecture names 20022 recognized by GCC. */ 20023static const struct arm_arch_option_table arm_archs[] = 20024{ 20025 {"all", ARM_ANY, FPU_ARCH_FPA}, 20026 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, 20027 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, 20028 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20029 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20030 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, 20031 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, 20032 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, 20033 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, 20034 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, 20035 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, 20036 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, 20037 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, 20038 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, 20039 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, 20040 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, 20041 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, 20042 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, 20043 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, 20044 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, 20045 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, 20046 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, 20047 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, 20048 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, 20049 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, 20050 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, 20051 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, 20052 /* The official spelling of the ARMv7 profile variants is the dashed form. 20053 Accept the non-dashed form for compatibility with old toolchains. */ 20054 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20055 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20056 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20057 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20058 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20059 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20060 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, 20061 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, 20062 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, 20063 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} 20064}; 20065 20066/* ISA extensions in the co-processor space. */ 20067struct arm_option_cpu_value_table 20068{ 20069 char *name; 20070 const arm_feature_set value; 20071}; 20072 20073static const struct arm_option_cpu_value_table arm_extensions[] = 20074{ 20075 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, 20076 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, 20077 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, 20078 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, 20079 {NULL, ARM_ARCH_NONE} 20080}; 20081 20082/* This list should, at a minimum, contain all the fpu names 20083 recognized by GCC. */ 20084static const struct arm_option_cpu_value_table arm_fpus[] = 20085{ 20086 {"softfpa", FPU_NONE}, 20087 {"fpe", FPU_ARCH_FPE}, 20088 {"fpe2", FPU_ARCH_FPE}, 20089 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ 20090 {"fpa", FPU_ARCH_FPA}, 20091 {"fpa10", FPU_ARCH_FPA}, 20092 {"fpa11", FPU_ARCH_FPA}, 20093 {"arm7500fe", FPU_ARCH_FPA}, 20094 {"softvfp", FPU_ARCH_VFP}, 20095 {"softvfp+vfp", FPU_ARCH_VFP_V2}, 20096 {"vfp", FPU_ARCH_VFP_V2}, 20097 {"vfp9", FPU_ARCH_VFP_V2}, 20098 {"vfp3", FPU_ARCH_VFP_V3}, 20099 {"vfp10", FPU_ARCH_VFP_V2}, 20100 {"vfp10-r0", FPU_ARCH_VFP_V1}, 20101 {"vfpxd", FPU_ARCH_VFP_V1xD}, 20102 {"arm1020t", FPU_ARCH_VFP_V1}, 20103 {"arm1020e", FPU_ARCH_VFP_V2}, 20104 {"arm1136jfs", FPU_ARCH_VFP_V2}, 20105 {"arm1136jf-s", FPU_ARCH_VFP_V2}, 20106 {"maverick", FPU_ARCH_MAVERICK}, 20107 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, 20108 {NULL, ARM_ARCH_NONE} 20109}; 20110 20111struct arm_option_value_table 20112{ 20113 char *name; 20114 long value; 20115}; 20116 20117static const struct arm_option_value_table arm_float_abis[] = 20118{ 20119 {"hard", ARM_FLOAT_ABI_HARD}, 20120 {"softfp", ARM_FLOAT_ABI_SOFTFP}, 20121 {"soft", ARM_FLOAT_ABI_SOFT}, 20122 {NULL, 0} 20123}; 20124 20125#ifdef OBJ_ELF 20126/* We only know how to output GNU and ver 4/5 (AAELF) formats. */ 20127static const struct arm_option_value_table arm_eabis[] = 20128{ 20129 {"gnu", EF_ARM_EABI_UNKNOWN}, 20130 {"4", EF_ARM_EABI_VER4}, 20131 {"5", EF_ARM_EABI_VER5}, 20132 {NULL, 0} 20133}; 20134#endif 20135 20136struct arm_long_option_table 20137{ 20138 char * option; /* Substring to match. */ 20139 char * help; /* Help information. */ 20140 int (* func) (char * subopt); /* Function to decode sub-option. */ 20141 char * deprecated; /* If non-null, print this message. */ 20142}; 20143 20144static int 20145arm_parse_extension (char * str, const arm_feature_set **opt_p) 20146{ 20147 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); 20148 20149 /* Copy the feature set, so that we can modify it. */ 20150 *ext_set = **opt_p; 20151 *opt_p = ext_set; 20152 20153 while (str != NULL && *str != 0) 20154 { 20155 const struct arm_option_cpu_value_table * opt; 20156 char * ext; 20157 int optlen; 20158 20159 if (*str != '+') 20160 { 20161 as_bad (_("invalid architectural extension")); 20162 return 0; 20163 } 20164 20165 str++; 20166 ext = strchr (str, '+'); 20167 20168 if (ext != NULL) 20169 optlen = ext - str; 20170 else 20171 optlen = strlen (str); 20172 20173 if (optlen == 0) 20174 { 20175 as_bad (_("missing architectural extension")); 20176 return 0; 20177 } 20178 20179 for (opt = arm_extensions; opt->name != NULL; opt++) 20180 if (strncmp (opt->name, str, optlen) == 0) 20181 { 20182 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); 20183 break; 20184 } 20185 20186 if (opt->name == NULL) 20187 { 20188 as_bad (_("unknown architectural extnsion `%s'"), str); 20189 return 0; 20190 } 20191 20192 str = ext; 20193 }; 20194 20195 return 1; 20196} 20197 20198static int 20199arm_parse_cpu (char * str) 20200{ 20201 const struct arm_cpu_option_table * opt; 20202 char * ext = strchr (str, '+'); 20203 int optlen; 20204 20205 if (ext != NULL) 20206 optlen = ext - str; 20207 else 20208 optlen = strlen (str); 20209 20210 if (optlen == 0) 20211 { 20212 as_bad (_("missing cpu name `%s'"), str); 20213 return 0; 20214 } 20215 20216 for (opt = arm_cpus; opt->name != NULL; opt++) 20217 if (strncmp (opt->name, str, optlen) == 0) 20218 { 20219 mcpu_cpu_opt = &opt->value; 20220 mcpu_fpu_opt = &opt->default_fpu; 20221 if (opt->canonical_name) 20222 strcpy(selected_cpu_name, opt->canonical_name); 20223 else 20224 { 20225 int i; 20226 for (i = 0; i < optlen; i++) 20227 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20228 selected_cpu_name[i] = 0; 20229 } 20230 20231 if (ext != NULL) 20232 return arm_parse_extension (ext, &mcpu_cpu_opt); 20233 20234 return 1; 20235 } 20236 20237 as_bad (_("unknown cpu `%s'"), str); 20238 return 0; 20239} 20240 20241static int 20242arm_parse_arch (char * str) 20243{ 20244 const struct arm_arch_option_table *opt; 20245 char *ext = strchr (str, '+'); 20246 int optlen; 20247 20248 if (ext != NULL) 20249 optlen = ext - str; 20250 else 20251 optlen = strlen (str); 20252 20253 if (optlen == 0) 20254 { 20255 as_bad (_("missing architecture name `%s'"), str); 20256 return 0; 20257 } 20258 20259 for (opt = arm_archs; opt->name != NULL; opt++) 20260 if (streq (opt->name, str)) 20261 { 20262 march_cpu_opt = &opt->value; 20263 march_fpu_opt = &opt->default_fpu; 20264 strcpy(selected_cpu_name, opt->name); 20265 20266 if (ext != NULL) 20267 return arm_parse_extension (ext, &march_cpu_opt); 20268 20269 return 1; 20270 } 20271 20272 as_bad (_("unknown architecture `%s'\n"), str); 20273 return 0; 20274} 20275 20276static int 20277arm_parse_fpu (char * str) 20278{ 20279 const struct arm_option_cpu_value_table * opt; 20280 20281 for (opt = arm_fpus; opt->name != NULL; opt++) 20282 if (streq (opt->name, str)) 20283 { 20284 mfpu_opt = &opt->value; 20285 return 1; 20286 } 20287 20288 as_bad (_("unknown floating point format `%s'\n"), str); 20289 return 0; 20290} 20291 20292static int 20293arm_parse_float_abi (char * str) 20294{ 20295 const struct arm_option_value_table * opt; 20296 20297 for (opt = arm_float_abis; opt->name != NULL; opt++) 20298 if (streq (opt->name, str)) 20299 { 20300 mfloat_abi_opt = opt->value; 20301 return 1; 20302 } 20303 20304 as_bad (_("unknown floating point abi `%s'\n"), str); 20305 return 0; 20306} 20307 20308#ifdef OBJ_ELF 20309static int 20310arm_parse_eabi (char * str) 20311{ 20312 const struct arm_option_value_table *opt; 20313 20314 for (opt = arm_eabis; opt->name != NULL; opt++) 20315 if (streq (opt->name, str)) 20316 { 20317 meabi_flags = opt->value; 20318 return 1; 20319 } 20320 as_bad (_("unknown EABI `%s'\n"), str); 20321 return 0; 20322} 20323#endif 20324 20325struct arm_long_option_table arm_long_opts[] = 20326{ 20327 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), 20328 arm_parse_cpu, NULL}, 20329 {"march=", N_("<arch name>\t assemble for architecture <arch name>"), 20330 arm_parse_arch, NULL}, 20331 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), 20332 arm_parse_fpu, NULL}, 20333 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), 20334 arm_parse_float_abi, NULL}, 20335#ifdef OBJ_ELF 20336 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), 20337 arm_parse_eabi, NULL}, 20338#endif 20339 {NULL, NULL, 0, NULL} 20340}; 20341 20342int 20343md_parse_option (int c, char * arg) 20344{ 20345 struct arm_option_table *opt; 20346 const struct arm_legacy_option_table *fopt; 20347 struct arm_long_option_table *lopt; 20348 20349 switch (c) 20350 { 20351#ifdef OPTION_EB 20352 case OPTION_EB: 20353 target_big_endian = 1; 20354 break; 20355#endif 20356 20357#ifdef OPTION_EL 20358 case OPTION_EL: 20359 target_big_endian = 0; 20360 break; 20361#endif 20362 20363 case 'a': 20364 /* Listing option. Just ignore these, we don't support additional 20365 ones. */ 20366 return 0; 20367 20368 default: 20369 for (opt = arm_opts; opt->option != NULL; opt++) 20370 { 20371 if (c == opt->option[0] 20372 && ((arg == NULL && opt->option[1] == 0) 20373 || streq (arg, opt->option + 1))) 20374 { 20375#if WARN_DEPRECATED 20376 /* If the option is deprecated, tell the user. */ 20377 if (opt->deprecated != NULL) 20378 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20379 arg ? arg : "", _(opt->deprecated)); 20380#endif 20381 20382 if (opt->var != NULL) 20383 *opt->var = opt->value; 20384 20385 return 1; 20386 } 20387 } 20388 20389 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) 20390 { 20391 if (c == fopt->option[0] 20392 && ((arg == NULL && fopt->option[1] == 0) 20393 || streq (arg, fopt->option + 1))) 20394 { 20395#if WARN_DEPRECATED 20396 /* If the option is deprecated, tell the user. */ 20397 if (fopt->deprecated != NULL) 20398 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20399 arg ? arg : "", _(fopt->deprecated)); 20400#endif 20401 20402 if (fopt->var != NULL) 20403 *fopt->var = &fopt->value; 20404 20405 return 1; 20406 } 20407 } 20408 20409 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20410 { 20411 /* These options are expected to have an argument. */ 20412 if (c == lopt->option[0] 20413 && arg != NULL 20414 && strncmp (arg, lopt->option + 1, 20415 strlen (lopt->option + 1)) == 0) 20416 { 20417#if WARN_DEPRECATED 20418 /* If the option is deprecated, tell the user. */ 20419 if (lopt->deprecated != NULL) 20420 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, 20421 _(lopt->deprecated)); 20422#endif 20423 20424 /* Call the sup-option parser. */ 20425 return lopt->func (arg + strlen (lopt->option) - 1); 20426 } 20427 } 20428 20429 return 0; 20430 } 20431 20432 return 1; 20433} 20434 20435void 20436md_show_usage (FILE * fp) 20437{ 20438 struct arm_option_table *opt; 20439 struct arm_long_option_table *lopt; 20440 20441 fprintf (fp, _(" ARM-specific assembler options:\n")); 20442 20443 for (opt = arm_opts; opt->option != NULL; opt++) 20444 if (opt->help != NULL) 20445 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); 20446 20447 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20448 if (lopt->help != NULL) 20449 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); 20450 20451#ifdef OPTION_EB 20452 fprintf (fp, _("\ 20453 -EB assemble code for a big-endian cpu\n")); 20454#endif 20455 20456#ifdef OPTION_EL 20457 fprintf (fp, _("\ 20458 -EL assemble code for a little-endian cpu\n")); 20459#endif 20460} 20461 20462 20463#ifdef OBJ_ELF 20464typedef struct 20465{ 20466 int val; 20467 arm_feature_set flags; 20468} cpu_arch_ver_table; 20469 20470/* Mapping from CPU features to EABI CPU arch values. Table must be sorted 20471 least features first. */ 20472static const cpu_arch_ver_table cpu_arch_ver[] = 20473{ 20474 {1, ARM_ARCH_V4}, 20475 {2, ARM_ARCH_V4T}, 20476 {3, ARM_ARCH_V5}, 20477 {4, ARM_ARCH_V5TE}, 20478 {5, ARM_ARCH_V5TEJ}, 20479 {6, ARM_ARCH_V6}, 20480 {7, ARM_ARCH_V6Z}, 20481 {8, ARM_ARCH_V6K}, 20482 {9, ARM_ARCH_V6T2}, 20483 {10, ARM_ARCH_V7A}, 20484 {10, ARM_ARCH_V7R}, 20485 {10, ARM_ARCH_V7M}, 20486 {0, ARM_ARCH_NONE} 20487}; 20488 20489/* Set the public EABI object attributes. */ 20490static void 20491aeabi_set_public_attributes (void) 20492{ 20493 int arch; 20494 arm_feature_set flags; 20495 arm_feature_set tmp; 20496 const cpu_arch_ver_table *p; 20497 20498 /* Choose the architecture based on the capabilities of the requested cpu 20499 (if any) and/or the instructions actually used. */ 20500 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); 20501 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); 20502 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); 20503 /*Allow the user to override the reported architecture. */ 20504 if (object_arch) 20505 { 20506 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); 20507 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); 20508 } 20509 20510 tmp = flags; 20511 arch = 0; 20512 for (p = cpu_arch_ver; p->val; p++) 20513 { 20514 if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) 20515 { 20516 arch = p->val; 20517 ARM_CLEAR_FEATURE (tmp, tmp, p->flags); 20518 } 20519 } 20520 20521 /* Tag_CPU_name. */ 20522 if (selected_cpu_name[0]) 20523 { 20524 char *p; 20525 20526 p = selected_cpu_name; 20527 if (strncmp(p, "armv", 4) == 0) 20528 { 20529 int i; 20530 20531 p += 4; 20532 for (i = 0; p[i]; i++) 20533 p[i] = TOUPPER (p[i]); 20534 } 20535 bfd_elf_add_proc_attr_string (stdoutput, 5, p); 20536 } 20537 /* Tag_CPU_arch. */ 20538 bfd_elf_add_proc_attr_int (stdoutput, 6, arch); 20539 /* Tag_CPU_arch_profile. */ 20540 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) 20541 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A'); 20542 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) 20543 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R'); 20544 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)) 20545 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M'); 20546 /* Tag_ARM_ISA_use. */ 20547 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) 20548 bfd_elf_add_proc_attr_int (stdoutput, 8, 1); 20549 /* Tag_THUMB_ISA_use. */ 20550 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) 20551 bfd_elf_add_proc_attr_int (stdoutput, 9, 20552 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); 20553 /* Tag_VFP_arch. */ 20554 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3) 20555 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3)) 20556 bfd_elf_add_proc_attr_int (stdoutput, 10, 3); 20557 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2) 20558 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2)) 20559 bfd_elf_add_proc_attr_int (stdoutput, 10, 2); 20560 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1) 20561 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1) 20562 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd) 20563 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd)) 20564 bfd_elf_add_proc_attr_int (stdoutput, 10, 1); 20565 /* Tag_WMMX_arch. */ 20566 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) 20567 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) 20568 bfd_elf_add_proc_attr_int (stdoutput, 11, 1); 20569 /* Tag_NEON_arch. */ 20570 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1) 20571 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1)) 20572 bfd_elf_add_proc_attr_int (stdoutput, 12, 1); 20573} 20574 20575/* Add the default contents for the .ARM.attributes section. */ 20576void 20577arm_md_end (void) 20578{ 20579 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 20580 return; 20581 20582 aeabi_set_public_attributes (); 20583} 20584#endif /* OBJ_ELF */ 20585 20586 20587/* Parse a .cpu directive. */ 20588 20589static void 20590s_arm_cpu (int ignored ATTRIBUTE_UNUSED) 20591{ 20592 const struct arm_cpu_option_table *opt; 20593 char *name; 20594 char saved_char; 20595 20596 name = input_line_pointer; 20597 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20598 input_line_pointer++; 20599 saved_char = *input_line_pointer; 20600 *input_line_pointer = 0; 20601 20602 /* Skip the first "all" entry. */ 20603 for (opt = arm_cpus + 1; opt->name != NULL; opt++) 20604 if (streq (opt->name, name)) 20605 { 20606 mcpu_cpu_opt = &opt->value; 20607 selected_cpu = opt->value; 20608 if (opt->canonical_name) 20609 strcpy(selected_cpu_name, opt->canonical_name); 20610 else 20611 { 20612 int i; 20613 for (i = 0; opt->name[i]; i++) 20614 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20615 selected_cpu_name[i] = 0; 20616 } 20617 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20618 *input_line_pointer = saved_char; 20619 demand_empty_rest_of_line (); 20620 return; 20621 } 20622 as_bad (_("unknown cpu `%s'"), name); 20623 *input_line_pointer = saved_char; 20624 ignore_rest_of_line (); 20625} 20626 20627 20628/* Parse a .arch directive. */ 20629 20630static void 20631s_arm_arch (int ignored ATTRIBUTE_UNUSED) 20632{ 20633 const struct arm_arch_option_table *opt; 20634 char saved_char; 20635 char *name; 20636 20637 name = input_line_pointer; 20638 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20639 input_line_pointer++; 20640 saved_char = *input_line_pointer; 20641 *input_line_pointer = 0; 20642 20643 /* Skip the first "all" entry. */ 20644 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20645 if (streq (opt->name, name)) 20646 { 20647 mcpu_cpu_opt = &opt->value; 20648 selected_cpu = opt->value; 20649 strcpy(selected_cpu_name, opt->name); 20650 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20651 *input_line_pointer = saved_char; 20652 demand_empty_rest_of_line (); 20653 return; 20654 } 20655 20656 as_bad (_("unknown architecture `%s'\n"), name); 20657 *input_line_pointer = saved_char; 20658 ignore_rest_of_line (); 20659} 20660 20661 20662/* Parse a .object_arch directive. */ 20663 20664static void 20665s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) 20666{ 20667 const struct arm_arch_option_table *opt; 20668 char saved_char; 20669 char *name; 20670 20671 name = input_line_pointer; 20672 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20673 input_line_pointer++; 20674 saved_char = *input_line_pointer; 20675 *input_line_pointer = 0; 20676 20677 /* Skip the first "all" entry. */ 20678 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20679 if (streq (opt->name, name)) 20680 { 20681 object_arch = &opt->value; 20682 *input_line_pointer = saved_char; 20683 demand_empty_rest_of_line (); 20684 return; 20685 } 20686 20687 as_bad (_("unknown architecture `%s'\n"), name); 20688 *input_line_pointer = saved_char; 20689 ignore_rest_of_line (); 20690} 20691 20692 20693/* Parse a .fpu directive. */ 20694 20695static void 20696s_arm_fpu (int ignored ATTRIBUTE_UNUSED) 20697{ 20698 const struct arm_option_cpu_value_table *opt; 20699 char saved_char; 20700 char *name; 20701 20702 name = input_line_pointer; 20703 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20704 input_line_pointer++; 20705 saved_char = *input_line_pointer; 20706 *input_line_pointer = 0; 20707 20708 for (opt = arm_fpus; opt->name != NULL; opt++) 20709 if (streq (opt->name, name)) 20710 { 20711 mfpu_opt = &opt->value; 20712 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20713 *input_line_pointer = saved_char; 20714 demand_empty_rest_of_line (); 20715 return; 20716 } 20717 20718 as_bad (_("unknown floating point format `%s'\n"), name); 20719 *input_line_pointer = saved_char; 20720 ignore_rest_of_line (); 20721} 20722 20723/* Copy symbol information. */ 20724void 20725arm_copy_symbol_attributes (symbolS *dest, symbolS *src) 20726{ 20727 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); 20728} 20729