tc-arm.c revision 248466
1/* tc-arm.c -- Assemble for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 3 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 6 Modified by David Taylor (dtaylor@armltd.co.uk) 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) 8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) 9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) 10 11 This file is part of GAS, the GNU Assembler. 12 13 GAS is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2, or (at your option) 16 any later version. 17 18 GAS is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with GAS; see the file COPYING. If not, write to the Free 25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 26 02110-1301, USA. */ 27 28#include <limits.h> 29#include <stdarg.h> 30#define NO_RELOC 0 31#include "as.h" 32#include "safe-ctype.h" 33#include "subsegs.h" 34#include "obstack.h" 35 36#include "opcode/arm.h" 37 38#ifdef OBJ_ELF 39#include "elf/arm.h" 40#include "dw2gencfi.h" 41#endif 42 43#include "dwarf2dbg.h" 44 45#define WARN_DEPRECATED 1 46 47#ifdef OBJ_ELF 48/* Must be at least the size of the largest unwind opcode (currently two). */ 49#define ARM_OPCODE_CHUNK_SIZE 8 50 51/* This structure holds the unwinding state. */ 52 53static struct 54{ 55 symbolS * proc_start; 56 symbolS * table_entry; 57 symbolS * personality_routine; 58 int personality_index; 59 /* The segment containing the function. */ 60 segT saved_seg; 61 subsegT saved_subseg; 62 /* Opcodes generated from this function. */ 63 unsigned char * opcodes; 64 int opcode_count; 65 int opcode_alloc; 66 /* The number of bytes pushed to the stack. */ 67 offsetT frame_size; 68 /* We don't add stack adjustment opcodes immediately so that we can merge 69 multiple adjustments. We can also omit the final adjustment 70 when using a frame pointer. */ 71 offsetT pending_offset; 72 /* These two fields are set by both unwind_movsp and unwind_setfp. They 73 hold the reg+offset to use when restoring sp from a frame pointer. */ 74 offsetT fp_offset; 75 int fp_reg; 76 /* Nonzero if an unwind_setfp directive has been seen. */ 77 unsigned fp_used:1; 78 /* Nonzero if the last opcode restores sp from fp_reg. */ 79 unsigned sp_restored:1; 80} unwind; 81 82/* Bit N indicates that an R_ARM_NONE relocation has been output for 83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be 84 emitted only once per section, to save unnecessary bloat. */ 85static unsigned int marked_pr_dependency = 0; 86 87#endif /* OBJ_ELF */ 88 89/* Results from operand parsing worker functions. */ 90 91typedef enum 92{ 93 PARSE_OPERAND_SUCCESS, 94 PARSE_OPERAND_FAIL, 95 PARSE_OPERAND_FAIL_NO_BACKTRACK 96} parse_operand_result; 97 98enum arm_float_abi 99{ 100 ARM_FLOAT_ABI_HARD, 101 ARM_FLOAT_ABI_SOFTFP, 102 ARM_FLOAT_ABI_SOFT 103}; 104 105/* Types of processor to assemble for. */ 106#ifndef CPU_DEFAULT 107#if defined __XSCALE__ 108#define CPU_DEFAULT ARM_ARCH_XSCALE 109#else 110#if defined __thumb__ 111#define CPU_DEFAULT ARM_ARCH_V5T 112#endif 113#endif 114#endif 115 116#ifndef FPU_DEFAULT 117# ifdef TE_LINUX 118# define FPU_DEFAULT FPU_ARCH_FPA 119# elif defined (TE_NetBSD) 120# ifdef OBJ_ELF 121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ 122# else 123 /* Legacy a.out format. */ 124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ 125# endif 126# elif defined (TE_VXWORKS) 127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ 128# else 129 /* For backwards compatibility, default to FPA. */ 130# define FPU_DEFAULT FPU_ARCH_FPA 131# endif 132#endif /* ifndef FPU_DEFAULT */ 133 134#define streq(a, b) (strcmp (a, b) == 0) 135 136static arm_feature_set cpu_variant; 137static arm_feature_set arm_arch_used; 138static arm_feature_set thumb_arch_used; 139 140/* Flags stored in private area of BFD structure. */ 141static int uses_apcs_26 = FALSE; 142static int atpcs = FALSE; 143static int support_interwork = FALSE; 144static int uses_apcs_float = FALSE; 145static int pic_code = FALSE; 146 147/* Variables that we set while parsing command-line options. Once all 148 options have been read we re-process these values to set the real 149 assembly flags. */ 150static const arm_feature_set *legacy_cpu = NULL; 151static const arm_feature_set *legacy_fpu = NULL; 152 153static const arm_feature_set *mcpu_cpu_opt = NULL; 154static const arm_feature_set *mcpu_fpu_opt = NULL; 155static const arm_feature_set *march_cpu_opt = NULL; 156static const arm_feature_set *march_fpu_opt = NULL; 157static const arm_feature_set *mfpu_opt = NULL; 158static const arm_feature_set *object_arch = NULL; 159 160/* Constants for known architecture features. */ 161static const arm_feature_set fpu_default = FPU_DEFAULT; 162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; 163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; 164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; 165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; 166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; 167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; 168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; 169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; 170 171#ifdef CPU_DEFAULT 172static const arm_feature_set cpu_default = CPU_DEFAULT; 173#endif 174 175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); 176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); 177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); 178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); 179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); 180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); 181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); 182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); 183static const arm_feature_set arm_ext_v4t_5 = 184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); 185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); 186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); 187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); 188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); 189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); 190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); 191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); 192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); 193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); 194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); 195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); 196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); 197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); 198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); 199 200static const arm_feature_set arm_arch_any = ARM_ANY; 201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); 202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; 203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; 204 205static const arm_feature_set arm_cext_iwmmxt2 = 206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2); 207static const arm_feature_set arm_cext_iwmmxt = 208 ARM_FEATURE (0, ARM_CEXT_IWMMXT); 209static const arm_feature_set arm_cext_xscale = 210 ARM_FEATURE (0, ARM_CEXT_XSCALE); 211static const arm_feature_set arm_cext_maverick = 212 ARM_FEATURE (0, ARM_CEXT_MAVERICK); 213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); 214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); 215static const arm_feature_set fpu_vfp_ext_v1xd = 216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD); 217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); 218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); 219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); 220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); 221static const arm_feature_set fpu_vfp_v3_or_neon_ext = 222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); 223 224static int mfloat_abi_opt = -1; 225/* Record user cpu selection for object attributes. */ 226static arm_feature_set selected_cpu = ARM_ARCH_NONE; 227/* Must be long enough to hold any of the names in arm_cpus. */ 228static char selected_cpu_name[16]; 229#ifdef OBJ_ELF 230# ifdef EABI_DEFAULT 231static int meabi_flags = EABI_DEFAULT; 232# else 233static int meabi_flags = EF_ARM_EABI_UNKNOWN; 234# endif 235 236bfd_boolean 237arm_is_eabi(void) 238{ 239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); 240} 241#endif 242 243#ifdef OBJ_ELF 244/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 245symbolS * GOT_symbol; 246#endif 247 248/* 0: assemble for ARM, 249 1: assemble for Thumb, 250 2: assemble for Thumb even though target CPU does not support thumb 251 instructions. */ 252static int thumb_mode = 0; 253 254/* If unified_syntax is true, we are processing the new unified 255 ARM/Thumb syntax. Important differences from the old ARM mode: 256 257 - Immediate operands do not require a # prefix. 258 - Conditional affixes always appear at the end of the 259 instruction. (For backward compatibility, those instructions 260 that formerly had them in the middle, continue to accept them 261 there.) 262 - The IT instruction may appear, and if it does is validated 263 against subsequent conditional affixes. It does not generate 264 machine code. 265 266 Important differences from the old Thumb mode: 267 268 - Immediate operands do not require a # prefix. 269 - Most of the V6T2 instructions are only available in unified mode. 270 - The .N and .W suffixes are recognized and honored (it is an error 271 if they cannot be honored). 272 - All instructions set the flags if and only if they have an 's' affix. 273 - Conditional affixes may be used. They are validated against 274 preceding IT instructions. Unlike ARM mode, you cannot use a 275 conditional affix except in the scope of an IT instruction. */ 276 277static bfd_boolean unified_syntax = FALSE; 278 279enum neon_el_type 280{ 281 NT_invtype, 282 NT_untyped, 283 NT_integer, 284 NT_float, 285 NT_poly, 286 NT_signed, 287 NT_unsigned 288}; 289 290struct neon_type_el 291{ 292 enum neon_el_type type; 293 unsigned size; 294}; 295 296#define NEON_MAX_TYPE_ELS 4 297 298struct neon_type 299{ 300 struct neon_type_el el[NEON_MAX_TYPE_ELS]; 301 unsigned elems; 302}; 303 304struct arm_it 305{ 306 const char * error; 307 unsigned long instruction; 308 int size; 309 int size_req; 310 int cond; 311 /* "uncond_value" is set to the value in place of the conditional field in 312 unconditional versions of the instruction, or -1 if nothing is 313 appropriate. */ 314 int uncond_value; 315 struct neon_type vectype; 316 /* Set to the opcode if the instruction needs relaxation. 317 Zero if the instruction is not relaxed. */ 318 unsigned long relax; 319 struct 320 { 321 bfd_reloc_code_real_type type; 322 expressionS exp; 323 int pc_rel; 324 } reloc; 325 326 struct 327 { 328 unsigned reg; 329 signed int imm; 330 struct neon_type_el vectype; 331 unsigned present : 1; /* Operand present. */ 332 unsigned isreg : 1; /* Operand was a register. */ 333 unsigned immisreg : 1; /* .imm field is a second register. */ 334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ 335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */ 336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */ 337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV 338 instructions. This allows us to disambiguate ARM <-> vector insns. */ 339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ 340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ 341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */ 342 unsigned issingle : 1; /* Operand is VFP single-precision register. */ 343 unsigned hasreloc : 1; /* Operand has relocation suffix. */ 344 unsigned writeback : 1; /* Operand has trailing ! */ 345 unsigned preind : 1; /* Preindexed address. */ 346 unsigned postind : 1; /* Postindexed address. */ 347 unsigned negative : 1; /* Index register was negated. */ 348 unsigned shifted : 1; /* Shift applied to operation. */ 349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ 350 } operands[6]; 351}; 352 353static struct arm_it inst; 354 355#define NUM_FLOAT_VALS 8 356 357const char * fp_const[] = 358{ 359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 360}; 361 362/* Number of littlenums required to hold an extended precision number. */ 363#define MAX_LITTLENUMS 6 364 365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; 366 367#define FAIL (-1) 368#define SUCCESS (0) 369 370#define SUFF_S 1 371#define SUFF_D 2 372#define SUFF_E 3 373#define SUFF_P 4 374 375#define CP_T_X 0x00008000 376#define CP_T_Y 0x00400000 377 378#define CONDS_BIT 0x00100000 379#define LOAD_BIT 0x00100000 380 381#define DOUBLE_LOAD_FLAG 0x00000001 382 383struct asm_cond 384{ 385 const char * template; 386 unsigned long value; 387}; 388 389#define COND_ALWAYS 0xE 390 391struct asm_psr 392{ 393 const char *template; 394 unsigned long field; 395}; 396 397struct asm_barrier_opt 398{ 399 const char *template; 400 unsigned long value; 401}; 402 403/* The bit that distinguishes CPSR and SPSR. */ 404#define SPSR_BIT (1 << 22) 405 406/* The individual PSR flag bits. */ 407#define PSR_c (1 << 16) 408#define PSR_x (1 << 17) 409#define PSR_s (1 << 18) 410#define PSR_f (1 << 19) 411 412struct reloc_entry 413{ 414 char *name; 415 bfd_reloc_code_real_type reloc; 416}; 417 418enum vfp_reg_pos 419{ 420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, 421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn 422}; 423 424enum vfp_ldstm_type 425{ 426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX 427}; 428 429/* Bits for DEFINED field in neon_typed_alias. */ 430#define NTA_HASTYPE 1 431#define NTA_HASINDEX 2 432 433struct neon_typed_alias 434{ 435 unsigned char defined; 436 unsigned char index; 437 struct neon_type_el eltype; 438}; 439 440/* ARM register categories. This includes coprocessor numbers and various 441 architecture extensions' registers. */ 442enum arm_reg_type 443{ 444 REG_TYPE_RN, 445 REG_TYPE_CP, 446 REG_TYPE_CN, 447 REG_TYPE_FN, 448 REG_TYPE_VFS, 449 REG_TYPE_VFD, 450 REG_TYPE_NQ, 451 REG_TYPE_VFSD, 452 REG_TYPE_NDQ, 453 REG_TYPE_NSDQ, 454 REG_TYPE_VFC, 455 REG_TYPE_MVF, 456 REG_TYPE_MVD, 457 REG_TYPE_MVFX, 458 REG_TYPE_MVDX, 459 REG_TYPE_MVAX, 460 REG_TYPE_DSPSC, 461 REG_TYPE_MMXWR, 462 REG_TYPE_MMXWC, 463 REG_TYPE_MMXWCG, 464 REG_TYPE_XSCALE, 465}; 466 467/* Structure for a hash table entry for a register. 468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra 469 information which states whether a vector type or index is specified (for a 470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */ 471struct reg_entry 472{ 473 const char *name; 474 unsigned char number; 475 unsigned char type; 476 unsigned char builtin; 477 struct neon_typed_alias *neon; 478}; 479 480/* Diagnostics used when we don't get a register of the expected type. */ 481const char *const reg_expected_msgs[] = 482{ 483 N_("ARM register expected"), 484 N_("bad or missing co-processor number"), 485 N_("co-processor register expected"), 486 N_("FPA register expected"), 487 N_("VFP single precision register expected"), 488 N_("VFP/Neon double precision register expected"), 489 N_("Neon quad precision register expected"), 490 N_("VFP single or double precision register expected"), 491 N_("Neon double or quad precision register expected"), 492 N_("VFP single, double or Neon quad precision register expected"), 493 N_("VFP system register expected"), 494 N_("Maverick MVF register expected"), 495 N_("Maverick MVD register expected"), 496 N_("Maverick MVFX register expected"), 497 N_("Maverick MVDX register expected"), 498 N_("Maverick MVAX register expected"), 499 N_("Maverick DSPSC register expected"), 500 N_("iWMMXt data register expected"), 501 N_("iWMMXt control register expected"), 502 N_("iWMMXt scalar register expected"), 503 N_("XScale accumulator register expected"), 504}; 505 506/* Some well known registers that we refer to directly elsewhere. */ 507#define REG_SP 13 508#define REG_LR 14 509#define REG_PC 15 510 511/* ARM instructions take 4bytes in the object file, Thumb instructions 512 take 2: */ 513#define INSN_SIZE 4 514 515struct asm_opcode 516{ 517 /* Basic string to match. */ 518 const char *template; 519 520 /* Parameters to instruction. */ 521 unsigned char operands[8]; 522 523 /* Conditional tag - see opcode_lookup. */ 524 unsigned int tag : 4; 525 526 /* Basic instruction code. */ 527 unsigned int avalue : 28; 528 529 /* Thumb-format instruction code. */ 530 unsigned int tvalue; 531 532 /* Which architecture variant provides this instruction. */ 533 const arm_feature_set *avariant; 534 const arm_feature_set *tvariant; 535 536 /* Function to call to encode instruction in ARM format. */ 537 void (* aencode) (void); 538 539 /* Function to call to encode instruction in Thumb format. */ 540 void (* tencode) (void); 541}; 542 543/* Defines for various bits that we will want to toggle. */ 544#define INST_IMMEDIATE 0x02000000 545#define OFFSET_REG 0x02000000 546#define HWOFFSET_IMM 0x00400000 547#define SHIFT_BY_REG 0x00000010 548#define PRE_INDEX 0x01000000 549#define INDEX_UP 0x00800000 550#define WRITE_BACK 0x00200000 551#define LDM_TYPE_2_OR_3 0x00400000 552#define CPSI_MMOD 0x00020000 553 554#define LITERAL_MASK 0xf000f000 555#define OPCODE_MASK 0xfe1fffff 556#define V4_STR_BIT 0x00000020 557 558#define T2_SUBS_PC_LR 0xf3de8f00 559 560#define DATA_OP_SHIFT 21 561 562#define T2_OPCODE_MASK 0xfe1fffff 563#define T2_DATA_OP_SHIFT 21 564 565/* Codes to distinguish the arithmetic instructions. */ 566#define OPCODE_AND 0 567#define OPCODE_EOR 1 568#define OPCODE_SUB 2 569#define OPCODE_RSB 3 570#define OPCODE_ADD 4 571#define OPCODE_ADC 5 572#define OPCODE_SBC 6 573#define OPCODE_RSC 7 574#define OPCODE_TST 8 575#define OPCODE_TEQ 9 576#define OPCODE_CMP 10 577#define OPCODE_CMN 11 578#define OPCODE_ORR 12 579#define OPCODE_MOV 13 580#define OPCODE_BIC 14 581#define OPCODE_MVN 15 582 583#define T2_OPCODE_AND 0 584#define T2_OPCODE_BIC 1 585#define T2_OPCODE_ORR 2 586#define T2_OPCODE_ORN 3 587#define T2_OPCODE_EOR 4 588#define T2_OPCODE_ADD 8 589#define T2_OPCODE_ADC 10 590#define T2_OPCODE_SBC 11 591#define T2_OPCODE_SUB 13 592#define T2_OPCODE_RSB 14 593 594#define T_OPCODE_MUL 0x4340 595#define T_OPCODE_TST 0x4200 596#define T_OPCODE_CMN 0x42c0 597#define T_OPCODE_NEG 0x4240 598#define T_OPCODE_MVN 0x43c0 599 600#define T_OPCODE_ADD_R3 0x1800 601#define T_OPCODE_SUB_R3 0x1a00 602#define T_OPCODE_ADD_HI 0x4400 603#define T_OPCODE_ADD_ST 0xb000 604#define T_OPCODE_SUB_ST 0xb080 605#define T_OPCODE_ADD_SP 0xa800 606#define T_OPCODE_ADD_PC 0xa000 607#define T_OPCODE_ADD_I8 0x3000 608#define T_OPCODE_SUB_I8 0x3800 609#define T_OPCODE_ADD_I3 0x1c00 610#define T_OPCODE_SUB_I3 0x1e00 611 612#define T_OPCODE_ASR_R 0x4100 613#define T_OPCODE_LSL_R 0x4080 614#define T_OPCODE_LSR_R 0x40c0 615#define T_OPCODE_ROR_R 0x41c0 616#define T_OPCODE_ASR_I 0x1000 617#define T_OPCODE_LSL_I 0x0000 618#define T_OPCODE_LSR_I 0x0800 619 620#define T_OPCODE_MOV_I8 0x2000 621#define T_OPCODE_CMP_I8 0x2800 622#define T_OPCODE_CMP_LR 0x4280 623#define T_OPCODE_MOV_HR 0x4600 624#define T_OPCODE_CMP_HR 0x4500 625 626#define T_OPCODE_LDR_PC 0x4800 627#define T_OPCODE_LDR_SP 0x9800 628#define T_OPCODE_STR_SP 0x9000 629#define T_OPCODE_LDR_IW 0x6800 630#define T_OPCODE_STR_IW 0x6000 631#define T_OPCODE_LDR_IH 0x8800 632#define T_OPCODE_STR_IH 0x8000 633#define T_OPCODE_LDR_IB 0x7800 634#define T_OPCODE_STR_IB 0x7000 635#define T_OPCODE_LDR_RW 0x5800 636#define T_OPCODE_STR_RW 0x5000 637#define T_OPCODE_LDR_RH 0x5a00 638#define T_OPCODE_STR_RH 0x5200 639#define T_OPCODE_LDR_RB 0x5c00 640#define T_OPCODE_STR_RB 0x5400 641 642#define T_OPCODE_PUSH 0xb400 643#define T_OPCODE_POP 0xbc00 644 645#define T_OPCODE_BRANCH 0xe000 646 647#define THUMB_SIZE 2 /* Size of thumb instruction. */ 648#define THUMB_PP_PC_LR 0x0100 649#define THUMB_LOAD_BIT 0x0800 650#define THUMB2_LOAD_BIT 0x00100000 651 652#define BAD_ARGS _("bad arguments to instruction") 653#define BAD_PC _("r15 not allowed here") 654#define BAD_SP _("r13 not allowed here") 655#define BAD_COND _("instruction cannot be conditional") 656#define BAD_OVERLAP _("registers may not be the same") 657#define BAD_HIREG _("lo register required") 658#define BAD_THUMB32 _("instruction not supported in Thumb16 mode") 659#define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); 660#define BAD_BRANCH _("branch must be last instruction in IT block") 661#define BAD_NOT_IT _("instruction not allowed in IT block") 662#define BAD_FPU _("selected FPU does not support instruction") 663#define BAD_VMRS _("APSR_nzcv may only be used with fpscr") 664 665static struct hash_control *arm_ops_hsh; 666static struct hash_control *arm_cond_hsh; 667static struct hash_control *arm_shift_hsh; 668static struct hash_control *arm_psr_hsh; 669static struct hash_control *arm_v7m_psr_hsh; 670static struct hash_control *arm_reg_hsh; 671static struct hash_control *arm_reloc_hsh; 672static struct hash_control *arm_barrier_opt_hsh; 673 674/* Stuff needed to resolve the label ambiguity 675 As: 676 ... 677 label: <insn> 678 may differ from: 679 ... 680 label: 681 <insn> 682*/ 683 684symbolS * last_label_seen; 685static int label_is_thumb_function_name = FALSE; 686 687/* Literal pool structure. Held on a per-section 688 and per-sub-section basis. */ 689 690#define MAX_LITERAL_POOL_SIZE 1024 691typedef struct literal_pool 692{ 693 expressionS literals [MAX_LITERAL_POOL_SIZE]; 694 unsigned int next_free_entry; 695 unsigned int id; 696 symbolS * symbol; 697 segT section; 698 subsegT sub_section; 699 struct literal_pool * next; 700} literal_pool; 701 702/* Pointer to a linked list of literal pools. */ 703literal_pool * list_of_pools = NULL; 704 705/* State variables for IT block handling. */ 706static bfd_boolean current_it_mask = 0; 707static int current_cc; 708 709 710/* Pure syntax. */ 711 712/* This array holds the chars that always start a comment. If the 713 pre-processor is disabled, these aren't very useful. */ 714const char comment_chars[] = "@"; 715 716/* This array holds the chars that only start a comment at the beginning of 717 a line. If the line seems to have the form '# 123 filename' 718 .line and .file directives will appear in the pre-processed output. */ 719/* Note that input_file.c hand checks for '#' at the beginning of the 720 first line of the input file. This is because the compiler outputs 721 #NO_APP at the beginning of its output. */ 722/* Also note that comments like this one will always work. */ 723const char line_comment_chars[] = "#"; 724 725const char line_separator_chars[] = ";"; 726 727/* Chars that can be used to separate mant 728 from exp in floating point numbers. */ 729const char EXP_CHARS[] = "eE"; 730 731/* Chars that mean this number is a floating point constant. */ 732/* As in 0f12.456 */ 733/* or 0d1.2345e12 */ 734 735const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 736 737/* Prefix characters that indicate the start of an immediate 738 value. */ 739#define is_immediate_prefix(C) ((C) == '#' || (C) == '$') 740 741/* Separator character handling. */ 742 743#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) 744 745static inline int 746skip_past_char (char ** str, char c) 747{ 748 if (**str == c) 749 { 750 (*str)++; 751 return SUCCESS; 752 } 753 else 754 return FAIL; 755} 756#define skip_past_comma(str) skip_past_char (str, ',') 757 758/* Arithmetic expressions (possibly involving symbols). */ 759 760/* Return TRUE if anything in the expression is a bignum. */ 761 762static int 763walk_no_bignums (symbolS * sp) 764{ 765 if (symbol_get_value_expression (sp)->X_op == O_big) 766 return 1; 767 768 if (symbol_get_value_expression (sp)->X_add_symbol) 769 { 770 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) 771 || (symbol_get_value_expression (sp)->X_op_symbol 772 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); 773 } 774 775 return 0; 776} 777 778static int in_my_get_expression = 0; 779 780/* Third argument to my_get_expression. */ 781#define GE_NO_PREFIX 0 782#define GE_IMM_PREFIX 1 783#define GE_OPT_PREFIX 2 784/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) 785 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ 786#define GE_OPT_PREFIX_BIG 3 787 788static int 789my_get_expression (expressionS * ep, char ** str, int prefix_mode) 790{ 791 char * save_in; 792 segT seg; 793 794 /* In unified syntax, all prefixes are optional. */ 795 if (unified_syntax) 796 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode 797 : GE_OPT_PREFIX; 798 799 switch (prefix_mode) 800 { 801 case GE_NO_PREFIX: break; 802 case GE_IMM_PREFIX: 803 if (!is_immediate_prefix (**str)) 804 { 805 inst.error = _("immediate expression requires a # prefix"); 806 return FAIL; 807 } 808 (*str)++; 809 break; 810 case GE_OPT_PREFIX: 811 case GE_OPT_PREFIX_BIG: 812 if (is_immediate_prefix (**str)) 813 (*str)++; 814 break; 815 default: abort (); 816 } 817 818 memset (ep, 0, sizeof (expressionS)); 819 820 save_in = input_line_pointer; 821 input_line_pointer = *str; 822 in_my_get_expression = 1; 823 seg = expression (ep); 824 in_my_get_expression = 0; 825 826 if (ep->X_op == O_illegal) 827 { 828 /* We found a bad expression in md_operand(). */ 829 *str = input_line_pointer; 830 input_line_pointer = save_in; 831 if (inst.error == NULL) 832 inst.error = _("bad expression"); 833 return 1; 834 } 835 836#ifdef OBJ_AOUT 837 if (seg != absolute_section 838 && seg != text_section 839 && seg != data_section 840 && seg != bss_section 841 && seg != undefined_section) 842 { 843 inst.error = _("bad segment"); 844 *str = input_line_pointer; 845 input_line_pointer = save_in; 846 return 1; 847 } 848#endif 849 850 /* Get rid of any bignums now, so that we don't generate an error for which 851 we can't establish a line number later on. Big numbers are never valid 852 in instructions, which is where this routine is always called. */ 853 if (prefix_mode != GE_OPT_PREFIX_BIG 854 && (ep->X_op == O_big 855 || (ep->X_add_symbol 856 && (walk_no_bignums (ep->X_add_symbol) 857 || (ep->X_op_symbol 858 && walk_no_bignums (ep->X_op_symbol)))))) 859 { 860 inst.error = _("invalid constant"); 861 *str = input_line_pointer; 862 input_line_pointer = save_in; 863 return 1; 864 } 865 866 *str = input_line_pointer; 867 input_line_pointer = save_in; 868 return 0; 869} 870 871/* Turn a string in input_line_pointer into a floating point constant 872 of type TYPE, and store the appropriate bytes in *LITP. The number 873 of LITTLENUMS emitted is stored in *SIZEP. An error message is 874 returned, or NULL on OK. 875 876 Note that fp constants aren't represent in the normal way on the ARM. 877 In big endian mode, things are as expected. However, in little endian 878 mode fp constants are big-endian word-wise, and little-endian byte-wise 879 within the words. For example, (double) 1.1 in big endian mode is 880 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is 881 the byte sequence 99 99 f1 3f 9a 99 99 99. 882 883 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ 884 885char * 886md_atof (int type, char * litP, int * sizeP) 887{ 888 int prec; 889 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 890 char *t; 891 int i; 892 893 switch (type) 894 { 895 case 'f': 896 case 'F': 897 case 's': 898 case 'S': 899 prec = 2; 900 break; 901 902 case 'd': 903 case 'D': 904 case 'r': 905 case 'R': 906 prec = 4; 907 break; 908 909 case 'x': 910 case 'X': 911 prec = 6; 912 break; 913 914 case 'p': 915 case 'P': 916 prec = 6; 917 break; 918 919 default: 920 *sizeP = 0; 921 return _("bad call to MD_ATOF()"); 922 } 923 924 t = atof_ieee (input_line_pointer, type, words); 925 if (t) 926 input_line_pointer = t; 927 *sizeP = prec * 2; 928 929 if (target_big_endian) 930 { 931 for (i = 0; i < prec; i++) 932 { 933 md_number_to_chars (litP, (valueT) words[i], 2); 934 litP += 2; 935 } 936 } 937 else 938 { 939 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 940 for (i = prec - 1; i >= 0; i--) 941 { 942 md_number_to_chars (litP, (valueT) words[i], 2); 943 litP += 2; 944 } 945 else 946 /* For a 4 byte float the order of elements in `words' is 1 0. 947 For an 8 byte float the order is 1 0 3 2. */ 948 for (i = 0; i < prec; i += 2) 949 { 950 md_number_to_chars (litP, (valueT) words[i + 1], 2); 951 md_number_to_chars (litP + 2, (valueT) words[i], 2); 952 litP += 4; 953 } 954 } 955 956 return 0; 957} 958 959/* We handle all bad expressions here, so that we can report the faulty 960 instruction in the error message. */ 961void 962md_operand (expressionS * expr) 963{ 964 if (in_my_get_expression) 965 expr->X_op = O_illegal; 966} 967 968/* Immediate values. */ 969 970/* Generic immediate-value read function for use in directives. 971 Accepts anything that 'expression' can fold to a constant. 972 *val receives the number. */ 973#ifdef OBJ_ELF 974static int 975immediate_for_directive (int *val) 976{ 977 expressionS exp; 978 exp.X_op = O_illegal; 979 980 if (is_immediate_prefix (*input_line_pointer)) 981 { 982 input_line_pointer++; 983 expression (&exp); 984 } 985 986 if (exp.X_op != O_constant) 987 { 988 as_bad (_("expected #constant")); 989 ignore_rest_of_line (); 990 return FAIL; 991 } 992 *val = exp.X_add_number; 993 return SUCCESS; 994} 995#endif 996 997/* Register parsing. */ 998 999/* Generic register parser. CCP points to what should be the 1000 beginning of a register name. If it is indeed a valid register 1001 name, advance CCP over it and return the reg_entry structure; 1002 otherwise return NULL. Does not issue diagnostics. */ 1003 1004static struct reg_entry * 1005arm_reg_parse_multi (char **ccp) 1006{ 1007 char *start = *ccp; 1008 char *p; 1009 struct reg_entry *reg; 1010 1011#ifdef REGISTER_PREFIX 1012 if (*start != REGISTER_PREFIX) 1013 return NULL; 1014 start++; 1015#endif 1016#ifdef OPTIONAL_REGISTER_PREFIX 1017 if (*start == OPTIONAL_REGISTER_PREFIX) 1018 start++; 1019#endif 1020 1021 p = start; 1022 if (!ISALPHA (*p) || !is_name_beginner (*p)) 1023 return NULL; 1024 1025 do 1026 p++; 1027 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); 1028 1029 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); 1030 1031 if (!reg) 1032 return NULL; 1033 1034 *ccp = p; 1035 return reg; 1036} 1037 1038static int 1039arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, 1040 enum arm_reg_type type) 1041{ 1042 /* Alternative syntaxes are accepted for a few register classes. */ 1043 switch (type) 1044 { 1045 case REG_TYPE_MVF: 1046 case REG_TYPE_MVD: 1047 case REG_TYPE_MVFX: 1048 case REG_TYPE_MVDX: 1049 /* Generic coprocessor register names are allowed for these. */ 1050 if (reg && reg->type == REG_TYPE_CN) 1051 return reg->number; 1052 break; 1053 1054 case REG_TYPE_CP: 1055 /* For backward compatibility, a bare number is valid here. */ 1056 { 1057 unsigned long processor = strtoul (start, ccp, 10); 1058 if (*ccp != start && processor <= 15) 1059 return processor; 1060 } 1061 1062 case REG_TYPE_MMXWC: 1063 /* WC includes WCG. ??? I'm not sure this is true for all 1064 instructions that take WC registers. */ 1065 if (reg && reg->type == REG_TYPE_MMXWCG) 1066 return reg->number; 1067 break; 1068 1069 default: 1070 break; 1071 } 1072 1073 return FAIL; 1074} 1075 1076/* As arm_reg_parse_multi, but the register must be of type TYPE, and the 1077 return value is the register number or FAIL. */ 1078 1079static int 1080arm_reg_parse (char **ccp, enum arm_reg_type type) 1081{ 1082 char *start = *ccp; 1083 struct reg_entry *reg = arm_reg_parse_multi (ccp); 1084 int ret; 1085 1086 /* Do not allow a scalar (reg+index) to parse as a register. */ 1087 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) 1088 return FAIL; 1089 1090 if (reg && reg->type == type) 1091 return reg->number; 1092 1093 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) 1094 return ret; 1095 1096 *ccp = start; 1097 return FAIL; 1098} 1099 1100/* Parse a Neon type specifier. *STR should point at the leading '.' 1101 character. Does no verification at this stage that the type fits the opcode 1102 properly. E.g., 1103 1104 .i32.i32.s16 1105 .s32.f32 1106 .u16 1107 1108 Can all be legally parsed by this function. 1109 1110 Fills in neon_type struct pointer with parsed information, and updates STR 1111 to point after the parsed type specifier. Returns SUCCESS if this was a legal 1112 type, FAIL if not. */ 1113 1114static int 1115parse_neon_type (struct neon_type *type, char **str) 1116{ 1117 char *ptr = *str; 1118 1119 if (type) 1120 type->elems = 0; 1121 1122 while (type->elems < NEON_MAX_TYPE_ELS) 1123 { 1124 enum neon_el_type thistype = NT_untyped; 1125 unsigned thissize = -1u; 1126 1127 if (*ptr != '.') 1128 break; 1129 1130 ptr++; 1131 1132 /* Just a size without an explicit type. */ 1133 if (ISDIGIT (*ptr)) 1134 goto parsesize; 1135 1136 switch (TOLOWER (*ptr)) 1137 { 1138 case 'i': thistype = NT_integer; break; 1139 case 'f': thistype = NT_float; break; 1140 case 'p': thistype = NT_poly; break; 1141 case 's': thistype = NT_signed; break; 1142 case 'u': thistype = NT_unsigned; break; 1143 case 'd': 1144 thistype = NT_float; 1145 thissize = 64; 1146 ptr++; 1147 goto done; 1148 default: 1149 as_bad (_("unexpected character `%c' in type specifier"), *ptr); 1150 return FAIL; 1151 } 1152 1153 ptr++; 1154 1155 /* .f is an abbreviation for .f32. */ 1156 if (thistype == NT_float && !ISDIGIT (*ptr)) 1157 thissize = 32; 1158 else 1159 { 1160 parsesize: 1161 thissize = strtoul (ptr, &ptr, 10); 1162 1163 if (thissize != 8 && thissize != 16 && thissize != 32 1164 && thissize != 64) 1165 { 1166 as_bad (_("bad size %d in type specifier"), thissize); 1167 return FAIL; 1168 } 1169 } 1170 1171 done: 1172 if (type) 1173 { 1174 type->el[type->elems].type = thistype; 1175 type->el[type->elems].size = thissize; 1176 type->elems++; 1177 } 1178 } 1179 1180 /* Empty/missing type is not a successful parse. */ 1181 if (type->elems == 0) 1182 return FAIL; 1183 1184 *str = ptr; 1185 1186 return SUCCESS; 1187} 1188 1189/* Errors may be set multiple times during parsing or bit encoding 1190 (particularly in the Neon bits), but usually the earliest error which is set 1191 will be the most meaningful. Avoid overwriting it with later (cascading) 1192 errors by calling this function. */ 1193 1194static void 1195first_error (const char *err) 1196{ 1197 if (!inst.error) 1198 inst.error = err; 1199} 1200 1201/* Parse a single type, e.g. ".s32", leading period included. */ 1202static int 1203parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) 1204{ 1205 char *str = *ccp; 1206 struct neon_type optype; 1207 1208 if (*str == '.') 1209 { 1210 if (parse_neon_type (&optype, &str) == SUCCESS) 1211 { 1212 if (optype.elems == 1) 1213 *vectype = optype.el[0]; 1214 else 1215 { 1216 first_error (_("only one type should be specified for operand")); 1217 return FAIL; 1218 } 1219 } 1220 else 1221 { 1222 first_error (_("vector type expected")); 1223 return FAIL; 1224 } 1225 } 1226 else 1227 return FAIL; 1228 1229 *ccp = str; 1230 1231 return SUCCESS; 1232} 1233 1234/* Special meanings for indices (which have a range of 0-7), which will fit into 1235 a 4-bit integer. */ 1236 1237#define NEON_ALL_LANES 15 1238#define NEON_INTERLEAVE_LANES 14 1239 1240/* Parse either a register or a scalar, with an optional type. Return the 1241 register number, and optionally fill in the actual type of the register 1242 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and 1243 type/index information in *TYPEINFO. */ 1244 1245static int 1246parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, 1247 enum arm_reg_type *rtype, 1248 struct neon_typed_alias *typeinfo) 1249{ 1250 char *str = *ccp; 1251 struct reg_entry *reg = arm_reg_parse_multi (&str); 1252 struct neon_typed_alias atype; 1253 struct neon_type_el parsetype; 1254 1255 atype.defined = 0; 1256 atype.index = -1; 1257 atype.eltype.type = NT_invtype; 1258 atype.eltype.size = -1; 1259 1260 /* Try alternate syntax for some types of register. Note these are mutually 1261 exclusive with the Neon syntax extensions. */ 1262 if (reg == NULL) 1263 { 1264 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); 1265 if (altreg != FAIL) 1266 *ccp = str; 1267 if (typeinfo) 1268 *typeinfo = atype; 1269 return altreg; 1270 } 1271 1272 /* Undo polymorphism when a set of register types may be accepted. */ 1273 if ((type == REG_TYPE_NDQ 1274 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) 1275 || (type == REG_TYPE_VFSD 1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) 1277 || (type == REG_TYPE_NSDQ 1278 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD 1279 || reg->type == REG_TYPE_NQ)) 1280 || (type == REG_TYPE_MMXWC 1281 && (reg->type == REG_TYPE_MMXWCG))) 1282 type = reg->type; 1283 1284 if (type != reg->type) 1285 return FAIL; 1286 1287 if (reg->neon) 1288 atype = *reg->neon; 1289 1290 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) 1291 { 1292 if ((atype.defined & NTA_HASTYPE) != 0) 1293 { 1294 first_error (_("can't redefine type for operand")); 1295 return FAIL; 1296 } 1297 atype.defined |= NTA_HASTYPE; 1298 atype.eltype = parsetype; 1299 } 1300 1301 if (skip_past_char (&str, '[') == SUCCESS) 1302 { 1303 if (type != REG_TYPE_VFD) 1304 { 1305 first_error (_("only D registers may be indexed")); 1306 return FAIL; 1307 } 1308 1309 if ((atype.defined & NTA_HASINDEX) != 0) 1310 { 1311 first_error (_("can't change index for operand")); 1312 return FAIL; 1313 } 1314 1315 atype.defined |= NTA_HASINDEX; 1316 1317 if (skip_past_char (&str, ']') == SUCCESS) 1318 atype.index = NEON_ALL_LANES; 1319 else 1320 { 1321 expressionS exp; 1322 1323 my_get_expression (&exp, &str, GE_NO_PREFIX); 1324 1325 if (exp.X_op != O_constant) 1326 { 1327 first_error (_("constant expression required")); 1328 return FAIL; 1329 } 1330 1331 if (skip_past_char (&str, ']') == FAIL) 1332 return FAIL; 1333 1334 atype.index = exp.X_add_number; 1335 } 1336 } 1337 1338 if (typeinfo) 1339 *typeinfo = atype; 1340 1341 if (rtype) 1342 *rtype = type; 1343 1344 *ccp = str; 1345 1346 return reg->number; 1347} 1348 1349/* Like arm_reg_parse, but allow allow the following extra features: 1350 - If RTYPE is non-zero, return the (possibly restricted) type of the 1351 register (e.g. Neon double or quad reg when either has been requested). 1352 - If this is a Neon vector type with additional type information, fill 1353 in the struct pointed to by VECTYPE (if non-NULL). 1354 This function will fault on encountering a scalar. 1355*/ 1356 1357static int 1358arm_typed_reg_parse (char **ccp, enum arm_reg_type type, 1359 enum arm_reg_type *rtype, struct neon_type_el *vectype) 1360{ 1361 struct neon_typed_alias atype; 1362 char *str = *ccp; 1363 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); 1364 1365 if (reg == FAIL) 1366 return FAIL; 1367 1368 /* Do not allow a scalar (reg+index) to parse as a register. */ 1369 if ((atype.defined & NTA_HASINDEX) != 0) 1370 { 1371 first_error (_("register operand expected, but got scalar")); 1372 return FAIL; 1373 } 1374 1375 if (vectype) 1376 *vectype = atype.eltype; 1377 1378 *ccp = str; 1379 1380 return reg; 1381} 1382 1383#define NEON_SCALAR_REG(X) ((X) >> 4) 1384#define NEON_SCALAR_INDEX(X) ((X) & 15) 1385 1386/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't 1387 have enough information to be able to do a good job bounds-checking. So, we 1388 just do easy checks here, and do further checks later. */ 1389 1390static int 1391parse_scalar (char **ccp, int elsize, struct neon_type_el *type) 1392{ 1393 int reg; 1394 char *str = *ccp; 1395 struct neon_typed_alias atype; 1396 1397 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); 1398 1399 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) 1400 return FAIL; 1401 1402 if (atype.index == NEON_ALL_LANES) 1403 { 1404 first_error (_("scalar must have an index")); 1405 return FAIL; 1406 } 1407 else if (atype.index >= 64 / elsize) 1408 { 1409 first_error (_("scalar index out of range")); 1410 return FAIL; 1411 } 1412 1413 if (type) 1414 *type = atype.eltype; 1415 1416 *ccp = str; 1417 1418 return reg * 16 + atype.index; 1419} 1420 1421/* Parse an ARM register list. Returns the bitmask, or FAIL. */ 1422static long 1423parse_reg_list (char ** strp) 1424{ 1425 char * str = * strp; 1426 long range = 0; 1427 int another_range; 1428 1429 /* We come back here if we get ranges concatenated by '+' or '|'. */ 1430 do 1431 { 1432 another_range = 0; 1433 1434 if (*str == '{') 1435 { 1436 int in_range = 0; 1437 int cur_reg = -1; 1438 1439 str++; 1440 do 1441 { 1442 int reg; 1443 1444 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) 1445 { 1446 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 1447 return FAIL; 1448 } 1449 1450 if (in_range) 1451 { 1452 int i; 1453 1454 if (reg <= cur_reg) 1455 { 1456 first_error (_("bad range in register list")); 1457 return FAIL; 1458 } 1459 1460 for (i = cur_reg + 1; i < reg; i++) 1461 { 1462 if (range & (1 << i)) 1463 as_tsktsk 1464 (_("Warning: duplicated register (r%d) in register list"), 1465 i); 1466 else 1467 range |= 1 << i; 1468 } 1469 in_range = 0; 1470 } 1471 1472 if (range & (1 << reg)) 1473 as_tsktsk (_("Warning: duplicated register (r%d) in register list"), 1474 reg); 1475 else if (reg <= cur_reg) 1476 as_tsktsk (_("Warning: register range not in ascending order")); 1477 1478 range |= 1 << reg; 1479 cur_reg = reg; 1480 } 1481 while (skip_past_comma (&str) != FAIL 1482 || (in_range = 1, *str++ == '-')); 1483 str--; 1484 1485 if (*str++ != '}') 1486 { 1487 first_error (_("missing `}'")); 1488 return FAIL; 1489 } 1490 } 1491 else 1492 { 1493 expressionS expr; 1494 1495 if (my_get_expression (&expr, &str, GE_NO_PREFIX)) 1496 return FAIL; 1497 1498 if (expr.X_op == O_constant) 1499 { 1500 if (expr.X_add_number 1501 != (expr.X_add_number & 0x0000ffff)) 1502 { 1503 inst.error = _("invalid register mask"); 1504 return FAIL; 1505 } 1506 1507 if ((range & expr.X_add_number) != 0) 1508 { 1509 int regno = range & expr.X_add_number; 1510 1511 regno &= -regno; 1512 regno = (1 << regno) - 1; 1513 as_tsktsk 1514 (_("Warning: duplicated register (r%d) in register list"), 1515 regno); 1516 } 1517 1518 range |= expr.X_add_number; 1519 } 1520 else 1521 { 1522 if (inst.reloc.type != 0) 1523 { 1524 inst.error = _("expression too complex"); 1525 return FAIL; 1526 } 1527 1528 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); 1529 inst.reloc.type = BFD_RELOC_ARM_MULTI; 1530 inst.reloc.pc_rel = 0; 1531 } 1532 } 1533 1534 if (*str == '|' || *str == '+') 1535 { 1536 str++; 1537 another_range = 1; 1538 } 1539 } 1540 while (another_range); 1541 1542 *strp = str; 1543 return range; 1544} 1545 1546/* Types of registers in a list. */ 1547 1548enum reg_list_els 1549{ 1550 REGLIST_VFP_S, 1551 REGLIST_VFP_D, 1552 REGLIST_NEON_D 1553}; 1554 1555/* Parse a VFP register list. If the string is invalid return FAIL. 1556 Otherwise return the number of registers, and set PBASE to the first 1557 register. Parses registers of type ETYPE. 1558 If REGLIST_NEON_D is used, several syntax enhancements are enabled: 1559 - Q registers can be used to specify pairs of D registers 1560 - { } can be omitted from around a singleton register list 1561 FIXME: This is not implemented, as it would require backtracking in 1562 some cases, e.g.: 1563 vtbl.8 d3,d4,d5 1564 This could be done (the meaning isn't really ambiguous), but doesn't 1565 fit in well with the current parsing framework. 1566 - 32 D registers may be used (also true for VFPv3). 1567 FIXME: Types are ignored in these register lists, which is probably a 1568 bug. */ 1569 1570static int 1571parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) 1572{ 1573 char *str = *ccp; 1574 int base_reg; 1575 int new_base; 1576 enum arm_reg_type regtype = 0; 1577 int max_regs = 0; 1578 int count = 0; 1579 int warned = 0; 1580 unsigned long mask = 0; 1581 int i; 1582 1583 if (*str != '{') 1584 { 1585 inst.error = _("expecting {"); 1586 return FAIL; 1587 } 1588 1589 str++; 1590 1591 switch (etype) 1592 { 1593 case REGLIST_VFP_S: 1594 regtype = REG_TYPE_VFS; 1595 max_regs = 32; 1596 break; 1597 1598 case REGLIST_VFP_D: 1599 regtype = REG_TYPE_VFD; 1600 break; 1601 1602 case REGLIST_NEON_D: 1603 regtype = REG_TYPE_NDQ; 1604 break; 1605 } 1606 1607 if (etype != REGLIST_VFP_S) 1608 { 1609 /* VFPv3 allows 32 D registers. */ 1610 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 1611 { 1612 max_regs = 32; 1613 if (thumb_mode) 1614 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 1615 fpu_vfp_ext_v3); 1616 else 1617 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 1618 fpu_vfp_ext_v3); 1619 } 1620 else 1621 max_regs = 16; 1622 } 1623 1624 base_reg = max_regs; 1625 1626 do 1627 { 1628 int setmask = 1, addregs = 1; 1629 1630 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); 1631 1632 if (new_base == FAIL) 1633 { 1634 first_error (_(reg_expected_msgs[regtype])); 1635 return FAIL; 1636 } 1637 1638 if (new_base >= max_regs) 1639 { 1640 first_error (_("register out of range in list")); 1641 return FAIL; 1642 } 1643 1644 /* Note: a value of 2 * n is returned for the register Q<n>. */ 1645 if (regtype == REG_TYPE_NQ) 1646 { 1647 setmask = 3; 1648 addregs = 2; 1649 } 1650 1651 if (new_base < base_reg) 1652 base_reg = new_base; 1653 1654 if (mask & (setmask << new_base)) 1655 { 1656 first_error (_("invalid register list")); 1657 return FAIL; 1658 } 1659 1660 if ((mask >> new_base) != 0 && ! warned) 1661 { 1662 as_tsktsk (_("register list not in ascending order")); 1663 warned = 1; 1664 } 1665 1666 mask |= setmask << new_base; 1667 count += addregs; 1668 1669 if (*str == '-') /* We have the start of a range expression */ 1670 { 1671 int high_range; 1672 1673 str++; 1674 1675 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) 1676 == FAIL) 1677 { 1678 inst.error = gettext (reg_expected_msgs[regtype]); 1679 return FAIL; 1680 } 1681 1682 if (high_range >= max_regs) 1683 { 1684 first_error (_("register out of range in list")); 1685 return FAIL; 1686 } 1687 1688 if (regtype == REG_TYPE_NQ) 1689 high_range = high_range + 1; 1690 1691 if (high_range <= new_base) 1692 { 1693 inst.error = _("register range not in ascending order"); 1694 return FAIL; 1695 } 1696 1697 for (new_base += addregs; new_base <= high_range; new_base += addregs) 1698 { 1699 if (mask & (setmask << new_base)) 1700 { 1701 inst.error = _("invalid register list"); 1702 return FAIL; 1703 } 1704 1705 mask |= setmask << new_base; 1706 count += addregs; 1707 } 1708 } 1709 } 1710 while (skip_past_comma (&str) != FAIL); 1711 1712 str++; 1713 1714 /* Sanity check -- should have raised a parse error above. */ 1715 if (count == 0 || count > max_regs) 1716 abort (); 1717 1718 *pbase = base_reg; 1719 1720 /* Final test -- the registers must be consecutive. */ 1721 mask >>= base_reg; 1722 for (i = 0; i < count; i++) 1723 { 1724 if ((mask & (1u << i)) == 0) 1725 { 1726 inst.error = _("non-contiguous register range"); 1727 return FAIL; 1728 } 1729 } 1730 1731 *ccp = str; 1732 1733 return count; 1734} 1735 1736/* True if two alias types are the same. */ 1737 1738static int 1739neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) 1740{ 1741 if (!a && !b) 1742 return 1; 1743 1744 if (!a || !b) 1745 return 0; 1746 1747 if (a->defined != b->defined) 1748 return 0; 1749 1750 if ((a->defined & NTA_HASTYPE) != 0 1751 && (a->eltype.type != b->eltype.type 1752 || a->eltype.size != b->eltype.size)) 1753 return 0; 1754 1755 if ((a->defined & NTA_HASINDEX) != 0 1756 && (a->index != b->index)) 1757 return 0; 1758 1759 return 1; 1760} 1761 1762/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. 1763 The base register is put in *PBASE. 1764 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of 1765 the return value. 1766 The register stride (minus one) is put in bit 4 of the return value. 1767 Bits [6:5] encode the list length (minus one). 1768 The type of the list elements is put in *ELTYPE, if non-NULL. */ 1769 1770#define NEON_LANE(X) ((X) & 0xf) 1771#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) 1772#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) 1773 1774static int 1775parse_neon_el_struct_list (char **str, unsigned *pbase, 1776 struct neon_type_el *eltype) 1777{ 1778 char *ptr = *str; 1779 int base_reg = -1; 1780 int reg_incr = -1; 1781 int count = 0; 1782 int lane = -1; 1783 int leading_brace = 0; 1784 enum arm_reg_type rtype = REG_TYPE_NDQ; 1785 int addregs = 1; 1786 const char *const incr_error = "register stride must be 1 or 2"; 1787 const char *const type_error = "mismatched element/structure types in list"; 1788 struct neon_typed_alias firsttype; 1789 1790 if (skip_past_char (&ptr, '{') == SUCCESS) 1791 leading_brace = 1; 1792 1793 do 1794 { 1795 struct neon_typed_alias atype; 1796 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); 1797 1798 if (getreg == FAIL) 1799 { 1800 first_error (_(reg_expected_msgs[rtype])); 1801 return FAIL; 1802 } 1803 1804 if (base_reg == -1) 1805 { 1806 base_reg = getreg; 1807 if (rtype == REG_TYPE_NQ) 1808 { 1809 reg_incr = 1; 1810 addregs = 2; 1811 } 1812 firsttype = atype; 1813 } 1814 else if (reg_incr == -1) 1815 { 1816 reg_incr = getreg - base_reg; 1817 if (reg_incr < 1 || reg_incr > 2) 1818 { 1819 first_error (_(incr_error)); 1820 return FAIL; 1821 } 1822 } 1823 else if (getreg != base_reg + reg_incr * count) 1824 { 1825 first_error (_(incr_error)); 1826 return FAIL; 1827 } 1828 1829 if (!neon_alias_types_same (&atype, &firsttype)) 1830 { 1831 first_error (_(type_error)); 1832 return FAIL; 1833 } 1834 1835 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list 1836 modes. */ 1837 if (ptr[0] == '-') 1838 { 1839 struct neon_typed_alias htype; 1840 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; 1841 if (lane == -1) 1842 lane = NEON_INTERLEAVE_LANES; 1843 else if (lane != NEON_INTERLEAVE_LANES) 1844 { 1845 first_error (_(type_error)); 1846 return FAIL; 1847 } 1848 if (reg_incr == -1) 1849 reg_incr = 1; 1850 else if (reg_incr != 1) 1851 { 1852 first_error (_("don't use Rn-Rm syntax with non-unit stride")); 1853 return FAIL; 1854 } 1855 ptr++; 1856 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); 1857 if (hireg == FAIL) 1858 { 1859 first_error (_(reg_expected_msgs[rtype])); 1860 return FAIL; 1861 } 1862 if (!neon_alias_types_same (&htype, &firsttype)) 1863 { 1864 first_error (_(type_error)); 1865 return FAIL; 1866 } 1867 count += hireg + dregs - getreg; 1868 continue; 1869 } 1870 1871 /* If we're using Q registers, we can't use [] or [n] syntax. */ 1872 if (rtype == REG_TYPE_NQ) 1873 { 1874 count += 2; 1875 continue; 1876 } 1877 1878 if ((atype.defined & NTA_HASINDEX) != 0) 1879 { 1880 if (lane == -1) 1881 lane = atype.index; 1882 else if (lane != atype.index) 1883 { 1884 first_error (_(type_error)); 1885 return FAIL; 1886 } 1887 } 1888 else if (lane == -1) 1889 lane = NEON_INTERLEAVE_LANES; 1890 else if (lane != NEON_INTERLEAVE_LANES) 1891 { 1892 first_error (_(type_error)); 1893 return FAIL; 1894 } 1895 count++; 1896 } 1897 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); 1898 1899 /* No lane set by [x]. We must be interleaving structures. */ 1900 if (lane == -1) 1901 lane = NEON_INTERLEAVE_LANES; 1902 1903 /* Sanity check. */ 1904 if (lane == -1 || base_reg == -1 || count < 1 || count > 4 1905 || (count > 1 && reg_incr == -1)) 1906 { 1907 first_error (_("error parsing element/structure list")); 1908 return FAIL; 1909 } 1910 1911 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) 1912 { 1913 first_error (_("expected }")); 1914 return FAIL; 1915 } 1916 1917 if (reg_incr == -1) 1918 reg_incr = 1; 1919 1920 if (eltype) 1921 *eltype = firsttype.eltype; 1922 1923 *pbase = base_reg; 1924 *str = ptr; 1925 1926 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); 1927} 1928 1929/* Parse an explicit relocation suffix on an expression. This is 1930 either nothing, or a word in parentheses. Note that if !OBJ_ELF, 1931 arm_reloc_hsh contains no entries, so this function can only 1932 succeed if there is no () after the word. Returns -1 on error, 1933 BFD_RELOC_UNUSED if there wasn't any suffix. */ 1934static int 1935parse_reloc (char **str) 1936{ 1937 struct reloc_entry *r; 1938 char *p, *q; 1939 1940 if (**str != '(') 1941 return BFD_RELOC_UNUSED; 1942 1943 p = *str + 1; 1944 q = p; 1945 1946 while (*q && *q != ')' && *q != ',') 1947 q++; 1948 if (*q != ')') 1949 return -1; 1950 1951 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) 1952 return -1; 1953 1954 *str = q + 1; 1955 return r->reloc; 1956} 1957 1958/* Directives: register aliases. */ 1959 1960static struct reg_entry * 1961insert_reg_alias (char *str, int number, int type) 1962{ 1963 struct reg_entry *new; 1964 const char *name; 1965 1966 if ((new = hash_find (arm_reg_hsh, str)) != 0) 1967 { 1968 if (new->builtin) 1969 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); 1970 1971 /* Only warn about a redefinition if it's not defined as the 1972 same register. */ 1973 else if (new->number != number || new->type != type) 1974 as_warn (_("ignoring redefinition of register alias '%s'"), str); 1975 1976 return 0; 1977 } 1978 1979 name = xstrdup (str); 1980 new = xmalloc (sizeof (struct reg_entry)); 1981 1982 new->name = name; 1983 new->number = number; 1984 new->type = type; 1985 new->builtin = FALSE; 1986 new->neon = NULL; 1987 1988 if (hash_insert (arm_reg_hsh, name, (PTR) new)) 1989 abort (); 1990 1991 return new; 1992} 1993 1994static void 1995insert_neon_reg_alias (char *str, int number, int type, 1996 struct neon_typed_alias *atype) 1997{ 1998 struct reg_entry *reg = insert_reg_alias (str, number, type); 1999 2000 if (!reg) 2001 { 2002 first_error (_("attempt to redefine typed alias")); 2003 return; 2004 } 2005 2006 if (atype) 2007 { 2008 reg->neon = xmalloc (sizeof (struct neon_typed_alias)); 2009 *reg->neon = *atype; 2010 } 2011} 2012 2013/* Look for the .req directive. This is of the form: 2014 2015 new_register_name .req existing_register_name 2016 2017 If we find one, or if it looks sufficiently like one that we want to 2018 handle any error here, return non-zero. Otherwise return zero. */ 2019 2020static int 2021create_register_alias (char * newname, char *p) 2022{ 2023 struct reg_entry *old; 2024 char *oldname, *nbuf; 2025 size_t nlen; 2026 2027 /* The input scrubber ensures that whitespace after the mnemonic is 2028 collapsed to single spaces. */ 2029 oldname = p; 2030 if (strncmp (oldname, " .req ", 6) != 0) 2031 return 0; 2032 2033 oldname += 6; 2034 if (*oldname == '\0') 2035 return 0; 2036 2037 old = hash_find (arm_reg_hsh, oldname); 2038 if (!old) 2039 { 2040 as_warn (_("unknown register '%s' -- .req ignored"), oldname); 2041 return 1; 2042 } 2043 2044 /* If TC_CASE_SENSITIVE is defined, then newname already points to 2045 the desired alias name, and p points to its end. If not, then 2046 the desired alias name is in the global original_case_string. */ 2047#ifdef TC_CASE_SENSITIVE 2048 nlen = p - newname; 2049#else 2050 newname = original_case_string; 2051 nlen = strlen (newname); 2052#endif 2053 2054 nbuf = alloca (nlen + 1); 2055 memcpy (nbuf, newname, nlen); 2056 nbuf[nlen] = '\0'; 2057 2058 /* Create aliases under the new name as stated; an all-lowercase 2059 version of the new name; and an all-uppercase version of the new 2060 name. */ 2061 insert_reg_alias (nbuf, old->number, old->type); 2062 2063 for (p = nbuf; *p; p++) 2064 *p = TOUPPER (*p); 2065 2066 if (strncmp (nbuf, newname, nlen)) 2067 insert_reg_alias (nbuf, old->number, old->type); 2068 2069 for (p = nbuf; *p; p++) 2070 *p = TOLOWER (*p); 2071 2072 if (strncmp (nbuf, newname, nlen)) 2073 insert_reg_alias (nbuf, old->number, old->type); 2074 2075 return 1; 2076} 2077 2078/* Create a Neon typed/indexed register alias using directives, e.g.: 2079 X .dn d5.s32[1] 2080 Y .qn 6.s16 2081 Z .dn d7 2082 T .dn Z[0] 2083 These typed registers can be used instead of the types specified after the 2084 Neon mnemonic, so long as all operands given have types. Types can also be 2085 specified directly, e.g.: 2086 vadd d0.s32, d1.s32, d2.s32 2087*/ 2088 2089static int 2090create_neon_reg_alias (char *newname, char *p) 2091{ 2092 enum arm_reg_type basetype; 2093 struct reg_entry *basereg; 2094 struct reg_entry mybasereg; 2095 struct neon_type ntype; 2096 struct neon_typed_alias typeinfo; 2097 char *namebuf, *nameend; 2098 int namelen; 2099 2100 typeinfo.defined = 0; 2101 typeinfo.eltype.type = NT_invtype; 2102 typeinfo.eltype.size = -1; 2103 typeinfo.index = -1; 2104 2105 nameend = p; 2106 2107 if (strncmp (p, " .dn ", 5) == 0) 2108 basetype = REG_TYPE_VFD; 2109 else if (strncmp (p, " .qn ", 5) == 0) 2110 basetype = REG_TYPE_NQ; 2111 else 2112 return 0; 2113 2114 p += 5; 2115 2116 if (*p == '\0') 2117 return 0; 2118 2119 basereg = arm_reg_parse_multi (&p); 2120 2121 if (basereg && basereg->type != basetype) 2122 { 2123 as_bad (_("bad type for register")); 2124 return 0; 2125 } 2126 2127 if (basereg == NULL) 2128 { 2129 expressionS exp; 2130 /* Try parsing as an integer. */ 2131 my_get_expression (&exp, &p, GE_NO_PREFIX); 2132 if (exp.X_op != O_constant) 2133 { 2134 as_bad (_("expression must be constant")); 2135 return 0; 2136 } 2137 basereg = &mybasereg; 2138 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 2139 : exp.X_add_number; 2140 basereg->neon = 0; 2141 } 2142 2143 if (basereg->neon) 2144 typeinfo = *basereg->neon; 2145 2146 if (parse_neon_type (&ntype, &p) == SUCCESS) 2147 { 2148 /* We got a type. */ 2149 if (typeinfo.defined & NTA_HASTYPE) 2150 { 2151 as_bad (_("can't redefine the type of a register alias")); 2152 return 0; 2153 } 2154 2155 typeinfo.defined |= NTA_HASTYPE; 2156 if (ntype.elems != 1) 2157 { 2158 as_bad (_("you must specify a single type only")); 2159 return 0; 2160 } 2161 typeinfo.eltype = ntype.el[0]; 2162 } 2163 2164 if (skip_past_char (&p, '[') == SUCCESS) 2165 { 2166 expressionS exp; 2167 /* We got a scalar index. */ 2168 2169 if (typeinfo.defined & NTA_HASINDEX) 2170 { 2171 as_bad (_("can't redefine the index of a scalar alias")); 2172 return 0; 2173 } 2174 2175 my_get_expression (&exp, &p, GE_NO_PREFIX); 2176 2177 if (exp.X_op != O_constant) 2178 { 2179 as_bad (_("scalar index must be constant")); 2180 return 0; 2181 } 2182 2183 typeinfo.defined |= NTA_HASINDEX; 2184 typeinfo.index = exp.X_add_number; 2185 2186 if (skip_past_char (&p, ']') == FAIL) 2187 { 2188 as_bad (_("expecting ]")); 2189 return 0; 2190 } 2191 } 2192 2193 namelen = nameend - newname; 2194 namebuf = alloca (namelen + 1); 2195 strncpy (namebuf, newname, namelen); 2196 namebuf[namelen] = '\0'; 2197 2198 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2199 typeinfo.defined != 0 ? &typeinfo : NULL); 2200 2201 /* Insert name in all uppercase. */ 2202 for (p = namebuf; *p; p++) 2203 *p = TOUPPER (*p); 2204 2205 if (strncmp (namebuf, newname, namelen)) 2206 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2207 typeinfo.defined != 0 ? &typeinfo : NULL); 2208 2209 /* Insert name in all lowercase. */ 2210 for (p = namebuf; *p; p++) 2211 *p = TOLOWER (*p); 2212 2213 if (strncmp (namebuf, newname, namelen)) 2214 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2215 typeinfo.defined != 0 ? &typeinfo : NULL); 2216 2217 return 1; 2218} 2219 2220/* Should never be called, as .req goes between the alias and the 2221 register name, not at the beginning of the line. */ 2222static void 2223s_req (int a ATTRIBUTE_UNUSED) 2224{ 2225 as_bad (_("invalid syntax for .req directive")); 2226} 2227 2228static void 2229s_dn (int a ATTRIBUTE_UNUSED) 2230{ 2231 as_bad (_("invalid syntax for .dn directive")); 2232} 2233 2234static void 2235s_qn (int a ATTRIBUTE_UNUSED) 2236{ 2237 as_bad (_("invalid syntax for .qn directive")); 2238} 2239 2240/* The .unreq directive deletes an alias which was previously defined 2241 by .req. For example: 2242 2243 my_alias .req r11 2244 .unreq my_alias */ 2245 2246static void 2247s_unreq (int a ATTRIBUTE_UNUSED) 2248{ 2249 char * name; 2250 char saved_char; 2251 2252 name = input_line_pointer; 2253 2254 while (*input_line_pointer != 0 2255 && *input_line_pointer != ' ' 2256 && *input_line_pointer != '\n') 2257 ++input_line_pointer; 2258 2259 saved_char = *input_line_pointer; 2260 *input_line_pointer = 0; 2261 2262 if (!*name) 2263 as_bad (_("invalid syntax for .unreq directive")); 2264 else 2265 { 2266 struct reg_entry *reg = hash_find (arm_reg_hsh, name); 2267 2268 if (!reg) 2269 as_bad (_("unknown register alias '%s'"), name); 2270 else if (reg->builtin) 2271 as_warn (_("ignoring attempt to undefine built-in register '%s'"), 2272 name); 2273 else 2274 { 2275 hash_delete (arm_reg_hsh, name); 2276 free ((char *) reg->name); 2277 if (reg->neon) 2278 free (reg->neon); 2279 free (reg); 2280 } 2281 } 2282 2283 *input_line_pointer = saved_char; 2284 demand_empty_rest_of_line (); 2285} 2286 2287/* Directives: Instruction set selection. */ 2288 2289#ifdef OBJ_ELF 2290/* This code is to handle mapping symbols as defined in the ARM ELF spec. 2291 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). 2292 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), 2293 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ 2294 2295static enum mstate mapstate = MAP_UNDEFINED; 2296 2297void 2298mapping_state (enum mstate state) 2299{ 2300 symbolS * symbolP; 2301 const char * symname; 2302 int type; 2303 2304 if (mapstate == state) 2305 /* The mapping symbol has already been emitted. 2306 There is nothing else to do. */ 2307 return; 2308 2309 mapstate = state; 2310 2311 switch (state) 2312 { 2313 case MAP_DATA: 2314 symname = "$d"; 2315 type = BSF_NO_FLAGS; 2316 break; 2317 case MAP_ARM: 2318 symname = "$a"; 2319 type = BSF_NO_FLAGS; 2320 break; 2321 case MAP_THUMB: 2322 symname = "$t"; 2323 type = BSF_NO_FLAGS; 2324 break; 2325 case MAP_UNDEFINED: 2326 return; 2327 default: 2328 abort (); 2329 } 2330 2331 seg_info (now_seg)->tc_segment_info_data.mapstate = state; 2332 2333 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); 2334 symbol_table_insert (symbolP); 2335 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; 2336 2337 switch (state) 2338 { 2339 case MAP_ARM: 2340 THUMB_SET_FUNC (symbolP, 0); 2341 ARM_SET_THUMB (symbolP, 0); 2342 ARM_SET_INTERWORK (symbolP, support_interwork); 2343 break; 2344 2345 case MAP_THUMB: 2346 THUMB_SET_FUNC (symbolP, 1); 2347 ARM_SET_THUMB (symbolP, 1); 2348 ARM_SET_INTERWORK (symbolP, support_interwork); 2349 break; 2350 2351 case MAP_DATA: 2352 default: 2353 return; 2354 } 2355} 2356#else 2357#define mapping_state(x) /* nothing */ 2358#endif 2359 2360/* Find the real, Thumb encoded start of a Thumb function. */ 2361 2362static symbolS * 2363find_real_start (symbolS * symbolP) 2364{ 2365 char * real_start; 2366 const char * name = S_GET_NAME (symbolP); 2367 symbolS * new_target; 2368 2369 /* This definition must agree with the one in gcc/config/arm/thumb.c. */ 2370#define STUB_NAME ".real_start_of" 2371 2372 if (name == NULL) 2373 abort (); 2374 2375 /* The compiler may generate BL instructions to local labels because 2376 it needs to perform a branch to a far away location. These labels 2377 do not have a corresponding ".real_start_of" label. We check 2378 both for S_IS_LOCAL and for a leading dot, to give a way to bypass 2379 the ".real_start_of" convention for nonlocal branches. */ 2380 if (S_IS_LOCAL (symbolP) || name[0] == '.') 2381 return symbolP; 2382 2383 real_start = ACONCAT ((STUB_NAME, name, NULL)); 2384 new_target = symbol_find (real_start); 2385 2386 if (new_target == NULL) 2387 { 2388 as_warn ("Failed to find real start of function: %s\n", name); 2389 new_target = symbolP; 2390 } 2391 2392 return new_target; 2393} 2394 2395static void 2396opcode_select (int width) 2397{ 2398 switch (width) 2399 { 2400 case 16: 2401 if (! thumb_mode) 2402 { 2403 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 2404 as_bad (_("selected processor does not support THUMB opcodes")); 2405 2406 thumb_mode = 1; 2407 /* No need to force the alignment, since we will have been 2408 coming from ARM mode, which is word-aligned. */ 2409 record_alignment (now_seg, 1); 2410 } 2411 mapping_state (MAP_THUMB); 2412 break; 2413 2414 case 32: 2415 if (thumb_mode) 2416 { 2417 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 2418 as_bad (_("selected processor does not support ARM opcodes")); 2419 2420 thumb_mode = 0; 2421 2422 if (!need_pass_2) 2423 frag_align (2, 0, 0); 2424 2425 record_alignment (now_seg, 1); 2426 } 2427 mapping_state (MAP_ARM); 2428 break; 2429 2430 default: 2431 as_bad (_("invalid instruction size selected (%d)"), width); 2432 } 2433} 2434 2435static void 2436s_arm (int ignore ATTRIBUTE_UNUSED) 2437{ 2438 opcode_select (32); 2439 demand_empty_rest_of_line (); 2440} 2441 2442static void 2443s_thumb (int ignore ATTRIBUTE_UNUSED) 2444{ 2445 opcode_select (16); 2446 demand_empty_rest_of_line (); 2447} 2448 2449static void 2450s_code (int unused ATTRIBUTE_UNUSED) 2451{ 2452 int temp; 2453 2454 temp = get_absolute_expression (); 2455 switch (temp) 2456 { 2457 case 16: 2458 case 32: 2459 opcode_select (temp); 2460 break; 2461 2462 default: 2463 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); 2464 } 2465} 2466 2467static void 2468s_force_thumb (int ignore ATTRIBUTE_UNUSED) 2469{ 2470 /* If we are not already in thumb mode go into it, EVEN if 2471 the target processor does not support thumb instructions. 2472 This is used by gcc/config/arm/lib1funcs.asm for example 2473 to compile interworking support functions even if the 2474 target processor should not support interworking. */ 2475 if (! thumb_mode) 2476 { 2477 thumb_mode = 2; 2478 record_alignment (now_seg, 1); 2479 } 2480 2481 demand_empty_rest_of_line (); 2482} 2483 2484static void 2485s_thumb_func (int ignore ATTRIBUTE_UNUSED) 2486{ 2487 s_thumb (0); 2488 2489 /* The following label is the name/address of the start of a Thumb function. 2490 We need to know this for the interworking support. */ 2491 label_is_thumb_function_name = TRUE; 2492} 2493 2494/* Perform a .set directive, but also mark the alias as 2495 being a thumb function. */ 2496 2497static void 2498s_thumb_set (int equiv) 2499{ 2500 /* XXX the following is a duplicate of the code for s_set() in read.c 2501 We cannot just call that code as we need to get at the symbol that 2502 is created. */ 2503 char * name; 2504 char delim; 2505 char * end_name; 2506 symbolS * symbolP; 2507 2508 /* Especial apologies for the random logic: 2509 This just grew, and could be parsed much more simply! 2510 Dean - in haste. */ 2511 name = input_line_pointer; 2512 delim = get_symbol_end (); 2513 end_name = input_line_pointer; 2514 *end_name = delim; 2515 2516 if (*input_line_pointer != ',') 2517 { 2518 *end_name = 0; 2519 as_bad (_("expected comma after name \"%s\""), name); 2520 *end_name = delim; 2521 ignore_rest_of_line (); 2522 return; 2523 } 2524 2525 input_line_pointer++; 2526 *end_name = 0; 2527 2528 if (name[0] == '.' && name[1] == '\0') 2529 { 2530 /* XXX - this should not happen to .thumb_set. */ 2531 abort (); 2532 } 2533 2534 if ((symbolP = symbol_find (name)) == NULL 2535 && (symbolP = md_undefined_symbol (name)) == NULL) 2536 { 2537#ifndef NO_LISTING 2538 /* When doing symbol listings, play games with dummy fragments living 2539 outside the normal fragment chain to record the file and line info 2540 for this symbol. */ 2541 if (listing & LISTING_SYMBOLS) 2542 { 2543 extern struct list_info_struct * listing_tail; 2544 fragS * dummy_frag = xmalloc (sizeof (fragS)); 2545 2546 memset (dummy_frag, 0, sizeof (fragS)); 2547 dummy_frag->fr_type = rs_fill; 2548 dummy_frag->line = listing_tail; 2549 symbolP = symbol_new (name, undefined_section, 0, dummy_frag); 2550 dummy_frag->fr_symbol = symbolP; 2551 } 2552 else 2553#endif 2554 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 2555 2556#ifdef OBJ_COFF 2557 /* "set" symbols are local unless otherwise specified. */ 2558 SF_SET_LOCAL (symbolP); 2559#endif /* OBJ_COFF */ 2560 } /* Make a new symbol. */ 2561 2562 symbol_table_insert (symbolP); 2563 2564 * end_name = delim; 2565 2566 if (equiv 2567 && S_IS_DEFINED (symbolP) 2568 && S_GET_SEGMENT (symbolP) != reg_section) 2569 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 2570 2571 pseudo_set (symbolP); 2572 2573 demand_empty_rest_of_line (); 2574 2575 /* XXX Now we come to the Thumb specific bit of code. */ 2576 2577 THUMB_SET_FUNC (symbolP, 1); 2578 ARM_SET_THUMB (symbolP, 1); 2579#if defined OBJ_ELF || defined OBJ_COFF 2580 ARM_SET_INTERWORK (symbolP, support_interwork); 2581#endif 2582} 2583 2584/* Directives: Mode selection. */ 2585 2586/* .syntax [unified|divided] - choose the new unified syntax 2587 (same for Arm and Thumb encoding, modulo slight differences in what 2588 can be represented) or the old divergent syntax for each mode. */ 2589static void 2590s_syntax (int unused ATTRIBUTE_UNUSED) 2591{ 2592 char *name, delim; 2593 2594 name = input_line_pointer; 2595 delim = get_symbol_end (); 2596 2597 if (!strcasecmp (name, "unified")) 2598 unified_syntax = TRUE; 2599 else if (!strcasecmp (name, "divided")) 2600 unified_syntax = FALSE; 2601 else 2602 { 2603 as_bad (_("unrecognized syntax mode \"%s\""), name); 2604 return; 2605 } 2606 *input_line_pointer = delim; 2607 demand_empty_rest_of_line (); 2608} 2609 2610/* Directives: sectioning and alignment. */ 2611 2612/* Same as s_align_ptwo but align 0 => align 2. */ 2613 2614static void 2615s_align (int unused ATTRIBUTE_UNUSED) 2616{ 2617 int temp; 2618 bfd_boolean fill_p; 2619 long temp_fill; 2620 long max_alignment = 15; 2621 2622 temp = get_absolute_expression (); 2623 if (temp > max_alignment) 2624 as_bad (_("alignment too large: %d assumed"), temp = max_alignment); 2625 else if (temp < 0) 2626 { 2627 as_bad (_("alignment negative. 0 assumed.")); 2628 temp = 0; 2629 } 2630 2631 if (*input_line_pointer == ',') 2632 { 2633 input_line_pointer++; 2634 temp_fill = get_absolute_expression (); 2635 fill_p = TRUE; 2636 } 2637 else 2638 { 2639 fill_p = FALSE; 2640 temp_fill = 0; 2641 } 2642 2643 if (!temp) 2644 temp = 2; 2645 2646 /* Only make a frag if we HAVE to. */ 2647 if (temp && !need_pass_2) 2648 { 2649 if (!fill_p && subseg_text_p (now_seg)) 2650 frag_align_code (temp, 0); 2651 else 2652 frag_align (temp, (int) temp_fill, 0); 2653 } 2654 demand_empty_rest_of_line (); 2655 2656 record_alignment (now_seg, temp); 2657} 2658 2659static void 2660s_bss (int ignore ATTRIBUTE_UNUSED) 2661{ 2662 /* We don't support putting frags in the BSS segment, we fake it by 2663 marking in_bss, then looking at s_skip for clues. */ 2664 subseg_set (bss_section, 0); 2665 demand_empty_rest_of_line (); 2666 mapping_state (MAP_DATA); 2667} 2668 2669static void 2670s_even (int ignore ATTRIBUTE_UNUSED) 2671{ 2672 /* Never make frag if expect extra pass. */ 2673 if (!need_pass_2) 2674 frag_align (1, 0, 0); 2675 2676 record_alignment (now_seg, 1); 2677 2678 demand_empty_rest_of_line (); 2679} 2680 2681/* Directives: Literal pools. */ 2682 2683static literal_pool * 2684find_literal_pool (void) 2685{ 2686 literal_pool * pool; 2687 2688 for (pool = list_of_pools; pool != NULL; pool = pool->next) 2689 { 2690 if (pool->section == now_seg 2691 && pool->sub_section == now_subseg) 2692 break; 2693 } 2694 2695 return pool; 2696} 2697 2698static literal_pool * 2699find_or_make_literal_pool (void) 2700{ 2701 /* Next literal pool ID number. */ 2702 static unsigned int latest_pool_num = 1; 2703 literal_pool * pool; 2704 2705 pool = find_literal_pool (); 2706 2707 if (pool == NULL) 2708 { 2709 /* Create a new pool. */ 2710 pool = xmalloc (sizeof (* pool)); 2711 if (! pool) 2712 return NULL; 2713 2714 pool->next_free_entry = 0; 2715 pool->section = now_seg; 2716 pool->sub_section = now_subseg; 2717 pool->next = list_of_pools; 2718 pool->symbol = NULL; 2719 2720 /* Add it to the list. */ 2721 list_of_pools = pool; 2722 } 2723 2724 /* New pools, and emptied pools, will have a NULL symbol. */ 2725 if (pool->symbol == NULL) 2726 { 2727 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, 2728 (valueT) 0, &zero_address_frag); 2729 pool->id = latest_pool_num ++; 2730 } 2731 2732 /* Done. */ 2733 return pool; 2734} 2735 2736/* Add the literal in the global 'inst' 2737 structure to the relevent literal pool. */ 2738 2739static int 2740add_to_lit_pool (void) 2741{ 2742 literal_pool * pool; 2743 unsigned int entry; 2744 2745 pool = find_or_make_literal_pool (); 2746 2747 /* Check if this literal value is already in the pool. */ 2748 for (entry = 0; entry < pool->next_free_entry; entry ++) 2749 { 2750 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2751 && (inst.reloc.exp.X_op == O_constant) 2752 && (pool->literals[entry].X_add_number 2753 == inst.reloc.exp.X_add_number) 2754 && (pool->literals[entry].X_unsigned 2755 == inst.reloc.exp.X_unsigned)) 2756 break; 2757 2758 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2759 && (inst.reloc.exp.X_op == O_symbol) 2760 && (pool->literals[entry].X_add_number 2761 == inst.reloc.exp.X_add_number) 2762 && (pool->literals[entry].X_add_symbol 2763 == inst.reloc.exp.X_add_symbol) 2764 && (pool->literals[entry].X_op_symbol 2765 == inst.reloc.exp.X_op_symbol)) 2766 break; 2767 } 2768 2769 /* Do we need to create a new entry? */ 2770 if (entry == pool->next_free_entry) 2771 { 2772 if (entry >= MAX_LITERAL_POOL_SIZE) 2773 { 2774 inst.error = _("literal pool overflow"); 2775 return FAIL; 2776 } 2777 2778 pool->literals[entry] = inst.reloc.exp; 2779 pool->next_free_entry += 1; 2780 } 2781 2782 inst.reloc.exp.X_op = O_symbol; 2783 inst.reloc.exp.X_add_number = ((int) entry) * 4; 2784 inst.reloc.exp.X_add_symbol = pool->symbol; 2785 2786 return SUCCESS; 2787} 2788 2789/* Can't use symbol_new here, so have to create a symbol and then at 2790 a later date assign it a value. Thats what these functions do. */ 2791 2792static void 2793symbol_locate (symbolS * symbolP, 2794 const char * name, /* It is copied, the caller can modify. */ 2795 segT segment, /* Segment identifier (SEG_<something>). */ 2796 valueT valu, /* Symbol value. */ 2797 fragS * frag) /* Associated fragment. */ 2798{ 2799 unsigned int name_length; 2800 char * preserved_copy_of_name; 2801 2802 name_length = strlen (name) + 1; /* +1 for \0. */ 2803 obstack_grow (¬es, name, name_length); 2804 preserved_copy_of_name = obstack_finish (¬es); 2805 2806#ifdef tc_canonicalize_symbol_name 2807 preserved_copy_of_name = 2808 tc_canonicalize_symbol_name (preserved_copy_of_name); 2809#endif 2810 2811 S_SET_NAME (symbolP, preserved_copy_of_name); 2812 2813 S_SET_SEGMENT (symbolP, segment); 2814 S_SET_VALUE (symbolP, valu); 2815 symbol_clear_list_pointers (symbolP); 2816 2817 symbol_set_frag (symbolP, frag); 2818 2819 /* Link to end of symbol chain. */ 2820 { 2821 extern int symbol_table_frozen; 2822 2823 if (symbol_table_frozen) 2824 abort (); 2825 } 2826 2827 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); 2828 2829 obj_symbol_new_hook (symbolP); 2830 2831#ifdef tc_symbol_new_hook 2832 tc_symbol_new_hook (symbolP); 2833#endif 2834 2835#ifdef DEBUG_SYMS 2836 verify_symbol_chain (symbol_rootP, symbol_lastP); 2837#endif /* DEBUG_SYMS */ 2838} 2839 2840 2841static void 2842s_ltorg (int ignored ATTRIBUTE_UNUSED) 2843{ 2844 unsigned int entry; 2845 literal_pool * pool; 2846 char sym_name[20]; 2847 2848 pool = find_literal_pool (); 2849 if (pool == NULL 2850 || pool->symbol == NULL 2851 || pool->next_free_entry == 0) 2852 return; 2853 2854 mapping_state (MAP_DATA); 2855 2856 /* Align pool as you have word accesses. 2857 Only make a frag if we have to. */ 2858 if (!need_pass_2) 2859 frag_align (2, 0, 0); 2860 2861 record_alignment (now_seg, 2); 2862 2863 sprintf (sym_name, "$$lit_\002%x", pool->id); 2864 2865 symbol_locate (pool->symbol, sym_name, now_seg, 2866 (valueT) frag_now_fix (), frag_now); 2867 symbol_table_insert (pool->symbol); 2868 2869 ARM_SET_THUMB (pool->symbol, thumb_mode); 2870 2871#if defined OBJ_COFF || defined OBJ_ELF 2872 ARM_SET_INTERWORK (pool->symbol, support_interwork); 2873#endif 2874 2875 for (entry = 0; entry < pool->next_free_entry; entry ++) 2876 /* First output the expression in the instruction to the pool. */ 2877 emit_expr (&(pool->literals[entry]), 4); /* .word */ 2878 2879 /* Mark the pool as empty. */ 2880 pool->next_free_entry = 0; 2881 pool->symbol = NULL; 2882} 2883 2884#ifdef OBJ_ELF 2885/* Forward declarations for functions below, in the MD interface 2886 section. */ 2887static void fix_new_arm (fragS *, int, short, expressionS *, int, int); 2888static valueT create_unwind_entry (int); 2889static void start_unwind_section (const segT, int); 2890static void add_unwind_opcode (valueT, int); 2891static void flush_pending_unwind (void); 2892 2893/* Directives: Data. */ 2894 2895static void 2896s_arm_elf_cons (int nbytes) 2897{ 2898 expressionS exp; 2899 2900#ifdef md_flush_pending_output 2901 md_flush_pending_output (); 2902#endif 2903 2904 if (is_it_end_of_statement ()) 2905 { 2906 demand_empty_rest_of_line (); 2907 return; 2908 } 2909 2910#ifdef md_cons_align 2911 md_cons_align (nbytes); 2912#endif 2913 2914 mapping_state (MAP_DATA); 2915 do 2916 { 2917 int reloc; 2918 char *base = input_line_pointer; 2919 2920 expression (& exp); 2921 2922 if (exp.X_op != O_symbol) 2923 emit_expr (&exp, (unsigned int) nbytes); 2924 else 2925 { 2926 char *before_reloc = input_line_pointer; 2927 reloc = parse_reloc (&input_line_pointer); 2928 if (reloc == -1) 2929 { 2930 as_bad (_("unrecognized relocation suffix")); 2931 ignore_rest_of_line (); 2932 return; 2933 } 2934 else if (reloc == BFD_RELOC_UNUSED) 2935 emit_expr (&exp, (unsigned int) nbytes); 2936 else 2937 { 2938 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); 2939 int size = bfd_get_reloc_size (howto); 2940 2941 if (reloc == BFD_RELOC_ARM_PLT32) 2942 { 2943 as_bad (_("(plt) is only valid on branch targets")); 2944 reloc = BFD_RELOC_UNUSED; 2945 size = 0; 2946 } 2947 2948 if (size > nbytes) 2949 as_bad (_("%s relocations do not fit in %d bytes"), 2950 howto->name, nbytes); 2951 else 2952 { 2953 /* We've parsed an expression stopping at O_symbol. 2954 But there may be more expression left now that we 2955 have parsed the relocation marker. Parse it again. 2956 XXX Surely there is a cleaner way to do this. */ 2957 char *p = input_line_pointer; 2958 int offset; 2959 char *save_buf = alloca (input_line_pointer - base); 2960 memcpy (save_buf, base, input_line_pointer - base); 2961 memmove (base + (input_line_pointer - before_reloc), 2962 base, before_reloc - base); 2963 2964 input_line_pointer = base + (input_line_pointer-before_reloc); 2965 expression (&exp); 2966 memcpy (base, save_buf, p - base); 2967 2968 offset = nbytes - size; 2969 p = frag_more ((int) nbytes); 2970 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, 2971 size, &exp, 0, reloc); 2972 } 2973 } 2974 } 2975 } 2976 while (*input_line_pointer++ == ','); 2977 2978 /* Put terminator back into stream. */ 2979 input_line_pointer --; 2980 demand_empty_rest_of_line (); 2981} 2982 2983 2984/* Parse a .rel31 directive. */ 2985 2986static void 2987s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) 2988{ 2989 expressionS exp; 2990 char *p; 2991 valueT highbit; 2992 2993 highbit = 0; 2994 if (*input_line_pointer == '1') 2995 highbit = 0x80000000; 2996 else if (*input_line_pointer != '0') 2997 as_bad (_("expected 0 or 1")); 2998 2999 input_line_pointer++; 3000 if (*input_line_pointer != ',') 3001 as_bad (_("missing comma")); 3002 input_line_pointer++; 3003 3004#ifdef md_flush_pending_output 3005 md_flush_pending_output (); 3006#endif 3007 3008#ifdef md_cons_align 3009 md_cons_align (4); 3010#endif 3011 3012 mapping_state (MAP_DATA); 3013 3014 expression (&exp); 3015 3016 p = frag_more (4); 3017 md_number_to_chars (p, highbit, 4); 3018 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, 3019 BFD_RELOC_ARM_PREL31); 3020 3021 demand_empty_rest_of_line (); 3022} 3023 3024/* Directives: AEABI stack-unwind tables. */ 3025 3026/* Parse an unwind_fnstart directive. Simply records the current location. */ 3027 3028static void 3029s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) 3030{ 3031 demand_empty_rest_of_line (); 3032 /* Mark the start of the function. */ 3033 unwind.proc_start = expr_build_dot (); 3034 3035 /* Reset the rest of the unwind info. */ 3036 unwind.opcode_count = 0; 3037 unwind.table_entry = NULL; 3038 unwind.personality_routine = NULL; 3039 unwind.personality_index = -1; 3040 unwind.frame_size = 0; 3041 unwind.fp_offset = 0; 3042 unwind.fp_reg = 13; 3043 unwind.fp_used = 0; 3044 unwind.sp_restored = 0; 3045} 3046 3047 3048/* Parse a handlerdata directive. Creates the exception handling table entry 3049 for the function. */ 3050 3051static void 3052s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) 3053{ 3054 demand_empty_rest_of_line (); 3055 if (unwind.table_entry) 3056 as_bad (_("dupicate .handlerdata directive")); 3057 3058 create_unwind_entry (1); 3059} 3060 3061/* Parse an unwind_fnend directive. Generates the index table entry. */ 3062 3063static void 3064s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) 3065{ 3066 long where; 3067 char *ptr; 3068 valueT val; 3069 3070 demand_empty_rest_of_line (); 3071 3072 /* Add eh table entry. */ 3073 if (unwind.table_entry == NULL) 3074 val = create_unwind_entry (0); 3075 else 3076 val = 0; 3077 3078 /* Add index table entry. This is two words. */ 3079 start_unwind_section (unwind.saved_seg, 1); 3080 frag_align (2, 0, 0); 3081 record_alignment (now_seg, 2); 3082 3083 ptr = frag_more (8); 3084 memset(ptr, 0, 8); 3085 where = frag_now_fix () - 8; 3086 3087 /* Self relative offset of the function start. */ 3088 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, 3089 BFD_RELOC_ARM_PREL31); 3090 3091 /* Indicate dependency on EHABI-defined personality routines to the 3092 linker, if it hasn't been done already. */ 3093 if (unwind.personality_index >= 0 && unwind.personality_index < 3 3094 && !(marked_pr_dependency & (1 << unwind.personality_index))) 3095 { 3096 static const char *const name[] = { 3097 "__aeabi_unwind_cpp_pr0", 3098 "__aeabi_unwind_cpp_pr1", 3099 "__aeabi_unwind_cpp_pr2" 3100 }; 3101 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); 3102 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); 3103 marked_pr_dependency |= 1 << unwind.personality_index; 3104 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency 3105 = marked_pr_dependency; 3106 } 3107 3108 if (val) 3109 /* Inline exception table entry. */ 3110 md_number_to_chars (ptr + 4, val, 4); 3111 else 3112 /* Self relative offset of the table entry. */ 3113 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, 3114 BFD_RELOC_ARM_PREL31); 3115 3116 /* Restore the original section. */ 3117 subseg_set (unwind.saved_seg, unwind.saved_subseg); 3118} 3119 3120 3121/* Parse an unwind_cantunwind directive. */ 3122 3123static void 3124s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) 3125{ 3126 demand_empty_rest_of_line (); 3127 if (unwind.personality_routine || unwind.personality_index != -1) 3128 as_bad (_("personality routine specified for cantunwind frame")); 3129 3130 unwind.personality_index = -2; 3131} 3132 3133 3134/* Parse a personalityindex directive. */ 3135 3136static void 3137s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) 3138{ 3139 expressionS exp; 3140 3141 if (unwind.personality_routine || unwind.personality_index != -1) 3142 as_bad (_("duplicate .personalityindex directive")); 3143 3144 expression (&exp); 3145 3146 if (exp.X_op != O_constant 3147 || exp.X_add_number < 0 || exp.X_add_number > 15) 3148 { 3149 as_bad (_("bad personality routine number")); 3150 ignore_rest_of_line (); 3151 return; 3152 } 3153 3154 unwind.personality_index = exp.X_add_number; 3155 3156 demand_empty_rest_of_line (); 3157} 3158 3159 3160/* Parse a personality directive. */ 3161 3162static void 3163s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) 3164{ 3165 char *name, *p, c; 3166 3167 if (unwind.personality_routine || unwind.personality_index != -1) 3168 as_bad (_("duplicate .personality directive")); 3169 3170 name = input_line_pointer; 3171 c = get_symbol_end (); 3172 p = input_line_pointer; 3173 unwind.personality_routine = symbol_find_or_make (name); 3174 *p = c; 3175 demand_empty_rest_of_line (); 3176} 3177 3178 3179/* Parse a directive saving core registers. */ 3180 3181static void 3182s_arm_unwind_save_core (void) 3183{ 3184 valueT op; 3185 long range; 3186 int n; 3187 3188 range = parse_reg_list (&input_line_pointer); 3189 if (range == FAIL) 3190 { 3191 as_bad (_("expected register list")); 3192 ignore_rest_of_line (); 3193 return; 3194 } 3195 3196 demand_empty_rest_of_line (); 3197 3198 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} 3199 into .unwind_save {..., sp...}. We aren't bothered about the value of 3200 ip because it is clobbered by calls. */ 3201 if (unwind.sp_restored && unwind.fp_reg == 12 3202 && (range & 0x3000) == 0x1000) 3203 { 3204 unwind.opcode_count--; 3205 unwind.sp_restored = 0; 3206 range = (range | 0x2000) & ~0x1000; 3207 unwind.pending_offset = 0; 3208 } 3209 3210 /* Pop r4-r15. */ 3211 if (range & 0xfff0) 3212 { 3213 /* See if we can use the short opcodes. These pop a block of up to 8 3214 registers starting with r4, plus maybe r14. */ 3215 for (n = 0; n < 8; n++) 3216 { 3217 /* Break at the first non-saved register. */ 3218 if ((range & (1 << (n + 4))) == 0) 3219 break; 3220 } 3221 /* See if there are any other bits set. */ 3222 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) 3223 { 3224 /* Use the long form. */ 3225 op = 0x8000 | ((range >> 4) & 0xfff); 3226 add_unwind_opcode (op, 2); 3227 } 3228 else 3229 { 3230 /* Use the short form. */ 3231 if (range & 0x4000) 3232 op = 0xa8; /* Pop r14. */ 3233 else 3234 op = 0xa0; /* Do not pop r14. */ 3235 op |= (n - 1); 3236 add_unwind_opcode (op, 1); 3237 } 3238 } 3239 3240 /* Pop r0-r3. */ 3241 if (range & 0xf) 3242 { 3243 op = 0xb100 | (range & 0xf); 3244 add_unwind_opcode (op, 2); 3245 } 3246 3247 /* Record the number of bytes pushed. */ 3248 for (n = 0; n < 16; n++) 3249 { 3250 if (range & (1 << n)) 3251 unwind.frame_size += 4; 3252 } 3253} 3254 3255 3256/* Parse a directive saving FPA registers. */ 3257 3258static void 3259s_arm_unwind_save_fpa (int reg) 3260{ 3261 expressionS exp; 3262 int num_regs; 3263 valueT op; 3264 3265 /* Get Number of registers to transfer. */ 3266 if (skip_past_comma (&input_line_pointer) != FAIL) 3267 expression (&exp); 3268 else 3269 exp.X_op = O_illegal; 3270 3271 if (exp.X_op != O_constant) 3272 { 3273 as_bad (_("expected , <constant>")); 3274 ignore_rest_of_line (); 3275 return; 3276 } 3277 3278 num_regs = exp.X_add_number; 3279 3280 if (num_regs < 1 || num_regs > 4) 3281 { 3282 as_bad (_("number of registers must be in the range [1:4]")); 3283 ignore_rest_of_line (); 3284 return; 3285 } 3286 3287 demand_empty_rest_of_line (); 3288 3289 if (reg == 4) 3290 { 3291 /* Short form. */ 3292 op = 0xb4 | (num_regs - 1); 3293 add_unwind_opcode (op, 1); 3294 } 3295 else 3296 { 3297 /* Long form. */ 3298 op = 0xc800 | (reg << 4) | (num_regs - 1); 3299 add_unwind_opcode (op, 2); 3300 } 3301 unwind.frame_size += num_regs * 12; 3302} 3303 3304 3305/* Parse a directive saving VFP registers for ARMv6 and above. */ 3306 3307static void 3308s_arm_unwind_save_vfp_armv6 (void) 3309{ 3310 int count; 3311 unsigned int start; 3312 valueT op; 3313 int num_vfpv3_regs = 0; 3314 int num_regs_below_16; 3315 3316 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); 3317 if (count == FAIL) 3318 { 3319 as_bad (_("expected register list")); 3320 ignore_rest_of_line (); 3321 return; 3322 } 3323 3324 demand_empty_rest_of_line (); 3325 3326 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather 3327 than FSTMX/FLDMX-style ones). */ 3328 3329 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ 3330 if (start >= 16) 3331 num_vfpv3_regs = count; 3332 else if (start + count > 16) 3333 num_vfpv3_regs = start + count - 16; 3334 3335 if (num_vfpv3_regs > 0) 3336 { 3337 int start_offset = start > 16 ? start - 16 : 0; 3338 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); 3339 add_unwind_opcode (op, 2); 3340 } 3341 3342 /* Generate opcode for registers numbered in the range 0 .. 15. */ 3343 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; 3344 assert (num_regs_below_16 + num_vfpv3_regs == count); 3345 if (num_regs_below_16 > 0) 3346 { 3347 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); 3348 add_unwind_opcode (op, 2); 3349 } 3350 3351 unwind.frame_size += count * 8; 3352} 3353 3354 3355/* Parse a directive saving VFP registers for pre-ARMv6. */ 3356 3357static void 3358s_arm_unwind_save_vfp (void) 3359{ 3360 int count; 3361 unsigned int reg; 3362 valueT op; 3363 3364 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); 3365 if (count == FAIL) 3366 { 3367 as_bad (_("expected register list")); 3368 ignore_rest_of_line (); 3369 return; 3370 } 3371 3372 demand_empty_rest_of_line (); 3373 3374 if (reg == 8) 3375 { 3376 /* Short form. */ 3377 op = 0xb8 | (count - 1); 3378 add_unwind_opcode (op, 1); 3379 } 3380 else 3381 { 3382 /* Long form. */ 3383 op = 0xb300 | (reg << 4) | (count - 1); 3384 add_unwind_opcode (op, 2); 3385 } 3386 unwind.frame_size += count * 8 + 4; 3387} 3388 3389 3390/* Parse a directive saving iWMMXt data registers. */ 3391 3392static void 3393s_arm_unwind_save_mmxwr (void) 3394{ 3395 int reg; 3396 int hi_reg; 3397 int i; 3398 unsigned mask = 0; 3399 valueT op; 3400 3401 if (*input_line_pointer == '{') 3402 input_line_pointer++; 3403 3404 do 3405 { 3406 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3407 3408 if (reg == FAIL) 3409 { 3410 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3411 goto error; 3412 } 3413 3414 if (mask >> reg) 3415 as_tsktsk (_("register list not in ascending order")); 3416 mask |= 1 << reg; 3417 3418 if (*input_line_pointer == '-') 3419 { 3420 input_line_pointer++; 3421 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3422 if (hi_reg == FAIL) 3423 { 3424 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3425 goto error; 3426 } 3427 else if (reg >= hi_reg) 3428 { 3429 as_bad (_("bad register range")); 3430 goto error; 3431 } 3432 for (; reg < hi_reg; reg++) 3433 mask |= 1 << reg; 3434 } 3435 } 3436 while (skip_past_comma (&input_line_pointer) != FAIL); 3437 3438 if (*input_line_pointer == '}') 3439 input_line_pointer++; 3440 3441 demand_empty_rest_of_line (); 3442 3443 /* Generate any deferred opcodes because we're going to be looking at 3444 the list. */ 3445 flush_pending_unwind (); 3446 3447 for (i = 0; i < 16; i++) 3448 { 3449 if (mask & (1 << i)) 3450 unwind.frame_size += 8; 3451 } 3452 3453 /* Attempt to combine with a previous opcode. We do this because gcc 3454 likes to output separate unwind directives for a single block of 3455 registers. */ 3456 if (unwind.opcode_count > 0) 3457 { 3458 i = unwind.opcodes[unwind.opcode_count - 1]; 3459 if ((i & 0xf8) == 0xc0) 3460 { 3461 i &= 7; 3462 /* Only merge if the blocks are contiguous. */ 3463 if (i < 6) 3464 { 3465 if ((mask & 0xfe00) == (1 << 9)) 3466 { 3467 mask |= ((1 << (i + 11)) - 1) & 0xfc00; 3468 unwind.opcode_count--; 3469 } 3470 } 3471 else if (i == 6 && unwind.opcode_count >= 2) 3472 { 3473 i = unwind.opcodes[unwind.opcode_count - 2]; 3474 reg = i >> 4; 3475 i &= 0xf; 3476 3477 op = 0xffff << (reg - 1); 3478 if (reg > 0 3479 && ((mask & op) == (1u << (reg - 1)))) 3480 { 3481 op = (1 << (reg + i + 1)) - 1; 3482 op &= ~((1 << reg) - 1); 3483 mask |= op; 3484 unwind.opcode_count -= 2; 3485 } 3486 } 3487 } 3488 } 3489 3490 hi_reg = 15; 3491 /* We want to generate opcodes in the order the registers have been 3492 saved, ie. descending order. */ 3493 for (reg = 15; reg >= -1; reg--) 3494 { 3495 /* Save registers in blocks. */ 3496 if (reg < 0 3497 || !(mask & (1 << reg))) 3498 { 3499 /* We found an unsaved reg. Generate opcodes to save the 3500 preceeding block. */ 3501 if (reg != hi_reg) 3502 { 3503 if (reg == 9) 3504 { 3505 /* Short form. */ 3506 op = 0xc0 | (hi_reg - 10); 3507 add_unwind_opcode (op, 1); 3508 } 3509 else 3510 { 3511 /* Long form. */ 3512 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); 3513 add_unwind_opcode (op, 2); 3514 } 3515 } 3516 hi_reg = reg - 1; 3517 } 3518 } 3519 3520 return; 3521error: 3522 ignore_rest_of_line (); 3523} 3524 3525static void 3526s_arm_unwind_save_mmxwcg (void) 3527{ 3528 int reg; 3529 int hi_reg; 3530 unsigned mask = 0; 3531 valueT op; 3532 3533 if (*input_line_pointer == '{') 3534 input_line_pointer++; 3535 3536 do 3537 { 3538 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3539 3540 if (reg == FAIL) 3541 { 3542 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3543 goto error; 3544 } 3545 3546 reg -= 8; 3547 if (mask >> reg) 3548 as_tsktsk (_("register list not in ascending order")); 3549 mask |= 1 << reg; 3550 3551 if (*input_line_pointer == '-') 3552 { 3553 input_line_pointer++; 3554 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3555 if (hi_reg == FAIL) 3556 { 3557 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3558 goto error; 3559 } 3560 else if (reg >= hi_reg) 3561 { 3562 as_bad (_("bad register range")); 3563 goto error; 3564 } 3565 for (; reg < hi_reg; reg++) 3566 mask |= 1 << reg; 3567 } 3568 } 3569 while (skip_past_comma (&input_line_pointer) != FAIL); 3570 3571 if (*input_line_pointer == '}') 3572 input_line_pointer++; 3573 3574 demand_empty_rest_of_line (); 3575 3576 /* Generate any deferred opcodes because we're going to be looking at 3577 the list. */ 3578 flush_pending_unwind (); 3579 3580 for (reg = 0; reg < 16; reg++) 3581 { 3582 if (mask & (1 << reg)) 3583 unwind.frame_size += 4; 3584 } 3585 op = 0xc700 | mask; 3586 add_unwind_opcode (op, 2); 3587 return; 3588error: 3589 ignore_rest_of_line (); 3590} 3591 3592 3593/* Parse an unwind_save directive. 3594 If the argument is non-zero, this is a .vsave directive. */ 3595 3596static void 3597s_arm_unwind_save (int arch_v6) 3598{ 3599 char *peek; 3600 struct reg_entry *reg; 3601 bfd_boolean had_brace = FALSE; 3602 3603 /* Figure out what sort of save we have. */ 3604 peek = input_line_pointer; 3605 3606 if (*peek == '{') 3607 { 3608 had_brace = TRUE; 3609 peek++; 3610 } 3611 3612 reg = arm_reg_parse_multi (&peek); 3613 3614 if (!reg) 3615 { 3616 as_bad (_("register expected")); 3617 ignore_rest_of_line (); 3618 return; 3619 } 3620 3621 switch (reg->type) 3622 { 3623 case REG_TYPE_FN: 3624 if (had_brace) 3625 { 3626 as_bad (_("FPA .unwind_save does not take a register list")); 3627 ignore_rest_of_line (); 3628 return; 3629 } 3630 s_arm_unwind_save_fpa (reg->number); 3631 return; 3632 3633 case REG_TYPE_RN: s_arm_unwind_save_core (); return; 3634 case REG_TYPE_VFD: 3635 if (arch_v6) 3636 s_arm_unwind_save_vfp_armv6 (); 3637 else 3638 s_arm_unwind_save_vfp (); 3639 return; 3640 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; 3641 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; 3642 3643 default: 3644 as_bad (_(".unwind_save does not support this kind of register")); 3645 ignore_rest_of_line (); 3646 } 3647} 3648 3649 3650/* Parse an unwind_movsp directive. */ 3651 3652static void 3653s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) 3654{ 3655 int reg; 3656 valueT op; 3657 int offset; 3658 3659 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3660 if (reg == FAIL) 3661 { 3662 as_bad (_(reg_expected_msgs[REG_TYPE_RN])); 3663 ignore_rest_of_line (); 3664 return; 3665 } 3666 3667 /* Optional constant. */ 3668 if (skip_past_comma (&input_line_pointer) != FAIL) 3669 { 3670 if (immediate_for_directive (&offset) == FAIL) 3671 return; 3672 } 3673 else 3674 offset = 0; 3675 3676 demand_empty_rest_of_line (); 3677 3678 if (reg == REG_SP || reg == REG_PC) 3679 { 3680 as_bad (_("SP and PC not permitted in .unwind_movsp directive")); 3681 return; 3682 } 3683 3684 if (unwind.fp_reg != REG_SP) 3685 as_bad (_("unexpected .unwind_movsp directive")); 3686 3687 /* Generate opcode to restore the value. */ 3688 op = 0x90 | reg; 3689 add_unwind_opcode (op, 1); 3690 3691 /* Record the information for later. */ 3692 unwind.fp_reg = reg; 3693 unwind.fp_offset = unwind.frame_size - offset; 3694 unwind.sp_restored = 1; 3695} 3696 3697/* Parse an unwind_pad directive. */ 3698 3699static void 3700s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) 3701{ 3702 int offset; 3703 3704 if (immediate_for_directive (&offset) == FAIL) 3705 return; 3706 3707 if (offset & 3) 3708 { 3709 as_bad (_("stack increment must be multiple of 4")); 3710 ignore_rest_of_line (); 3711 return; 3712 } 3713 3714 /* Don't generate any opcodes, just record the details for later. */ 3715 unwind.frame_size += offset; 3716 unwind.pending_offset += offset; 3717 3718 demand_empty_rest_of_line (); 3719} 3720 3721/* Parse an unwind_setfp directive. */ 3722 3723static void 3724s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) 3725{ 3726 int sp_reg; 3727 int fp_reg; 3728 int offset; 3729 3730 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3731 if (skip_past_comma (&input_line_pointer) == FAIL) 3732 sp_reg = FAIL; 3733 else 3734 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3735 3736 if (fp_reg == FAIL || sp_reg == FAIL) 3737 { 3738 as_bad (_("expected <reg>, <reg>")); 3739 ignore_rest_of_line (); 3740 return; 3741 } 3742 3743 /* Optional constant. */ 3744 if (skip_past_comma (&input_line_pointer) != FAIL) 3745 { 3746 if (immediate_for_directive (&offset) == FAIL) 3747 return; 3748 } 3749 else 3750 offset = 0; 3751 3752 demand_empty_rest_of_line (); 3753 3754 if (sp_reg != 13 && sp_reg != unwind.fp_reg) 3755 { 3756 as_bad (_("register must be either sp or set by a previous" 3757 "unwind_movsp directive")); 3758 return; 3759 } 3760 3761 /* Don't generate any opcodes, just record the information for later. */ 3762 unwind.fp_reg = fp_reg; 3763 unwind.fp_used = 1; 3764 if (sp_reg == 13) 3765 unwind.fp_offset = unwind.frame_size - offset; 3766 else 3767 unwind.fp_offset -= offset; 3768} 3769 3770/* Parse an unwind_raw directive. */ 3771 3772static void 3773s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) 3774{ 3775 expressionS exp; 3776 /* This is an arbitrary limit. */ 3777 unsigned char op[16]; 3778 int count; 3779 3780 expression (&exp); 3781 if (exp.X_op == O_constant 3782 && skip_past_comma (&input_line_pointer) != FAIL) 3783 { 3784 unwind.frame_size += exp.X_add_number; 3785 expression (&exp); 3786 } 3787 else 3788 exp.X_op = O_illegal; 3789 3790 if (exp.X_op != O_constant) 3791 { 3792 as_bad (_("expected <offset>, <opcode>")); 3793 ignore_rest_of_line (); 3794 return; 3795 } 3796 3797 count = 0; 3798 3799 /* Parse the opcode. */ 3800 for (;;) 3801 { 3802 if (count >= 16) 3803 { 3804 as_bad (_("unwind opcode too long")); 3805 ignore_rest_of_line (); 3806 } 3807 if (exp.X_op != O_constant || exp.X_add_number & ~0xff) 3808 { 3809 as_bad (_("invalid unwind opcode")); 3810 ignore_rest_of_line (); 3811 return; 3812 } 3813 op[count++] = exp.X_add_number; 3814 3815 /* Parse the next byte. */ 3816 if (skip_past_comma (&input_line_pointer) == FAIL) 3817 break; 3818 3819 expression (&exp); 3820 } 3821 3822 /* Add the opcode bytes in reverse order. */ 3823 while (count--) 3824 add_unwind_opcode (op[count], 1); 3825 3826 demand_empty_rest_of_line (); 3827} 3828 3829 3830/* Parse a .eabi_attribute directive. */ 3831 3832static void 3833s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) 3834{ 3835 s_vendor_attribute (OBJ_ATTR_PROC); 3836} 3837#endif /* OBJ_ELF */ 3838 3839static void s_arm_arch (int); 3840static void s_arm_object_arch (int); 3841static void s_arm_cpu (int); 3842static void s_arm_fpu (int); 3843 3844#ifdef TE_PE 3845 3846static void 3847pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 3848{ 3849 expressionS exp; 3850 3851 do 3852 { 3853 expression (&exp); 3854 if (exp.X_op == O_symbol) 3855 exp.X_op = O_secrel; 3856 3857 emit_expr (&exp, 4); 3858 } 3859 while (*input_line_pointer++ == ','); 3860 3861 input_line_pointer--; 3862 demand_empty_rest_of_line (); 3863} 3864#endif /* TE_PE */ 3865 3866/* This table describes all the machine specific pseudo-ops the assembler 3867 has to support. The fields are: 3868 pseudo-op name without dot 3869 function to call to execute this pseudo-op 3870 Integer arg to pass to the function. */ 3871 3872const pseudo_typeS md_pseudo_table[] = 3873{ 3874 /* Never called because '.req' does not start a line. */ 3875 { "req", s_req, 0 }, 3876 /* Following two are likewise never called. */ 3877 { "dn", s_dn, 0 }, 3878 { "qn", s_qn, 0 }, 3879 { "unreq", s_unreq, 0 }, 3880 { "bss", s_bss, 0 }, 3881 { "align", s_align, 0 }, 3882 { "arm", s_arm, 0 }, 3883 { "thumb", s_thumb, 0 }, 3884 { "code", s_code, 0 }, 3885 { "force_thumb", s_force_thumb, 0 }, 3886 { "thumb_func", s_thumb_func, 0 }, 3887 { "thumb_set", s_thumb_set, 0 }, 3888 { "even", s_even, 0 }, 3889 { "ltorg", s_ltorg, 0 }, 3890 { "pool", s_ltorg, 0 }, 3891 { "syntax", s_syntax, 0 }, 3892 { "cpu", s_arm_cpu, 0 }, 3893 { "arch", s_arm_arch, 0 }, 3894 { "object_arch", s_arm_object_arch, 0 }, 3895 { "fpu", s_arm_fpu, 0 }, 3896#ifdef OBJ_ELF 3897 { "word", s_arm_elf_cons, 4 }, 3898 { "long", s_arm_elf_cons, 4 }, 3899 { "rel31", s_arm_rel31, 0 }, 3900 { "fnstart", s_arm_unwind_fnstart, 0 }, 3901 { "fnend", s_arm_unwind_fnend, 0 }, 3902 { "cantunwind", s_arm_unwind_cantunwind, 0 }, 3903 { "personality", s_arm_unwind_personality, 0 }, 3904 { "personalityindex", s_arm_unwind_personalityindex, 0 }, 3905 { "handlerdata", s_arm_unwind_handlerdata, 0 }, 3906 { "save", s_arm_unwind_save, 0 }, 3907 { "vsave", s_arm_unwind_save, 1 }, 3908 { "movsp", s_arm_unwind_movsp, 0 }, 3909 { "pad", s_arm_unwind_pad, 0 }, 3910 { "setfp", s_arm_unwind_setfp, 0 }, 3911 { "unwind_raw", s_arm_unwind_raw, 0 }, 3912 { "eabi_attribute", s_arm_eabi_attribute, 0 }, 3913#else 3914 { "word", cons, 4}, 3915 3916 /* These are used for dwarf. */ 3917 {"2byte", cons, 2}, 3918 {"4byte", cons, 4}, 3919 {"8byte", cons, 8}, 3920 /* These are used for dwarf2. */ 3921 { "file", (void (*) (int)) dwarf2_directive_file, 0 }, 3922 { "loc", dwarf2_directive_loc, 0 }, 3923 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, 3924#endif 3925 { "extend", float_cons, 'x' }, 3926 { "ldouble", float_cons, 'x' }, 3927 { "packed", float_cons, 'p' }, 3928#ifdef TE_PE 3929 {"secrel32", pe_directive_secrel, 0}, 3930#endif 3931 { 0, 0, 0 } 3932}; 3933 3934/* Parser functions used exclusively in instruction operands. */ 3935 3936/* Generic immediate-value read function for use in insn parsing. 3937 STR points to the beginning of the immediate (the leading #); 3938 VAL receives the value; if the value is outside [MIN, MAX] 3939 issue an error. PREFIX_OPT is true if the immediate prefix is 3940 optional. */ 3941 3942static int 3943parse_immediate (char **str, int *val, int min, int max, 3944 bfd_boolean prefix_opt) 3945{ 3946 expressionS exp; 3947 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); 3948 if (exp.X_op != O_constant) 3949 { 3950 inst.error = _("constant expression required"); 3951 return FAIL; 3952 } 3953 3954 if (exp.X_add_number < min || exp.X_add_number > max) 3955 { 3956 inst.error = _("immediate value out of range"); 3957 return FAIL; 3958 } 3959 3960 *val = exp.X_add_number; 3961 return SUCCESS; 3962} 3963 3964/* Less-generic immediate-value read function with the possibility of loading a 3965 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate 3966 instructions. Puts the result directly in inst.operands[i]. */ 3967 3968static int 3969parse_big_immediate (char **str, int i) 3970{ 3971 expressionS exp; 3972 char *ptr = *str; 3973 3974 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); 3975 3976 if (exp.X_op == O_constant) 3977 { 3978 inst.operands[i].imm = exp.X_add_number & 0xffffffff; 3979 /* If we're on a 64-bit host, then a 64-bit number can be returned using 3980 O_constant. We have to be careful not to break compilation for 3981 32-bit X_add_number, though. */ 3982 if ((exp.X_add_number & ~0xffffffffl) != 0) 3983 { 3984 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ 3985 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; 3986 inst.operands[i].regisimm = 1; 3987 } 3988 } 3989 else if (exp.X_op == O_big 3990 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 3991 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) 3992 { 3993 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; 3994 /* Bignums have their least significant bits in 3995 generic_bignum[0]. Make sure we put 32 bits in imm and 3996 32 bits in reg, in a (hopefully) portable way. */ 3997 assert (parts != 0); 3998 inst.operands[i].imm = 0; 3999 for (j = 0; j < parts; j++, idx++) 4000 inst.operands[i].imm |= generic_bignum[idx] 4001 << (LITTLENUM_NUMBER_OF_BITS * j); 4002 inst.operands[i].reg = 0; 4003 for (j = 0; j < parts; j++, idx++) 4004 inst.operands[i].reg |= generic_bignum[idx] 4005 << (LITTLENUM_NUMBER_OF_BITS * j); 4006 inst.operands[i].regisimm = 1; 4007 } 4008 else 4009 return FAIL; 4010 4011 *str = ptr; 4012 4013 return SUCCESS; 4014} 4015 4016/* Returns the pseudo-register number of an FPA immediate constant, 4017 or FAIL if there isn't a valid constant here. */ 4018 4019static int 4020parse_fpa_immediate (char ** str) 4021{ 4022 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4023 char * save_in; 4024 expressionS exp; 4025 int i; 4026 int j; 4027 4028 /* First try and match exact strings, this is to guarantee 4029 that some formats will work even for cross assembly. */ 4030 4031 for (i = 0; fp_const[i]; i++) 4032 { 4033 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) 4034 { 4035 char *start = *str; 4036 4037 *str += strlen (fp_const[i]); 4038 if (is_end_of_line[(unsigned char) **str]) 4039 return i + 8; 4040 *str = start; 4041 } 4042 } 4043 4044 /* Just because we didn't get a match doesn't mean that the constant 4045 isn't valid, just that it is in a format that we don't 4046 automatically recognize. Try parsing it with the standard 4047 expression routines. */ 4048 4049 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); 4050 4051 /* Look for a raw floating point number. */ 4052 if ((save_in = atof_ieee (*str, 'x', words)) != NULL 4053 && is_end_of_line[(unsigned char) *save_in]) 4054 { 4055 for (i = 0; i < NUM_FLOAT_VALS; i++) 4056 { 4057 for (j = 0; j < MAX_LITTLENUMS; j++) 4058 { 4059 if (words[j] != fp_values[i][j]) 4060 break; 4061 } 4062 4063 if (j == MAX_LITTLENUMS) 4064 { 4065 *str = save_in; 4066 return i + 8; 4067 } 4068 } 4069 } 4070 4071 /* Try and parse a more complex expression, this will probably fail 4072 unless the code uses a floating point prefix (eg "0f"). */ 4073 save_in = input_line_pointer; 4074 input_line_pointer = *str; 4075 if (expression (&exp) == absolute_section 4076 && exp.X_op == O_big 4077 && exp.X_add_number < 0) 4078 { 4079 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. 4080 Ditto for 15. */ 4081 if (gen_to_words (words, 5, (long) 15) == 0) 4082 { 4083 for (i = 0; i < NUM_FLOAT_VALS; i++) 4084 { 4085 for (j = 0; j < MAX_LITTLENUMS; j++) 4086 { 4087 if (words[j] != fp_values[i][j]) 4088 break; 4089 } 4090 4091 if (j == MAX_LITTLENUMS) 4092 { 4093 *str = input_line_pointer; 4094 input_line_pointer = save_in; 4095 return i + 8; 4096 } 4097 } 4098 } 4099 } 4100 4101 *str = input_line_pointer; 4102 input_line_pointer = save_in; 4103 inst.error = _("invalid FPA immediate expression"); 4104 return FAIL; 4105} 4106 4107/* Returns 1 if a number has "quarter-precision" float format 4108 0baBbbbbbc defgh000 00000000 00000000. */ 4109 4110static int 4111is_quarter_float (unsigned imm) 4112{ 4113 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; 4114 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; 4115} 4116 4117/* Parse an 8-bit "quarter-precision" floating point number of the form: 4118 0baBbbbbbc defgh000 00000000 00000000. 4119 The zero and minus-zero cases need special handling, since they can't be 4120 encoded in the "quarter-precision" float format, but can nonetheless be 4121 loaded as integer constants. */ 4122 4123static unsigned 4124parse_qfloat_immediate (char **ccp, int *immed) 4125{ 4126 char *str = *ccp; 4127 char *fpnum; 4128 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4129 int found_fpchar = 0; 4130 4131 skip_past_char (&str, '#'); 4132 4133 /* We must not accidentally parse an integer as a floating-point number. Make 4134 sure that the value we parse is not an integer by checking for special 4135 characters '.' or 'e'. 4136 FIXME: This is a horrible hack, but doing better is tricky because type 4137 information isn't in a very usable state at parse time. */ 4138 fpnum = str; 4139 skip_whitespace (fpnum); 4140 4141 if (strncmp (fpnum, "0x", 2) == 0) 4142 return FAIL; 4143 else 4144 { 4145 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) 4146 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') 4147 { 4148 found_fpchar = 1; 4149 break; 4150 } 4151 4152 if (!found_fpchar) 4153 return FAIL; 4154 } 4155 4156 if ((str = atof_ieee (str, 's', words)) != NULL) 4157 { 4158 unsigned fpword = 0; 4159 int i; 4160 4161 /* Our FP word must be 32 bits (single-precision FP). */ 4162 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) 4163 { 4164 fpword <<= LITTLENUM_NUMBER_OF_BITS; 4165 fpword |= words[i]; 4166 } 4167 4168 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) 4169 *immed = fpword; 4170 else 4171 return FAIL; 4172 4173 *ccp = str; 4174 4175 return SUCCESS; 4176 } 4177 4178 return FAIL; 4179} 4180 4181/* Shift operands. */ 4182enum shift_kind 4183{ 4184 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX 4185}; 4186 4187struct asm_shift_name 4188{ 4189 const char *name; 4190 enum shift_kind kind; 4191}; 4192 4193/* Third argument to parse_shift. */ 4194enum parse_shift_mode 4195{ 4196 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ 4197 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ 4198 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ 4199 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ 4200 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ 4201}; 4202 4203/* Parse a <shift> specifier on an ARM data processing instruction. 4204 This has three forms: 4205 4206 (LSL|LSR|ASL|ASR|ROR) Rs 4207 (LSL|LSR|ASL|ASR|ROR) #imm 4208 RRX 4209 4210 Note that ASL is assimilated to LSL in the instruction encoding, and 4211 RRX to ROR #0 (which cannot be written as such). */ 4212 4213static int 4214parse_shift (char **str, int i, enum parse_shift_mode mode) 4215{ 4216 const struct asm_shift_name *shift_name; 4217 enum shift_kind shift; 4218 char *s = *str; 4219 char *p = s; 4220 int reg; 4221 4222 for (p = *str; ISALPHA (*p); p++) 4223 ; 4224 4225 if (p == *str) 4226 { 4227 inst.error = _("shift expression expected"); 4228 return FAIL; 4229 } 4230 4231 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); 4232 4233 if (shift_name == NULL) 4234 { 4235 inst.error = _("shift expression expected"); 4236 return FAIL; 4237 } 4238 4239 shift = shift_name->kind; 4240 4241 switch (mode) 4242 { 4243 case NO_SHIFT_RESTRICT: 4244 case SHIFT_IMMEDIATE: break; 4245 4246 case SHIFT_LSL_OR_ASR_IMMEDIATE: 4247 if (shift != SHIFT_LSL && shift != SHIFT_ASR) 4248 { 4249 inst.error = _("'LSL' or 'ASR' required"); 4250 return FAIL; 4251 } 4252 break; 4253 4254 case SHIFT_LSL_IMMEDIATE: 4255 if (shift != SHIFT_LSL) 4256 { 4257 inst.error = _("'LSL' required"); 4258 return FAIL; 4259 } 4260 break; 4261 4262 case SHIFT_ASR_IMMEDIATE: 4263 if (shift != SHIFT_ASR) 4264 { 4265 inst.error = _("'ASR' required"); 4266 return FAIL; 4267 } 4268 break; 4269 4270 default: abort (); 4271 } 4272 4273 if (shift != SHIFT_RRX) 4274 { 4275 /* Whitespace can appear here if the next thing is a bare digit. */ 4276 skip_whitespace (p); 4277 4278 if (mode == NO_SHIFT_RESTRICT 4279 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4280 { 4281 inst.operands[i].imm = reg; 4282 inst.operands[i].immisreg = 1; 4283 } 4284 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4285 return FAIL; 4286 } 4287 inst.operands[i].shift_kind = shift; 4288 inst.operands[i].shifted = 1; 4289 *str = p; 4290 return SUCCESS; 4291} 4292 4293/* Parse a <shifter_operand> for an ARM data processing instruction: 4294 4295 #<immediate> 4296 #<immediate>, <rotate> 4297 <Rm> 4298 <Rm>, <shift> 4299 4300 where <shift> is defined by parse_shift above, and <rotate> is a 4301 multiple of 2 between 0 and 30. Validation of immediate operands 4302 is deferred to md_apply_fix. */ 4303 4304static int 4305parse_shifter_operand (char **str, int i) 4306{ 4307 int value; 4308 expressionS expr; 4309 4310 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) 4311 { 4312 inst.operands[i].reg = value; 4313 inst.operands[i].isreg = 1; 4314 4315 /* parse_shift will override this if appropriate */ 4316 inst.reloc.exp.X_op = O_constant; 4317 inst.reloc.exp.X_add_number = 0; 4318 4319 if (skip_past_comma (str) == FAIL) 4320 return SUCCESS; 4321 4322 /* Shift operation on register. */ 4323 return parse_shift (str, i, NO_SHIFT_RESTRICT); 4324 } 4325 4326 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) 4327 return FAIL; 4328 4329 if (skip_past_comma (str) == SUCCESS) 4330 { 4331 /* #x, y -- ie explicit rotation by Y. */ 4332 if (my_get_expression (&expr, str, GE_NO_PREFIX)) 4333 return FAIL; 4334 4335 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) 4336 { 4337 inst.error = _("constant expression expected"); 4338 return FAIL; 4339 } 4340 4341 value = expr.X_add_number; 4342 if (value < 0 || value > 30 || value % 2 != 0) 4343 { 4344 inst.error = _("invalid rotation"); 4345 return FAIL; 4346 } 4347 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) 4348 { 4349 inst.error = _("invalid constant"); 4350 return FAIL; 4351 } 4352 4353 /* Convert to decoded value. md_apply_fix will put it back. */ 4354 inst.reloc.exp.X_add_number 4355 = (((inst.reloc.exp.X_add_number << (32 - value)) 4356 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); 4357 } 4358 4359 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 4360 inst.reloc.pc_rel = 0; 4361 return SUCCESS; 4362} 4363 4364/* Group relocation information. Each entry in the table contains the 4365 textual name of the relocation as may appear in assembler source 4366 and must end with a colon. 4367 Along with this textual name are the relocation codes to be used if 4368 the corresponding instruction is an ALU instruction (ADD or SUB only), 4369 an LDR, an LDRS, or an LDC. */ 4370 4371struct group_reloc_table_entry 4372{ 4373 const char *name; 4374 int alu_code; 4375 int ldr_code; 4376 int ldrs_code; 4377 int ldc_code; 4378}; 4379 4380typedef enum 4381{ 4382 /* Varieties of non-ALU group relocation. */ 4383 4384 GROUP_LDR, 4385 GROUP_LDRS, 4386 GROUP_LDC 4387} group_reloc_type; 4388 4389static struct group_reloc_table_entry group_reloc_table[] = 4390 { /* Program counter relative: */ 4391 { "pc_g0_nc", 4392 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ 4393 0, /* LDR */ 4394 0, /* LDRS */ 4395 0 }, /* LDC */ 4396 { "pc_g0", 4397 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ 4398 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ 4399 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ 4400 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ 4401 { "pc_g1_nc", 4402 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ 4403 0, /* LDR */ 4404 0, /* LDRS */ 4405 0 }, /* LDC */ 4406 { "pc_g1", 4407 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ 4408 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ 4409 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ 4410 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ 4411 { "pc_g2", 4412 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ 4413 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ 4414 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ 4415 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ 4416 /* Section base relative */ 4417 { "sb_g0_nc", 4418 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ 4419 0, /* LDR */ 4420 0, /* LDRS */ 4421 0 }, /* LDC */ 4422 { "sb_g0", 4423 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ 4424 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ 4425 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ 4426 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ 4427 { "sb_g1_nc", 4428 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ 4429 0, /* LDR */ 4430 0, /* LDRS */ 4431 0 }, /* LDC */ 4432 { "sb_g1", 4433 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ 4434 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ 4435 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ 4436 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ 4437 { "sb_g2", 4438 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ 4439 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ 4440 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ 4441 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ 4442 4443/* Given the address of a pointer pointing to the textual name of a group 4444 relocation as may appear in assembler source, attempt to find its details 4445 in group_reloc_table. The pointer will be updated to the character after 4446 the trailing colon. On failure, FAIL will be returned; SUCCESS 4447 otherwise. On success, *entry will be updated to point at the relevant 4448 group_reloc_table entry. */ 4449 4450static int 4451find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) 4452{ 4453 unsigned int i; 4454 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) 4455 { 4456 int length = strlen (group_reloc_table[i].name); 4457 4458 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 && 4459 (*str)[length] == ':') 4460 { 4461 *out = &group_reloc_table[i]; 4462 *str += (length + 1); 4463 return SUCCESS; 4464 } 4465 } 4466 4467 return FAIL; 4468} 4469 4470/* Parse a <shifter_operand> for an ARM data processing instruction 4471 (as for parse_shifter_operand) where group relocations are allowed: 4472 4473 #<immediate> 4474 #<immediate>, <rotate> 4475 #:<group_reloc>:<expression> 4476 <Rm> 4477 <Rm>, <shift> 4478 4479 where <group_reloc> is one of the strings defined in group_reloc_table. 4480 The hashes are optional. 4481 4482 Everything else is as for parse_shifter_operand. */ 4483 4484static parse_operand_result 4485parse_shifter_operand_group_reloc (char **str, int i) 4486{ 4487 /* Determine if we have the sequence of characters #: or just : 4488 coming next. If we do, then we check for a group relocation. 4489 If we don't, punt the whole lot to parse_shifter_operand. */ 4490 4491 if (((*str)[0] == '#' && (*str)[1] == ':') 4492 || (*str)[0] == ':') 4493 { 4494 struct group_reloc_table_entry *entry; 4495 4496 if ((*str)[0] == '#') 4497 (*str) += 2; 4498 else 4499 (*str)++; 4500 4501 /* Try to parse a group relocation. Anything else is an error. */ 4502 if (find_group_reloc_table_entry (str, &entry) == FAIL) 4503 { 4504 inst.error = _("unknown group relocation"); 4505 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4506 } 4507 4508 /* We now have the group relocation table entry corresponding to 4509 the name in the assembler source. Next, we parse the expression. */ 4510 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) 4511 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4512 4513 /* Record the relocation type (always the ALU variant here). */ 4514 inst.reloc.type = entry->alu_code; 4515 assert (inst.reloc.type != 0); 4516 4517 return PARSE_OPERAND_SUCCESS; 4518 } 4519 else 4520 return parse_shifter_operand (str, i) == SUCCESS 4521 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; 4522 4523 /* Never reached. */ 4524} 4525 4526/* Parse all forms of an ARM address expression. Information is written 4527 to inst.operands[i] and/or inst.reloc. 4528 4529 Preindexed addressing (.preind=1): 4530 4531 [Rn, #offset] .reg=Rn .reloc.exp=offset 4532 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4533 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4534 .shift_kind=shift .reloc.exp=shift_imm 4535 4536 These three may have a trailing ! which causes .writeback to be set also. 4537 4538 Postindexed addressing (.postind=1, .writeback=1): 4539 4540 [Rn], #offset .reg=Rn .reloc.exp=offset 4541 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4542 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4543 .shift_kind=shift .reloc.exp=shift_imm 4544 4545 Unindexed addressing (.preind=0, .postind=0): 4546 4547 [Rn], {option} .reg=Rn .imm=option .immisreg=0 4548 4549 Other: 4550 4551 [Rn]{!} shorthand for [Rn,#0]{!} 4552 =immediate .isreg=0 .reloc.exp=immediate 4553 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label 4554 4555 It is the caller's responsibility to check for addressing modes not 4556 supported by the instruction, and to set inst.reloc.type. */ 4557 4558static parse_operand_result 4559parse_address_main (char **str, int i, int group_relocations, 4560 group_reloc_type group_type) 4561{ 4562 char *p = *str; 4563 int reg; 4564 4565 if (skip_past_char (&p, '[') == FAIL) 4566 { 4567 if (skip_past_char (&p, '=') == FAIL) 4568 { 4569 /* bare address - translate to PC-relative offset */ 4570 inst.reloc.pc_rel = 1; 4571 inst.operands[i].reg = REG_PC; 4572 inst.operands[i].isreg = 1; 4573 inst.operands[i].preind = 1; 4574 } 4575 /* else a load-constant pseudo op, no special treatment needed here */ 4576 4577 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4578 return PARSE_OPERAND_FAIL; 4579 4580 *str = p; 4581 return PARSE_OPERAND_SUCCESS; 4582 } 4583 4584 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 4585 { 4586 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 4587 return PARSE_OPERAND_FAIL; 4588 } 4589 inst.operands[i].reg = reg; 4590 inst.operands[i].isreg = 1; 4591 4592 if (skip_past_comma (&p) == SUCCESS) 4593 { 4594 inst.operands[i].preind = 1; 4595 4596 if (*p == '+') p++; 4597 else if (*p == '-') p++, inst.operands[i].negative = 1; 4598 4599 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4600 { 4601 inst.operands[i].imm = reg; 4602 inst.operands[i].immisreg = 1; 4603 4604 if (skip_past_comma (&p) == SUCCESS) 4605 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4606 return PARSE_OPERAND_FAIL; 4607 } 4608 else if (skip_past_char (&p, ':') == SUCCESS) 4609 { 4610 /* FIXME: '@' should be used here, but it's filtered out by generic 4611 code before we get to see it here. This may be subject to 4612 change. */ 4613 expressionS exp; 4614 my_get_expression (&exp, &p, GE_NO_PREFIX); 4615 if (exp.X_op != O_constant) 4616 { 4617 inst.error = _("alignment must be constant"); 4618 return PARSE_OPERAND_FAIL; 4619 } 4620 inst.operands[i].imm = exp.X_add_number << 8; 4621 inst.operands[i].immisalign = 1; 4622 /* Alignments are not pre-indexes. */ 4623 inst.operands[i].preind = 0; 4624 } 4625 else 4626 { 4627 if (inst.operands[i].negative) 4628 { 4629 inst.operands[i].negative = 0; 4630 p--; 4631 } 4632 4633 if (group_relocations && 4634 ((*p == '#' && *(p + 1) == ':') || *p == ':')) 4635 4636 { 4637 struct group_reloc_table_entry *entry; 4638 4639 /* Skip over the #: or : sequence. */ 4640 if (*p == '#') 4641 p += 2; 4642 else 4643 p++; 4644 4645 /* Try to parse a group relocation. Anything else is an 4646 error. */ 4647 if (find_group_reloc_table_entry (&p, &entry) == FAIL) 4648 { 4649 inst.error = _("unknown group relocation"); 4650 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4651 } 4652 4653 /* We now have the group relocation table entry corresponding to 4654 the name in the assembler source. Next, we parse the 4655 expression. */ 4656 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4657 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4658 4659 /* Record the relocation type. */ 4660 switch (group_type) 4661 { 4662 case GROUP_LDR: 4663 inst.reloc.type = entry->ldr_code; 4664 break; 4665 4666 case GROUP_LDRS: 4667 inst.reloc.type = entry->ldrs_code; 4668 break; 4669 4670 case GROUP_LDC: 4671 inst.reloc.type = entry->ldc_code; 4672 break; 4673 4674 default: 4675 assert (0); 4676 } 4677 4678 if (inst.reloc.type == 0) 4679 { 4680 inst.error = _("this group relocation is not allowed on this instruction"); 4681 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4682 } 4683 } 4684 else 4685 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4686 return PARSE_OPERAND_FAIL; 4687 } 4688 } 4689 4690 if (skip_past_char (&p, ']') == FAIL) 4691 { 4692 inst.error = _("']' expected"); 4693 return PARSE_OPERAND_FAIL; 4694 } 4695 4696 if (skip_past_char (&p, '!') == SUCCESS) 4697 inst.operands[i].writeback = 1; 4698 4699 else if (skip_past_comma (&p) == SUCCESS) 4700 { 4701 if (skip_past_char (&p, '{') == SUCCESS) 4702 { 4703 /* [Rn], {expr} - unindexed, with option */ 4704 if (parse_immediate (&p, &inst.operands[i].imm, 4705 0, 255, TRUE) == FAIL) 4706 return PARSE_OPERAND_FAIL; 4707 4708 if (skip_past_char (&p, '}') == FAIL) 4709 { 4710 inst.error = _("'}' expected at end of 'option' field"); 4711 return PARSE_OPERAND_FAIL; 4712 } 4713 if (inst.operands[i].preind) 4714 { 4715 inst.error = _("cannot combine index with option"); 4716 return PARSE_OPERAND_FAIL; 4717 } 4718 *str = p; 4719 return PARSE_OPERAND_SUCCESS; 4720 } 4721 else 4722 { 4723 inst.operands[i].postind = 1; 4724 inst.operands[i].writeback = 1; 4725 4726 if (inst.operands[i].preind) 4727 { 4728 inst.error = _("cannot combine pre- and post-indexing"); 4729 return PARSE_OPERAND_FAIL; 4730 } 4731 4732 if (*p == '+') p++; 4733 else if (*p == '-') p++, inst.operands[i].negative = 1; 4734 4735 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4736 { 4737 /* We might be using the immediate for alignment already. If we 4738 are, OR the register number into the low-order bits. */ 4739 if (inst.operands[i].immisalign) 4740 inst.operands[i].imm |= reg; 4741 else 4742 inst.operands[i].imm = reg; 4743 inst.operands[i].immisreg = 1; 4744 4745 if (skip_past_comma (&p) == SUCCESS) 4746 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4747 return PARSE_OPERAND_FAIL; 4748 } 4749 else 4750 { 4751 if (inst.operands[i].negative) 4752 { 4753 inst.operands[i].negative = 0; 4754 p--; 4755 } 4756 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4757 return PARSE_OPERAND_FAIL; 4758 } 4759 } 4760 } 4761 4762 /* If at this point neither .preind nor .postind is set, we have a 4763 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ 4764 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) 4765 { 4766 inst.operands[i].preind = 1; 4767 inst.reloc.exp.X_op = O_constant; 4768 inst.reloc.exp.X_add_number = 0; 4769 } 4770 *str = p; 4771 return PARSE_OPERAND_SUCCESS; 4772} 4773 4774static int 4775parse_address (char **str, int i) 4776{ 4777 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS 4778 ? SUCCESS : FAIL; 4779} 4780 4781static parse_operand_result 4782parse_address_group_reloc (char **str, int i, group_reloc_type type) 4783{ 4784 return parse_address_main (str, i, 1, type); 4785} 4786 4787/* Parse an operand for a MOVW or MOVT instruction. */ 4788static int 4789parse_half (char **str) 4790{ 4791 char * p; 4792 4793 p = *str; 4794 skip_past_char (&p, '#'); 4795 if (strncasecmp (p, ":lower16:", 9) == 0) 4796 inst.reloc.type = BFD_RELOC_ARM_MOVW; 4797 else if (strncasecmp (p, ":upper16:", 9) == 0) 4798 inst.reloc.type = BFD_RELOC_ARM_MOVT; 4799 4800 if (inst.reloc.type != BFD_RELOC_UNUSED) 4801 { 4802 p += 9; 4803 skip_whitespace(p); 4804 } 4805 4806 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4807 return FAIL; 4808 4809 if (inst.reloc.type == BFD_RELOC_UNUSED) 4810 { 4811 if (inst.reloc.exp.X_op != O_constant) 4812 { 4813 inst.error = _("constant expression expected"); 4814 return FAIL; 4815 } 4816 if (inst.reloc.exp.X_add_number < 0 4817 || inst.reloc.exp.X_add_number > 0xffff) 4818 { 4819 inst.error = _("immediate value out of range"); 4820 return FAIL; 4821 } 4822 } 4823 *str = p; 4824 return SUCCESS; 4825} 4826 4827/* Miscellaneous. */ 4828 4829/* Parse a PSR flag operand. The value returned is FAIL on syntax error, 4830 or a bitmask suitable to be or-ed into the ARM msr instruction. */ 4831static int 4832parse_psr (char **str) 4833{ 4834 char *p; 4835 unsigned long psr_field; 4836 const struct asm_psr *psr; 4837 char *start; 4838 4839 /* CPSR's and SPSR's can now be lowercase. This is just a convenience 4840 feature for ease of use and backwards compatibility. */ 4841 p = *str; 4842 if (strncasecmp (p, "SPSR", 4) == 0) 4843 psr_field = SPSR_BIT; 4844 else if (strncasecmp (p, "CPSR", 4) == 0) 4845 psr_field = 0; 4846 else 4847 { 4848 start = p; 4849 do 4850 p++; 4851 while (ISALNUM (*p) || *p == '_'); 4852 4853 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); 4854 if (!psr) 4855 return FAIL; 4856 4857 *str = p; 4858 return psr->field; 4859 } 4860 4861 p += 4; 4862 if (*p == '_') 4863 { 4864 /* A suffix follows. */ 4865 p++; 4866 start = p; 4867 4868 do 4869 p++; 4870 while (ISALNUM (*p) || *p == '_'); 4871 4872 psr = hash_find_n (arm_psr_hsh, start, p - start); 4873 if (!psr) 4874 goto error; 4875 4876 psr_field |= psr->field; 4877 } 4878 else 4879 { 4880 if (ISALNUM (*p)) 4881 goto error; /* Garbage after "[CS]PSR". */ 4882 4883 psr_field |= (PSR_c | PSR_f); 4884 } 4885 *str = p; 4886 return psr_field; 4887 4888 error: 4889 inst.error = _("flag for {c}psr instruction expected"); 4890 return FAIL; 4891} 4892 4893/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a 4894 value suitable for splatting into the AIF field of the instruction. */ 4895 4896static int 4897parse_cps_flags (char **str) 4898{ 4899 int val = 0; 4900 int saw_a_flag = 0; 4901 char *s = *str; 4902 4903 for (;;) 4904 switch (*s++) 4905 { 4906 case '\0': case ',': 4907 goto done; 4908 4909 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; 4910 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; 4911 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; 4912 4913 default: 4914 inst.error = _("unrecognized CPS flag"); 4915 return FAIL; 4916 } 4917 4918 done: 4919 if (saw_a_flag == 0) 4920 { 4921 inst.error = _("missing CPS flags"); 4922 return FAIL; 4923 } 4924 4925 *str = s - 1; 4926 return val; 4927} 4928 4929/* Parse an endian specifier ("BE" or "LE", case insensitive); 4930 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ 4931 4932static int 4933parse_endian_specifier (char **str) 4934{ 4935 int little_endian; 4936 char *s = *str; 4937 4938 if (strncasecmp (s, "BE", 2)) 4939 little_endian = 0; 4940 else if (strncasecmp (s, "LE", 2)) 4941 little_endian = 1; 4942 else 4943 { 4944 inst.error = _("valid endian specifiers are be or le"); 4945 return FAIL; 4946 } 4947 4948 if (ISALNUM (s[2]) || s[2] == '_') 4949 { 4950 inst.error = _("valid endian specifiers are be or le"); 4951 return FAIL; 4952 } 4953 4954 *str = s + 2; 4955 return little_endian; 4956} 4957 4958/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a 4959 value suitable for poking into the rotate field of an sxt or sxta 4960 instruction, or FAIL on error. */ 4961 4962static int 4963parse_ror (char **str) 4964{ 4965 int rot; 4966 char *s = *str; 4967 4968 if (strncasecmp (s, "ROR", 3) == 0) 4969 s += 3; 4970 else 4971 { 4972 inst.error = _("missing rotation field after comma"); 4973 return FAIL; 4974 } 4975 4976 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) 4977 return FAIL; 4978 4979 switch (rot) 4980 { 4981 case 0: *str = s; return 0x0; 4982 case 8: *str = s; return 0x1; 4983 case 16: *str = s; return 0x2; 4984 case 24: *str = s; return 0x3; 4985 4986 default: 4987 inst.error = _("rotation can only be 0, 8, 16, or 24"); 4988 return FAIL; 4989 } 4990} 4991 4992/* Parse a conditional code (from conds[] below). The value returned is in the 4993 range 0 .. 14, or FAIL. */ 4994static int 4995parse_cond (char **str) 4996{ 4997 char *p, *q; 4998 const struct asm_cond *c; 4999 5000 p = q = *str; 5001 while (ISALPHA (*q)) 5002 q++; 5003 5004 c = hash_find_n (arm_cond_hsh, p, q - p); 5005 if (!c) 5006 { 5007 inst.error = _("condition required"); 5008 return FAIL; 5009 } 5010 5011 *str = q; 5012 return c->value; 5013} 5014 5015/* Parse an option for a barrier instruction. Returns the encoding for the 5016 option, or FAIL. */ 5017static int 5018parse_barrier (char **str) 5019{ 5020 char *p, *q; 5021 const struct asm_barrier_opt *o; 5022 5023 p = q = *str; 5024 while (ISALPHA (*q)) 5025 q++; 5026 5027 o = hash_find_n (arm_barrier_opt_hsh, p, q - p); 5028 if (!o) 5029 return FAIL; 5030 5031 *str = q; 5032 return o->value; 5033} 5034 5035/* Parse the operands of a table branch instruction. Similar to a memory 5036 operand. */ 5037static int 5038parse_tb (char **str) 5039{ 5040 char * p = *str; 5041 int reg; 5042 5043 if (skip_past_char (&p, '[') == FAIL) 5044 { 5045 inst.error = _("'[' expected"); 5046 return FAIL; 5047 } 5048 5049 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5050 { 5051 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5052 return FAIL; 5053 } 5054 inst.operands[0].reg = reg; 5055 5056 if (skip_past_comma (&p) == FAIL) 5057 { 5058 inst.error = _("',' expected"); 5059 return FAIL; 5060 } 5061 5062 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5063 { 5064 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5065 return FAIL; 5066 } 5067 inst.operands[0].imm = reg; 5068 5069 if (skip_past_comma (&p) == SUCCESS) 5070 { 5071 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) 5072 return FAIL; 5073 if (inst.reloc.exp.X_add_number != 1) 5074 { 5075 inst.error = _("invalid shift"); 5076 return FAIL; 5077 } 5078 inst.operands[0].shifted = 1; 5079 } 5080 5081 if (skip_past_char (&p, ']') == FAIL) 5082 { 5083 inst.error = _("']' expected"); 5084 return FAIL; 5085 } 5086 *str = p; 5087 return SUCCESS; 5088} 5089 5090/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more 5091 information on the types the operands can take and how they are encoded. 5092 Up to four operands may be read; this function handles setting the 5093 ".present" field for each read operand itself. 5094 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, 5095 else returns FAIL. */ 5096 5097static int 5098parse_neon_mov (char **str, int *which_operand) 5099{ 5100 int i = *which_operand, val; 5101 enum arm_reg_type rtype; 5102 char *ptr = *str; 5103 struct neon_type_el optype; 5104 5105 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5106 { 5107 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 5108 inst.operands[i].reg = val; 5109 inst.operands[i].isscalar = 1; 5110 inst.operands[i].vectype = optype; 5111 inst.operands[i++].present = 1; 5112 5113 if (skip_past_comma (&ptr) == FAIL) 5114 goto wanted_comma; 5115 5116 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5117 goto wanted_arm; 5118 5119 inst.operands[i].reg = val; 5120 inst.operands[i].isreg = 1; 5121 inst.operands[i].present = 1; 5122 } 5123 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) 5124 != FAIL) 5125 { 5126 /* Cases 0, 1, 2, 3, 5 (D only). */ 5127 if (skip_past_comma (&ptr) == FAIL) 5128 goto wanted_comma; 5129 5130 inst.operands[i].reg = val; 5131 inst.operands[i].isreg = 1; 5132 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5133 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5134 inst.operands[i].isvec = 1; 5135 inst.operands[i].vectype = optype; 5136 inst.operands[i++].present = 1; 5137 5138 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5139 { 5140 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 5141 Case 13: VMOV <Sd>, <Rm> */ 5142 inst.operands[i].reg = val; 5143 inst.operands[i].isreg = 1; 5144 inst.operands[i].present = 1; 5145 5146 if (rtype == REG_TYPE_NQ) 5147 { 5148 first_error (_("can't use Neon quad register here")); 5149 return FAIL; 5150 } 5151 else if (rtype != REG_TYPE_VFS) 5152 { 5153 i++; 5154 if (skip_past_comma (&ptr) == FAIL) 5155 goto wanted_comma; 5156 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5157 goto wanted_arm; 5158 inst.operands[i].reg = val; 5159 inst.operands[i].isreg = 1; 5160 inst.operands[i].present = 1; 5161 } 5162 } 5163 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) 5164 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> 5165 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> 5166 Case 10: VMOV.F32 <Sd>, #<imm> 5167 Case 11: VMOV.F64 <Dd>, #<imm> */ 5168 inst.operands[i].immisfloat = 1; 5169 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, 5170 &optype)) != FAIL) 5171 { 5172 /* Case 0: VMOV<c><q> <Qd>, <Qm> 5173 Case 1: VMOV<c><q> <Dd>, <Dm> 5174 Case 8: VMOV.F32 <Sd>, <Sm> 5175 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ 5176 5177 inst.operands[i].reg = val; 5178 inst.operands[i].isreg = 1; 5179 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5180 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5181 inst.operands[i].isvec = 1; 5182 inst.operands[i].vectype = optype; 5183 inst.operands[i].present = 1; 5184 5185 if (skip_past_comma (&ptr) == SUCCESS) 5186 { 5187 /* Case 15. */ 5188 i++; 5189 5190 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5191 goto wanted_arm; 5192 5193 inst.operands[i].reg = val; 5194 inst.operands[i].isreg = 1; 5195 inst.operands[i++].present = 1; 5196 5197 if (skip_past_comma (&ptr) == FAIL) 5198 goto wanted_comma; 5199 5200 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5201 goto wanted_arm; 5202 5203 inst.operands[i].reg = val; 5204 inst.operands[i].isreg = 1; 5205 inst.operands[i++].present = 1; 5206 } 5207 } 5208 else if (parse_big_immediate (&ptr, i) == SUCCESS) 5209 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> 5210 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ 5211 ; 5212 else 5213 { 5214 first_error (_("expected <Rm> or <Dm> or <Qm> operand")); 5215 return FAIL; 5216 } 5217 } 5218 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5219 { 5220 /* Cases 6, 7. */ 5221 inst.operands[i].reg = val; 5222 inst.operands[i].isreg = 1; 5223 inst.operands[i++].present = 1; 5224 5225 if (skip_past_comma (&ptr) == FAIL) 5226 goto wanted_comma; 5227 5228 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5229 { 5230 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 5231 inst.operands[i].reg = val; 5232 inst.operands[i].isscalar = 1; 5233 inst.operands[i].present = 1; 5234 inst.operands[i].vectype = optype; 5235 } 5236 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5237 { 5238 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 5239 inst.operands[i].reg = val; 5240 inst.operands[i].isreg = 1; 5241 inst.operands[i++].present = 1; 5242 5243 if (skip_past_comma (&ptr) == FAIL) 5244 goto wanted_comma; 5245 5246 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) 5247 == FAIL) 5248 { 5249 first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); 5250 return FAIL; 5251 } 5252 5253 inst.operands[i].reg = val; 5254 inst.operands[i].isreg = 1; 5255 inst.operands[i].isvec = 1; 5256 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5257 inst.operands[i].vectype = optype; 5258 inst.operands[i].present = 1; 5259 5260 if (rtype == REG_TYPE_VFS) 5261 { 5262 /* Case 14. */ 5263 i++; 5264 if (skip_past_comma (&ptr) == FAIL) 5265 goto wanted_comma; 5266 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, 5267 &optype)) == FAIL) 5268 { 5269 first_error (_(reg_expected_msgs[REG_TYPE_VFS])); 5270 return FAIL; 5271 } 5272 inst.operands[i].reg = val; 5273 inst.operands[i].isreg = 1; 5274 inst.operands[i].isvec = 1; 5275 inst.operands[i].issingle = 1; 5276 inst.operands[i].vectype = optype; 5277 inst.operands[i].present = 1; 5278 } 5279 } 5280 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) 5281 != FAIL) 5282 { 5283 /* Case 13. */ 5284 inst.operands[i].reg = val; 5285 inst.operands[i].isreg = 1; 5286 inst.operands[i].isvec = 1; 5287 inst.operands[i].issingle = 1; 5288 inst.operands[i].vectype = optype; 5289 inst.operands[i++].present = 1; 5290 } 5291 } 5292 else 5293 { 5294 first_error (_("parse error")); 5295 return FAIL; 5296 } 5297 5298 /* Successfully parsed the operands. Update args. */ 5299 *which_operand = i; 5300 *str = ptr; 5301 return SUCCESS; 5302 5303 wanted_comma: 5304 first_error (_("expected comma")); 5305 return FAIL; 5306 5307 wanted_arm: 5308 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 5309 return FAIL; 5310} 5311 5312/* Matcher codes for parse_operands. */ 5313enum operand_parse_code 5314{ 5315 OP_stop, /* end of line */ 5316 5317 OP_RR, /* ARM register */ 5318 OP_RRnpc, /* ARM register, not r15 */ 5319 OP_RRnpcb, /* ARM register, not r15, in square brackets */ 5320 OP_RRw, /* ARM register, not r15, optional trailing ! */ 5321 OP_RCP, /* Coprocessor number */ 5322 OP_RCN, /* Coprocessor register */ 5323 OP_RF, /* FPA register */ 5324 OP_RVS, /* VFP single precision register */ 5325 OP_RVD, /* VFP double precision register (0..15) */ 5326 OP_RND, /* Neon double precision register (0..31) */ 5327 OP_RNQ, /* Neon quad precision register */ 5328 OP_RVSD, /* VFP single or double precision register */ 5329 OP_RNDQ, /* Neon double or quad precision register */ 5330 OP_RNSDQ, /* Neon single, double or quad precision register */ 5331 OP_RNSC, /* Neon scalar D[X] */ 5332 OP_RVC, /* VFP control register */ 5333 OP_RMF, /* Maverick F register */ 5334 OP_RMD, /* Maverick D register */ 5335 OP_RMFX, /* Maverick FX register */ 5336 OP_RMDX, /* Maverick DX register */ 5337 OP_RMAX, /* Maverick AX register */ 5338 OP_RMDS, /* Maverick DSPSC register */ 5339 OP_RIWR, /* iWMMXt wR register */ 5340 OP_RIWC, /* iWMMXt wC register */ 5341 OP_RIWG, /* iWMMXt wCG register */ 5342 OP_RXA, /* XScale accumulator register */ 5343 5344 OP_REGLST, /* ARM register list */ 5345 OP_VRSLST, /* VFP single-precision register list */ 5346 OP_VRDLST, /* VFP double-precision register list */ 5347 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ 5348 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ 5349 OP_NSTRLST, /* Neon element/structure list */ 5350 5351 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ 5352 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ 5353 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ 5354 OP_RR_RNSC, /* ARM reg or Neon scalar. */ 5355 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ 5356 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ 5357 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ 5358 OP_VMOV, /* Neon VMOV operands. */ 5359 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ 5360 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ 5361 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ 5362 5363 OP_I0, /* immediate zero */ 5364 OP_I7, /* immediate value 0 .. 7 */ 5365 OP_I15, /* 0 .. 15 */ 5366 OP_I16, /* 1 .. 16 */ 5367 OP_I16z, /* 0 .. 16 */ 5368 OP_I31, /* 0 .. 31 */ 5369 OP_I31w, /* 0 .. 31, optional trailing ! */ 5370 OP_I32, /* 1 .. 32 */ 5371 OP_I32z, /* 0 .. 32 */ 5372 OP_I63, /* 0 .. 63 */ 5373 OP_I63s, /* -64 .. 63 */ 5374 OP_I64, /* 1 .. 64 */ 5375 OP_I64z, /* 0 .. 64 */ 5376 OP_I255, /* 0 .. 255 */ 5377 5378 OP_I4b, /* immediate, prefix optional, 1 .. 4 */ 5379 OP_I7b, /* 0 .. 7 */ 5380 OP_I15b, /* 0 .. 15 */ 5381 OP_I31b, /* 0 .. 31 */ 5382 5383 OP_SH, /* shifter operand */ 5384 OP_SHG, /* shifter operand with possible group relocation */ 5385 OP_ADDR, /* Memory address expression (any mode) */ 5386 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ 5387 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ 5388 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ 5389 OP_EXP, /* arbitrary expression */ 5390 OP_EXPi, /* same, with optional immediate prefix */ 5391 OP_EXPr, /* same, with optional relocation suffix */ 5392 OP_HALF, /* 0 .. 65535 or low/high reloc. */ 5393 5394 OP_CPSF, /* CPS flags */ 5395 OP_ENDI, /* Endianness specifier */ 5396 OP_PSR, /* CPSR/SPSR mask for msr */ 5397 OP_COND, /* conditional code */ 5398 OP_TB, /* Table branch. */ 5399 5400 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ 5401 OP_APSR_RR, /* ARM register or "APSR_nzcv". */ 5402 5403 OP_RRnpc_I0, /* ARM register or literal 0 */ 5404 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ 5405 OP_RR_EXi, /* ARM register or expression with imm prefix */ 5406 OP_RF_IF, /* FPA register or immediate */ 5407 OP_RIWR_RIWC, /* iWMMXt R or C reg */ 5408 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ 5409 5410 /* Optional operands. */ 5411 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ 5412 OP_oI31b, /* 0 .. 31 */ 5413 OP_oI32b, /* 1 .. 32 */ 5414 OP_oIffffb, /* 0 .. 65535 */ 5415 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ 5416 5417 OP_oRR, /* ARM register */ 5418 OP_oRRnpc, /* ARM register, not the PC */ 5419 OP_oRRw, /* ARM register, not r15, optional trailing ! */ 5420 OP_oRND, /* Optional Neon double precision register */ 5421 OP_oRNQ, /* Optional Neon quad precision register */ 5422 OP_oRNDQ, /* Optional Neon double or quad precision register */ 5423 OP_oRNSDQ, /* Optional single, double or quad precision vector register */ 5424 OP_oSHll, /* LSL immediate */ 5425 OP_oSHar, /* ASR immediate */ 5426 OP_oSHllar, /* LSL or ASR immediate */ 5427 OP_oROR, /* ROR 0/8/16/24 */ 5428 OP_oBARRIER, /* Option argument for a barrier instruction. */ 5429 5430 OP_FIRST_OPTIONAL = OP_oI7b 5431}; 5432 5433/* Generic instruction operand parser. This does no encoding and no 5434 semantic validation; it merely squirrels values away in the inst 5435 structure. Returns SUCCESS or FAIL depending on whether the 5436 specified grammar matched. */ 5437static int 5438parse_operands (char *str, const unsigned char *pattern) 5439{ 5440 unsigned const char *upat = pattern; 5441 char *backtrack_pos = 0; 5442 const char *backtrack_error = 0; 5443 int i, val, backtrack_index = 0; 5444 enum arm_reg_type rtype; 5445 parse_operand_result result; 5446 5447#define po_char_or_fail(chr) do { \ 5448 if (skip_past_char (&str, chr) == FAIL) \ 5449 goto bad_args; \ 5450} while (0) 5451 5452#define po_reg_or_fail(regtype) do { \ 5453 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5454 &inst.operands[i].vectype); \ 5455 if (val == FAIL) \ 5456 { \ 5457 first_error (_(reg_expected_msgs[regtype])); \ 5458 goto failure; \ 5459 } \ 5460 inst.operands[i].reg = val; \ 5461 inst.operands[i].isreg = 1; \ 5462 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5463 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5464 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5465 || rtype == REG_TYPE_VFD \ 5466 || rtype == REG_TYPE_NQ); \ 5467} while (0) 5468 5469#define po_reg_or_goto(regtype, label) do { \ 5470 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5471 &inst.operands[i].vectype); \ 5472 if (val == FAIL) \ 5473 goto label; \ 5474 \ 5475 inst.operands[i].reg = val; \ 5476 inst.operands[i].isreg = 1; \ 5477 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5478 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5479 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5480 || rtype == REG_TYPE_VFD \ 5481 || rtype == REG_TYPE_NQ); \ 5482} while (0) 5483 5484#define po_imm_or_fail(min, max, popt) do { \ 5485 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ 5486 goto failure; \ 5487 inst.operands[i].imm = val; \ 5488} while (0) 5489 5490#define po_scalar_or_goto(elsz, label) do { \ 5491 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \ 5492 if (val == FAIL) \ 5493 goto label; \ 5494 inst.operands[i].reg = val; \ 5495 inst.operands[i].isscalar = 1; \ 5496} while (0) 5497 5498#define po_misc_or_fail(expr) do { \ 5499 if (expr) \ 5500 goto failure; \ 5501} while (0) 5502 5503#define po_misc_or_fail_no_backtrack(expr) do { \ 5504 result = expr; \ 5505 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\ 5506 backtrack_pos = 0; \ 5507 if (result != PARSE_OPERAND_SUCCESS) \ 5508 goto failure; \ 5509} while (0) 5510 5511 skip_whitespace (str); 5512 5513 for (i = 0; upat[i] != OP_stop; i++) 5514 { 5515 if (upat[i] >= OP_FIRST_OPTIONAL) 5516 { 5517 /* Remember where we are in case we need to backtrack. */ 5518 assert (!backtrack_pos); 5519 backtrack_pos = str; 5520 backtrack_error = inst.error; 5521 backtrack_index = i; 5522 } 5523 5524 if (i > 0 && (i > 1 || inst.operands[0].present)) 5525 po_char_or_fail (','); 5526 5527 switch (upat[i]) 5528 { 5529 /* Registers */ 5530 case OP_oRRnpc: 5531 case OP_RRnpc: 5532 case OP_oRR: 5533 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; 5534 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; 5535 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; 5536 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; 5537 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; 5538 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; 5539 case OP_oRND: 5540 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; 5541 case OP_RVC: 5542 po_reg_or_goto (REG_TYPE_VFC, coproc_reg); 5543 break; 5544 /* Also accept generic coprocessor regs for unknown registers. */ 5545 coproc_reg: 5546 po_reg_or_fail (REG_TYPE_CN); 5547 break; 5548 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; 5549 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; 5550 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; 5551 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; 5552 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; 5553 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; 5554 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; 5555 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; 5556 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; 5557 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; 5558 case OP_oRNQ: 5559 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; 5560 case OP_oRNDQ: 5561 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; 5562 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; 5563 case OP_oRNSDQ: 5564 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; 5565 5566 /* Neon scalar. Using an element size of 8 means that some invalid 5567 scalars are accepted here, so deal with those in later code. */ 5568 case OP_RNSC: po_scalar_or_goto (8, failure); break; 5569 5570 /* WARNING: We can expand to two operands here. This has the potential 5571 to totally confuse the backtracking mechanism! It will be OK at 5572 least as long as we don't try to use optional args as well, 5573 though. */ 5574 case OP_NILO: 5575 { 5576 po_reg_or_goto (REG_TYPE_NDQ, try_imm); 5577 inst.operands[i].present = 1; 5578 i++; 5579 skip_past_comma (&str); 5580 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); 5581 break; 5582 one_reg_only: 5583 /* Optional register operand was omitted. Unfortunately, it's in 5584 operands[i-1] and we need it to be in inst.operands[i]. Fix that 5585 here (this is a bit grotty). */ 5586 inst.operands[i] = inst.operands[i-1]; 5587 inst.operands[i-1].present = 0; 5588 break; 5589 try_imm: 5590 /* There's a possibility of getting a 64-bit immediate here, so 5591 we need special handling. */ 5592 if (parse_big_immediate (&str, i) == FAIL) 5593 { 5594 inst.error = _("immediate value is out of range"); 5595 goto failure; 5596 } 5597 } 5598 break; 5599 5600 case OP_RNDQ_I0: 5601 { 5602 po_reg_or_goto (REG_TYPE_NDQ, try_imm0); 5603 break; 5604 try_imm0: 5605 po_imm_or_fail (0, 0, TRUE); 5606 } 5607 break; 5608 5609 case OP_RVSD_I0: 5610 po_reg_or_goto (REG_TYPE_VFSD, try_imm0); 5611 break; 5612 5613 case OP_RR_RNSC: 5614 { 5615 po_scalar_or_goto (8, try_rr); 5616 break; 5617 try_rr: 5618 po_reg_or_fail (REG_TYPE_RN); 5619 } 5620 break; 5621 5622 case OP_RNSDQ_RNSC: 5623 { 5624 po_scalar_or_goto (8, try_nsdq); 5625 break; 5626 try_nsdq: 5627 po_reg_or_fail (REG_TYPE_NSDQ); 5628 } 5629 break; 5630 5631 case OP_RNDQ_RNSC: 5632 { 5633 po_scalar_or_goto (8, try_ndq); 5634 break; 5635 try_ndq: 5636 po_reg_or_fail (REG_TYPE_NDQ); 5637 } 5638 break; 5639 5640 case OP_RND_RNSC: 5641 { 5642 po_scalar_or_goto (8, try_vfd); 5643 break; 5644 try_vfd: 5645 po_reg_or_fail (REG_TYPE_VFD); 5646 } 5647 break; 5648 5649 case OP_VMOV: 5650 /* WARNING: parse_neon_mov can move the operand counter, i. If we're 5651 not careful then bad things might happen. */ 5652 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); 5653 break; 5654 5655 case OP_RNDQ_IMVNb: 5656 { 5657 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); 5658 break; 5659 try_mvnimm: 5660 /* There's a possibility of getting a 64-bit immediate here, so 5661 we need special handling. */ 5662 if (parse_big_immediate (&str, i) == FAIL) 5663 { 5664 inst.error = _("immediate value is out of range"); 5665 goto failure; 5666 } 5667 } 5668 break; 5669 5670 case OP_RNDQ_I63b: 5671 { 5672 po_reg_or_goto (REG_TYPE_NDQ, try_shimm); 5673 break; 5674 try_shimm: 5675 po_imm_or_fail (0, 63, TRUE); 5676 } 5677 break; 5678 5679 case OP_RRnpcb: 5680 po_char_or_fail ('['); 5681 po_reg_or_fail (REG_TYPE_RN); 5682 po_char_or_fail (']'); 5683 break; 5684 5685 case OP_RRw: 5686 case OP_oRRw: 5687 po_reg_or_fail (REG_TYPE_RN); 5688 if (skip_past_char (&str, '!') == SUCCESS) 5689 inst.operands[i].writeback = 1; 5690 break; 5691 5692 /* Immediates */ 5693 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; 5694 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; 5695 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; 5696 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; 5697 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; 5698 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; 5699 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; 5700 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; 5701 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; 5702 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; 5703 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; 5704 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; 5705 5706 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; 5707 case OP_oI7b: 5708 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; 5709 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; 5710 case OP_oI31b: 5711 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; 5712 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; 5713 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; 5714 5715 /* Immediate variants */ 5716 case OP_oI255c: 5717 po_char_or_fail ('{'); 5718 po_imm_or_fail (0, 255, TRUE); 5719 po_char_or_fail ('}'); 5720 break; 5721 5722 case OP_I31w: 5723 /* The expression parser chokes on a trailing !, so we have 5724 to find it first and zap it. */ 5725 { 5726 char *s = str; 5727 while (*s && *s != ',') 5728 s++; 5729 if (s[-1] == '!') 5730 { 5731 s[-1] = '\0'; 5732 inst.operands[i].writeback = 1; 5733 } 5734 po_imm_or_fail (0, 31, TRUE); 5735 if (str == s - 1) 5736 str = s; 5737 } 5738 break; 5739 5740 /* Expressions */ 5741 case OP_EXPi: EXPi: 5742 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5743 GE_OPT_PREFIX)); 5744 break; 5745 5746 case OP_EXP: 5747 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5748 GE_NO_PREFIX)); 5749 break; 5750 5751 case OP_EXPr: EXPr: 5752 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5753 GE_NO_PREFIX)); 5754 if (inst.reloc.exp.X_op == O_symbol) 5755 { 5756 val = parse_reloc (&str); 5757 if (val == -1) 5758 { 5759 inst.error = _("unrecognized relocation suffix"); 5760 goto failure; 5761 } 5762 else if (val != BFD_RELOC_UNUSED) 5763 { 5764 inst.operands[i].imm = val; 5765 inst.operands[i].hasreloc = 1; 5766 } 5767 } 5768 break; 5769 5770 /* Operand for MOVW or MOVT. */ 5771 case OP_HALF: 5772 po_misc_or_fail (parse_half (&str)); 5773 break; 5774 5775 /* Register or expression */ 5776 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; 5777 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; 5778 5779 /* Register or immediate */ 5780 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; 5781 I0: po_imm_or_fail (0, 0, FALSE); break; 5782 5783 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; 5784 IF: 5785 if (!is_immediate_prefix (*str)) 5786 goto bad_args; 5787 str++; 5788 val = parse_fpa_immediate (&str); 5789 if (val == FAIL) 5790 goto failure; 5791 /* FPA immediates are encoded as registers 8-15. 5792 parse_fpa_immediate has already applied the offset. */ 5793 inst.operands[i].reg = val; 5794 inst.operands[i].isreg = 1; 5795 break; 5796 5797 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; 5798 I32z: po_imm_or_fail (0, 32, FALSE); break; 5799 5800 /* Two kinds of register */ 5801 case OP_RIWR_RIWC: 5802 { 5803 struct reg_entry *rege = arm_reg_parse_multi (&str); 5804 if (!rege 5805 || (rege->type != REG_TYPE_MMXWR 5806 && rege->type != REG_TYPE_MMXWC 5807 && rege->type != REG_TYPE_MMXWCG)) 5808 { 5809 inst.error = _("iWMMXt data or control register expected"); 5810 goto failure; 5811 } 5812 inst.operands[i].reg = rege->number; 5813 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); 5814 } 5815 break; 5816 5817 case OP_RIWC_RIWG: 5818 { 5819 struct reg_entry *rege = arm_reg_parse_multi (&str); 5820 if (!rege 5821 || (rege->type != REG_TYPE_MMXWC 5822 && rege->type != REG_TYPE_MMXWCG)) 5823 { 5824 inst.error = _("iWMMXt control register expected"); 5825 goto failure; 5826 } 5827 inst.operands[i].reg = rege->number; 5828 inst.operands[i].isreg = 1; 5829 } 5830 break; 5831 5832 /* Misc */ 5833 case OP_CPSF: val = parse_cps_flags (&str); break; 5834 case OP_ENDI: val = parse_endian_specifier (&str); break; 5835 case OP_oROR: val = parse_ror (&str); break; 5836 case OP_PSR: val = parse_psr (&str); break; 5837 case OP_COND: val = parse_cond (&str); break; 5838 case OP_oBARRIER:val = parse_barrier (&str); break; 5839 5840 case OP_RVC_PSR: 5841 po_reg_or_goto (REG_TYPE_VFC, try_psr); 5842 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ 5843 break; 5844 try_psr: 5845 val = parse_psr (&str); 5846 break; 5847 5848 case OP_APSR_RR: 5849 po_reg_or_goto (REG_TYPE_RN, try_apsr); 5850 break; 5851 try_apsr: 5852 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS 5853 instruction). */ 5854 if (strncasecmp (str, "APSR_", 5) == 0) 5855 { 5856 unsigned found = 0; 5857 str += 5; 5858 while (found < 15) 5859 switch (*str++) 5860 { 5861 case 'c': found = (found & 1) ? 16 : found | 1; break; 5862 case 'n': found = (found & 2) ? 16 : found | 2; break; 5863 case 'z': found = (found & 4) ? 16 : found | 4; break; 5864 case 'v': found = (found & 8) ? 16 : found | 8; break; 5865 default: found = 16; 5866 } 5867 if (found != 15) 5868 goto failure; 5869 inst.operands[i].isvec = 1; 5870 } 5871 else 5872 goto failure; 5873 break; 5874 5875 case OP_TB: 5876 po_misc_or_fail (parse_tb (&str)); 5877 break; 5878 5879 /* Register lists */ 5880 case OP_REGLST: 5881 val = parse_reg_list (&str); 5882 if (*str == '^') 5883 { 5884 inst.operands[1].writeback = 1; 5885 str++; 5886 } 5887 break; 5888 5889 case OP_VRSLST: 5890 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); 5891 break; 5892 5893 case OP_VRDLST: 5894 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); 5895 break; 5896 5897 case OP_VRSDLST: 5898 /* Allow Q registers too. */ 5899 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5900 REGLIST_NEON_D); 5901 if (val == FAIL) 5902 { 5903 inst.error = NULL; 5904 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5905 REGLIST_VFP_S); 5906 inst.operands[i].issingle = 1; 5907 } 5908 break; 5909 5910 case OP_NRDLST: 5911 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5912 REGLIST_NEON_D); 5913 break; 5914 5915 case OP_NSTRLST: 5916 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, 5917 &inst.operands[i].vectype); 5918 break; 5919 5920 /* Addressing modes */ 5921 case OP_ADDR: 5922 po_misc_or_fail (parse_address (&str, i)); 5923 break; 5924 5925 case OP_ADDRGLDR: 5926 po_misc_or_fail_no_backtrack ( 5927 parse_address_group_reloc (&str, i, GROUP_LDR)); 5928 break; 5929 5930 case OP_ADDRGLDRS: 5931 po_misc_or_fail_no_backtrack ( 5932 parse_address_group_reloc (&str, i, GROUP_LDRS)); 5933 break; 5934 5935 case OP_ADDRGLDC: 5936 po_misc_or_fail_no_backtrack ( 5937 parse_address_group_reloc (&str, i, GROUP_LDC)); 5938 break; 5939 5940 case OP_SH: 5941 po_misc_or_fail (parse_shifter_operand (&str, i)); 5942 break; 5943 5944 case OP_SHG: 5945 po_misc_or_fail_no_backtrack ( 5946 parse_shifter_operand_group_reloc (&str, i)); 5947 break; 5948 5949 case OP_oSHll: 5950 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); 5951 break; 5952 5953 case OP_oSHar: 5954 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); 5955 break; 5956 5957 case OP_oSHllar: 5958 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); 5959 break; 5960 5961 default: 5962 as_fatal ("unhandled operand code %d", upat[i]); 5963 } 5964 5965 /* Various value-based sanity checks and shared operations. We 5966 do not signal immediate failures for the register constraints; 5967 this allows a syntax error to take precedence. */ 5968 switch (upat[i]) 5969 { 5970 case OP_oRRnpc: 5971 case OP_RRnpc: 5972 case OP_RRnpcb: 5973 case OP_RRw: 5974 case OP_oRRw: 5975 case OP_RRnpc_I0: 5976 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) 5977 inst.error = BAD_PC; 5978 break; 5979 5980 case OP_CPSF: 5981 case OP_ENDI: 5982 case OP_oROR: 5983 case OP_PSR: 5984 case OP_RVC_PSR: 5985 case OP_COND: 5986 case OP_oBARRIER: 5987 case OP_REGLST: 5988 case OP_VRSLST: 5989 case OP_VRDLST: 5990 case OP_VRSDLST: 5991 case OP_NRDLST: 5992 case OP_NSTRLST: 5993 if (val == FAIL) 5994 goto failure; 5995 inst.operands[i].imm = val; 5996 break; 5997 5998 default: 5999 break; 6000 } 6001 6002 /* If we get here, this operand was successfully parsed. */ 6003 inst.operands[i].present = 1; 6004 continue; 6005 6006 bad_args: 6007 inst.error = BAD_ARGS; 6008 6009 failure: 6010 if (!backtrack_pos) 6011 { 6012 /* The parse routine should already have set inst.error, but set a 6013 defaut here just in case. */ 6014 if (!inst.error) 6015 inst.error = _("syntax error"); 6016 return FAIL; 6017 } 6018 6019 /* Do not backtrack over a trailing optional argument that 6020 absorbed some text. We will only fail again, with the 6021 'garbage following instruction' error message, which is 6022 probably less helpful than the current one. */ 6023 if (backtrack_index == i && backtrack_pos != str 6024 && upat[i+1] == OP_stop) 6025 { 6026 if (!inst.error) 6027 inst.error = _("syntax error"); 6028 return FAIL; 6029 } 6030 6031 /* Try again, skipping the optional argument at backtrack_pos. */ 6032 str = backtrack_pos; 6033 inst.error = backtrack_error; 6034 inst.operands[backtrack_index].present = 0; 6035 i = backtrack_index; 6036 backtrack_pos = 0; 6037 } 6038 6039 /* Check that we have parsed all the arguments. */ 6040 if (*str != '\0' && !inst.error) 6041 inst.error = _("garbage following instruction"); 6042 6043 return inst.error ? FAIL : SUCCESS; 6044} 6045 6046#undef po_char_or_fail 6047#undef po_reg_or_fail 6048#undef po_reg_or_goto 6049#undef po_imm_or_fail 6050#undef po_scalar_or_fail 6051 6052/* Shorthand macro for instruction encoding functions issuing errors. */ 6053#define constraint(expr, err) do { \ 6054 if (expr) \ 6055 { \ 6056 inst.error = err; \ 6057 return; \ 6058 } \ 6059} while (0) 6060 6061/* Functions for operand encoding. ARM, then Thumb. */ 6062 6063#define rotate_left(v, n) (v << n | v >> (32 - n)) 6064 6065/* If VAL can be encoded in the immediate field of an ARM instruction, 6066 return the encoded form. Otherwise, return FAIL. */ 6067 6068static unsigned int 6069encode_arm_immediate (unsigned int val) 6070{ 6071 unsigned int a, i; 6072 6073 for (i = 0; i < 32; i += 2) 6074 if ((a = rotate_left (val, i)) <= 0xff) 6075 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ 6076 6077 return FAIL; 6078} 6079 6080/* If VAL can be encoded in the immediate field of a Thumb32 instruction, 6081 return the encoded form. Otherwise, return FAIL. */ 6082static unsigned int 6083encode_thumb32_immediate (unsigned int val) 6084{ 6085 unsigned int a, i; 6086 6087 if (val <= 0xff) 6088 return val; 6089 6090 for (i = 1; i <= 24; i++) 6091 { 6092 a = val >> i; 6093 if ((val & ~(0xff << i)) == 0) 6094 return ((val >> i) & 0x7f) | ((32 - i) << 7); 6095 } 6096 6097 a = val & 0xff; 6098 if (val == ((a << 16) | a)) 6099 return 0x100 | a; 6100 if (val == ((a << 24) | (a << 16) | (a << 8) | a)) 6101 return 0x300 | a; 6102 6103 a = val & 0xff00; 6104 if (val == ((a << 16) | a)) 6105 return 0x200 | (a >> 8); 6106 6107 return FAIL; 6108} 6109/* Encode a VFP SP or DP register number into inst.instruction. */ 6110 6111static void 6112encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) 6113{ 6114 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) 6115 && reg > 15) 6116 { 6117 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 6118 { 6119 if (thumb_mode) 6120 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 6121 fpu_vfp_ext_v3); 6122 else 6123 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 6124 fpu_vfp_ext_v3); 6125 } 6126 else 6127 { 6128 first_error (_("D register out of range for selected VFP version")); 6129 return; 6130 } 6131 } 6132 6133 switch (pos) 6134 { 6135 case VFP_REG_Sd: 6136 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); 6137 break; 6138 6139 case VFP_REG_Sn: 6140 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); 6141 break; 6142 6143 case VFP_REG_Sm: 6144 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); 6145 break; 6146 6147 case VFP_REG_Dd: 6148 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); 6149 break; 6150 6151 case VFP_REG_Dn: 6152 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); 6153 break; 6154 6155 case VFP_REG_Dm: 6156 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); 6157 break; 6158 6159 default: 6160 abort (); 6161 } 6162} 6163 6164/* Encode a <shift> in an ARM-format instruction. The immediate, 6165 if any, is handled by md_apply_fix. */ 6166static void 6167encode_arm_shift (int i) 6168{ 6169 if (inst.operands[i].shift_kind == SHIFT_RRX) 6170 inst.instruction |= SHIFT_ROR << 5; 6171 else 6172 { 6173 inst.instruction |= inst.operands[i].shift_kind << 5; 6174 if (inst.operands[i].immisreg) 6175 { 6176 inst.instruction |= SHIFT_BY_REG; 6177 inst.instruction |= inst.operands[i].imm << 8; 6178 } 6179 else 6180 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6181 } 6182} 6183 6184static void 6185encode_arm_shifter_operand (int i) 6186{ 6187 if (inst.operands[i].isreg) 6188 { 6189 inst.instruction |= inst.operands[i].reg; 6190 encode_arm_shift (i); 6191 } 6192 else 6193 inst.instruction |= INST_IMMEDIATE; 6194} 6195 6196/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ 6197static void 6198encode_arm_addr_mode_common (int i, bfd_boolean is_t) 6199{ 6200 assert (inst.operands[i].isreg); 6201 inst.instruction |= inst.operands[i].reg << 16; 6202 6203 if (inst.operands[i].preind) 6204 { 6205 if (is_t) 6206 { 6207 inst.error = _("instruction does not accept preindexed addressing"); 6208 return; 6209 } 6210 inst.instruction |= PRE_INDEX; 6211 if (inst.operands[i].writeback) 6212 inst.instruction |= WRITE_BACK; 6213 6214 } 6215 else if (inst.operands[i].postind) 6216 { 6217 assert (inst.operands[i].writeback); 6218 if (is_t) 6219 inst.instruction |= WRITE_BACK; 6220 } 6221 else /* unindexed - only for coprocessor */ 6222 { 6223 inst.error = _("instruction does not accept unindexed addressing"); 6224 return; 6225 } 6226 6227 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) 6228 && (((inst.instruction & 0x000f0000) >> 16) 6229 == ((inst.instruction & 0x0000f000) >> 12))) 6230 as_warn ((inst.instruction & LOAD_BIT) 6231 ? _("destination register same as write-back base") 6232 : _("source register same as write-back base")); 6233} 6234 6235/* inst.operands[i] was set up by parse_address. Encode it into an 6236 ARM-format mode 2 load or store instruction. If is_t is true, 6237 reject forms that cannot be used with a T instruction (i.e. not 6238 post-indexed). */ 6239static void 6240encode_arm_addr_mode_2 (int i, bfd_boolean is_t) 6241{ 6242 encode_arm_addr_mode_common (i, is_t); 6243 6244 if (inst.operands[i].immisreg) 6245 { 6246 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ 6247 inst.instruction |= inst.operands[i].imm; 6248 if (!inst.operands[i].negative) 6249 inst.instruction |= INDEX_UP; 6250 if (inst.operands[i].shifted) 6251 { 6252 if (inst.operands[i].shift_kind == SHIFT_RRX) 6253 inst.instruction |= SHIFT_ROR << 5; 6254 else 6255 { 6256 inst.instruction |= inst.operands[i].shift_kind << 5; 6257 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6258 } 6259 } 6260 } 6261 else /* immediate offset in inst.reloc */ 6262 { 6263 if (inst.reloc.type == BFD_RELOC_UNUSED) 6264 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; 6265 } 6266} 6267 6268/* inst.operands[i] was set up by parse_address. Encode it into an 6269 ARM-format mode 3 load or store instruction. Reject forms that 6270 cannot be used with such instructions. If is_t is true, reject 6271 forms that cannot be used with a T instruction (i.e. not 6272 post-indexed). */ 6273static void 6274encode_arm_addr_mode_3 (int i, bfd_boolean is_t) 6275{ 6276 if (inst.operands[i].immisreg && inst.operands[i].shifted) 6277 { 6278 inst.error = _("instruction does not accept scaled register index"); 6279 return; 6280 } 6281 6282 encode_arm_addr_mode_common (i, is_t); 6283 6284 if (inst.operands[i].immisreg) 6285 { 6286 inst.instruction |= inst.operands[i].imm; 6287 if (!inst.operands[i].negative) 6288 inst.instruction |= INDEX_UP; 6289 } 6290 else /* immediate offset in inst.reloc */ 6291 { 6292 inst.instruction |= HWOFFSET_IMM; 6293 if (inst.reloc.type == BFD_RELOC_UNUSED) 6294 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; 6295 } 6296} 6297 6298/* inst.operands[i] was set up by parse_address. Encode it into an 6299 ARM-format instruction. Reject all forms which cannot be encoded 6300 into a coprocessor load/store instruction. If wb_ok is false, 6301 reject use of writeback; if unind_ok is false, reject use of 6302 unindexed addressing. If reloc_override is not 0, use it instead 6303 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one 6304 (in which case it is preserved). */ 6305 6306static int 6307encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) 6308{ 6309 inst.instruction |= inst.operands[i].reg << 16; 6310 6311 assert (!(inst.operands[i].preind && inst.operands[i].postind)); 6312 6313 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ 6314 { 6315 assert (!inst.operands[i].writeback); 6316 if (!unind_ok) 6317 { 6318 inst.error = _("instruction does not support unindexed addressing"); 6319 return FAIL; 6320 } 6321 inst.instruction |= inst.operands[i].imm; 6322 inst.instruction |= INDEX_UP; 6323 return SUCCESS; 6324 } 6325 6326 if (inst.operands[i].preind) 6327 inst.instruction |= PRE_INDEX; 6328 6329 if (inst.operands[i].writeback) 6330 { 6331 if (inst.operands[i].reg == REG_PC) 6332 { 6333 inst.error = _("pc may not be used with write-back"); 6334 return FAIL; 6335 } 6336 if (!wb_ok) 6337 { 6338 inst.error = _("instruction does not support writeback"); 6339 return FAIL; 6340 } 6341 inst.instruction |= WRITE_BACK; 6342 } 6343 6344 if (reloc_override) 6345 inst.reloc.type = reloc_override; 6346 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC 6347 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) 6348 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) 6349 { 6350 if (thumb_mode) 6351 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; 6352 else 6353 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; 6354 } 6355 6356 return SUCCESS; 6357} 6358 6359/* inst.reloc.exp describes an "=expr" load pseudo-operation. 6360 Determine whether it can be performed with a move instruction; if 6361 it can, convert inst.instruction to that move instruction and 6362 return 1; if it can't, convert inst.instruction to a literal-pool 6363 load and return 0. If this is not a valid thing to do in the 6364 current context, set inst.error and return 1. 6365 6366 inst.operands[i] describes the destination register. */ 6367 6368static int 6369move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) 6370{ 6371 unsigned long tbit; 6372 6373 if (thumb_p) 6374 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; 6375 else 6376 tbit = LOAD_BIT; 6377 6378 if ((inst.instruction & tbit) == 0) 6379 { 6380 inst.error = _("invalid pseudo operation"); 6381 return 1; 6382 } 6383 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) 6384 { 6385 inst.error = _("constant expression expected"); 6386 return 1; 6387 } 6388 if (inst.reloc.exp.X_op == O_constant) 6389 { 6390 if (thumb_p) 6391 { 6392 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) 6393 { 6394 /* This can be done with a mov(1) instruction. */ 6395 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); 6396 inst.instruction |= inst.reloc.exp.X_add_number; 6397 return 1; 6398 } 6399 } 6400 else 6401 { 6402 int value = encode_arm_immediate (inst.reloc.exp.X_add_number); 6403 if (value != FAIL) 6404 { 6405 /* This can be done with a mov instruction. */ 6406 inst.instruction &= LITERAL_MASK; 6407 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); 6408 inst.instruction |= value & 0xfff; 6409 return 1; 6410 } 6411 6412 value = encode_arm_immediate (~inst.reloc.exp.X_add_number); 6413 if (value != FAIL) 6414 { 6415 /* This can be done with a mvn instruction. */ 6416 inst.instruction &= LITERAL_MASK; 6417 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); 6418 inst.instruction |= value & 0xfff; 6419 return 1; 6420 } 6421 } 6422 } 6423 6424 if (add_to_lit_pool () == FAIL) 6425 { 6426 inst.error = _("literal pool insertion failed"); 6427 return 1; 6428 } 6429 inst.operands[1].reg = REG_PC; 6430 inst.operands[1].isreg = 1; 6431 inst.operands[1].preind = 1; 6432 inst.reloc.pc_rel = 1; 6433 inst.reloc.type = (thumb_p 6434 ? BFD_RELOC_ARM_THUMB_OFFSET 6435 : (mode_3 6436 ? BFD_RELOC_ARM_HWLITERAL 6437 : BFD_RELOC_ARM_LITERAL)); 6438 return 0; 6439} 6440 6441/* Functions for instruction encoding, sorted by subarchitecture. 6442 First some generics; their names are taken from the conventional 6443 bit positions for register arguments in ARM format instructions. */ 6444 6445static void 6446do_noargs (void) 6447{ 6448} 6449 6450static void 6451do_rd (void) 6452{ 6453 inst.instruction |= inst.operands[0].reg << 12; 6454} 6455 6456static void 6457do_rd_rm (void) 6458{ 6459 inst.instruction |= inst.operands[0].reg << 12; 6460 inst.instruction |= inst.operands[1].reg; 6461} 6462 6463static void 6464do_rd_rn (void) 6465{ 6466 inst.instruction |= inst.operands[0].reg << 12; 6467 inst.instruction |= inst.operands[1].reg << 16; 6468} 6469 6470static void 6471do_rn_rd (void) 6472{ 6473 inst.instruction |= inst.operands[0].reg << 16; 6474 inst.instruction |= inst.operands[1].reg << 12; 6475} 6476 6477static void 6478do_rd_rm_rn (void) 6479{ 6480 unsigned Rn = inst.operands[2].reg; 6481 /* Enforce restrictions on SWP instruction. */ 6482 if ((inst.instruction & 0x0fbfffff) == 0x01000090) 6483 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, 6484 _("Rn must not overlap other operands")); 6485 inst.instruction |= inst.operands[0].reg << 12; 6486 inst.instruction |= inst.operands[1].reg; 6487 inst.instruction |= Rn << 16; 6488} 6489 6490static void 6491do_rd_rn_rm (void) 6492{ 6493 inst.instruction |= inst.operands[0].reg << 12; 6494 inst.instruction |= inst.operands[1].reg << 16; 6495 inst.instruction |= inst.operands[2].reg; 6496} 6497 6498static void 6499do_rm_rd_rn (void) 6500{ 6501 inst.instruction |= inst.operands[0].reg; 6502 inst.instruction |= inst.operands[1].reg << 12; 6503 inst.instruction |= inst.operands[2].reg << 16; 6504} 6505 6506static void 6507do_imm0 (void) 6508{ 6509 inst.instruction |= inst.operands[0].imm; 6510} 6511 6512static void 6513do_rd_cpaddr (void) 6514{ 6515 inst.instruction |= inst.operands[0].reg << 12; 6516 encode_arm_cp_address (1, TRUE, TRUE, 0); 6517} 6518 6519/* ARM instructions, in alphabetical order by function name (except 6520 that wrapper functions appear immediately after the function they 6521 wrap). */ 6522 6523/* This is a pseudo-op of the form "adr rd, label" to be converted 6524 into a relative address of the form "add rd, pc, #label-.-8". */ 6525 6526static void 6527do_adr (void) 6528{ 6529 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6530 6531 /* Frag hacking will turn this into a sub instruction if the offset turns 6532 out to be negative. */ 6533 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 6534 inst.reloc.pc_rel = 1; 6535 inst.reloc.exp.X_add_number -= 8; 6536} 6537 6538/* This is a pseudo-op of the form "adrl rd, label" to be converted 6539 into a relative address of the form: 6540 add rd, pc, #low(label-.-8)" 6541 add rd, rd, #high(label-.-8)" */ 6542 6543static void 6544do_adrl (void) 6545{ 6546 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6547 6548 /* Frag hacking will turn this into a sub instruction if the offset turns 6549 out to be negative. */ 6550 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; 6551 inst.reloc.pc_rel = 1; 6552 inst.size = INSN_SIZE * 2; 6553 inst.reloc.exp.X_add_number -= 8; 6554} 6555 6556static void 6557do_arit (void) 6558{ 6559 if (!inst.operands[1].present) 6560 inst.operands[1].reg = inst.operands[0].reg; 6561 inst.instruction |= inst.operands[0].reg << 12; 6562 inst.instruction |= inst.operands[1].reg << 16; 6563 encode_arm_shifter_operand (2); 6564} 6565 6566static void 6567do_barrier (void) 6568{ 6569 if (inst.operands[0].present) 6570 { 6571 constraint ((inst.instruction & 0xf0) != 0x40 6572 && inst.operands[0].imm != 0xf, 6573 "bad barrier type"); 6574 inst.instruction |= inst.operands[0].imm; 6575 } 6576 else 6577 inst.instruction |= 0xf; 6578} 6579 6580static void 6581do_bfc (void) 6582{ 6583 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 6584 constraint (msb > 32, _("bit-field extends past end of register")); 6585 /* The instruction encoding stores the LSB and MSB, 6586 not the LSB and width. */ 6587 inst.instruction |= inst.operands[0].reg << 12; 6588 inst.instruction |= inst.operands[1].imm << 7; 6589 inst.instruction |= (msb - 1) << 16; 6590} 6591 6592static void 6593do_bfi (void) 6594{ 6595 unsigned int msb; 6596 6597 /* #0 in second position is alternative syntax for bfc, which is 6598 the same instruction but with REG_PC in the Rm field. */ 6599 if (!inst.operands[1].isreg) 6600 inst.operands[1].reg = REG_PC; 6601 6602 msb = inst.operands[2].imm + inst.operands[3].imm; 6603 constraint (msb > 32, _("bit-field extends past end of register")); 6604 /* The instruction encoding stores the LSB and MSB, 6605 not the LSB and width. */ 6606 inst.instruction |= inst.operands[0].reg << 12; 6607 inst.instruction |= inst.operands[1].reg; 6608 inst.instruction |= inst.operands[2].imm << 7; 6609 inst.instruction |= (msb - 1) << 16; 6610} 6611 6612static void 6613do_bfx (void) 6614{ 6615 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 6616 _("bit-field extends past end of register")); 6617 inst.instruction |= inst.operands[0].reg << 12; 6618 inst.instruction |= inst.operands[1].reg; 6619 inst.instruction |= inst.operands[2].imm << 7; 6620 inst.instruction |= (inst.operands[3].imm - 1) << 16; 6621} 6622 6623/* ARM V5 breakpoint instruction (argument parse) 6624 BKPT <16 bit unsigned immediate> 6625 Instruction is not conditional. 6626 The bit pattern given in insns[] has the COND_ALWAYS condition, 6627 and it is an error if the caller tried to override that. */ 6628 6629static void 6630do_bkpt (void) 6631{ 6632 /* Top 12 of 16 bits to bits 19:8. */ 6633 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; 6634 6635 /* Bottom 4 of 16 bits to bits 3:0. */ 6636 inst.instruction |= inst.operands[0].imm & 0xf; 6637} 6638 6639static void 6640encode_branch (int default_reloc) 6641{ 6642 if (inst.operands[0].hasreloc) 6643 { 6644 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, 6645 _("the only suffix valid here is '(plt)'")); 6646 inst.reloc.type = BFD_RELOC_ARM_PLT32; 6647 } 6648 else 6649 { 6650 inst.reloc.type = default_reloc; 6651 } 6652 inst.reloc.pc_rel = 1; 6653} 6654 6655static void 6656do_branch (void) 6657{ 6658#ifdef OBJ_ELF 6659 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6660 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6661 else 6662#endif 6663 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6664} 6665 6666static void 6667do_bl (void) 6668{ 6669#ifdef OBJ_ELF 6670 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6671 { 6672 if (inst.cond == COND_ALWAYS) 6673 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6674 else 6675 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6676 } 6677 else 6678#endif 6679 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6680} 6681 6682/* ARM V5 branch-link-exchange instruction (argument parse) 6683 BLX <target_addr> ie BLX(1) 6684 BLX{<condition>} <Rm> ie BLX(2) 6685 Unfortunately, there are two different opcodes for this mnemonic. 6686 So, the insns[].value is not used, and the code here zaps values 6687 into inst.instruction. 6688 Also, the <target_addr> can be 25 bits, hence has its own reloc. */ 6689 6690static void 6691do_blx (void) 6692{ 6693 if (inst.operands[0].isreg) 6694 { 6695 /* Arg is a register; the opcode provided by insns[] is correct. 6696 It is not illegal to do "blx pc", just useless. */ 6697 if (inst.operands[0].reg == REG_PC) 6698 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); 6699 6700 inst.instruction |= inst.operands[0].reg; 6701 } 6702 else 6703 { 6704 /* Arg is an address; this instruction cannot be executed 6705 conditionally, and the opcode must be adjusted. */ 6706 constraint (inst.cond != COND_ALWAYS, BAD_COND); 6707 inst.instruction = 0xfa000000; 6708#ifdef OBJ_ELF 6709 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6710 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6711 else 6712#endif 6713 encode_branch (BFD_RELOC_ARM_PCREL_BLX); 6714 } 6715} 6716 6717static void 6718do_bx (void) 6719{ 6720 if (inst.operands[0].reg == REG_PC) 6721 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); 6722 6723 inst.instruction |= inst.operands[0].reg; 6724} 6725 6726 6727/* ARM v5TEJ. Jump to Jazelle code. */ 6728 6729static void 6730do_bxj (void) 6731{ 6732 if (inst.operands[0].reg == REG_PC) 6733 as_tsktsk (_("use of r15 in bxj is not really useful")); 6734 6735 inst.instruction |= inst.operands[0].reg; 6736} 6737 6738/* Co-processor data operation: 6739 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} 6740 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ 6741static void 6742do_cdp (void) 6743{ 6744 inst.instruction |= inst.operands[0].reg << 8; 6745 inst.instruction |= inst.operands[1].imm << 20; 6746 inst.instruction |= inst.operands[2].reg << 12; 6747 inst.instruction |= inst.operands[3].reg << 16; 6748 inst.instruction |= inst.operands[4].reg; 6749 inst.instruction |= inst.operands[5].imm << 5; 6750} 6751 6752static void 6753do_cmp (void) 6754{ 6755 inst.instruction |= inst.operands[0].reg << 16; 6756 encode_arm_shifter_operand (1); 6757} 6758 6759/* Transfer between coprocessor and ARM registers. 6760 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 6761 MRC2 6762 MCR{cond} 6763 MCR2 6764 6765 No special properties. */ 6766 6767static void 6768do_co_reg (void) 6769{ 6770 inst.instruction |= inst.operands[0].reg << 8; 6771 inst.instruction |= inst.operands[1].imm << 21; 6772 inst.instruction |= inst.operands[2].reg << 12; 6773 inst.instruction |= inst.operands[3].reg << 16; 6774 inst.instruction |= inst.operands[4].reg; 6775 inst.instruction |= inst.operands[5].imm << 5; 6776} 6777 6778/* Transfer between coprocessor register and pair of ARM registers. 6779 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 6780 MCRR2 6781 MRRC{cond} 6782 MRRC2 6783 6784 Two XScale instructions are special cases of these: 6785 6786 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 6787 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 6788 6789 Result unpredicatable if Rd or Rn is R15. */ 6790 6791static void 6792do_co_reg2c (void) 6793{ 6794 inst.instruction |= inst.operands[0].reg << 8; 6795 inst.instruction |= inst.operands[1].imm << 4; 6796 inst.instruction |= inst.operands[2].reg << 12; 6797 inst.instruction |= inst.operands[3].reg << 16; 6798 inst.instruction |= inst.operands[4].reg; 6799} 6800 6801static void 6802do_cpsi (void) 6803{ 6804 inst.instruction |= inst.operands[0].imm << 6; 6805 if (inst.operands[1].present) 6806 { 6807 inst.instruction |= CPSI_MMOD; 6808 inst.instruction |= inst.operands[1].imm; 6809 } 6810} 6811 6812static void 6813do_dbg (void) 6814{ 6815 inst.instruction |= inst.operands[0].imm; 6816} 6817 6818static void 6819do_it (void) 6820{ 6821 /* There is no IT instruction in ARM mode. We 6822 process it but do not generate code for it. */ 6823 inst.size = 0; 6824} 6825 6826static void 6827do_ldmstm (void) 6828{ 6829 int base_reg = inst.operands[0].reg; 6830 int range = inst.operands[1].imm; 6831 6832 inst.instruction |= base_reg << 16; 6833 inst.instruction |= range; 6834 6835 if (inst.operands[1].writeback) 6836 inst.instruction |= LDM_TYPE_2_OR_3; 6837 6838 if (inst.operands[0].writeback) 6839 { 6840 inst.instruction |= WRITE_BACK; 6841 /* Check for unpredictable uses of writeback. */ 6842 if (inst.instruction & LOAD_BIT) 6843 { 6844 /* Not allowed in LDM type 2. */ 6845 if ((inst.instruction & LDM_TYPE_2_OR_3) 6846 && ((range & (1 << REG_PC)) == 0)) 6847 as_warn (_("writeback of base register is UNPREDICTABLE")); 6848 /* Only allowed if base reg not in list for other types. */ 6849 else if (range & (1 << base_reg)) 6850 as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); 6851 } 6852 else /* STM. */ 6853 { 6854 /* Not allowed for type 2. */ 6855 if (inst.instruction & LDM_TYPE_2_OR_3) 6856 as_warn (_("writeback of base register is UNPREDICTABLE")); 6857 /* Only allowed if base reg not in list, or first in list. */ 6858 else if ((range & (1 << base_reg)) 6859 && (range & ((1 << base_reg) - 1))) 6860 as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); 6861 } 6862 } 6863} 6864 6865/* ARMv5TE load-consecutive (argument parse) 6866 Mode is like LDRH. 6867 6868 LDRccD R, mode 6869 STRccD R, mode. */ 6870 6871static void 6872do_ldrd (void) 6873{ 6874 constraint (inst.operands[0].reg % 2 != 0, 6875 _("first destination register must be even")); 6876 constraint (inst.operands[1].present 6877 && inst.operands[1].reg != inst.operands[0].reg + 1, 6878 _("can only load two consecutive registers")); 6879 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6880 constraint (!inst.operands[2].isreg, _("'[' expected")); 6881 6882 if (!inst.operands[1].present) 6883 inst.operands[1].reg = inst.operands[0].reg + 1; 6884 6885 if (inst.instruction & LOAD_BIT) 6886 { 6887 /* encode_arm_addr_mode_3 will diagnose overlap between the base 6888 register and the first register written; we have to diagnose 6889 overlap between the base and the second register written here. */ 6890 6891 if (inst.operands[2].reg == inst.operands[1].reg 6892 && (inst.operands[2].writeback || inst.operands[2].postind)) 6893 as_warn (_("base register written back, and overlaps " 6894 "second destination register")); 6895 6896 /* For an index-register load, the index register must not overlap the 6897 destination (even if not write-back). */ 6898 else if (inst.operands[2].immisreg 6899 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg 6900 || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) 6901 as_warn (_("index register overlaps destination register")); 6902 } 6903 6904 inst.instruction |= inst.operands[0].reg << 12; 6905 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); 6906} 6907 6908static void 6909do_ldrex (void) 6910{ 6911 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 6912 || inst.operands[1].postind || inst.operands[1].writeback 6913 || inst.operands[1].immisreg || inst.operands[1].shifted 6914 || inst.operands[1].negative 6915 /* This can arise if the programmer has written 6916 strex rN, rM, foo 6917 or if they have mistakenly used a register name as the last 6918 operand, eg: 6919 strex rN, rM, rX 6920 It is very difficult to distinguish between these two cases 6921 because "rX" might actually be a label. ie the register 6922 name has been occluded by a symbol of the same name. So we 6923 just generate a general 'bad addressing mode' type error 6924 message and leave it up to the programmer to discover the 6925 true cause and fix their mistake. */ 6926 || (inst.operands[1].reg == REG_PC), 6927 BAD_ADDR_MODE); 6928 6929 constraint (inst.reloc.exp.X_op != O_constant 6930 || inst.reloc.exp.X_add_number != 0, 6931 _("offset must be zero in ARM encoding")); 6932 6933 inst.instruction |= inst.operands[0].reg << 12; 6934 inst.instruction |= inst.operands[1].reg << 16; 6935 inst.reloc.type = BFD_RELOC_UNUSED; 6936} 6937 6938static void 6939do_ldrexd (void) 6940{ 6941 constraint (inst.operands[0].reg % 2 != 0, 6942 _("even register required")); 6943 constraint (inst.operands[1].present 6944 && inst.operands[1].reg != inst.operands[0].reg + 1, 6945 _("can only load two consecutive registers")); 6946 /* If op 1 were present and equal to PC, this function wouldn't 6947 have been called in the first place. */ 6948 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6949 6950 inst.instruction |= inst.operands[0].reg << 12; 6951 inst.instruction |= inst.operands[2].reg << 16; 6952} 6953 6954static void 6955do_ldst (void) 6956{ 6957 inst.instruction |= inst.operands[0].reg << 12; 6958 if (!inst.operands[1].isreg) 6959 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) 6960 return; 6961 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); 6962} 6963 6964static void 6965do_ldstt (void) 6966{ 6967 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 6968 reject [Rn,...]. */ 6969 if (inst.operands[1].preind) 6970 { 6971 constraint (inst.reloc.exp.X_op != O_constant || 6972 inst.reloc.exp.X_add_number != 0, 6973 _("this instruction requires a post-indexed address")); 6974 6975 inst.operands[1].preind = 0; 6976 inst.operands[1].postind = 1; 6977 inst.operands[1].writeback = 1; 6978 } 6979 inst.instruction |= inst.operands[0].reg << 12; 6980 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); 6981} 6982 6983/* Halfword and signed-byte load/store operations. */ 6984 6985static void 6986do_ldstv4 (void) 6987{ 6988 inst.instruction |= inst.operands[0].reg << 12; 6989 if (!inst.operands[1].isreg) 6990 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) 6991 return; 6992 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); 6993} 6994 6995static void 6996do_ldsttv4 (void) 6997{ 6998 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 6999 reject [Rn,...]. */ 7000 if (inst.operands[1].preind) 7001 { 7002 constraint (inst.reloc.exp.X_op != O_constant || 7003 inst.reloc.exp.X_add_number != 0, 7004 _("this instruction requires a post-indexed address")); 7005 7006 inst.operands[1].preind = 0; 7007 inst.operands[1].postind = 1; 7008 inst.operands[1].writeback = 1; 7009 } 7010 inst.instruction |= inst.operands[0].reg << 12; 7011 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); 7012} 7013 7014/* Co-processor register load/store. 7015 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ 7016static void 7017do_lstc (void) 7018{ 7019 inst.instruction |= inst.operands[0].reg << 8; 7020 inst.instruction |= inst.operands[1].reg << 12; 7021 encode_arm_cp_address (2, TRUE, TRUE, 0); 7022} 7023 7024static void 7025do_mlas (void) 7026{ 7027 /* This restriction does not apply to mls (nor to mla in v6 or later). */ 7028 if (inst.operands[0].reg == inst.operands[1].reg 7029 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) 7030 && !(inst.instruction & 0x00400000)) 7031 as_tsktsk (_("Rd and Rm should be different in mla")); 7032 7033 inst.instruction |= inst.operands[0].reg << 16; 7034 inst.instruction |= inst.operands[1].reg; 7035 inst.instruction |= inst.operands[2].reg << 8; 7036 inst.instruction |= inst.operands[3].reg << 12; 7037} 7038 7039static void 7040do_mov (void) 7041{ 7042 inst.instruction |= inst.operands[0].reg << 12; 7043 encode_arm_shifter_operand (1); 7044} 7045 7046/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ 7047static void 7048do_mov16 (void) 7049{ 7050 bfd_vma imm; 7051 bfd_boolean top; 7052 7053 top = (inst.instruction & 0x00400000) != 0; 7054 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, 7055 _(":lower16: not allowed this instruction")); 7056 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, 7057 _(":upper16: not allowed instruction")); 7058 inst.instruction |= inst.operands[0].reg << 12; 7059 if (inst.reloc.type == BFD_RELOC_UNUSED) 7060 { 7061 imm = inst.reloc.exp.X_add_number; 7062 /* The value is in two pieces: 0:11, 16:19. */ 7063 inst.instruction |= (imm & 0x00000fff); 7064 inst.instruction |= (imm & 0x0000f000) << 4; 7065 } 7066} 7067 7068static void do_vfp_nsyn_opcode (const char *); 7069 7070static int 7071do_vfp_nsyn_mrs (void) 7072{ 7073 if (inst.operands[0].isvec) 7074 { 7075 if (inst.operands[1].reg != 1) 7076 first_error (_("operand 1 must be FPSCR")); 7077 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 7078 memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); 7079 do_vfp_nsyn_opcode ("fmstat"); 7080 } 7081 else if (inst.operands[1].isvec) 7082 do_vfp_nsyn_opcode ("fmrx"); 7083 else 7084 return FAIL; 7085 7086 return SUCCESS; 7087} 7088 7089static int 7090do_vfp_nsyn_msr (void) 7091{ 7092 if (inst.operands[0].isvec) 7093 do_vfp_nsyn_opcode ("fmxr"); 7094 else 7095 return FAIL; 7096 7097 return SUCCESS; 7098} 7099 7100static void 7101do_vfp_vmrs (void) 7102{ 7103 int rt; 7104 7105 /* The destination register can be r0-r14 or APSR_nzcv */ 7106 if (inst.operands[0].reg > 14) 7107 { 7108 inst.error = BAD_PC; 7109 return; 7110 } 7111 7112 /* If the destination is r13 and not in ARM mode then unprefictable */ 7113 if (thumb_mode && inst.operands[0].reg == REG_SP) 7114 { 7115 inst.error = BAD_SP; 7116 return; 7117 } 7118 7119 /* If the destination is APSR_nzcv */ 7120 if (inst.operands[0].isvec && inst.operands[1].reg != 1) 7121 { 7122 inst.error = BAD_VMRS; 7123 return; 7124 } 7125 7126 if (inst.operands[0].isvec) 7127 rt = 15; 7128 else 7129 rt = inst.operands[0].reg; 7130 7131 /* Or in the registers to use */ 7132 inst.instruction |= rt << 12; 7133 inst.instruction |= inst.operands[1].reg << 16; 7134} 7135 7136static void 7137do_vfp_vmsr (void) 7138{ 7139 /* The destination register can be r0-r14 or APSR_nzcv */ 7140 if (inst.operands[1].reg > 14) 7141 { 7142 inst.error = BAD_PC; 7143 return; 7144 } 7145 7146 /* If the destination is r13 and not in ARM mode then unprefictable */ 7147 if (thumb_mode && inst.operands[0].reg == REG_SP) 7148 { 7149 inst.error = BAD_SP; 7150 return; 7151 } 7152 7153 /* Or in the registers to use */ 7154 inst.instruction |= inst.operands[1].reg << 12; 7155 inst.instruction |= inst.operands[0].reg << 16; 7156} 7157 7158static void 7159do_mrs (void) 7160{ 7161 if (do_vfp_nsyn_mrs () == SUCCESS) 7162 return; 7163 7164 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 7165 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) 7166 != (PSR_c|PSR_f), 7167 _("'CPSR' or 'SPSR' expected")); 7168 inst.instruction |= inst.operands[0].reg << 12; 7169 inst.instruction |= (inst.operands[1].imm & SPSR_BIT); 7170} 7171 7172/* Two possible forms: 7173 "{C|S}PSR_<field>, Rm", 7174 "{C|S}PSR_f, #expression". */ 7175 7176static void 7177do_msr (void) 7178{ 7179 if (do_vfp_nsyn_msr () == SUCCESS) 7180 return; 7181 7182 inst.instruction |= inst.operands[0].imm; 7183 if (inst.operands[1].isreg) 7184 inst.instruction |= inst.operands[1].reg; 7185 else 7186 { 7187 inst.instruction |= INST_IMMEDIATE; 7188 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 7189 inst.reloc.pc_rel = 0; 7190 } 7191} 7192 7193static void 7194do_mul (void) 7195{ 7196 if (!inst.operands[2].present) 7197 inst.operands[2].reg = inst.operands[0].reg; 7198 inst.instruction |= inst.operands[0].reg << 16; 7199 inst.instruction |= inst.operands[1].reg; 7200 inst.instruction |= inst.operands[2].reg << 8; 7201 7202 if (inst.operands[0].reg == inst.operands[1].reg 7203 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7204 as_tsktsk (_("Rd and Rm should be different in mul")); 7205} 7206 7207/* Long Multiply Parser 7208 UMULL RdLo, RdHi, Rm, Rs 7209 SMULL RdLo, RdHi, Rm, Rs 7210 UMLAL RdLo, RdHi, Rm, Rs 7211 SMLAL RdLo, RdHi, Rm, Rs. */ 7212 7213static void 7214do_mull (void) 7215{ 7216 inst.instruction |= inst.operands[0].reg << 12; 7217 inst.instruction |= inst.operands[1].reg << 16; 7218 inst.instruction |= inst.operands[2].reg; 7219 inst.instruction |= inst.operands[3].reg << 8; 7220 7221 /* rdhi, rdlo and rm must all be different. */ 7222 if (inst.operands[0].reg == inst.operands[1].reg 7223 || inst.operands[0].reg == inst.operands[2].reg 7224 || inst.operands[1].reg == inst.operands[2].reg) 7225 as_tsktsk (_("rdhi, rdlo and rm must all be different")); 7226} 7227 7228static void 7229do_nop (void) 7230{ 7231 if (inst.operands[0].present) 7232 { 7233 /* Architectural NOP hints are CPSR sets with no bits selected. */ 7234 inst.instruction &= 0xf0000000; 7235 inst.instruction |= 0x0320f000 + inst.operands[0].imm; 7236 } 7237} 7238 7239/* ARM V6 Pack Halfword Bottom Top instruction (argument parse). 7240 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 7241 Condition defaults to COND_ALWAYS. 7242 Error if Rd, Rn or Rm are R15. */ 7243 7244static void 7245do_pkhbt (void) 7246{ 7247 inst.instruction |= inst.operands[0].reg << 12; 7248 inst.instruction |= inst.operands[1].reg << 16; 7249 inst.instruction |= inst.operands[2].reg; 7250 if (inst.operands[3].present) 7251 encode_arm_shift (3); 7252} 7253 7254/* ARM V6 PKHTB (Argument Parse). */ 7255 7256static void 7257do_pkhtb (void) 7258{ 7259 if (!inst.operands[3].present) 7260 { 7261 /* If the shift specifier is omitted, turn the instruction 7262 into pkhbt rd, rm, rn. */ 7263 inst.instruction &= 0xfff00010; 7264 inst.instruction |= inst.operands[0].reg << 12; 7265 inst.instruction |= inst.operands[1].reg; 7266 inst.instruction |= inst.operands[2].reg << 16; 7267 } 7268 else 7269 { 7270 inst.instruction |= inst.operands[0].reg << 12; 7271 inst.instruction |= inst.operands[1].reg << 16; 7272 inst.instruction |= inst.operands[2].reg; 7273 encode_arm_shift (3); 7274 } 7275} 7276 7277/* ARMv5TE: Preload-Cache 7278 7279 PLD <addr_mode> 7280 7281 Syntactically, like LDR with B=1, W=0, L=1. */ 7282 7283static void 7284do_pld (void) 7285{ 7286 constraint (!inst.operands[0].isreg, 7287 _("'[' expected after PLD mnemonic")); 7288 constraint (inst.operands[0].postind, 7289 _("post-indexed expression used in preload instruction")); 7290 constraint (inst.operands[0].writeback, 7291 _("writeback used in preload instruction")); 7292 constraint (!inst.operands[0].preind, 7293 _("unindexed addressing used in preload instruction")); 7294 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7295} 7296 7297/* ARMv7: PLI <addr_mode> */ 7298static void 7299do_pli (void) 7300{ 7301 constraint (!inst.operands[0].isreg, 7302 _("'[' expected after PLI mnemonic")); 7303 constraint (inst.operands[0].postind, 7304 _("post-indexed expression used in preload instruction")); 7305 constraint (inst.operands[0].writeback, 7306 _("writeback used in preload instruction")); 7307 constraint (!inst.operands[0].preind, 7308 _("unindexed addressing used in preload instruction")); 7309 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7310 inst.instruction &= ~PRE_INDEX; 7311} 7312 7313static void 7314do_push_pop (void) 7315{ 7316 inst.operands[1] = inst.operands[0]; 7317 memset (&inst.operands[0], 0, sizeof inst.operands[0]); 7318 inst.operands[0].isreg = 1; 7319 inst.operands[0].writeback = 1; 7320 inst.operands[0].reg = REG_SP; 7321 do_ldmstm (); 7322} 7323 7324/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the 7325 word at the specified address and the following word 7326 respectively. 7327 Unconditionally executed. 7328 Error if Rn is R15. */ 7329 7330static void 7331do_rfe (void) 7332{ 7333 inst.instruction |= inst.operands[0].reg << 16; 7334 if (inst.operands[0].writeback) 7335 inst.instruction |= WRITE_BACK; 7336} 7337 7338/* ARM V6 ssat (argument parse). */ 7339 7340static void 7341do_ssat (void) 7342{ 7343 inst.instruction |= inst.operands[0].reg << 12; 7344 inst.instruction |= (inst.operands[1].imm - 1) << 16; 7345 inst.instruction |= inst.operands[2].reg; 7346 7347 if (inst.operands[3].present) 7348 encode_arm_shift (3); 7349} 7350 7351/* ARM V6 usat (argument parse). */ 7352 7353static void 7354do_usat (void) 7355{ 7356 inst.instruction |= inst.operands[0].reg << 12; 7357 inst.instruction |= inst.operands[1].imm << 16; 7358 inst.instruction |= inst.operands[2].reg; 7359 7360 if (inst.operands[3].present) 7361 encode_arm_shift (3); 7362} 7363 7364/* ARM V6 ssat16 (argument parse). */ 7365 7366static void 7367do_ssat16 (void) 7368{ 7369 inst.instruction |= inst.operands[0].reg << 12; 7370 inst.instruction |= ((inst.operands[1].imm - 1) << 16); 7371 inst.instruction |= inst.operands[2].reg; 7372} 7373 7374static void 7375do_usat16 (void) 7376{ 7377 inst.instruction |= inst.operands[0].reg << 12; 7378 inst.instruction |= inst.operands[1].imm << 16; 7379 inst.instruction |= inst.operands[2].reg; 7380} 7381 7382/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while 7383 preserving the other bits. 7384 7385 setend <endian_specifier>, where <endian_specifier> is either 7386 BE or LE. */ 7387 7388static void 7389do_setend (void) 7390{ 7391 if (inst.operands[0].imm) 7392 inst.instruction |= 0x200; 7393} 7394 7395static void 7396do_shift (void) 7397{ 7398 unsigned int Rm = (inst.operands[1].present 7399 ? inst.operands[1].reg 7400 : inst.operands[0].reg); 7401 7402 inst.instruction |= inst.operands[0].reg << 12; 7403 inst.instruction |= Rm; 7404 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ 7405 { 7406 inst.instruction |= inst.operands[2].reg << 8; 7407 inst.instruction |= SHIFT_BY_REG; 7408 } 7409 else 7410 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 7411} 7412 7413static void 7414do_smc (void) 7415{ 7416 inst.reloc.type = BFD_RELOC_ARM_SMC; 7417 inst.reloc.pc_rel = 0; 7418} 7419 7420static void 7421do_swi (void) 7422{ 7423 inst.reloc.type = BFD_RELOC_ARM_SWI; 7424 inst.reloc.pc_rel = 0; 7425} 7426 7427/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) 7428 SMLAxy{cond} Rd,Rm,Rs,Rn 7429 SMLAWy{cond} Rd,Rm,Rs,Rn 7430 Error if any register is R15. */ 7431 7432static void 7433do_smla (void) 7434{ 7435 inst.instruction |= inst.operands[0].reg << 16; 7436 inst.instruction |= inst.operands[1].reg; 7437 inst.instruction |= inst.operands[2].reg << 8; 7438 inst.instruction |= inst.operands[3].reg << 12; 7439} 7440 7441/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) 7442 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs 7443 Error if any register is R15. 7444 Warning if Rdlo == Rdhi. */ 7445 7446static void 7447do_smlal (void) 7448{ 7449 inst.instruction |= inst.operands[0].reg << 12; 7450 inst.instruction |= inst.operands[1].reg << 16; 7451 inst.instruction |= inst.operands[2].reg; 7452 inst.instruction |= inst.operands[3].reg << 8; 7453 7454 if (inst.operands[0].reg == inst.operands[1].reg) 7455 as_tsktsk (_("rdhi and rdlo must be different")); 7456} 7457 7458/* ARM V5E (El Segundo) signed-multiply (argument parse) 7459 SMULxy{cond} Rd,Rm,Rs 7460 Error if any register is R15. */ 7461 7462static void 7463do_smul (void) 7464{ 7465 inst.instruction |= inst.operands[0].reg << 16; 7466 inst.instruction |= inst.operands[1].reg; 7467 inst.instruction |= inst.operands[2].reg << 8; 7468} 7469 7470/* ARM V6 srs (argument parse). The variable fields in the encoding are 7471 the same for both ARM and Thumb-2. */ 7472 7473static void 7474do_srs (void) 7475{ 7476 int reg; 7477 7478 if (inst.operands[0].present) 7479 { 7480 reg = inst.operands[0].reg; 7481 constraint (reg != 13, _("SRS base register must be r13")); 7482 } 7483 else 7484 reg = 13; 7485 7486 inst.instruction |= reg << 16; 7487 inst.instruction |= inst.operands[1].imm; 7488 if (inst.operands[0].writeback || inst.operands[1].writeback) 7489 inst.instruction |= WRITE_BACK; 7490} 7491 7492/* ARM V6 strex (argument parse). */ 7493 7494static void 7495do_strex (void) 7496{ 7497 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 7498 || inst.operands[2].postind || inst.operands[2].writeback 7499 || inst.operands[2].immisreg || inst.operands[2].shifted 7500 || inst.operands[2].negative 7501 /* See comment in do_ldrex(). */ 7502 || (inst.operands[2].reg == REG_PC), 7503 BAD_ADDR_MODE); 7504 7505 constraint (inst.operands[0].reg == inst.operands[1].reg 7506 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); 7507 7508 constraint (inst.reloc.exp.X_op != O_constant 7509 || inst.reloc.exp.X_add_number != 0, 7510 _("offset must be zero in ARM encoding")); 7511 7512 inst.instruction |= inst.operands[0].reg << 12; 7513 inst.instruction |= inst.operands[1].reg; 7514 inst.instruction |= inst.operands[2].reg << 16; 7515 inst.reloc.type = BFD_RELOC_UNUSED; 7516} 7517 7518static void 7519do_strexd (void) 7520{ 7521 constraint (inst.operands[1].reg % 2 != 0, 7522 _("even register required")); 7523 constraint (inst.operands[2].present 7524 && inst.operands[2].reg != inst.operands[1].reg + 1, 7525 _("can only store two consecutive registers")); 7526 /* If op 2 were present and equal to PC, this function wouldn't 7527 have been called in the first place. */ 7528 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); 7529 7530 constraint (inst.operands[0].reg == inst.operands[1].reg 7531 || inst.operands[0].reg == inst.operands[1].reg + 1 7532 || inst.operands[0].reg == inst.operands[3].reg, 7533 BAD_OVERLAP); 7534 7535 inst.instruction |= inst.operands[0].reg << 12; 7536 inst.instruction |= inst.operands[1].reg; 7537 inst.instruction |= inst.operands[3].reg << 16; 7538} 7539 7540/* ARM V6 SXTAH extracts a 16-bit value from a register, sign 7541 extends it to 32-bits, and adds the result to a value in another 7542 register. You can specify a rotation by 0, 8, 16, or 24 bits 7543 before extracting the 16-bit value. 7544 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} 7545 Condition defaults to COND_ALWAYS. 7546 Error if any register uses R15. */ 7547 7548static void 7549do_sxtah (void) 7550{ 7551 inst.instruction |= inst.operands[0].reg << 12; 7552 inst.instruction |= inst.operands[1].reg << 16; 7553 inst.instruction |= inst.operands[2].reg; 7554 inst.instruction |= inst.operands[3].imm << 10; 7555} 7556 7557/* ARM V6 SXTH. 7558 7559 SXTH {<cond>} <Rd>, <Rm>{, <rotation>} 7560 Condition defaults to COND_ALWAYS. 7561 Error if any register uses R15. */ 7562 7563static void 7564do_sxth (void) 7565{ 7566 inst.instruction |= inst.operands[0].reg << 12; 7567 inst.instruction |= inst.operands[1].reg; 7568 inst.instruction |= inst.operands[2].imm << 10; 7569} 7570 7571/* VFP instructions. In a logical order: SP variant first, monad 7572 before dyad, arithmetic then move then load/store. */ 7573 7574static void 7575do_vfp_sp_monadic (void) 7576{ 7577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7578 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7579} 7580 7581static void 7582do_vfp_sp_dyadic (void) 7583{ 7584 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7585 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7586 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7587} 7588 7589static void 7590do_vfp_sp_compare_z (void) 7591{ 7592 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7593} 7594 7595static void 7596do_vfp_dp_sp_cvt (void) 7597{ 7598 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7599 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7600} 7601 7602static void 7603do_vfp_sp_dp_cvt (void) 7604{ 7605 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7606 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7607} 7608 7609static void 7610do_vfp_reg_from_sp (void) 7611{ 7612 inst.instruction |= inst.operands[0].reg << 12; 7613 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7614} 7615 7616static void 7617do_vfp_reg2_from_sp2 (void) 7618{ 7619 constraint (inst.operands[2].imm != 2, 7620 _("only two consecutive VFP SP registers allowed here")); 7621 inst.instruction |= inst.operands[0].reg << 12; 7622 inst.instruction |= inst.operands[1].reg << 16; 7623 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7624} 7625 7626static void 7627do_vfp_sp_from_reg (void) 7628{ 7629 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); 7630 inst.instruction |= inst.operands[1].reg << 12; 7631} 7632 7633static void 7634do_vfp_sp2_from_reg2 (void) 7635{ 7636 constraint (inst.operands[0].imm != 2, 7637 _("only two consecutive VFP SP registers allowed here")); 7638 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); 7639 inst.instruction |= inst.operands[1].reg << 12; 7640 inst.instruction |= inst.operands[2].reg << 16; 7641} 7642 7643static void 7644do_vfp_sp_ldst (void) 7645{ 7646 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7647 encode_arm_cp_address (1, FALSE, TRUE, 0); 7648} 7649 7650static void 7651do_vfp_dp_ldst (void) 7652{ 7653 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7654 encode_arm_cp_address (1, FALSE, TRUE, 0); 7655} 7656 7657 7658static void 7659vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) 7660{ 7661 if (inst.operands[0].writeback) 7662 inst.instruction |= WRITE_BACK; 7663 else 7664 constraint (ldstm_type != VFP_LDSTMIA, 7665 _("this addressing mode requires base-register writeback")); 7666 inst.instruction |= inst.operands[0].reg << 16; 7667 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); 7668 inst.instruction |= inst.operands[1].imm; 7669} 7670 7671static void 7672vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) 7673{ 7674 int count; 7675 7676 if (inst.operands[0].writeback) 7677 inst.instruction |= WRITE_BACK; 7678 else 7679 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, 7680 _("this addressing mode requires base-register writeback")); 7681 7682 inst.instruction |= inst.operands[0].reg << 16; 7683 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7684 7685 count = inst.operands[1].imm << 1; 7686 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) 7687 count += 1; 7688 7689 inst.instruction |= count; 7690} 7691 7692static void 7693do_vfp_sp_ldstmia (void) 7694{ 7695 vfp_sp_ldstm (VFP_LDSTMIA); 7696} 7697 7698static void 7699do_vfp_sp_ldstmdb (void) 7700{ 7701 vfp_sp_ldstm (VFP_LDSTMDB); 7702} 7703 7704static void 7705do_vfp_dp_ldstmia (void) 7706{ 7707 vfp_dp_ldstm (VFP_LDSTMIA); 7708} 7709 7710static void 7711do_vfp_dp_ldstmdb (void) 7712{ 7713 vfp_dp_ldstm (VFP_LDSTMDB); 7714} 7715 7716static void 7717do_vfp_xp_ldstmia (void) 7718{ 7719 vfp_dp_ldstm (VFP_LDSTMIAX); 7720} 7721 7722static void 7723do_vfp_xp_ldstmdb (void) 7724{ 7725 vfp_dp_ldstm (VFP_LDSTMDBX); 7726} 7727 7728static void 7729do_vfp_dp_rd_rm (void) 7730{ 7731 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7732 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7733} 7734 7735static void 7736do_vfp_dp_rn_rd (void) 7737{ 7738 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); 7739 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7740} 7741 7742static void 7743do_vfp_dp_rd_rn (void) 7744{ 7745 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7746 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7747} 7748 7749static void 7750do_vfp_dp_rd_rn_rm (void) 7751{ 7752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7753 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7754 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); 7755} 7756 7757static void 7758do_vfp_dp_rd (void) 7759{ 7760 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7761} 7762 7763static void 7764do_vfp_dp_rm_rd_rn (void) 7765{ 7766 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); 7767 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7768 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); 7769} 7770 7771/* VFPv3 instructions. */ 7772static void 7773do_vfp_sp_const (void) 7774{ 7775 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7776 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7777 inst.instruction |= (inst.operands[1].imm & 0x0f); 7778} 7779 7780static void 7781do_vfp_dp_const (void) 7782{ 7783 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7784 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7785 inst.instruction |= (inst.operands[1].imm & 0x0f); 7786} 7787 7788static void 7789vfp_conv (int srcsize) 7790{ 7791 unsigned immbits = srcsize - inst.operands[1].imm; 7792 inst.instruction |= (immbits & 1) << 5; 7793 inst.instruction |= (immbits >> 1); 7794} 7795 7796static void 7797do_vfp_sp_conv_16 (void) 7798{ 7799 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7800 vfp_conv (16); 7801} 7802 7803static void 7804do_vfp_dp_conv_16 (void) 7805{ 7806 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7807 vfp_conv (16); 7808} 7809 7810static void 7811do_vfp_sp_conv_32 (void) 7812{ 7813 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7814 vfp_conv (32); 7815} 7816 7817static void 7818do_vfp_dp_conv_32 (void) 7819{ 7820 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7821 vfp_conv (32); 7822} 7823 7824 7825/* FPA instructions. Also in a logical order. */ 7826 7827static void 7828do_fpa_cmp (void) 7829{ 7830 inst.instruction |= inst.operands[0].reg << 16; 7831 inst.instruction |= inst.operands[1].reg; 7832} 7833 7834static void 7835do_fpa_ldmstm (void) 7836{ 7837 inst.instruction |= inst.operands[0].reg << 12; 7838 switch (inst.operands[1].imm) 7839 { 7840 case 1: inst.instruction |= CP_T_X; break; 7841 case 2: inst.instruction |= CP_T_Y; break; 7842 case 3: inst.instruction |= CP_T_Y | CP_T_X; break; 7843 case 4: break; 7844 default: abort (); 7845 } 7846 7847 if (inst.instruction & (PRE_INDEX | INDEX_UP)) 7848 { 7849 /* The instruction specified "ea" or "fd", so we can only accept 7850 [Rn]{!}. The instruction does not really support stacking or 7851 unstacking, so we have to emulate these by setting appropriate 7852 bits and offsets. */ 7853 constraint (inst.reloc.exp.X_op != O_constant 7854 || inst.reloc.exp.X_add_number != 0, 7855 _("this instruction does not support indexing")); 7856 7857 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) 7858 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; 7859 7860 if (!(inst.instruction & INDEX_UP)) 7861 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; 7862 7863 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) 7864 { 7865 inst.operands[2].preind = 0; 7866 inst.operands[2].postind = 1; 7867 } 7868 } 7869 7870 encode_arm_cp_address (2, TRUE, TRUE, 0); 7871} 7872 7873 7874/* iWMMXt instructions: strictly in alphabetical order. */ 7875 7876static void 7877do_iwmmxt_tandorc (void) 7878{ 7879 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); 7880} 7881 7882static void 7883do_iwmmxt_textrc (void) 7884{ 7885 inst.instruction |= inst.operands[0].reg << 12; 7886 inst.instruction |= inst.operands[1].imm; 7887} 7888 7889static void 7890do_iwmmxt_textrm (void) 7891{ 7892 inst.instruction |= inst.operands[0].reg << 12; 7893 inst.instruction |= inst.operands[1].reg << 16; 7894 inst.instruction |= inst.operands[2].imm; 7895} 7896 7897static void 7898do_iwmmxt_tinsr (void) 7899{ 7900 inst.instruction |= inst.operands[0].reg << 16; 7901 inst.instruction |= inst.operands[1].reg << 12; 7902 inst.instruction |= inst.operands[2].imm; 7903} 7904 7905static void 7906do_iwmmxt_tmia (void) 7907{ 7908 inst.instruction |= inst.operands[0].reg << 5; 7909 inst.instruction |= inst.operands[1].reg; 7910 inst.instruction |= inst.operands[2].reg << 12; 7911} 7912 7913static void 7914do_iwmmxt_waligni (void) 7915{ 7916 inst.instruction |= inst.operands[0].reg << 12; 7917 inst.instruction |= inst.operands[1].reg << 16; 7918 inst.instruction |= inst.operands[2].reg; 7919 inst.instruction |= inst.operands[3].imm << 20; 7920} 7921 7922static void 7923do_iwmmxt_wmerge (void) 7924{ 7925 inst.instruction |= inst.operands[0].reg << 12; 7926 inst.instruction |= inst.operands[1].reg << 16; 7927 inst.instruction |= inst.operands[2].reg; 7928 inst.instruction |= inst.operands[3].imm << 21; 7929} 7930 7931static void 7932do_iwmmxt_wmov (void) 7933{ 7934 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ 7935 inst.instruction |= inst.operands[0].reg << 12; 7936 inst.instruction |= inst.operands[1].reg << 16; 7937 inst.instruction |= inst.operands[1].reg; 7938} 7939 7940static void 7941do_iwmmxt_wldstbh (void) 7942{ 7943 int reloc; 7944 inst.instruction |= inst.operands[0].reg << 12; 7945 if (thumb_mode) 7946 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; 7947 else 7948 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; 7949 encode_arm_cp_address (1, TRUE, FALSE, reloc); 7950} 7951 7952static void 7953do_iwmmxt_wldstw (void) 7954{ 7955 /* RIWR_RIWC clears .isreg for a control register. */ 7956 if (!inst.operands[0].isreg) 7957 { 7958 constraint (inst.cond != COND_ALWAYS, BAD_COND); 7959 inst.instruction |= 0xf0000000; 7960 } 7961 7962 inst.instruction |= inst.operands[0].reg << 12; 7963 encode_arm_cp_address (1, TRUE, TRUE, 0); 7964} 7965 7966static void 7967do_iwmmxt_wldstd (void) 7968{ 7969 inst.instruction |= inst.operands[0].reg << 12; 7970 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) 7971 && inst.operands[1].immisreg) 7972 { 7973 inst.instruction &= ~0x1a000ff; 7974 inst.instruction |= (0xf << 28); 7975 if (inst.operands[1].preind) 7976 inst.instruction |= PRE_INDEX; 7977 if (!inst.operands[1].negative) 7978 inst.instruction |= INDEX_UP; 7979 if (inst.operands[1].writeback) 7980 inst.instruction |= WRITE_BACK; 7981 inst.instruction |= inst.operands[1].reg << 16; 7982 inst.instruction |= inst.reloc.exp.X_add_number << 4; 7983 inst.instruction |= inst.operands[1].imm; 7984 } 7985 else 7986 encode_arm_cp_address (1, TRUE, FALSE, 0); 7987} 7988 7989static void 7990do_iwmmxt_wshufh (void) 7991{ 7992 inst.instruction |= inst.operands[0].reg << 12; 7993 inst.instruction |= inst.operands[1].reg << 16; 7994 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); 7995 inst.instruction |= (inst.operands[2].imm & 0x0f); 7996} 7997 7998static void 7999do_iwmmxt_wzero (void) 8000{ 8001 /* WZERO reg is an alias for WANDN reg, reg, reg. */ 8002 inst.instruction |= inst.operands[0].reg; 8003 inst.instruction |= inst.operands[0].reg << 12; 8004 inst.instruction |= inst.operands[0].reg << 16; 8005} 8006 8007static void 8008do_iwmmxt_wrwrwr_or_imm5 (void) 8009{ 8010 if (inst.operands[2].isreg) 8011 do_rd_rn_rm (); 8012 else { 8013 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), 8014 _("immediate operand requires iWMMXt2")); 8015 do_rd_rn (); 8016 if (inst.operands[2].imm == 0) 8017 { 8018 switch ((inst.instruction >> 20) & 0xf) 8019 { 8020 case 4: 8021 case 5: 8022 case 6: 8023 case 7: 8024 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ 8025 inst.operands[2].imm = 16; 8026 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); 8027 break; 8028 case 8: 8029 case 9: 8030 case 10: 8031 case 11: 8032 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ 8033 inst.operands[2].imm = 32; 8034 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); 8035 break; 8036 case 12: 8037 case 13: 8038 case 14: 8039 case 15: 8040 { 8041 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ 8042 unsigned long wrn; 8043 wrn = (inst.instruction >> 16) & 0xf; 8044 inst.instruction &= 0xff0fff0f; 8045 inst.instruction |= wrn; 8046 /* Bail out here; the instruction is now assembled. */ 8047 return; 8048 } 8049 } 8050 } 8051 /* Map 32 -> 0, etc. */ 8052 inst.operands[2].imm &= 0x1f; 8053 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); 8054 } 8055} 8056 8057/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register 8058 operations first, then control, shift, and load/store. */ 8059 8060/* Insns like "foo X,Y,Z". */ 8061 8062static void 8063do_mav_triple (void) 8064{ 8065 inst.instruction |= inst.operands[0].reg << 16; 8066 inst.instruction |= inst.operands[1].reg; 8067 inst.instruction |= inst.operands[2].reg << 12; 8068} 8069 8070/* Insns like "foo W,X,Y,Z". 8071 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ 8072 8073static void 8074do_mav_quad (void) 8075{ 8076 inst.instruction |= inst.operands[0].reg << 5; 8077 inst.instruction |= inst.operands[1].reg << 12; 8078 inst.instruction |= inst.operands[2].reg << 16; 8079 inst.instruction |= inst.operands[3].reg; 8080} 8081 8082/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ 8083static void 8084do_mav_dspsc (void) 8085{ 8086 inst.instruction |= inst.operands[1].reg << 12; 8087} 8088 8089/* Maverick shift immediate instructions. 8090 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. 8091 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ 8092 8093static void 8094do_mav_shift (void) 8095{ 8096 int imm = inst.operands[2].imm; 8097 8098 inst.instruction |= inst.operands[0].reg << 12; 8099 inst.instruction |= inst.operands[1].reg << 16; 8100 8101 /* Bits 0-3 of the insn should have bits 0-3 of the immediate. 8102 Bits 5-7 of the insn should have bits 4-6 of the immediate. 8103 Bit 4 should be 0. */ 8104 imm = (imm & 0xf) | ((imm & 0x70) << 1); 8105 8106 inst.instruction |= imm; 8107} 8108 8109/* XScale instructions. Also sorted arithmetic before move. */ 8110 8111/* Xscale multiply-accumulate (argument parse) 8112 MIAcc acc0,Rm,Rs 8113 MIAPHcc acc0,Rm,Rs 8114 MIAxycc acc0,Rm,Rs. */ 8115 8116static void 8117do_xsc_mia (void) 8118{ 8119 inst.instruction |= inst.operands[1].reg; 8120 inst.instruction |= inst.operands[2].reg << 12; 8121} 8122 8123/* Xscale move-accumulator-register (argument parse) 8124 8125 MARcc acc0,RdLo,RdHi. */ 8126 8127static void 8128do_xsc_mar (void) 8129{ 8130 inst.instruction |= inst.operands[1].reg << 12; 8131 inst.instruction |= inst.operands[2].reg << 16; 8132} 8133 8134/* Xscale move-register-accumulator (argument parse) 8135 8136 MRAcc RdLo,RdHi,acc0. */ 8137 8138static void 8139do_xsc_mra (void) 8140{ 8141 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); 8142 inst.instruction |= inst.operands[0].reg << 12; 8143 inst.instruction |= inst.operands[1].reg << 16; 8144} 8145 8146/* Encoding functions relevant only to Thumb. */ 8147 8148/* inst.operands[i] is a shifted-register operand; encode 8149 it into inst.instruction in the format used by Thumb32. */ 8150 8151static void 8152encode_thumb32_shifted_operand (int i) 8153{ 8154 unsigned int value = inst.reloc.exp.X_add_number; 8155 unsigned int shift = inst.operands[i].shift_kind; 8156 8157 constraint (inst.operands[i].immisreg, 8158 _("shift by register not allowed in thumb mode")); 8159 inst.instruction |= inst.operands[i].reg; 8160 if (shift == SHIFT_RRX) 8161 inst.instruction |= SHIFT_ROR << 4; 8162 else 8163 { 8164 constraint (inst.reloc.exp.X_op != O_constant, 8165 _("expression too complex")); 8166 8167 constraint (value > 32 8168 || (value == 32 && (shift == SHIFT_LSL 8169 || shift == SHIFT_ROR)), 8170 _("shift expression is too large")); 8171 8172 if (value == 0) 8173 shift = SHIFT_LSL; 8174 else if (value == 32) 8175 value = 0; 8176 8177 inst.instruction |= shift << 4; 8178 inst.instruction |= (value & 0x1c) << 10; 8179 inst.instruction |= (value & 0x03) << 6; 8180 } 8181} 8182 8183 8184/* inst.operands[i] was set up by parse_address. Encode it into a 8185 Thumb32 format load or store instruction. Reject forms that cannot 8186 be used with such instructions. If is_t is true, reject forms that 8187 cannot be used with a T instruction; if is_d is true, reject forms 8188 that cannot be used with a D instruction. */ 8189 8190static void 8191encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) 8192{ 8193 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); 8194 8195 constraint (!inst.operands[i].isreg, 8196 _("Instruction does not support =N addresses")); 8197 8198 inst.instruction |= inst.operands[i].reg << 16; 8199 if (inst.operands[i].immisreg) 8200 { 8201 constraint (is_pc, _("cannot use register index with PC-relative addressing")); 8202 constraint (is_t || is_d, _("cannot use register index with this instruction")); 8203 constraint (inst.operands[i].negative, 8204 _("Thumb does not support negative register indexing")); 8205 constraint (inst.operands[i].postind, 8206 _("Thumb does not support register post-indexing")); 8207 constraint (inst.operands[i].writeback, 8208 _("Thumb does not support register indexing with writeback")); 8209 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, 8210 _("Thumb supports only LSL in shifted register indexing")); 8211 8212 inst.instruction |= inst.operands[i].imm; 8213 if (inst.operands[i].shifted) 8214 { 8215 constraint (inst.reloc.exp.X_op != O_constant, 8216 _("expression too complex")); 8217 constraint (inst.reloc.exp.X_add_number < 0 8218 || inst.reloc.exp.X_add_number > 3, 8219 _("shift out of range")); 8220 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8221 } 8222 inst.reloc.type = BFD_RELOC_UNUSED; 8223 } 8224 else if (inst.operands[i].preind) 8225 { 8226 constraint (is_pc && inst.operands[i].writeback, 8227 _("cannot use writeback with PC-relative addressing")); 8228 constraint (is_t && inst.operands[i].writeback, 8229 _("cannot use writeback with this instruction")); 8230 8231 if (is_d) 8232 { 8233 inst.instruction |= 0x01000000; 8234 if (inst.operands[i].writeback) 8235 inst.instruction |= 0x00200000; 8236 } 8237 else 8238 { 8239 inst.instruction |= 0x00000c00; 8240 if (inst.operands[i].writeback) 8241 inst.instruction |= 0x00000100; 8242 } 8243 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8244 } 8245 else if (inst.operands[i].postind) 8246 { 8247 assert (inst.operands[i].writeback); 8248 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); 8249 constraint (is_t, _("cannot use post-indexing with this instruction")); 8250 8251 if (is_d) 8252 inst.instruction |= 0x00200000; 8253 else 8254 inst.instruction |= 0x00000900; 8255 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8256 } 8257 else /* unindexed - only for coprocessor */ 8258 inst.error = _("instruction does not accept unindexed addressing"); 8259} 8260 8261/* Table of Thumb instructions which exist in both 16- and 32-bit 8262 encodings (the latter only in post-V6T2 cores). The index is the 8263 value used in the insns table below. When there is more than one 8264 possible 16-bit encoding for the instruction, this table always 8265 holds variant (1). 8266 Also contains several pseudo-instructions used during relaxation. */ 8267#define T16_32_TAB \ 8268 X(adc, 4140, eb400000), \ 8269 X(adcs, 4140, eb500000), \ 8270 X(add, 1c00, eb000000), \ 8271 X(adds, 1c00, eb100000), \ 8272 X(addi, 0000, f1000000), \ 8273 X(addis, 0000, f1100000), \ 8274 X(add_pc,000f, f20f0000), \ 8275 X(add_sp,000d, f10d0000), \ 8276 X(adr, 000f, f20f0000), \ 8277 X(and, 4000, ea000000), \ 8278 X(ands, 4000, ea100000), \ 8279 X(asr, 1000, fa40f000), \ 8280 X(asrs, 1000, fa50f000), \ 8281 X(b, e000, f000b000), \ 8282 X(bcond, d000, f0008000), \ 8283 X(bic, 4380, ea200000), \ 8284 X(bics, 4380, ea300000), \ 8285 X(cmn, 42c0, eb100f00), \ 8286 X(cmp, 2800, ebb00f00), \ 8287 X(cpsie, b660, f3af8400), \ 8288 X(cpsid, b670, f3af8600), \ 8289 X(cpy, 4600, ea4f0000), \ 8290 X(dec_sp,80dd, f1ad0d00), \ 8291 X(eor, 4040, ea800000), \ 8292 X(eors, 4040, ea900000), \ 8293 X(inc_sp,00dd, f10d0d00), \ 8294 X(ldmia, c800, e8900000), \ 8295 X(ldr, 6800, f8500000), \ 8296 X(ldrb, 7800, f8100000), \ 8297 X(ldrh, 8800, f8300000), \ 8298 X(ldrsb, 5600, f9100000), \ 8299 X(ldrsh, 5e00, f9300000), \ 8300 X(ldr_pc,4800, f85f0000), \ 8301 X(ldr_pc2,4800, f85f0000), \ 8302 X(ldr_sp,9800, f85d0000), \ 8303 X(lsl, 0000, fa00f000), \ 8304 X(lsls, 0000, fa10f000), \ 8305 X(lsr, 0800, fa20f000), \ 8306 X(lsrs, 0800, fa30f000), \ 8307 X(mov, 2000, ea4f0000), \ 8308 X(movs, 2000, ea5f0000), \ 8309 X(mul, 4340, fb00f000), \ 8310 X(muls, 4340, ffffffff), /* no 32b muls */ \ 8311 X(mvn, 43c0, ea6f0000), \ 8312 X(mvns, 43c0, ea7f0000), \ 8313 X(neg, 4240, f1c00000), /* rsb #0 */ \ 8314 X(negs, 4240, f1d00000), /* rsbs #0 */ \ 8315 X(orr, 4300, ea400000), \ 8316 X(orrs, 4300, ea500000), \ 8317 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ 8318 X(push, b400, e92d0000), /* stmdb sp!,... */ \ 8319 X(rev, ba00, fa90f080), \ 8320 X(rev16, ba40, fa90f090), \ 8321 X(revsh, bac0, fa90f0b0), \ 8322 X(ror, 41c0, fa60f000), \ 8323 X(rors, 41c0, fa70f000), \ 8324 X(sbc, 4180, eb600000), \ 8325 X(sbcs, 4180, eb700000), \ 8326 X(stmia, c000, e8800000), \ 8327 X(str, 6000, f8400000), \ 8328 X(strb, 7000, f8000000), \ 8329 X(strh, 8000, f8200000), \ 8330 X(str_sp,9000, f84d0000), \ 8331 X(sub, 1e00, eba00000), \ 8332 X(subs, 1e00, ebb00000), \ 8333 X(subi, 8000, f1a00000), \ 8334 X(subis, 8000, f1b00000), \ 8335 X(sxtb, b240, fa4ff080), \ 8336 X(sxth, b200, fa0ff080), \ 8337 X(tst, 4200, ea100f00), \ 8338 X(uxtb, b2c0, fa5ff080), \ 8339 X(uxth, b280, fa1ff080), \ 8340 X(nop, bf00, f3af8000), \ 8341 X(yield, bf10, f3af8001), \ 8342 X(wfe, bf20, f3af8002), \ 8343 X(wfi, bf30, f3af8003), \ 8344 X(sev, bf40, f3af9004), /* typo, 8004? */ 8345 8346/* To catch errors in encoding functions, the codes are all offset by 8347 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined 8348 as 16-bit instructions. */ 8349#define X(a,b,c) T_MNEM_##a 8350enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; 8351#undef X 8352 8353#define X(a,b,c) 0x##b 8354static const unsigned short thumb_op16[] = { T16_32_TAB }; 8355#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) 8356#undef X 8357 8358#define X(a,b,c) 0x##c 8359static const unsigned int thumb_op32[] = { T16_32_TAB }; 8360#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) 8361#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) 8362#undef X 8363#undef T16_32_TAB 8364 8365/* Thumb instruction encoders, in alphabetical order. */ 8366 8367/* ADDW or SUBW. */ 8368static void 8369do_t_add_sub_w (void) 8370{ 8371 int Rd, Rn; 8372 8373 Rd = inst.operands[0].reg; 8374 Rn = inst.operands[1].reg; 8375 8376 constraint (Rd == 15, _("PC not allowed as destination")); 8377 inst.instruction |= (Rn << 16) | (Rd << 8); 8378 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8379} 8380 8381/* Parse an add or subtract instruction. We get here with inst.instruction 8382 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ 8383 8384static void 8385do_t_add_sub (void) 8386{ 8387 int Rd, Rs, Rn; 8388 8389 Rd = inst.operands[0].reg; 8390 Rs = (inst.operands[1].present 8391 ? inst.operands[1].reg /* Rd, Rs, foo */ 8392 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8393 8394 if (unified_syntax) 8395 { 8396 bfd_boolean flags; 8397 bfd_boolean narrow; 8398 int opcode; 8399 8400 flags = (inst.instruction == T_MNEM_adds 8401 || inst.instruction == T_MNEM_subs); 8402 if (flags) 8403 narrow = (current_it_mask == 0); 8404 else 8405 narrow = (current_it_mask != 0); 8406 if (!inst.operands[2].isreg) 8407 { 8408 int add; 8409 8410 add = (inst.instruction == T_MNEM_add 8411 || inst.instruction == T_MNEM_adds); 8412 opcode = 0; 8413 if (inst.size_req != 4) 8414 { 8415 /* Attempt to use a narrow opcode, with relaxation if 8416 appropriate. */ 8417 if (Rd == REG_SP && Rs == REG_SP && !flags) 8418 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; 8419 else if (Rd <= 7 && Rs == REG_SP && add && !flags) 8420 opcode = T_MNEM_add_sp; 8421 else if (Rd <= 7 && Rs == REG_PC && add && !flags) 8422 opcode = T_MNEM_add_pc; 8423 else if (Rd <= 7 && Rs <= 7 && narrow) 8424 { 8425 if (flags) 8426 opcode = add ? T_MNEM_addis : T_MNEM_subis; 8427 else 8428 opcode = add ? T_MNEM_addi : T_MNEM_subi; 8429 } 8430 if (opcode) 8431 { 8432 inst.instruction = THUMB_OP16(opcode); 8433 inst.instruction |= (Rd << 4) | Rs; 8434 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8435 if (inst.size_req != 2) 8436 inst.relax = opcode; 8437 } 8438 else 8439 constraint (inst.size_req == 2, BAD_HIREG); 8440 } 8441 if (inst.size_req == 4 8442 || (inst.size_req != 2 && !opcode)) 8443 { 8444 if (Rd == REG_PC) 8445 { 8446 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, 8447 _("only SUBS PC, LR, #const allowed")); 8448 constraint (inst.reloc.exp.X_op != O_constant, 8449 _("expression too complex")); 8450 constraint (inst.reloc.exp.X_add_number < 0 8451 || inst.reloc.exp.X_add_number > 0xff, 8452 _("immediate value out of range")); 8453 inst.instruction = T2_SUBS_PC_LR 8454 | inst.reloc.exp.X_add_number; 8455 inst.reloc.type = BFD_RELOC_UNUSED; 8456 return; 8457 } 8458 else if (Rs == REG_PC) 8459 { 8460 /* Always use addw/subw. */ 8461 inst.instruction = add ? 0xf20f0000 : 0xf2af0000; 8462 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8463 } 8464 else 8465 { 8466 inst.instruction = THUMB_OP32 (inst.instruction); 8467 inst.instruction = (inst.instruction & 0xe1ffffff) 8468 | 0x10000000; 8469 if (flags) 8470 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8471 else 8472 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; 8473 } 8474 inst.instruction |= Rd << 8; 8475 inst.instruction |= Rs << 16; 8476 } 8477 } 8478 else 8479 { 8480 Rn = inst.operands[2].reg; 8481 /* See if we can do this with a 16-bit instruction. */ 8482 if (!inst.operands[2].shifted && inst.size_req != 4) 8483 { 8484 if (Rd > 7 || Rs > 7 || Rn > 7) 8485 narrow = FALSE; 8486 8487 if (narrow) 8488 { 8489 inst.instruction = ((inst.instruction == T_MNEM_adds 8490 || inst.instruction == T_MNEM_add) 8491 ? T_OPCODE_ADD_R3 8492 : T_OPCODE_SUB_R3); 8493 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8494 return; 8495 } 8496 8497 if (inst.instruction == T_MNEM_add) 8498 { 8499 if (Rd == Rs) 8500 { 8501 inst.instruction = T_OPCODE_ADD_HI; 8502 inst.instruction |= (Rd & 8) << 4; 8503 inst.instruction |= (Rd & 7); 8504 inst.instruction |= Rn << 3; 8505 return; 8506 } 8507 /* ... because addition is commutative! */ 8508 else if (Rd == Rn) 8509 { 8510 inst.instruction = T_OPCODE_ADD_HI; 8511 inst.instruction |= (Rd & 8) << 4; 8512 inst.instruction |= (Rd & 7); 8513 inst.instruction |= Rs << 3; 8514 return; 8515 } 8516 } 8517 } 8518 /* If we get here, it can't be done in 16 bits. */ 8519 constraint (inst.operands[2].shifted && inst.operands[2].immisreg, 8520 _("shift must be constant")); 8521 inst.instruction = THUMB_OP32 (inst.instruction); 8522 inst.instruction |= Rd << 8; 8523 inst.instruction |= Rs << 16; 8524 encode_thumb32_shifted_operand (2); 8525 } 8526 } 8527 else 8528 { 8529 constraint (inst.instruction == T_MNEM_adds 8530 || inst.instruction == T_MNEM_subs, 8531 BAD_THUMB32); 8532 8533 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ 8534 { 8535 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) 8536 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), 8537 BAD_HIREG); 8538 8539 inst.instruction = (inst.instruction == T_MNEM_add 8540 ? 0x0000 : 0x8000); 8541 inst.instruction |= (Rd << 4) | Rs; 8542 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8543 return; 8544 } 8545 8546 Rn = inst.operands[2].reg; 8547 constraint (inst.operands[2].shifted, _("unshifted register required")); 8548 8549 /* We now have Rd, Rs, and Rn set to registers. */ 8550 if (Rd > 7 || Rs > 7 || Rn > 7) 8551 { 8552 /* Can't do this for SUB. */ 8553 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); 8554 inst.instruction = T_OPCODE_ADD_HI; 8555 inst.instruction |= (Rd & 8) << 4; 8556 inst.instruction |= (Rd & 7); 8557 if (Rs == Rd) 8558 inst.instruction |= Rn << 3; 8559 else if (Rn == Rd) 8560 inst.instruction |= Rs << 3; 8561 else 8562 constraint (1, _("dest must overlap one source register")); 8563 } 8564 else 8565 { 8566 inst.instruction = (inst.instruction == T_MNEM_add 8567 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); 8568 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8569 } 8570 } 8571} 8572 8573static void 8574do_t_adr (void) 8575{ 8576 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) 8577 { 8578 /* Defer to section relaxation. */ 8579 inst.relax = inst.instruction; 8580 inst.instruction = THUMB_OP16 (inst.instruction); 8581 inst.instruction |= inst.operands[0].reg << 4; 8582 } 8583 else if (unified_syntax && inst.size_req != 2) 8584 { 8585 /* Generate a 32-bit opcode. */ 8586 inst.instruction = THUMB_OP32 (inst.instruction); 8587 inst.instruction |= inst.operands[0].reg << 8; 8588 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; 8589 inst.reloc.pc_rel = 1; 8590 } 8591 else 8592 { 8593 /* Generate a 16-bit opcode. */ 8594 inst.instruction = THUMB_OP16 (inst.instruction); 8595 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8596 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ 8597 inst.reloc.pc_rel = 1; 8598 8599 inst.instruction |= inst.operands[0].reg << 4; 8600 } 8601} 8602 8603/* Arithmetic instructions for which there is just one 16-bit 8604 instruction encoding, and it allows only two low registers. 8605 For maximal compatibility with ARM syntax, we allow three register 8606 operands even when Thumb-32 instructions are not available, as long 8607 as the first two are identical. For instance, both "sbc r0,r1" and 8608 "sbc r0,r0,r1" are allowed. */ 8609static void 8610do_t_arit3 (void) 8611{ 8612 int Rd, Rs, Rn; 8613 8614 Rd = inst.operands[0].reg; 8615 Rs = (inst.operands[1].present 8616 ? inst.operands[1].reg /* Rd, Rs, foo */ 8617 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8618 Rn = inst.operands[2].reg; 8619 8620 if (unified_syntax) 8621 { 8622 if (!inst.operands[2].isreg) 8623 { 8624 /* For an immediate, we always generate a 32-bit opcode; 8625 section relaxation will shrink it later if possible. */ 8626 inst.instruction = THUMB_OP32 (inst.instruction); 8627 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8628 inst.instruction |= Rd << 8; 8629 inst.instruction |= Rs << 16; 8630 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8631 } 8632 else 8633 { 8634 bfd_boolean narrow; 8635 8636 /* See if we can do this with a 16-bit instruction. */ 8637 if (THUMB_SETS_FLAGS (inst.instruction)) 8638 narrow = current_it_mask == 0; 8639 else 8640 narrow = current_it_mask != 0; 8641 8642 if (Rd > 7 || Rn > 7 || Rs > 7) 8643 narrow = FALSE; 8644 if (inst.operands[2].shifted) 8645 narrow = FALSE; 8646 if (inst.size_req == 4) 8647 narrow = FALSE; 8648 8649 if (narrow 8650 && Rd == Rs) 8651 { 8652 inst.instruction = THUMB_OP16 (inst.instruction); 8653 inst.instruction |= Rd; 8654 inst.instruction |= Rn << 3; 8655 return; 8656 } 8657 8658 /* If we get here, it can't be done in 16 bits. */ 8659 constraint (inst.operands[2].shifted 8660 && inst.operands[2].immisreg, 8661 _("shift must be constant")); 8662 inst.instruction = THUMB_OP32 (inst.instruction); 8663 inst.instruction |= Rd << 8; 8664 inst.instruction |= Rs << 16; 8665 encode_thumb32_shifted_operand (2); 8666 } 8667 } 8668 else 8669 { 8670 /* On its face this is a lie - the instruction does set the 8671 flags. However, the only supported mnemonic in this mode 8672 says it doesn't. */ 8673 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8674 8675 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8676 _("unshifted register required")); 8677 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8678 constraint (Rd != Rs, 8679 _("dest and source1 must be the same register")); 8680 8681 inst.instruction = THUMB_OP16 (inst.instruction); 8682 inst.instruction |= Rd; 8683 inst.instruction |= Rn << 3; 8684 } 8685} 8686 8687/* Similarly, but for instructions where the arithmetic operation is 8688 commutative, so we can allow either of them to be different from 8689 the destination operand in a 16-bit instruction. For instance, all 8690 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are 8691 accepted. */ 8692static void 8693do_t_arit3c (void) 8694{ 8695 int Rd, Rs, Rn; 8696 8697 Rd = inst.operands[0].reg; 8698 Rs = (inst.operands[1].present 8699 ? inst.operands[1].reg /* Rd, Rs, foo */ 8700 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8701 Rn = inst.operands[2].reg; 8702 8703 if (unified_syntax) 8704 { 8705 if (!inst.operands[2].isreg) 8706 { 8707 /* For an immediate, we always generate a 32-bit opcode; 8708 section relaxation will shrink it later if possible. */ 8709 inst.instruction = THUMB_OP32 (inst.instruction); 8710 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8711 inst.instruction |= Rd << 8; 8712 inst.instruction |= Rs << 16; 8713 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8714 } 8715 else 8716 { 8717 bfd_boolean narrow; 8718 8719 /* See if we can do this with a 16-bit instruction. */ 8720 if (THUMB_SETS_FLAGS (inst.instruction)) 8721 narrow = current_it_mask == 0; 8722 else 8723 narrow = current_it_mask != 0; 8724 8725 if (Rd > 7 || Rn > 7 || Rs > 7) 8726 narrow = FALSE; 8727 if (inst.operands[2].shifted) 8728 narrow = FALSE; 8729 if (inst.size_req == 4) 8730 narrow = FALSE; 8731 8732 if (narrow) 8733 { 8734 if (Rd == Rs) 8735 { 8736 inst.instruction = THUMB_OP16 (inst.instruction); 8737 inst.instruction |= Rd; 8738 inst.instruction |= Rn << 3; 8739 return; 8740 } 8741 if (Rd == Rn) 8742 { 8743 inst.instruction = THUMB_OP16 (inst.instruction); 8744 inst.instruction |= Rd; 8745 inst.instruction |= Rs << 3; 8746 return; 8747 } 8748 } 8749 8750 /* If we get here, it can't be done in 16 bits. */ 8751 constraint (inst.operands[2].shifted 8752 && inst.operands[2].immisreg, 8753 _("shift must be constant")); 8754 inst.instruction = THUMB_OP32 (inst.instruction); 8755 inst.instruction |= Rd << 8; 8756 inst.instruction |= Rs << 16; 8757 encode_thumb32_shifted_operand (2); 8758 } 8759 } 8760 else 8761 { 8762 /* On its face this is a lie - the instruction does set the 8763 flags. However, the only supported mnemonic in this mode 8764 says it doesn't. */ 8765 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8766 8767 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8768 _("unshifted register required")); 8769 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8770 8771 inst.instruction = THUMB_OP16 (inst.instruction); 8772 inst.instruction |= Rd; 8773 8774 if (Rd == Rs) 8775 inst.instruction |= Rn << 3; 8776 else if (Rd == Rn) 8777 inst.instruction |= Rs << 3; 8778 else 8779 constraint (1, _("dest must overlap one source register")); 8780 } 8781} 8782 8783static void 8784do_t_barrier (void) 8785{ 8786 if (inst.operands[0].present) 8787 { 8788 constraint ((inst.instruction & 0xf0) != 0x40 8789 && inst.operands[0].imm != 0xf, 8790 "bad barrier type"); 8791 inst.instruction |= inst.operands[0].imm; 8792 } 8793 else 8794 inst.instruction |= 0xf; 8795} 8796 8797static void 8798do_t_bfc (void) 8799{ 8800 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 8801 constraint (msb > 32, _("bit-field extends past end of register")); 8802 /* The instruction encoding stores the LSB and MSB, 8803 not the LSB and width. */ 8804 inst.instruction |= inst.operands[0].reg << 8; 8805 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; 8806 inst.instruction |= (inst.operands[1].imm & 0x03) << 6; 8807 inst.instruction |= msb - 1; 8808} 8809 8810static void 8811do_t_bfi (void) 8812{ 8813 unsigned int msb; 8814 8815 /* #0 in second position is alternative syntax for bfc, which is 8816 the same instruction but with REG_PC in the Rm field. */ 8817 if (!inst.operands[1].isreg) 8818 inst.operands[1].reg = REG_PC; 8819 8820 msb = inst.operands[2].imm + inst.operands[3].imm; 8821 constraint (msb > 32, _("bit-field extends past end of register")); 8822 /* The instruction encoding stores the LSB and MSB, 8823 not the LSB and width. */ 8824 inst.instruction |= inst.operands[0].reg << 8; 8825 inst.instruction |= inst.operands[1].reg << 16; 8826 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8827 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8828 inst.instruction |= msb - 1; 8829} 8830 8831static void 8832do_t_bfx (void) 8833{ 8834 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 8835 _("bit-field extends past end of register")); 8836 inst.instruction |= inst.operands[0].reg << 8; 8837 inst.instruction |= inst.operands[1].reg << 16; 8838 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8839 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8840 inst.instruction |= inst.operands[3].imm - 1; 8841} 8842 8843/* ARM V5 Thumb BLX (argument parse) 8844 BLX <target_addr> which is BLX(1) 8845 BLX <Rm> which is BLX(2) 8846 Unfortunately, there are two different opcodes for this mnemonic. 8847 So, the insns[].value is not used, and the code here zaps values 8848 into inst.instruction. 8849 8850 ??? How to take advantage of the additional two bits of displacement 8851 available in Thumb32 mode? Need new relocation? */ 8852 8853static void 8854do_t_blx (void) 8855{ 8856 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8857 if (inst.operands[0].isreg) 8858 /* We have a register, so this is BLX(2). */ 8859 inst.instruction |= inst.operands[0].reg << 3; 8860 else 8861 { 8862 /* No register. This must be BLX(1). */ 8863 inst.instruction = 0xf000e800; 8864#ifdef OBJ_ELF 8865 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 8866 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8867 else 8868#endif 8869 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; 8870 inst.reloc.pc_rel = 1; 8871 } 8872} 8873 8874static void 8875do_t_branch (void) 8876{ 8877 int opcode; 8878 int cond; 8879 8880 if (current_it_mask) 8881 { 8882 /* Conditional branches inside IT blocks are encoded as unconditional 8883 branches. */ 8884 cond = COND_ALWAYS; 8885 /* A branch must be the last instruction in an IT block. */ 8886 constraint (current_it_mask != 0x10, BAD_BRANCH); 8887 } 8888 else 8889 cond = inst.cond; 8890 8891 if (cond != COND_ALWAYS) 8892 opcode = T_MNEM_bcond; 8893 else 8894 opcode = inst.instruction; 8895 8896 if (unified_syntax && inst.size_req == 4) 8897 { 8898 inst.instruction = THUMB_OP32(opcode); 8899 if (cond == COND_ALWAYS) 8900 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; 8901 else 8902 { 8903 assert (cond != 0xF); 8904 inst.instruction |= cond << 22; 8905 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; 8906 } 8907 } 8908 else 8909 { 8910 inst.instruction = THUMB_OP16(opcode); 8911 if (cond == COND_ALWAYS) 8912 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; 8913 else 8914 { 8915 inst.instruction |= cond << 8; 8916 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; 8917 } 8918 /* Allow section relaxation. */ 8919 if (unified_syntax && inst.size_req != 2) 8920 inst.relax = opcode; 8921 } 8922 8923 inst.reloc.pc_rel = 1; 8924} 8925 8926static void 8927do_t_bkpt (void) 8928{ 8929 constraint (inst.cond != COND_ALWAYS, 8930 _("instruction is always unconditional")); 8931 if (inst.operands[0].present) 8932 { 8933 constraint (inst.operands[0].imm > 255, 8934 _("immediate value out of range")); 8935 inst.instruction |= inst.operands[0].imm; 8936 } 8937} 8938 8939static void 8940do_t_branch23 (void) 8941{ 8942 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8943 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8944 inst.reloc.pc_rel = 1; 8945 8946 /* If the destination of the branch is a defined symbol which does not have 8947 the THUMB_FUNC attribute, then we must be calling a function which has 8948 the (interfacearm) attribute. We look for the Thumb entry point to that 8949 function and change the branch to refer to that function instead. */ 8950 if ( inst.reloc.exp.X_op == O_symbol 8951 && inst.reloc.exp.X_add_symbol != NULL 8952 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) 8953 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) 8954 inst.reloc.exp.X_add_symbol = 8955 find_real_start (inst.reloc.exp.X_add_symbol); 8956} 8957 8958static void 8959do_t_bx (void) 8960{ 8961 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8962 inst.instruction |= inst.operands[0].reg << 3; 8963 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc 8964 should cause the alignment to be checked once it is known. This is 8965 because BX PC only works if the instruction is word aligned. */ 8966} 8967 8968static void 8969do_t_bxj (void) 8970{ 8971 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8972 if (inst.operands[0].reg == REG_PC) 8973 as_tsktsk (_("use of r15 in bxj is not really useful")); 8974 8975 inst.instruction |= inst.operands[0].reg << 16; 8976} 8977 8978static void 8979do_t_clz (void) 8980{ 8981 inst.instruction |= inst.operands[0].reg << 8; 8982 inst.instruction |= inst.operands[1].reg << 16; 8983 inst.instruction |= inst.operands[1].reg; 8984} 8985 8986static void 8987do_t_cps (void) 8988{ 8989 constraint (current_it_mask, BAD_NOT_IT); 8990 inst.instruction |= inst.operands[0].imm; 8991} 8992 8993static void 8994do_t_cpsi (void) 8995{ 8996 constraint (current_it_mask, BAD_NOT_IT); 8997 if (unified_syntax 8998 && (inst.operands[1].present || inst.size_req == 4) 8999 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) 9000 { 9001 unsigned int imod = (inst.instruction & 0x0030) >> 4; 9002 inst.instruction = 0xf3af8000; 9003 inst.instruction |= imod << 9; 9004 inst.instruction |= inst.operands[0].imm << 5; 9005 if (inst.operands[1].present) 9006 inst.instruction |= 0x100 | inst.operands[1].imm; 9007 } 9008 else 9009 { 9010 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) 9011 && (inst.operands[0].imm & 4), 9012 _("selected processor does not support 'A' form " 9013 "of this instruction")); 9014 constraint (inst.operands[1].present || inst.size_req == 4, 9015 _("Thumb does not support the 2-argument " 9016 "form of this instruction")); 9017 inst.instruction |= inst.operands[0].imm; 9018 } 9019} 9020 9021/* THUMB CPY instruction (argument parse). */ 9022 9023static void 9024do_t_cpy (void) 9025{ 9026 if (inst.size_req == 4) 9027 { 9028 inst.instruction = THUMB_OP32 (T_MNEM_mov); 9029 inst.instruction |= inst.operands[0].reg << 8; 9030 inst.instruction |= inst.operands[1].reg; 9031 } 9032 else 9033 { 9034 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9035 inst.instruction |= (inst.operands[0].reg & 0x7); 9036 inst.instruction |= inst.operands[1].reg << 3; 9037 } 9038} 9039 9040static void 9041do_t_cbz (void) 9042{ 9043 constraint (current_it_mask, BAD_NOT_IT); 9044 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9045 inst.instruction |= inst.operands[0].reg; 9046 inst.reloc.pc_rel = 1; 9047 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; 9048} 9049 9050static void 9051do_t_dbg (void) 9052{ 9053 inst.instruction |= inst.operands[0].imm; 9054} 9055 9056static void 9057do_t_div (void) 9058{ 9059 if (!inst.operands[1].present) 9060 inst.operands[1].reg = inst.operands[0].reg; 9061 inst.instruction |= inst.operands[0].reg << 8; 9062 inst.instruction |= inst.operands[1].reg << 16; 9063 inst.instruction |= inst.operands[2].reg; 9064} 9065 9066static void 9067do_t_hint (void) 9068{ 9069 if (unified_syntax && inst.size_req == 4) 9070 inst.instruction = THUMB_OP32 (inst.instruction); 9071 else 9072 inst.instruction = THUMB_OP16 (inst.instruction); 9073} 9074 9075static void 9076do_t_it (void) 9077{ 9078 unsigned int cond = inst.operands[0].imm; 9079 9080 constraint (current_it_mask, BAD_NOT_IT); 9081 current_it_mask = (inst.instruction & 0xf) | 0x10; 9082 current_cc = cond; 9083 9084 /* If the condition is a negative condition, invert the mask. */ 9085 if ((cond & 0x1) == 0x0) 9086 { 9087 unsigned int mask = inst.instruction & 0x000f; 9088 9089 if ((mask & 0x7) == 0) 9090 /* no conversion needed */; 9091 else if ((mask & 0x3) == 0) 9092 mask ^= 0x8; 9093 else if ((mask & 0x1) == 0) 9094 mask ^= 0xC; 9095 else 9096 mask ^= 0xE; 9097 9098 inst.instruction &= 0xfff0; 9099 inst.instruction |= mask; 9100 } 9101 9102 inst.instruction |= cond << 4; 9103} 9104 9105/* Helper function used for both push/pop and ldm/stm. */ 9106static void 9107encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) 9108{ 9109 bfd_boolean load; 9110 9111 load = (inst.instruction & (1 << 20)) != 0; 9112 9113 if (mask & (1 << 13)) 9114 inst.error = _("SP not allowed in register list"); 9115 if (load) 9116 { 9117 if (mask & (1 << 14) 9118 && mask & (1 << 15)) 9119 inst.error = _("LR and PC should not both be in register list"); 9120 9121 if ((mask & (1 << base)) != 0 9122 && writeback) 9123 as_warn (_("base register should not be in register list " 9124 "when written back")); 9125 } 9126 else 9127 { 9128 if (mask & (1 << 15)) 9129 inst.error = _("PC not allowed in register list"); 9130 9131 if (mask & (1 << base)) 9132 as_warn (_("value stored for r%d is UNPREDICTABLE"), base); 9133 } 9134 9135 if ((mask & (mask - 1)) == 0) 9136 { 9137 /* Single register transfers implemented as str/ldr. */ 9138 if (writeback) 9139 { 9140 if (inst.instruction & (1 << 23)) 9141 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ 9142 else 9143 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ 9144 } 9145 else 9146 { 9147 if (inst.instruction & (1 << 23)) 9148 inst.instruction = 0x00800000; /* ia -> [base] */ 9149 else 9150 inst.instruction = 0x00000c04; /* db -> [base, #-4] */ 9151 } 9152 9153 inst.instruction |= 0xf8400000; 9154 if (load) 9155 inst.instruction |= 0x00100000; 9156 9157 mask = ffs(mask) - 1; 9158 mask <<= 12; 9159 } 9160 else if (writeback) 9161 inst.instruction |= WRITE_BACK; 9162 9163 inst.instruction |= mask; 9164 inst.instruction |= base << 16; 9165} 9166 9167static void 9168do_t_ldmstm (void) 9169{ 9170 /* This really doesn't seem worth it. */ 9171 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 9172 _("expression too complex")); 9173 constraint (inst.operands[1].writeback, 9174 _("Thumb load/store multiple does not support {reglist}^")); 9175 9176 if (unified_syntax) 9177 { 9178 bfd_boolean narrow; 9179 unsigned mask; 9180 9181 narrow = FALSE; 9182 /* See if we can use a 16-bit instruction. */ 9183 if (inst.instruction < 0xffff /* not ldmdb/stmdb */ 9184 && inst.size_req != 4 9185 && !(inst.operands[1].imm & ~0xff)) 9186 { 9187 mask = 1 << inst.operands[0].reg; 9188 9189 if (inst.operands[0].reg <= 7 9190 && (inst.instruction == T_MNEM_stmia 9191 ? inst.operands[0].writeback 9192 : (inst.operands[0].writeback 9193 == !(inst.operands[1].imm & mask)))) 9194 { 9195 if (inst.instruction == T_MNEM_stmia 9196 && (inst.operands[1].imm & mask) 9197 && (inst.operands[1].imm & (mask - 1))) 9198 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9199 inst.operands[0].reg); 9200 9201 inst.instruction = THUMB_OP16 (inst.instruction); 9202 inst.instruction |= inst.operands[0].reg << 8; 9203 inst.instruction |= inst.operands[1].imm; 9204 narrow = TRUE; 9205 } 9206 else if (inst.operands[0] .reg == REG_SP 9207 && inst.operands[0].writeback) 9208 { 9209 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia 9210 ? T_MNEM_push : T_MNEM_pop); 9211 inst.instruction |= inst.operands[1].imm; 9212 narrow = TRUE; 9213 } 9214 } 9215 9216 if (!narrow) 9217 { 9218 if (inst.instruction < 0xffff) 9219 inst.instruction = THUMB_OP32 (inst.instruction); 9220 9221 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm, 9222 inst.operands[0].writeback); 9223 } 9224 } 9225 else 9226 { 9227 constraint (inst.operands[0].reg > 7 9228 || (inst.operands[1].imm & ~0xff), BAD_HIREG); 9229 constraint (inst.instruction != T_MNEM_ldmia 9230 && inst.instruction != T_MNEM_stmia, 9231 _("Thumb-2 instruction only valid in unified syntax")); 9232 if (inst.instruction == T_MNEM_stmia) 9233 { 9234 if (!inst.operands[0].writeback) 9235 as_warn (_("this instruction will write back the base register")); 9236 if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) 9237 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) 9238 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9239 inst.operands[0].reg); 9240 } 9241 else 9242 { 9243 if (!inst.operands[0].writeback 9244 && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) 9245 as_warn (_("this instruction will write back the base register")); 9246 else if (inst.operands[0].writeback 9247 && (inst.operands[1].imm & (1 << inst.operands[0].reg))) 9248 as_warn (_("this instruction will not write back the base register")); 9249 } 9250 9251 inst.instruction = THUMB_OP16 (inst.instruction); 9252 inst.instruction |= inst.operands[0].reg << 8; 9253 inst.instruction |= inst.operands[1].imm; 9254 } 9255} 9256 9257static void 9258do_t_ldrex (void) 9259{ 9260 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 9261 || inst.operands[1].postind || inst.operands[1].writeback 9262 || inst.operands[1].immisreg || inst.operands[1].shifted 9263 || inst.operands[1].negative, 9264 BAD_ADDR_MODE); 9265 9266 inst.instruction |= inst.operands[0].reg << 12; 9267 inst.instruction |= inst.operands[1].reg << 16; 9268 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 9269} 9270 9271static void 9272do_t_ldrexd (void) 9273{ 9274 if (!inst.operands[1].present) 9275 { 9276 constraint (inst.operands[0].reg == REG_LR, 9277 _("r14 not allowed as first register " 9278 "when second register is omitted")); 9279 inst.operands[1].reg = inst.operands[0].reg + 1; 9280 } 9281 constraint (inst.operands[0].reg == inst.operands[1].reg, 9282 BAD_OVERLAP); 9283 9284 inst.instruction |= inst.operands[0].reg << 12; 9285 inst.instruction |= inst.operands[1].reg << 8; 9286 inst.instruction |= inst.operands[2].reg << 16; 9287} 9288 9289static void 9290do_t_ldst (void) 9291{ 9292 unsigned long opcode; 9293 int Rn; 9294 9295 opcode = inst.instruction; 9296 if (unified_syntax) 9297 { 9298 if (!inst.operands[1].isreg) 9299 { 9300 if (opcode <= 0xffff) 9301 inst.instruction = THUMB_OP32 (opcode); 9302 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9303 return; 9304 } 9305 if (inst.operands[1].isreg 9306 && !inst.operands[1].writeback 9307 && !inst.operands[1].shifted && !inst.operands[1].postind 9308 && !inst.operands[1].negative && inst.operands[0].reg <= 7 9309 && opcode <= 0xffff 9310 && inst.size_req != 4) 9311 { 9312 /* Insn may have a 16-bit form. */ 9313 Rn = inst.operands[1].reg; 9314 if (inst.operands[1].immisreg) 9315 { 9316 inst.instruction = THUMB_OP16 (opcode); 9317 /* [Rn, Ri] */ 9318 if (Rn <= 7 && inst.operands[1].imm <= 7) 9319 goto op16; 9320 } 9321 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh 9322 && opcode != T_MNEM_ldrsb) 9323 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) 9324 || (Rn == REG_SP && opcode == T_MNEM_str)) 9325 { 9326 /* [Rn, #const] */ 9327 if (Rn > 7) 9328 { 9329 if (Rn == REG_PC) 9330 { 9331 if (inst.reloc.pc_rel) 9332 opcode = T_MNEM_ldr_pc2; 9333 else 9334 opcode = T_MNEM_ldr_pc; 9335 } 9336 else 9337 { 9338 if (opcode == T_MNEM_ldr) 9339 opcode = T_MNEM_ldr_sp; 9340 else 9341 opcode = T_MNEM_str_sp; 9342 } 9343 inst.instruction = inst.operands[0].reg << 8; 9344 } 9345 else 9346 { 9347 inst.instruction = inst.operands[0].reg; 9348 inst.instruction |= inst.operands[1].reg << 3; 9349 } 9350 inst.instruction |= THUMB_OP16 (opcode); 9351 if (inst.size_req == 2) 9352 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9353 else 9354 inst.relax = opcode; 9355 return; 9356 } 9357 } 9358 /* Definitely a 32-bit variant. */ 9359 inst.instruction = THUMB_OP32 (opcode); 9360 inst.instruction |= inst.operands[0].reg << 12; 9361 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); 9362 return; 9363 } 9364 9365 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9366 9367 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) 9368 { 9369 /* Only [Rn,Rm] is acceptable. */ 9370 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); 9371 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg 9372 || inst.operands[1].postind || inst.operands[1].shifted 9373 || inst.operands[1].negative, 9374 _("Thumb does not support this addressing mode")); 9375 inst.instruction = THUMB_OP16 (inst.instruction); 9376 goto op16; 9377 } 9378 9379 inst.instruction = THUMB_OP16 (inst.instruction); 9380 if (!inst.operands[1].isreg) 9381 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9382 return; 9383 9384 constraint (!inst.operands[1].preind 9385 || inst.operands[1].shifted 9386 || inst.operands[1].writeback, 9387 _("Thumb does not support this addressing mode")); 9388 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) 9389 { 9390 constraint (inst.instruction & 0x0600, 9391 _("byte or halfword not valid for base register")); 9392 constraint (inst.operands[1].reg == REG_PC 9393 && !(inst.instruction & THUMB_LOAD_BIT), 9394 _("r15 based store not allowed")); 9395 constraint (inst.operands[1].immisreg, 9396 _("invalid base register for register offset")); 9397 9398 if (inst.operands[1].reg == REG_PC) 9399 inst.instruction = T_OPCODE_LDR_PC; 9400 else if (inst.instruction & THUMB_LOAD_BIT) 9401 inst.instruction = T_OPCODE_LDR_SP; 9402 else 9403 inst.instruction = T_OPCODE_STR_SP; 9404 9405 inst.instruction |= inst.operands[0].reg << 8; 9406 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9407 return; 9408 } 9409 9410 constraint (inst.operands[1].reg > 7, BAD_HIREG); 9411 if (!inst.operands[1].immisreg) 9412 { 9413 /* Immediate offset. */ 9414 inst.instruction |= inst.operands[0].reg; 9415 inst.instruction |= inst.operands[1].reg << 3; 9416 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9417 return; 9418 } 9419 9420 /* Register offset. */ 9421 constraint (inst.operands[1].imm > 7, BAD_HIREG); 9422 constraint (inst.operands[1].negative, 9423 _("Thumb does not support this addressing mode")); 9424 9425 op16: 9426 switch (inst.instruction) 9427 { 9428 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; 9429 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; 9430 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; 9431 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; 9432 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; 9433 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; 9434 case 0x5600 /* ldrsb */: 9435 case 0x5e00 /* ldrsh */: break; 9436 default: abort (); 9437 } 9438 9439 inst.instruction |= inst.operands[0].reg; 9440 inst.instruction |= inst.operands[1].reg << 3; 9441 inst.instruction |= inst.operands[1].imm << 6; 9442} 9443 9444static void 9445do_t_ldstd (void) 9446{ 9447 if (!inst.operands[1].present) 9448 { 9449 inst.operands[1].reg = inst.operands[0].reg + 1; 9450 constraint (inst.operands[0].reg == REG_LR, 9451 _("r14 not allowed here")); 9452 } 9453 inst.instruction |= inst.operands[0].reg << 12; 9454 inst.instruction |= inst.operands[1].reg << 8; 9455 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); 9456 9457} 9458 9459static void 9460do_t_ldstt (void) 9461{ 9462 inst.instruction |= inst.operands[0].reg << 12; 9463 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); 9464} 9465 9466static void 9467do_t_mla (void) 9468{ 9469 inst.instruction |= inst.operands[0].reg << 8; 9470 inst.instruction |= inst.operands[1].reg << 16; 9471 inst.instruction |= inst.operands[2].reg; 9472 inst.instruction |= inst.operands[3].reg << 12; 9473} 9474 9475static void 9476do_t_mlal (void) 9477{ 9478 inst.instruction |= inst.operands[0].reg << 12; 9479 inst.instruction |= inst.operands[1].reg << 8; 9480 inst.instruction |= inst.operands[2].reg << 16; 9481 inst.instruction |= inst.operands[3].reg; 9482} 9483 9484static void 9485do_t_mov_cmp (void) 9486{ 9487 if (unified_syntax) 9488 { 9489 int r0off = (inst.instruction == T_MNEM_mov 9490 || inst.instruction == T_MNEM_movs) ? 8 : 16; 9491 unsigned long opcode; 9492 bfd_boolean narrow; 9493 bfd_boolean low_regs; 9494 9495 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); 9496 opcode = inst.instruction; 9497 if (current_it_mask) 9498 narrow = opcode != T_MNEM_movs; 9499 else 9500 narrow = opcode != T_MNEM_movs || low_regs; 9501 if (inst.size_req == 4 9502 || inst.operands[1].shifted) 9503 narrow = FALSE; 9504 9505 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ 9506 if (opcode == T_MNEM_movs && inst.operands[1].isreg 9507 && !inst.operands[1].shifted 9508 && inst.operands[0].reg == REG_PC 9509 && inst.operands[1].reg == REG_LR) 9510 { 9511 inst.instruction = T2_SUBS_PC_LR; 9512 return; 9513 } 9514 9515 if (!inst.operands[1].isreg) 9516 { 9517 /* Immediate operand. */ 9518 if (current_it_mask == 0 && opcode == T_MNEM_mov) 9519 narrow = 0; 9520 if (low_regs && narrow) 9521 { 9522 inst.instruction = THUMB_OP16 (opcode); 9523 inst.instruction |= inst.operands[0].reg << 8; 9524 if (inst.size_req == 2) 9525 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9526 else 9527 inst.relax = opcode; 9528 } 9529 else 9530 { 9531 inst.instruction = THUMB_OP32 (inst.instruction); 9532 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9533 inst.instruction |= inst.operands[0].reg << r0off; 9534 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9535 } 9536 } 9537 else if (inst.operands[1].shifted && inst.operands[1].immisreg 9538 && (inst.instruction == T_MNEM_mov 9539 || inst.instruction == T_MNEM_movs)) 9540 { 9541 /* Register shifts are encoded as separate shift instructions. */ 9542 bfd_boolean flags = (inst.instruction == T_MNEM_movs); 9543 9544 if (current_it_mask) 9545 narrow = !flags; 9546 else 9547 narrow = flags; 9548 9549 if (inst.size_req == 4) 9550 narrow = FALSE; 9551 9552 if (!low_regs || inst.operands[1].imm > 7) 9553 narrow = FALSE; 9554 9555 if (inst.operands[0].reg != inst.operands[1].reg) 9556 narrow = FALSE; 9557 9558 switch (inst.operands[1].shift_kind) 9559 { 9560 case SHIFT_LSL: 9561 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); 9562 break; 9563 case SHIFT_ASR: 9564 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); 9565 break; 9566 case SHIFT_LSR: 9567 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); 9568 break; 9569 case SHIFT_ROR: 9570 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); 9571 break; 9572 default: 9573 abort(); 9574 } 9575 9576 inst.instruction = opcode; 9577 if (narrow) 9578 { 9579 inst.instruction |= inst.operands[0].reg; 9580 inst.instruction |= inst.operands[1].imm << 3; 9581 } 9582 else 9583 { 9584 if (flags) 9585 inst.instruction |= CONDS_BIT; 9586 9587 inst.instruction |= inst.operands[0].reg << 8; 9588 inst.instruction |= inst.operands[1].reg << 16; 9589 inst.instruction |= inst.operands[1].imm; 9590 } 9591 } 9592 else if (!narrow) 9593 { 9594 /* Some mov with immediate shift have narrow variants. 9595 Register shifts are handled above. */ 9596 if (low_regs && inst.operands[1].shifted 9597 && (inst.instruction == T_MNEM_mov 9598 || inst.instruction == T_MNEM_movs)) 9599 { 9600 if (current_it_mask) 9601 narrow = (inst.instruction == T_MNEM_mov); 9602 else 9603 narrow = (inst.instruction == T_MNEM_movs); 9604 } 9605 9606 if (narrow) 9607 { 9608 switch (inst.operands[1].shift_kind) 9609 { 9610 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 9611 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 9612 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 9613 default: narrow = FALSE; break; 9614 } 9615 } 9616 9617 if (narrow) 9618 { 9619 inst.instruction |= inst.operands[0].reg; 9620 inst.instruction |= inst.operands[1].reg << 3; 9621 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 9622 } 9623 else 9624 { 9625 inst.instruction = THUMB_OP32 (inst.instruction); 9626 inst.instruction |= inst.operands[0].reg << r0off; 9627 encode_thumb32_shifted_operand (1); 9628 } 9629 } 9630 else 9631 switch (inst.instruction) 9632 { 9633 case T_MNEM_mov: 9634 inst.instruction = T_OPCODE_MOV_HR; 9635 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9636 inst.instruction |= (inst.operands[0].reg & 0x7); 9637 inst.instruction |= inst.operands[1].reg << 3; 9638 break; 9639 9640 case T_MNEM_movs: 9641 /* We know we have low registers at this point. 9642 Generate ADD Rd, Rs, #0. */ 9643 inst.instruction = T_OPCODE_ADD_I3; 9644 inst.instruction |= inst.operands[0].reg; 9645 inst.instruction |= inst.operands[1].reg << 3; 9646 break; 9647 9648 case T_MNEM_cmp: 9649 if (low_regs) 9650 { 9651 inst.instruction = T_OPCODE_CMP_LR; 9652 inst.instruction |= inst.operands[0].reg; 9653 inst.instruction |= inst.operands[1].reg << 3; 9654 } 9655 else 9656 { 9657 inst.instruction = T_OPCODE_CMP_HR; 9658 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9659 inst.instruction |= (inst.operands[0].reg & 0x7); 9660 inst.instruction |= inst.operands[1].reg << 3; 9661 } 9662 break; 9663 } 9664 return; 9665 } 9666 9667 inst.instruction = THUMB_OP16 (inst.instruction); 9668 if (inst.operands[1].isreg) 9669 { 9670 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) 9671 { 9672 /* A move of two lowregs is encoded as ADD Rd, Rs, #0 9673 since a MOV instruction produces unpredictable results. */ 9674 if (inst.instruction == T_OPCODE_MOV_I8) 9675 inst.instruction = T_OPCODE_ADD_I3; 9676 else 9677 inst.instruction = T_OPCODE_CMP_LR; 9678 9679 inst.instruction |= inst.operands[0].reg; 9680 inst.instruction |= inst.operands[1].reg << 3; 9681 } 9682 else 9683 { 9684 if (inst.instruction == T_OPCODE_MOV_I8) 9685 inst.instruction = T_OPCODE_MOV_HR; 9686 else 9687 inst.instruction = T_OPCODE_CMP_HR; 9688 do_t_cpy (); 9689 } 9690 } 9691 else 9692 { 9693 constraint (inst.operands[0].reg > 7, 9694 _("only lo regs allowed with immediate")); 9695 inst.instruction |= inst.operands[0].reg << 8; 9696 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9697 } 9698} 9699 9700static void 9701do_t_mov16 (void) 9702{ 9703 bfd_vma imm; 9704 bfd_boolean top; 9705 9706 top = (inst.instruction & 0x00800000) != 0; 9707 if (inst.reloc.type == BFD_RELOC_ARM_MOVW) 9708 { 9709 constraint (top, _(":lower16: not allowed this instruction")); 9710 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; 9711 } 9712 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) 9713 { 9714 constraint (!top, _(":upper16: not allowed this instruction")); 9715 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; 9716 } 9717 9718 inst.instruction |= inst.operands[0].reg << 8; 9719 if (inst.reloc.type == BFD_RELOC_UNUSED) 9720 { 9721 imm = inst.reloc.exp.X_add_number; 9722 inst.instruction |= (imm & 0xf000) << 4; 9723 inst.instruction |= (imm & 0x0800) << 15; 9724 inst.instruction |= (imm & 0x0700) << 4; 9725 inst.instruction |= (imm & 0x00ff); 9726 } 9727} 9728 9729static void 9730do_t_mvn_tst (void) 9731{ 9732 if (unified_syntax) 9733 { 9734 int r0off = (inst.instruction == T_MNEM_mvn 9735 || inst.instruction == T_MNEM_mvns) ? 8 : 16; 9736 bfd_boolean narrow; 9737 9738 if (inst.size_req == 4 9739 || inst.instruction > 0xffff 9740 || inst.operands[1].shifted 9741 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9742 narrow = FALSE; 9743 else if (inst.instruction == T_MNEM_cmn) 9744 narrow = TRUE; 9745 else if (THUMB_SETS_FLAGS (inst.instruction)) 9746 narrow = (current_it_mask == 0); 9747 else 9748 narrow = (current_it_mask != 0); 9749 9750 if (!inst.operands[1].isreg) 9751 { 9752 /* For an immediate, we always generate a 32-bit opcode; 9753 section relaxation will shrink it later if possible. */ 9754 if (inst.instruction < 0xffff) 9755 inst.instruction = THUMB_OP32 (inst.instruction); 9756 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9757 inst.instruction |= inst.operands[0].reg << r0off; 9758 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9759 } 9760 else 9761 { 9762 /* See if we can do this with a 16-bit instruction. */ 9763 if (narrow) 9764 { 9765 inst.instruction = THUMB_OP16 (inst.instruction); 9766 inst.instruction |= inst.operands[0].reg; 9767 inst.instruction |= inst.operands[1].reg << 3; 9768 } 9769 else 9770 { 9771 constraint (inst.operands[1].shifted 9772 && inst.operands[1].immisreg, 9773 _("shift must be constant")); 9774 if (inst.instruction < 0xffff) 9775 inst.instruction = THUMB_OP32 (inst.instruction); 9776 inst.instruction |= inst.operands[0].reg << r0off; 9777 encode_thumb32_shifted_operand (1); 9778 } 9779 } 9780 } 9781 else 9782 { 9783 constraint (inst.instruction > 0xffff 9784 || inst.instruction == T_MNEM_mvns, BAD_THUMB32); 9785 constraint (!inst.operands[1].isreg || inst.operands[1].shifted, 9786 _("unshifted register required")); 9787 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9788 BAD_HIREG); 9789 9790 inst.instruction = THUMB_OP16 (inst.instruction); 9791 inst.instruction |= inst.operands[0].reg; 9792 inst.instruction |= inst.operands[1].reg << 3; 9793 } 9794} 9795 9796static void 9797do_t_mrs (void) 9798{ 9799 int flags; 9800 9801 if (do_vfp_nsyn_mrs () == SUCCESS) 9802 return; 9803 9804 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); 9805 if (flags == 0) 9806 { 9807 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9808 _("selected processor does not support " 9809 "requested special purpose register")); 9810 } 9811 else 9812 { 9813 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9814 _("selected processor does not support " 9815 "requested special purpose register %x")); 9816 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 9817 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), 9818 _("'CPSR' or 'SPSR' expected")); 9819 } 9820 9821 inst.instruction |= inst.operands[0].reg << 8; 9822 inst.instruction |= (flags & SPSR_BIT) >> 2; 9823 inst.instruction |= inst.operands[1].imm & 0xff; 9824} 9825 9826static void 9827do_t_msr (void) 9828{ 9829 int flags; 9830 9831 if (do_vfp_nsyn_msr () == SUCCESS) 9832 return; 9833 9834 constraint (!inst.operands[1].isreg, 9835 _("Thumb encoding does not support an immediate here")); 9836 flags = inst.operands[0].imm; 9837 if (flags & ~0xff) 9838 { 9839 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9840 _("selected processor does not support " 9841 "requested special purpose register")); 9842 } 9843 else 9844 { 9845 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9846 _("selected processor does not support " 9847 "requested special purpose register")); 9848 flags |= PSR_f; 9849 } 9850 inst.instruction |= (flags & SPSR_BIT) >> 2; 9851 inst.instruction |= (flags & ~SPSR_BIT) >> 8; 9852 inst.instruction |= (flags & 0xff); 9853 inst.instruction |= inst.operands[1].reg << 16; 9854} 9855 9856static void 9857do_t_mul (void) 9858{ 9859 if (!inst.operands[2].present) 9860 inst.operands[2].reg = inst.operands[0].reg; 9861 9862 /* There is no 32-bit MULS and no 16-bit MUL. */ 9863 if (unified_syntax && inst.instruction == T_MNEM_mul) 9864 { 9865 inst.instruction = THUMB_OP32 (inst.instruction); 9866 inst.instruction |= inst.operands[0].reg << 8; 9867 inst.instruction |= inst.operands[1].reg << 16; 9868 inst.instruction |= inst.operands[2].reg << 0; 9869 } 9870 else 9871 { 9872 constraint (!unified_syntax 9873 && inst.instruction == T_MNEM_muls, BAD_THUMB32); 9874 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9875 BAD_HIREG); 9876 9877 inst.instruction = THUMB_OP16 (inst.instruction); 9878 inst.instruction |= inst.operands[0].reg; 9879 9880 if (inst.operands[0].reg == inst.operands[1].reg) 9881 inst.instruction |= inst.operands[2].reg << 3; 9882 else if (inst.operands[0].reg == inst.operands[2].reg) 9883 inst.instruction |= inst.operands[1].reg << 3; 9884 else 9885 constraint (1, _("dest must overlap one source register")); 9886 } 9887} 9888 9889static void 9890do_t_mull (void) 9891{ 9892 inst.instruction |= inst.operands[0].reg << 12; 9893 inst.instruction |= inst.operands[1].reg << 8; 9894 inst.instruction |= inst.operands[2].reg << 16; 9895 inst.instruction |= inst.operands[3].reg; 9896 9897 if (inst.operands[0].reg == inst.operands[1].reg) 9898 as_tsktsk (_("rdhi and rdlo must be different")); 9899} 9900 9901static void 9902do_t_nop (void) 9903{ 9904 if (unified_syntax) 9905 { 9906 if (inst.size_req == 4 || inst.operands[0].imm > 15) 9907 { 9908 inst.instruction = THUMB_OP32 (inst.instruction); 9909 inst.instruction |= inst.operands[0].imm; 9910 } 9911 else 9912 { 9913 inst.instruction = THUMB_OP16 (inst.instruction); 9914 inst.instruction |= inst.operands[0].imm << 4; 9915 } 9916 } 9917 else 9918 { 9919 constraint (inst.operands[0].present, 9920 _("Thumb does not support NOP with hints")); 9921 inst.instruction = 0x46c0; 9922 } 9923} 9924 9925static void 9926do_t_neg (void) 9927{ 9928 if (unified_syntax) 9929 { 9930 bfd_boolean narrow; 9931 9932 if (THUMB_SETS_FLAGS (inst.instruction)) 9933 narrow = (current_it_mask == 0); 9934 else 9935 narrow = (current_it_mask != 0); 9936 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9937 narrow = FALSE; 9938 if (inst.size_req == 4) 9939 narrow = FALSE; 9940 9941 if (!narrow) 9942 { 9943 inst.instruction = THUMB_OP32 (inst.instruction); 9944 inst.instruction |= inst.operands[0].reg << 8; 9945 inst.instruction |= inst.operands[1].reg << 16; 9946 } 9947 else 9948 { 9949 inst.instruction = THUMB_OP16 (inst.instruction); 9950 inst.instruction |= inst.operands[0].reg; 9951 inst.instruction |= inst.operands[1].reg << 3; 9952 } 9953 } 9954 else 9955 { 9956 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9957 BAD_HIREG); 9958 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 9959 9960 inst.instruction = THUMB_OP16 (inst.instruction); 9961 inst.instruction |= inst.operands[0].reg; 9962 inst.instruction |= inst.operands[1].reg << 3; 9963 } 9964} 9965 9966static void 9967do_t_pkhbt (void) 9968{ 9969 inst.instruction |= inst.operands[0].reg << 8; 9970 inst.instruction |= inst.operands[1].reg << 16; 9971 inst.instruction |= inst.operands[2].reg; 9972 if (inst.operands[3].present) 9973 { 9974 unsigned int val = inst.reloc.exp.X_add_number; 9975 constraint (inst.reloc.exp.X_op != O_constant, 9976 _("expression too complex")); 9977 inst.instruction |= (val & 0x1c) << 10; 9978 inst.instruction |= (val & 0x03) << 6; 9979 } 9980} 9981 9982static void 9983do_t_pkhtb (void) 9984{ 9985 if (!inst.operands[3].present) 9986 inst.instruction &= ~0x00000020; 9987 do_t_pkhbt (); 9988} 9989 9990static void 9991do_t_pld (void) 9992{ 9993 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); 9994} 9995 9996static void 9997do_t_push_pop (void) 9998{ 9999 unsigned mask; 10000 10001 constraint (inst.operands[0].writeback, 10002 _("push/pop do not support {reglist}^")); 10003 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 10004 _("expression too complex")); 10005 10006 mask = inst.operands[0].imm; 10007 if ((mask & ~0xff) == 0) 10008 inst.instruction = THUMB_OP16 (inst.instruction) | mask; 10009 else if ((inst.instruction == T_MNEM_push 10010 && (mask & ~0xff) == 1 << REG_LR) 10011 || (inst.instruction == T_MNEM_pop 10012 && (mask & ~0xff) == 1 << REG_PC)) 10013 { 10014 inst.instruction = THUMB_OP16 (inst.instruction); 10015 inst.instruction |= THUMB_PP_PC_LR; 10016 inst.instruction |= mask & 0xff; 10017 } 10018 else if (unified_syntax) 10019 { 10020 inst.instruction = THUMB_OP32 (inst.instruction); 10021 encode_thumb2_ldmstm(13, mask, TRUE); 10022 } 10023 else 10024 { 10025 inst.error = _("invalid register list to push/pop instruction"); 10026 return; 10027 } 10028} 10029 10030static void 10031do_t_rbit (void) 10032{ 10033 inst.instruction |= inst.operands[0].reg << 8; 10034 inst.instruction |= inst.operands[1].reg << 16; 10035} 10036 10037static void 10038do_t_rd_rm (void) 10039{ 10040 inst.instruction |= inst.operands[0].reg << 8; 10041 inst.instruction |= inst.operands[1].reg; 10042} 10043 10044static void 10045do_t_rev (void) 10046{ 10047 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10048 && inst.size_req != 4) 10049 { 10050 inst.instruction = THUMB_OP16 (inst.instruction); 10051 inst.instruction |= inst.operands[0].reg; 10052 inst.instruction |= inst.operands[1].reg << 3; 10053 } 10054 else if (unified_syntax) 10055 { 10056 inst.instruction = THUMB_OP32 (inst.instruction); 10057 inst.instruction |= inst.operands[0].reg << 8; 10058 inst.instruction |= inst.operands[1].reg << 16; 10059 inst.instruction |= inst.operands[1].reg; 10060 } 10061 else 10062 inst.error = BAD_HIREG; 10063} 10064 10065static void 10066do_t_rsb (void) 10067{ 10068 int Rd, Rs; 10069 10070 Rd = inst.operands[0].reg; 10071 Rs = (inst.operands[1].present 10072 ? inst.operands[1].reg /* Rd, Rs, foo */ 10073 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 10074 10075 inst.instruction |= Rd << 8; 10076 inst.instruction |= Rs << 16; 10077 if (!inst.operands[2].isreg) 10078 { 10079 bfd_boolean narrow; 10080 10081 if ((inst.instruction & 0x00100000) != 0) 10082 narrow = (current_it_mask == 0); 10083 else 10084 narrow = (current_it_mask != 0); 10085 10086 if (Rd > 7 || Rs > 7) 10087 narrow = FALSE; 10088 10089 if (inst.size_req == 4 || !unified_syntax) 10090 narrow = FALSE; 10091 10092 if (inst.reloc.exp.X_op != O_constant 10093 || inst.reloc.exp.X_add_number != 0) 10094 narrow = FALSE; 10095 10096 /* Turn rsb #0 into 16-bit neg. We should probably do this via 10097 relaxation, but it doesn't seem worth the hassle. */ 10098 if (narrow) 10099 { 10100 inst.reloc.type = BFD_RELOC_UNUSED; 10101 inst.instruction = THUMB_OP16 (T_MNEM_negs); 10102 inst.instruction |= Rs << 3; 10103 inst.instruction |= Rd; 10104 } 10105 else 10106 { 10107 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 10108 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 10109 } 10110 } 10111 else 10112 encode_thumb32_shifted_operand (2); 10113} 10114 10115static void 10116do_t_setend (void) 10117{ 10118 constraint (current_it_mask, BAD_NOT_IT); 10119 if (inst.operands[0].imm) 10120 inst.instruction |= 0x8; 10121} 10122 10123static void 10124do_t_shift (void) 10125{ 10126 if (!inst.operands[1].present) 10127 inst.operands[1].reg = inst.operands[0].reg; 10128 10129 if (unified_syntax) 10130 { 10131 bfd_boolean narrow; 10132 int shift_kind; 10133 10134 switch (inst.instruction) 10135 { 10136 case T_MNEM_asr: 10137 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; 10138 case T_MNEM_lsl: 10139 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; 10140 case T_MNEM_lsr: 10141 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; 10142 case T_MNEM_ror: 10143 case T_MNEM_rors: shift_kind = SHIFT_ROR; break; 10144 default: abort (); 10145 } 10146 10147 if (THUMB_SETS_FLAGS (inst.instruction)) 10148 narrow = (current_it_mask == 0); 10149 else 10150 narrow = (current_it_mask != 0); 10151 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 10152 narrow = FALSE; 10153 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) 10154 narrow = FALSE; 10155 if (inst.operands[2].isreg 10156 && (inst.operands[1].reg != inst.operands[0].reg 10157 || inst.operands[2].reg > 7)) 10158 narrow = FALSE; 10159 if (inst.size_req == 4) 10160 narrow = FALSE; 10161 10162 if (!narrow) 10163 { 10164 if (inst.operands[2].isreg) 10165 { 10166 inst.instruction = THUMB_OP32 (inst.instruction); 10167 inst.instruction |= inst.operands[0].reg << 8; 10168 inst.instruction |= inst.operands[1].reg << 16; 10169 inst.instruction |= inst.operands[2].reg; 10170 } 10171 else 10172 { 10173 inst.operands[1].shifted = 1; 10174 inst.operands[1].shift_kind = shift_kind; 10175 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) 10176 ? T_MNEM_movs : T_MNEM_mov); 10177 inst.instruction |= inst.operands[0].reg << 8; 10178 encode_thumb32_shifted_operand (1); 10179 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ 10180 inst.reloc.type = BFD_RELOC_UNUSED; 10181 } 10182 } 10183 else 10184 { 10185 if (inst.operands[2].isreg) 10186 { 10187 switch (shift_kind) 10188 { 10189 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; 10190 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; 10191 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; 10192 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; 10193 default: abort (); 10194 } 10195 10196 inst.instruction |= inst.operands[0].reg; 10197 inst.instruction |= inst.operands[2].reg << 3; 10198 } 10199 else 10200 { 10201 switch (shift_kind) 10202 { 10203 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 10204 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 10205 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 10206 default: abort (); 10207 } 10208 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10209 inst.instruction |= inst.operands[0].reg; 10210 inst.instruction |= inst.operands[1].reg << 3; 10211 } 10212 } 10213 } 10214 else 10215 { 10216 constraint (inst.operands[0].reg > 7 10217 || inst.operands[1].reg > 7, BAD_HIREG); 10218 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 10219 10220 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ 10221 { 10222 constraint (inst.operands[2].reg > 7, BAD_HIREG); 10223 constraint (inst.operands[0].reg != inst.operands[1].reg, 10224 _("source1 and dest must be same register")); 10225 10226 switch (inst.instruction) 10227 { 10228 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; 10229 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; 10230 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; 10231 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; 10232 default: abort (); 10233 } 10234 10235 inst.instruction |= inst.operands[0].reg; 10236 inst.instruction |= inst.operands[2].reg << 3; 10237 } 10238 else 10239 { 10240 switch (inst.instruction) 10241 { 10242 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; 10243 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; 10244 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; 10245 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; 10246 default: abort (); 10247 } 10248 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10249 inst.instruction |= inst.operands[0].reg; 10250 inst.instruction |= inst.operands[1].reg << 3; 10251 } 10252 } 10253} 10254 10255static void 10256do_t_simd (void) 10257{ 10258 inst.instruction |= inst.operands[0].reg << 8; 10259 inst.instruction |= inst.operands[1].reg << 16; 10260 inst.instruction |= inst.operands[2].reg; 10261} 10262 10263static void 10264do_t_smc (void) 10265{ 10266 unsigned int value = inst.reloc.exp.X_add_number; 10267 constraint (inst.reloc.exp.X_op != O_constant, 10268 _("expression too complex")); 10269 inst.reloc.type = BFD_RELOC_UNUSED; 10270 inst.instruction |= (value & 0xf000) >> 12; 10271 inst.instruction |= (value & 0x0ff0); 10272 inst.instruction |= (value & 0x000f) << 16; 10273} 10274 10275static void 10276do_t_ssat (void) 10277{ 10278 inst.instruction |= inst.operands[0].reg << 8; 10279 inst.instruction |= inst.operands[1].imm - 1; 10280 inst.instruction |= inst.operands[2].reg << 16; 10281 10282 if (inst.operands[3].present) 10283 { 10284 constraint (inst.reloc.exp.X_op != O_constant, 10285 _("expression too complex")); 10286 10287 if (inst.reloc.exp.X_add_number != 0) 10288 { 10289 if (inst.operands[3].shift_kind == SHIFT_ASR) 10290 inst.instruction |= 0x00200000; /* sh bit */ 10291 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10292 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10293 } 10294 inst.reloc.type = BFD_RELOC_UNUSED; 10295 } 10296} 10297 10298static void 10299do_t_ssat16 (void) 10300{ 10301 inst.instruction |= inst.operands[0].reg << 8; 10302 inst.instruction |= inst.operands[1].imm - 1; 10303 inst.instruction |= inst.operands[2].reg << 16; 10304} 10305 10306static void 10307do_t_strex (void) 10308{ 10309 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 10310 || inst.operands[2].postind || inst.operands[2].writeback 10311 || inst.operands[2].immisreg || inst.operands[2].shifted 10312 || inst.operands[2].negative, 10313 BAD_ADDR_MODE); 10314 10315 inst.instruction |= inst.operands[0].reg << 8; 10316 inst.instruction |= inst.operands[1].reg << 12; 10317 inst.instruction |= inst.operands[2].reg << 16; 10318 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 10319} 10320 10321static void 10322do_t_strexd (void) 10323{ 10324 if (!inst.operands[2].present) 10325 inst.operands[2].reg = inst.operands[1].reg + 1; 10326 10327 constraint (inst.operands[0].reg == inst.operands[1].reg 10328 || inst.operands[0].reg == inst.operands[2].reg 10329 || inst.operands[0].reg == inst.operands[3].reg 10330 || inst.operands[1].reg == inst.operands[2].reg, 10331 BAD_OVERLAP); 10332 10333 inst.instruction |= inst.operands[0].reg; 10334 inst.instruction |= inst.operands[1].reg << 12; 10335 inst.instruction |= inst.operands[2].reg << 8; 10336 inst.instruction |= inst.operands[3].reg << 16; 10337} 10338 10339static void 10340do_t_sxtah (void) 10341{ 10342 inst.instruction |= inst.operands[0].reg << 8; 10343 inst.instruction |= inst.operands[1].reg << 16; 10344 inst.instruction |= inst.operands[2].reg; 10345 inst.instruction |= inst.operands[3].imm << 4; 10346} 10347 10348static void 10349do_t_sxth (void) 10350{ 10351 if (inst.instruction <= 0xffff && inst.size_req != 4 10352 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10353 && (!inst.operands[2].present || inst.operands[2].imm == 0)) 10354 { 10355 inst.instruction = THUMB_OP16 (inst.instruction); 10356 inst.instruction |= inst.operands[0].reg; 10357 inst.instruction |= inst.operands[1].reg << 3; 10358 } 10359 else if (unified_syntax) 10360 { 10361 if (inst.instruction <= 0xffff) 10362 inst.instruction = THUMB_OP32 (inst.instruction); 10363 inst.instruction |= inst.operands[0].reg << 8; 10364 inst.instruction |= inst.operands[1].reg; 10365 inst.instruction |= inst.operands[2].imm << 4; 10366 } 10367 else 10368 { 10369 constraint (inst.operands[2].present && inst.operands[2].imm != 0, 10370 _("Thumb encoding does not support rotation")); 10371 constraint (1, BAD_HIREG); 10372 } 10373} 10374 10375static void 10376do_t_swi (void) 10377{ 10378 inst.reloc.type = BFD_RELOC_ARM_SWI; 10379} 10380 10381static void 10382do_t_tb (void) 10383{ 10384 int half; 10385 10386 half = (inst.instruction & 0x10) != 0; 10387 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 10388 constraint (inst.operands[0].immisreg, 10389 _("instruction requires register index")); 10390 constraint (inst.operands[0].imm == 15, 10391 _("PC is not a valid index register")); 10392 constraint (!half && inst.operands[0].shifted, 10393 _("instruction does not allow shifted index")); 10394 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; 10395} 10396 10397static void 10398do_t_usat (void) 10399{ 10400 inst.instruction |= inst.operands[0].reg << 8; 10401 inst.instruction |= inst.operands[1].imm; 10402 inst.instruction |= inst.operands[2].reg << 16; 10403 10404 if (inst.operands[3].present) 10405 { 10406 constraint (inst.reloc.exp.X_op != O_constant, 10407 _("expression too complex")); 10408 if (inst.reloc.exp.X_add_number != 0) 10409 { 10410 if (inst.operands[3].shift_kind == SHIFT_ASR) 10411 inst.instruction |= 0x00200000; /* sh bit */ 10412 10413 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10414 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10415 } 10416 inst.reloc.type = BFD_RELOC_UNUSED; 10417 } 10418} 10419 10420static void 10421do_t_usat16 (void) 10422{ 10423 inst.instruction |= inst.operands[0].reg << 8; 10424 inst.instruction |= inst.operands[1].imm; 10425 inst.instruction |= inst.operands[2].reg << 16; 10426} 10427 10428/* Neon instruction encoder helpers. */ 10429 10430/* Encodings for the different types for various Neon opcodes. */ 10431 10432/* An "invalid" code for the following tables. */ 10433#define N_INV -1u 10434 10435struct neon_tab_entry 10436{ 10437 unsigned integer; 10438 unsigned float_or_poly; 10439 unsigned scalar_or_imm; 10440}; 10441 10442/* Map overloaded Neon opcodes to their respective encodings. */ 10443#define NEON_ENC_TAB \ 10444 X(vabd, 0x0000700, 0x1200d00, N_INV), \ 10445 X(vmax, 0x0000600, 0x0000f00, N_INV), \ 10446 X(vmin, 0x0000610, 0x0200f00, N_INV), \ 10447 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ 10448 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ 10449 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ 10450 X(vadd, 0x0000800, 0x0000d00, N_INV), \ 10451 X(vsub, 0x1000800, 0x0200d00, N_INV), \ 10452 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ 10453 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ 10454 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ 10455 /* Register variants of the following two instructions are encoded as 10456 vcge / vcgt with the operands reversed. */ \ 10457 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ 10458 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ 10459 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ 10460 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ 10461 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ 10462 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ 10463 X(vmlal, 0x0800800, N_INV, 0x0800240), \ 10464 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ 10465 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ 10466 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ 10467 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ 10468 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ 10469 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ 10470 X(vshl, 0x0000400, N_INV, 0x0800510), \ 10471 X(vqshl, 0x0000410, N_INV, 0x0800710), \ 10472 X(vand, 0x0000110, N_INV, 0x0800030), \ 10473 X(vbic, 0x0100110, N_INV, 0x0800030), \ 10474 X(veor, 0x1000110, N_INV, N_INV), \ 10475 X(vorn, 0x0300110, N_INV, 0x0800010), \ 10476 X(vorr, 0x0200110, N_INV, 0x0800010), \ 10477 X(vmvn, 0x1b00580, N_INV, 0x0800030), \ 10478 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ 10479 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ 10480 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ 10481 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ 10482 X(vst1, 0x0000000, 0x0800000, N_INV), \ 10483 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ 10484 X(vst2, 0x0000100, 0x0800100, N_INV), \ 10485 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ 10486 X(vst3, 0x0000200, 0x0800200, N_INV), \ 10487 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ 10488 X(vst4, 0x0000300, 0x0800300, N_INV), \ 10489 X(vmovn, 0x1b20200, N_INV, N_INV), \ 10490 X(vtrn, 0x1b20080, N_INV, N_INV), \ 10491 X(vqmovn, 0x1b20200, N_INV, N_INV), \ 10492 X(vqmovun, 0x1b20240, N_INV, N_INV), \ 10493 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ 10494 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ 10495 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ 10496 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ 10497 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ 10498 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ 10499 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) 10500 10501enum neon_opc 10502{ 10503#define X(OPC,I,F,S) N_MNEM_##OPC 10504NEON_ENC_TAB 10505#undef X 10506}; 10507 10508static const struct neon_tab_entry neon_enc_tab[] = 10509{ 10510#define X(OPC,I,F,S) { (I), (F), (S) } 10511NEON_ENC_TAB 10512#undef X 10513}; 10514 10515#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10516#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10517#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10518#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10519#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10520#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10521#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10522#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10523#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10524#define NEON_ENC_SINGLE(X) \ 10525 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) 10526#define NEON_ENC_DOUBLE(X) \ 10527 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) 10528 10529/* Define shapes for instruction operands. The following mnemonic characters 10530 are used in this table: 10531 10532 F - VFP S<n> register 10533 D - Neon D<n> register 10534 Q - Neon Q<n> register 10535 I - Immediate 10536 S - Scalar 10537 R - ARM register 10538 L - D<n> register list 10539 10540 This table is used to generate various data: 10541 - enumerations of the form NS_DDR to be used as arguments to 10542 neon_select_shape. 10543 - a table classifying shapes into single, double, quad, mixed. 10544 - a table used to drive neon_select_shape. 10545*/ 10546 10547#define NEON_SHAPE_DEF \ 10548 X(3, (D, D, D), DOUBLE), \ 10549 X(3, (Q, Q, Q), QUAD), \ 10550 X(3, (D, D, I), DOUBLE), \ 10551 X(3, (Q, Q, I), QUAD), \ 10552 X(3, (D, D, S), DOUBLE), \ 10553 X(3, (Q, Q, S), QUAD), \ 10554 X(2, (D, D), DOUBLE), \ 10555 X(2, (Q, Q), QUAD), \ 10556 X(2, (D, S), DOUBLE), \ 10557 X(2, (Q, S), QUAD), \ 10558 X(2, (D, R), DOUBLE), \ 10559 X(2, (Q, R), QUAD), \ 10560 X(2, (D, I), DOUBLE), \ 10561 X(2, (Q, I), QUAD), \ 10562 X(3, (D, L, D), DOUBLE), \ 10563 X(2, (D, Q), MIXED), \ 10564 X(2, (Q, D), MIXED), \ 10565 X(3, (D, Q, I), MIXED), \ 10566 X(3, (Q, D, I), MIXED), \ 10567 X(3, (Q, D, D), MIXED), \ 10568 X(3, (D, Q, Q), MIXED), \ 10569 X(3, (Q, Q, D), MIXED), \ 10570 X(3, (Q, D, S), MIXED), \ 10571 X(3, (D, Q, S), MIXED), \ 10572 X(4, (D, D, D, I), DOUBLE), \ 10573 X(4, (Q, Q, Q, I), QUAD), \ 10574 X(2, (F, F), SINGLE), \ 10575 X(3, (F, F, F), SINGLE), \ 10576 X(2, (F, I), SINGLE), \ 10577 X(2, (F, D), MIXED), \ 10578 X(2, (D, F), MIXED), \ 10579 X(3, (F, F, I), MIXED), \ 10580 X(4, (R, R, F, F), SINGLE), \ 10581 X(4, (F, F, R, R), SINGLE), \ 10582 X(3, (D, R, R), DOUBLE), \ 10583 X(3, (R, R, D), DOUBLE), \ 10584 X(2, (S, R), SINGLE), \ 10585 X(2, (R, S), SINGLE), \ 10586 X(2, (F, R), SINGLE), \ 10587 X(2, (R, F), SINGLE) 10588 10589#define S2(A,B) NS_##A##B 10590#define S3(A,B,C) NS_##A##B##C 10591#define S4(A,B,C,D) NS_##A##B##C##D 10592 10593#define X(N, L, C) S##N L 10594 10595enum neon_shape 10596{ 10597 NEON_SHAPE_DEF, 10598 NS_NULL 10599}; 10600 10601#undef X 10602#undef S2 10603#undef S3 10604#undef S4 10605 10606enum neon_shape_class 10607{ 10608 SC_SINGLE, 10609 SC_DOUBLE, 10610 SC_QUAD, 10611 SC_MIXED 10612}; 10613 10614#define X(N, L, C) SC_##C 10615 10616static enum neon_shape_class neon_shape_class[] = 10617{ 10618 NEON_SHAPE_DEF 10619}; 10620 10621#undef X 10622 10623enum neon_shape_el 10624{ 10625 SE_F, 10626 SE_D, 10627 SE_Q, 10628 SE_I, 10629 SE_S, 10630 SE_R, 10631 SE_L 10632}; 10633 10634/* Register widths of above. */ 10635static unsigned neon_shape_el_size[] = 10636{ 10637 32, 10638 64, 10639 128, 10640 0, 10641 32, 10642 32, 10643 0 10644}; 10645 10646struct neon_shape_info 10647{ 10648 unsigned els; 10649 enum neon_shape_el el[NEON_MAX_TYPE_ELS]; 10650}; 10651 10652#define S2(A,B) { SE_##A, SE_##B } 10653#define S3(A,B,C) { SE_##A, SE_##B, SE_##C } 10654#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } 10655 10656#define X(N, L, C) { N, S##N L } 10657 10658static struct neon_shape_info neon_shape_tab[] = 10659{ 10660 NEON_SHAPE_DEF 10661}; 10662 10663#undef X 10664#undef S2 10665#undef S3 10666#undef S4 10667 10668/* Bit masks used in type checking given instructions. 10669 'N_EQK' means the type must be the same as (or based on in some way) the key 10670 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is 10671 set, various other bits can be set as well in order to modify the meaning of 10672 the type constraint. */ 10673 10674enum neon_type_mask 10675{ 10676 N_S8 = 0x000001, 10677 N_S16 = 0x000002, 10678 N_S32 = 0x000004, 10679 N_S64 = 0x000008, 10680 N_U8 = 0x000010, 10681 N_U16 = 0x000020, 10682 N_U32 = 0x000040, 10683 N_U64 = 0x000080, 10684 N_I8 = 0x000100, 10685 N_I16 = 0x000200, 10686 N_I32 = 0x000400, 10687 N_I64 = 0x000800, 10688 N_8 = 0x001000, 10689 N_16 = 0x002000, 10690 N_32 = 0x004000, 10691 N_64 = 0x008000, 10692 N_P8 = 0x010000, 10693 N_P16 = 0x020000, 10694 N_F32 = 0x040000, 10695 N_F64 = 0x080000, 10696 N_KEY = 0x100000, /* key element (main type specifier). */ 10697 N_EQK = 0x200000, /* given operand has the same type & size as the key. */ 10698 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */ 10699 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */ 10700 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */ 10701 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */ 10702 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */ 10703 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */ 10704 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */ 10705 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */ 10706 N_UTYP = 0, 10707 N_MAX_NONSPECIAL = N_F64 10708}; 10709 10710#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) 10711 10712#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) 10713#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) 10714#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) 10715#define N_SUF_32 (N_SU_32 | N_F32) 10716#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) 10717#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) 10718 10719/* Pass this as the first type argument to neon_check_type to ignore types 10720 altogether. */ 10721#define N_IGNORE_TYPE (N_KEY | N_EQK) 10722 10723/* Select a "shape" for the current instruction (describing register types or 10724 sizes) from a list of alternatives. Return NS_NULL if the current instruction 10725 doesn't fit. For non-polymorphic shapes, checking is usually done as a 10726 function of operand parsing, so this function doesn't need to be called. 10727 Shapes should be listed in order of decreasing length. */ 10728 10729static enum neon_shape 10730neon_select_shape (enum neon_shape shape, ...) 10731{ 10732 va_list ap; 10733 enum neon_shape first_shape = shape; 10734 10735 /* Fix missing optional operands. FIXME: we don't know at this point how 10736 many arguments we should have, so this makes the assumption that we have 10737 > 1. This is true of all current Neon opcodes, I think, but may not be 10738 true in the future. */ 10739 if (!inst.operands[1].present) 10740 inst.operands[1] = inst.operands[0]; 10741 10742 va_start (ap, shape); 10743 10744 for (; shape != NS_NULL; shape = va_arg (ap, int)) 10745 { 10746 unsigned j; 10747 int matches = 1; 10748 10749 for (j = 0; j < neon_shape_tab[shape].els; j++) 10750 { 10751 if (!inst.operands[j].present) 10752 { 10753 matches = 0; 10754 break; 10755 } 10756 10757 switch (neon_shape_tab[shape].el[j]) 10758 { 10759 case SE_F: 10760 if (!(inst.operands[j].isreg 10761 && inst.operands[j].isvec 10762 && inst.operands[j].issingle 10763 && !inst.operands[j].isquad)) 10764 matches = 0; 10765 break; 10766 10767 case SE_D: 10768 if (!(inst.operands[j].isreg 10769 && inst.operands[j].isvec 10770 && !inst.operands[j].isquad 10771 && !inst.operands[j].issingle)) 10772 matches = 0; 10773 break; 10774 10775 case SE_R: 10776 if (!(inst.operands[j].isreg 10777 && !inst.operands[j].isvec)) 10778 matches = 0; 10779 break; 10780 10781 case SE_Q: 10782 if (!(inst.operands[j].isreg 10783 && inst.operands[j].isvec 10784 && inst.operands[j].isquad 10785 && !inst.operands[j].issingle)) 10786 matches = 0; 10787 break; 10788 10789 case SE_I: 10790 if (!(!inst.operands[j].isreg 10791 && !inst.operands[j].isscalar)) 10792 matches = 0; 10793 break; 10794 10795 case SE_S: 10796 if (!(!inst.operands[j].isreg 10797 && inst.operands[j].isscalar)) 10798 matches = 0; 10799 break; 10800 10801 case SE_L: 10802 break; 10803 } 10804 } 10805 if (matches) 10806 break; 10807 } 10808 10809 va_end (ap); 10810 10811 if (shape == NS_NULL && first_shape != NS_NULL) 10812 first_error (_("invalid instruction shape")); 10813 10814 return shape; 10815} 10816 10817/* True if SHAPE is predominantly a quadword operation (most of the time, this 10818 means the Q bit should be set). */ 10819 10820static int 10821neon_quad (enum neon_shape shape) 10822{ 10823 return neon_shape_class[shape] == SC_QUAD; 10824} 10825 10826static void 10827neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, 10828 unsigned *g_size) 10829{ 10830 /* Allow modification to be made to types which are constrained to be 10831 based on the key element, based on bits set alongside N_EQK. */ 10832 if ((typebits & N_EQK) != 0) 10833 { 10834 if ((typebits & N_HLF) != 0) 10835 *g_size /= 2; 10836 else if ((typebits & N_DBL) != 0) 10837 *g_size *= 2; 10838 if ((typebits & N_SGN) != 0) 10839 *g_type = NT_signed; 10840 else if ((typebits & N_UNS) != 0) 10841 *g_type = NT_unsigned; 10842 else if ((typebits & N_INT) != 0) 10843 *g_type = NT_integer; 10844 else if ((typebits & N_FLT) != 0) 10845 *g_type = NT_float; 10846 else if ((typebits & N_SIZ) != 0) 10847 *g_type = NT_untyped; 10848 } 10849} 10850 10851/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" 10852 operand type, i.e. the single type specified in a Neon instruction when it 10853 is the only one given. */ 10854 10855static struct neon_type_el 10856neon_type_promote (struct neon_type_el *key, unsigned thisarg) 10857{ 10858 struct neon_type_el dest = *key; 10859 10860 assert ((thisarg & N_EQK) != 0); 10861 10862 neon_modify_type_size (thisarg, &dest.type, &dest.size); 10863 10864 return dest; 10865} 10866 10867/* Convert Neon type and size into compact bitmask representation. */ 10868 10869static enum neon_type_mask 10870type_chk_of_el_type (enum neon_el_type type, unsigned size) 10871{ 10872 switch (type) 10873 { 10874 case NT_untyped: 10875 switch (size) 10876 { 10877 case 8: return N_8; 10878 case 16: return N_16; 10879 case 32: return N_32; 10880 case 64: return N_64; 10881 default: ; 10882 } 10883 break; 10884 10885 case NT_integer: 10886 switch (size) 10887 { 10888 case 8: return N_I8; 10889 case 16: return N_I16; 10890 case 32: return N_I32; 10891 case 64: return N_I64; 10892 default: ; 10893 } 10894 break; 10895 10896 case NT_float: 10897 switch (size) 10898 { 10899 case 32: return N_F32; 10900 case 64: return N_F64; 10901 default: ; 10902 } 10903 break; 10904 10905 case NT_poly: 10906 switch (size) 10907 { 10908 case 8: return N_P8; 10909 case 16: return N_P16; 10910 default: ; 10911 } 10912 break; 10913 10914 case NT_signed: 10915 switch (size) 10916 { 10917 case 8: return N_S8; 10918 case 16: return N_S16; 10919 case 32: return N_S32; 10920 case 64: return N_S64; 10921 default: ; 10922 } 10923 break; 10924 10925 case NT_unsigned: 10926 switch (size) 10927 { 10928 case 8: return N_U8; 10929 case 16: return N_U16; 10930 case 32: return N_U32; 10931 case 64: return N_U64; 10932 default: ; 10933 } 10934 break; 10935 10936 default: ; 10937 } 10938 10939 return N_UTYP; 10940} 10941 10942/* Convert compact Neon bitmask type representation to a type and size. Only 10943 handles the case where a single bit is set in the mask. */ 10944 10945static int 10946el_type_of_type_chk (enum neon_el_type *type, unsigned *size, 10947 enum neon_type_mask mask) 10948{ 10949 if ((mask & N_EQK) != 0) 10950 return FAIL; 10951 10952 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) 10953 *size = 8; 10954 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) 10955 *size = 16; 10956 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) 10957 *size = 32; 10958 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) 10959 *size = 64; 10960 else 10961 return FAIL; 10962 10963 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) 10964 *type = NT_signed; 10965 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) 10966 *type = NT_unsigned; 10967 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) 10968 *type = NT_integer; 10969 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) 10970 *type = NT_untyped; 10971 else if ((mask & (N_P8 | N_P16)) != 0) 10972 *type = NT_poly; 10973 else if ((mask & (N_F32 | N_F64)) != 0) 10974 *type = NT_float; 10975 else 10976 return FAIL; 10977 10978 return SUCCESS; 10979} 10980 10981/* Modify a bitmask of allowed types. This is only needed for type 10982 relaxation. */ 10983 10984static unsigned 10985modify_types_allowed (unsigned allowed, unsigned mods) 10986{ 10987 unsigned size; 10988 enum neon_el_type type; 10989 unsigned destmask; 10990 int i; 10991 10992 destmask = 0; 10993 10994 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) 10995 { 10996 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) 10997 { 10998 neon_modify_type_size (mods, &type, &size); 10999 destmask |= type_chk_of_el_type (type, size); 11000 } 11001 } 11002 11003 return destmask; 11004} 11005 11006/* Check type and return type classification. 11007 The manual states (paraphrase): If one datatype is given, it indicates the 11008 type given in: 11009 - the second operand, if there is one 11010 - the operand, if there is no second operand 11011 - the result, if there are no operands. 11012 This isn't quite good enough though, so we use a concept of a "key" datatype 11013 which is set on a per-instruction basis, which is the one which matters when 11014 only one data type is written. 11015 Note: this function has side-effects (e.g. filling in missing operands). All 11016 Neon instructions should call it before performing bit encoding. */ 11017 11018static struct neon_type_el 11019neon_check_type (unsigned els, enum neon_shape ns, ...) 11020{ 11021 va_list ap; 11022 unsigned i, pass, key_el = 0; 11023 unsigned types[NEON_MAX_TYPE_ELS]; 11024 enum neon_el_type k_type = NT_invtype; 11025 unsigned k_size = -1u; 11026 struct neon_type_el badtype = {NT_invtype, -1}; 11027 unsigned key_allowed = 0; 11028 11029 /* Optional registers in Neon instructions are always (not) in operand 1. 11030 Fill in the missing operand here, if it was omitted. */ 11031 if (els > 1 && !inst.operands[1].present) 11032 inst.operands[1] = inst.operands[0]; 11033 11034 /* Suck up all the varargs. */ 11035 va_start (ap, ns); 11036 for (i = 0; i < els; i++) 11037 { 11038 unsigned thisarg = va_arg (ap, unsigned); 11039 if (thisarg == N_IGNORE_TYPE) 11040 { 11041 va_end (ap); 11042 return badtype; 11043 } 11044 types[i] = thisarg; 11045 if ((thisarg & N_KEY) != 0) 11046 key_el = i; 11047 } 11048 va_end (ap); 11049 11050 if (inst.vectype.elems > 0) 11051 for (i = 0; i < els; i++) 11052 if (inst.operands[i].vectype.type != NT_invtype) 11053 { 11054 first_error (_("types specified in both the mnemonic and operands")); 11055 return badtype; 11056 } 11057 11058 /* Duplicate inst.vectype elements here as necessary. 11059 FIXME: No idea if this is exactly the same as the ARM assembler, 11060 particularly when an insn takes one register and one non-register 11061 operand. */ 11062 if (inst.vectype.elems == 1 && els > 1) 11063 { 11064 unsigned j; 11065 inst.vectype.elems = els; 11066 inst.vectype.el[key_el] = inst.vectype.el[0]; 11067 for (j = 0; j < els; j++) 11068 if (j != key_el) 11069 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11070 types[j]); 11071 } 11072 else if (inst.vectype.elems == 0 && els > 0) 11073 { 11074 unsigned j; 11075 /* No types were given after the mnemonic, so look for types specified 11076 after each operand. We allow some flexibility here; as long as the 11077 "key" operand has a type, we can infer the others. */ 11078 for (j = 0; j < els; j++) 11079 if (inst.operands[j].vectype.type != NT_invtype) 11080 inst.vectype.el[j] = inst.operands[j].vectype; 11081 11082 if (inst.operands[key_el].vectype.type != NT_invtype) 11083 { 11084 for (j = 0; j < els; j++) 11085 if (inst.operands[j].vectype.type == NT_invtype) 11086 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11087 types[j]); 11088 } 11089 else 11090 { 11091 first_error (_("operand types can't be inferred")); 11092 return badtype; 11093 } 11094 } 11095 else if (inst.vectype.elems != els) 11096 { 11097 first_error (_("type specifier has the wrong number of parts")); 11098 return badtype; 11099 } 11100 11101 for (pass = 0; pass < 2; pass++) 11102 { 11103 for (i = 0; i < els; i++) 11104 { 11105 unsigned thisarg = types[i]; 11106 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) 11107 ? modify_types_allowed (key_allowed, thisarg) : thisarg; 11108 enum neon_el_type g_type = inst.vectype.el[i].type; 11109 unsigned g_size = inst.vectype.el[i].size; 11110 11111 /* Decay more-specific signed & unsigned types to sign-insensitive 11112 integer types if sign-specific variants are unavailable. */ 11113 if ((g_type == NT_signed || g_type == NT_unsigned) 11114 && (types_allowed & N_SU_ALL) == 0) 11115 g_type = NT_integer; 11116 11117 /* If only untyped args are allowed, decay any more specific types to 11118 them. Some instructions only care about signs for some element 11119 sizes, so handle that properly. */ 11120 if ((g_size == 8 && (types_allowed & N_8) != 0) 11121 || (g_size == 16 && (types_allowed & N_16) != 0) 11122 || (g_size == 32 && (types_allowed & N_32) != 0) 11123 || (g_size == 64 && (types_allowed & N_64) != 0)) 11124 g_type = NT_untyped; 11125 11126 if (pass == 0) 11127 { 11128 if ((thisarg & N_KEY) != 0) 11129 { 11130 k_type = g_type; 11131 k_size = g_size; 11132 key_allowed = thisarg & ~N_KEY; 11133 } 11134 } 11135 else 11136 { 11137 if ((thisarg & N_VFP) != 0) 11138 { 11139 enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; 11140 unsigned regwidth = neon_shape_el_size[regshape], match; 11141 11142 /* In VFP mode, operands must match register widths. If we 11143 have a key operand, use its width, else use the width of 11144 the current operand. */ 11145 if (k_size != -1u) 11146 match = k_size; 11147 else 11148 match = g_size; 11149 11150 if (regwidth != match) 11151 { 11152 first_error (_("operand size must match register width")); 11153 return badtype; 11154 } 11155 } 11156 11157 if ((thisarg & N_EQK) == 0) 11158 { 11159 unsigned given_type = type_chk_of_el_type (g_type, g_size); 11160 11161 if ((given_type & types_allowed) == 0) 11162 { 11163 first_error (_("bad type in Neon instruction")); 11164 return badtype; 11165 } 11166 } 11167 else 11168 { 11169 enum neon_el_type mod_k_type = k_type; 11170 unsigned mod_k_size = k_size; 11171 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); 11172 if (g_type != mod_k_type || g_size != mod_k_size) 11173 { 11174 first_error (_("inconsistent types in Neon instruction")); 11175 return badtype; 11176 } 11177 } 11178 } 11179 } 11180 } 11181 11182 return inst.vectype.el[key_el]; 11183} 11184 11185/* Neon-style VFP instruction forwarding. */ 11186 11187/* Thumb VFP instructions have 0xE in the condition field. */ 11188 11189static void 11190do_vfp_cond_or_thumb (void) 11191{ 11192 if (thumb_mode) 11193 inst.instruction |= 0xe0000000; 11194 else 11195 inst.instruction |= inst.cond << 28; 11196} 11197 11198/* Look up and encode a simple mnemonic, for use as a helper function for the 11199 Neon-style VFP syntax. This avoids duplication of bits of the insns table, 11200 etc. It is assumed that operand parsing has already been done, and that the 11201 operands are in the form expected by the given opcode (this isn't necessarily 11202 the same as the form in which they were parsed, hence some massaging must 11203 take place before this function is called). 11204 Checks current arch version against that in the looked-up opcode. */ 11205 11206static void 11207do_vfp_nsyn_opcode (const char *opname) 11208{ 11209 const struct asm_opcode *opcode; 11210 11211 opcode = hash_find (arm_ops_hsh, opname); 11212 11213 if (!opcode) 11214 abort (); 11215 11216 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, 11217 thumb_mode ? *opcode->tvariant : *opcode->avariant), 11218 _(BAD_FPU)); 11219 11220 if (thumb_mode) 11221 { 11222 inst.instruction = opcode->tvalue; 11223 opcode->tencode (); 11224 } 11225 else 11226 { 11227 inst.instruction = (inst.cond << 28) | opcode->avalue; 11228 opcode->aencode (); 11229 } 11230} 11231 11232static void 11233do_vfp_nsyn_add_sub (enum neon_shape rs) 11234{ 11235 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; 11236 11237 if (rs == NS_FFF) 11238 { 11239 if (is_add) 11240 do_vfp_nsyn_opcode ("fadds"); 11241 else 11242 do_vfp_nsyn_opcode ("fsubs"); 11243 } 11244 else 11245 { 11246 if (is_add) 11247 do_vfp_nsyn_opcode ("faddd"); 11248 else 11249 do_vfp_nsyn_opcode ("fsubd"); 11250 } 11251} 11252 11253/* Check operand types to see if this is a VFP instruction, and if so call 11254 PFN (). */ 11255 11256static int 11257try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) 11258{ 11259 enum neon_shape rs; 11260 struct neon_type_el et; 11261 11262 switch (args) 11263 { 11264 case 2: 11265 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11266 et = neon_check_type (2, rs, 11267 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11268 break; 11269 11270 case 3: 11271 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11272 et = neon_check_type (3, rs, 11273 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11274 break; 11275 11276 default: 11277 abort (); 11278 } 11279 11280 if (et.type != NT_invtype) 11281 { 11282 pfn (rs); 11283 return SUCCESS; 11284 } 11285 else 11286 inst.error = NULL; 11287 11288 return FAIL; 11289} 11290 11291static void 11292do_vfp_nsyn_mla_mls (enum neon_shape rs) 11293{ 11294 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; 11295 11296 if (rs == NS_FFF) 11297 { 11298 if (is_mla) 11299 do_vfp_nsyn_opcode ("fmacs"); 11300 else 11301 do_vfp_nsyn_opcode ("fmscs"); 11302 } 11303 else 11304 { 11305 if (is_mla) 11306 do_vfp_nsyn_opcode ("fmacd"); 11307 else 11308 do_vfp_nsyn_opcode ("fmscd"); 11309 } 11310} 11311 11312static void 11313do_vfp_nsyn_mul (enum neon_shape rs) 11314{ 11315 if (rs == NS_FFF) 11316 do_vfp_nsyn_opcode ("fmuls"); 11317 else 11318 do_vfp_nsyn_opcode ("fmuld"); 11319} 11320 11321static void 11322do_vfp_nsyn_abs_neg (enum neon_shape rs) 11323{ 11324 int is_neg = (inst.instruction & 0x80) != 0; 11325 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); 11326 11327 if (rs == NS_FF) 11328 { 11329 if (is_neg) 11330 do_vfp_nsyn_opcode ("fnegs"); 11331 else 11332 do_vfp_nsyn_opcode ("fabss"); 11333 } 11334 else 11335 { 11336 if (is_neg) 11337 do_vfp_nsyn_opcode ("fnegd"); 11338 else 11339 do_vfp_nsyn_opcode ("fabsd"); 11340 } 11341} 11342 11343/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision 11344 insns belong to Neon, and are handled elsewhere. */ 11345 11346static void 11347do_vfp_nsyn_ldm_stm (int is_dbmode) 11348{ 11349 int is_ldm = (inst.instruction & (1 << 20)) != 0; 11350 if (is_ldm) 11351 { 11352 if (is_dbmode) 11353 do_vfp_nsyn_opcode ("fldmdbs"); 11354 else 11355 do_vfp_nsyn_opcode ("fldmias"); 11356 } 11357 else 11358 { 11359 if (is_dbmode) 11360 do_vfp_nsyn_opcode ("fstmdbs"); 11361 else 11362 do_vfp_nsyn_opcode ("fstmias"); 11363 } 11364} 11365 11366static void 11367do_vfp_nsyn_sqrt (void) 11368{ 11369 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11370 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11371 11372 if (rs == NS_FF) 11373 do_vfp_nsyn_opcode ("fsqrts"); 11374 else 11375 do_vfp_nsyn_opcode ("fsqrtd"); 11376} 11377 11378static void 11379do_vfp_nsyn_div (void) 11380{ 11381 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11382 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11383 N_F32 | N_F64 | N_KEY | N_VFP); 11384 11385 if (rs == NS_FFF) 11386 do_vfp_nsyn_opcode ("fdivs"); 11387 else 11388 do_vfp_nsyn_opcode ("fdivd"); 11389} 11390 11391static void 11392do_vfp_nsyn_nmul (void) 11393{ 11394 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11395 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11396 N_F32 | N_F64 | N_KEY | N_VFP); 11397 11398 if (rs == NS_FFF) 11399 { 11400 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11401 do_vfp_sp_dyadic (); 11402 } 11403 else 11404 { 11405 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11406 do_vfp_dp_rd_rn_rm (); 11407 } 11408 do_vfp_cond_or_thumb (); 11409} 11410 11411static void 11412do_vfp_nsyn_cmp (void) 11413{ 11414 if (inst.operands[1].isreg) 11415 { 11416 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11417 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11418 11419 if (rs == NS_FF) 11420 { 11421 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11422 do_vfp_sp_monadic (); 11423 } 11424 else 11425 { 11426 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11427 do_vfp_dp_rd_rm (); 11428 } 11429 } 11430 else 11431 { 11432 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); 11433 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); 11434 11435 switch (inst.instruction & 0x0fffffff) 11436 { 11437 case N_MNEM_vcmp: 11438 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; 11439 break; 11440 case N_MNEM_vcmpe: 11441 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; 11442 break; 11443 default: 11444 abort (); 11445 } 11446 11447 if (rs == NS_FI) 11448 { 11449 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11450 do_vfp_sp_compare_z (); 11451 } 11452 else 11453 { 11454 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11455 do_vfp_dp_rd (); 11456 } 11457 } 11458 do_vfp_cond_or_thumb (); 11459} 11460 11461static void 11462nsyn_insert_sp (void) 11463{ 11464 inst.operands[1] = inst.operands[0]; 11465 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 11466 inst.operands[0].reg = 13; 11467 inst.operands[0].isreg = 1; 11468 inst.operands[0].writeback = 1; 11469 inst.operands[0].present = 1; 11470} 11471 11472static void 11473do_vfp_nsyn_push (void) 11474{ 11475 nsyn_insert_sp (); 11476 if (inst.operands[1].issingle) 11477 do_vfp_nsyn_opcode ("fstmdbs"); 11478 else 11479 do_vfp_nsyn_opcode ("fstmdbd"); 11480} 11481 11482static void 11483do_vfp_nsyn_pop (void) 11484{ 11485 nsyn_insert_sp (); 11486 if (inst.operands[1].issingle) 11487 do_vfp_nsyn_opcode ("fldmias"); 11488 else 11489 do_vfp_nsyn_opcode ("fldmiad"); 11490} 11491 11492/* Fix up Neon data-processing instructions, ORing in the correct bits for 11493 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ 11494 11495static unsigned 11496neon_dp_fixup (unsigned i) 11497{ 11498 if (thumb_mode) 11499 { 11500 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ 11501 if (i & (1 << 24)) 11502 i |= 1 << 28; 11503 11504 i &= ~(1 << 24); 11505 11506 i |= 0xef000000; 11507 } 11508 else 11509 i |= 0xf2000000; 11510 11511 return i; 11512} 11513 11514/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 11515 (0, 1, 2, 3). */ 11516 11517static unsigned 11518neon_logbits (unsigned x) 11519{ 11520 return ffs (x) - 4; 11521} 11522 11523#define LOW4(R) ((R) & 0xf) 11524#define HI1(R) (((R) >> 4) & 1) 11525 11526/* Encode insns with bit pattern: 11527 11528 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| 11529 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | 11530 11531 SIZE is passed in bits. -1 means size field isn't changed, in case it has a 11532 different meaning for some instruction. */ 11533 11534static void 11535neon_three_same (int isquad, int ubit, int size) 11536{ 11537 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11538 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11539 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 11540 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 11541 inst.instruction |= LOW4 (inst.operands[2].reg); 11542 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 11543 inst.instruction |= (isquad != 0) << 6; 11544 inst.instruction |= (ubit != 0) << 24; 11545 if (size != -1) 11546 inst.instruction |= neon_logbits (size) << 20; 11547 11548 inst.instruction = neon_dp_fixup (inst.instruction); 11549} 11550 11551/* Encode instructions of the form: 11552 11553 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| 11554 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | 11555 11556 Don't write size if SIZE == -1. */ 11557 11558static void 11559neon_two_same (int qbit, int ubit, int size) 11560{ 11561 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11562 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11563 inst.instruction |= LOW4 (inst.operands[1].reg); 11564 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11565 inst.instruction |= (qbit != 0) << 6; 11566 inst.instruction |= (ubit != 0) << 24; 11567 11568 if (size != -1) 11569 inst.instruction |= neon_logbits (size) << 18; 11570 11571 inst.instruction = neon_dp_fixup (inst.instruction); 11572} 11573 11574/* Neon instruction encoders, in approximate order of appearance. */ 11575 11576static void 11577do_neon_dyadic_i_su (void) 11578{ 11579 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11580 struct neon_type_el et = neon_check_type (3, rs, 11581 N_EQK, N_EQK, N_SU_32 | N_KEY); 11582 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11583} 11584 11585static void 11586do_neon_dyadic_i64_su (void) 11587{ 11588 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11589 struct neon_type_el et = neon_check_type (3, rs, 11590 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11591 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11592} 11593 11594static void 11595neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, 11596 unsigned immbits) 11597{ 11598 unsigned size = et.size >> 3; 11599 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11600 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11601 inst.instruction |= LOW4 (inst.operands[1].reg); 11602 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11603 inst.instruction |= (isquad != 0) << 6; 11604 inst.instruction |= immbits << 16; 11605 inst.instruction |= (size >> 3) << 7; 11606 inst.instruction |= (size & 0x7) << 19; 11607 if (write_ubit) 11608 inst.instruction |= (uval != 0) << 24; 11609 11610 inst.instruction = neon_dp_fixup (inst.instruction); 11611} 11612 11613static void 11614do_neon_shl_imm (void) 11615{ 11616 if (!inst.operands[2].isreg) 11617 { 11618 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11619 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); 11620 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11621 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); 11622 } 11623 else 11624 { 11625 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11626 struct neon_type_el et = neon_check_type (3, rs, 11627 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11628 unsigned int tmp; 11629 11630 /* VSHL/VQSHL 3-register variants have syntax such as: 11631 vshl.xx Dd, Dm, Dn 11632 whereas other 3-register operations encoded by neon_three_same have 11633 syntax like: 11634 vadd.xx Dd, Dn, Dm 11635 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg 11636 here. */ 11637 tmp = inst.operands[2].reg; 11638 inst.operands[2].reg = inst.operands[1].reg; 11639 inst.operands[1].reg = tmp; 11640 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11641 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11642 } 11643} 11644 11645static void 11646do_neon_qshl_imm (void) 11647{ 11648 if (!inst.operands[2].isreg) 11649 { 11650 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11651 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 11652 11653 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11654 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 11655 inst.operands[2].imm); 11656 } 11657 else 11658 { 11659 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11660 struct neon_type_el et = neon_check_type (3, rs, 11661 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11662 unsigned int tmp; 11663 11664 /* See note in do_neon_shl_imm. */ 11665 tmp = inst.operands[2].reg; 11666 inst.operands[2].reg = inst.operands[1].reg; 11667 inst.operands[1].reg = tmp; 11668 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11669 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11670 } 11671} 11672 11673static void 11674do_neon_rshl (void) 11675{ 11676 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11677 struct neon_type_el et = neon_check_type (3, rs, 11678 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11679 unsigned int tmp; 11680 11681 tmp = inst.operands[2].reg; 11682 inst.operands[2].reg = inst.operands[1].reg; 11683 inst.operands[1].reg = tmp; 11684 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11685} 11686 11687static int 11688neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) 11689{ 11690 /* Handle .I8 pseudo-instructions. */ 11691 if (size == 8) 11692 { 11693 /* Unfortunately, this will make everything apart from zero out-of-range. 11694 FIXME is this the intended semantics? There doesn't seem much point in 11695 accepting .I8 if so. */ 11696 immediate |= immediate << 8; 11697 size = 16; 11698 } 11699 11700 if (size >= 32) 11701 { 11702 if (immediate == (immediate & 0x000000ff)) 11703 { 11704 *immbits = immediate; 11705 return 0x1; 11706 } 11707 else if (immediate == (immediate & 0x0000ff00)) 11708 { 11709 *immbits = immediate >> 8; 11710 return 0x3; 11711 } 11712 else if (immediate == (immediate & 0x00ff0000)) 11713 { 11714 *immbits = immediate >> 16; 11715 return 0x5; 11716 } 11717 else if (immediate == (immediate & 0xff000000)) 11718 { 11719 *immbits = immediate >> 24; 11720 return 0x7; 11721 } 11722 if ((immediate & 0xffff) != (immediate >> 16)) 11723 goto bad_immediate; 11724 immediate &= 0xffff; 11725 } 11726 11727 if (immediate == (immediate & 0x000000ff)) 11728 { 11729 *immbits = immediate; 11730 return 0x9; 11731 } 11732 else if (immediate == (immediate & 0x0000ff00)) 11733 { 11734 *immbits = immediate >> 8; 11735 return 0xb; 11736 } 11737 11738 bad_immediate: 11739 first_error (_("immediate value out of range")); 11740 return FAIL; 11741} 11742 11743/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits 11744 A, B, C, D. */ 11745 11746static int 11747neon_bits_same_in_bytes (unsigned imm) 11748{ 11749 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) 11750 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) 11751 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) 11752 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); 11753} 11754 11755/* For immediate of above form, return 0bABCD. */ 11756 11757static unsigned 11758neon_squash_bits (unsigned imm) 11759{ 11760 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) 11761 | ((imm & 0x01000000) >> 21); 11762} 11763 11764/* Compress quarter-float representation to 0b...000 abcdefgh. */ 11765 11766static unsigned 11767neon_qfloat_bits (unsigned imm) 11768{ 11769 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); 11770} 11771 11772/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into 11773 the instruction. *OP is passed as the initial value of the op field, and 11774 may be set to a different value depending on the constant (i.e. 11775 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not 11776 MVN). If the immediate looks like a repeated parttern then also 11777 try smaller element sizes. */ 11778 11779static int 11780neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, 11781 unsigned *immbits, int *op, int size, 11782 enum neon_el_type type) 11783{ 11784 /* Only permit float immediates (including 0.0/-0.0) if the operand type is 11785 float. */ 11786 if (type == NT_float && !float_p) 11787 return FAIL; 11788 11789 if (type == NT_float && is_quarter_float (immlo) && immhi == 0) 11790 { 11791 if (size != 32 || *op == 1) 11792 return FAIL; 11793 *immbits = neon_qfloat_bits (immlo); 11794 return 0xf; 11795 } 11796 11797 if (size == 64) 11798 { 11799 if (neon_bits_same_in_bytes (immhi) 11800 && neon_bits_same_in_bytes (immlo)) 11801 { 11802 if (*op == 1) 11803 return FAIL; 11804 *immbits = (neon_squash_bits (immhi) << 4) 11805 | neon_squash_bits (immlo); 11806 *op = 1; 11807 return 0xe; 11808 } 11809 11810 if (immhi != immlo) 11811 return FAIL; 11812 } 11813 11814 if (size >= 32) 11815 { 11816 if (immlo == (immlo & 0x000000ff)) 11817 { 11818 *immbits = immlo; 11819 return 0x0; 11820 } 11821 else if (immlo == (immlo & 0x0000ff00)) 11822 { 11823 *immbits = immlo >> 8; 11824 return 0x2; 11825 } 11826 else if (immlo == (immlo & 0x00ff0000)) 11827 { 11828 *immbits = immlo >> 16; 11829 return 0x4; 11830 } 11831 else if (immlo == (immlo & 0xff000000)) 11832 { 11833 *immbits = immlo >> 24; 11834 return 0x6; 11835 } 11836 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) 11837 { 11838 *immbits = (immlo >> 8) & 0xff; 11839 return 0xc; 11840 } 11841 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) 11842 { 11843 *immbits = (immlo >> 16) & 0xff; 11844 return 0xd; 11845 } 11846 11847 if ((immlo & 0xffff) != (immlo >> 16)) 11848 return FAIL; 11849 immlo &= 0xffff; 11850 } 11851 11852 if (size >= 16) 11853 { 11854 if (immlo == (immlo & 0x000000ff)) 11855 { 11856 *immbits = immlo; 11857 return 0x8; 11858 } 11859 else if (immlo == (immlo & 0x0000ff00)) 11860 { 11861 *immbits = immlo >> 8; 11862 return 0xa; 11863 } 11864 11865 if ((immlo & 0xff) != (immlo >> 8)) 11866 return FAIL; 11867 immlo &= 0xff; 11868 } 11869 11870 if (immlo == (immlo & 0x000000ff)) 11871 { 11872 /* Don't allow MVN with 8-bit immediate. */ 11873 if (*op == 1) 11874 return FAIL; 11875 *immbits = immlo; 11876 return 0xe; 11877 } 11878 11879 return FAIL; 11880} 11881 11882/* Write immediate bits [7:0] to the following locations: 11883 11884 |28/24|23 19|18 16|15 4|3 0| 11885 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| 11886 11887 This function is used by VMOV/VMVN/VORR/VBIC. */ 11888 11889static void 11890neon_write_immbits (unsigned immbits) 11891{ 11892 inst.instruction |= immbits & 0xf; 11893 inst.instruction |= ((immbits >> 4) & 0x7) << 16; 11894 inst.instruction |= ((immbits >> 7) & 0x1) << 24; 11895} 11896 11897/* Invert low-order SIZE bits of XHI:XLO. */ 11898 11899static void 11900neon_invert_size (unsigned *xlo, unsigned *xhi, int size) 11901{ 11902 unsigned immlo = xlo ? *xlo : 0; 11903 unsigned immhi = xhi ? *xhi : 0; 11904 11905 switch (size) 11906 { 11907 case 8: 11908 immlo = (~immlo) & 0xff; 11909 break; 11910 11911 case 16: 11912 immlo = (~immlo) & 0xffff; 11913 break; 11914 11915 case 64: 11916 immhi = (~immhi) & 0xffffffff; 11917 /* fall through. */ 11918 11919 case 32: 11920 immlo = (~immlo) & 0xffffffff; 11921 break; 11922 11923 default: 11924 abort (); 11925 } 11926 11927 if (xlo) 11928 *xlo = immlo; 11929 11930 if (xhi) 11931 *xhi = immhi; 11932} 11933 11934static void 11935do_neon_logic (void) 11936{ 11937 if (inst.operands[2].present && inst.operands[2].isreg) 11938 { 11939 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11940 neon_check_type (3, rs, N_IGNORE_TYPE); 11941 /* U bit and size field were set as part of the bitmask. */ 11942 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11943 neon_three_same (neon_quad (rs), 0, -1); 11944 } 11945 else 11946 { 11947 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 11948 struct neon_type_el et = neon_check_type (2, rs, 11949 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 11950 enum neon_opc opcode = inst.instruction & 0x0fffffff; 11951 unsigned immbits; 11952 int cmode; 11953 11954 if (et.type == NT_invtype) 11955 return; 11956 11957 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11958 11959 immbits = inst.operands[1].imm; 11960 if (et.size == 64) 11961 { 11962 /* .i64 is a pseudo-op, so the immediate must be a repeating 11963 pattern. */ 11964 if (immbits != (inst.operands[1].regisimm ? 11965 inst.operands[1].reg : 0)) 11966 { 11967 /* Set immbits to an invalid constant. */ 11968 immbits = 0xdeadbeef; 11969 } 11970 } 11971 11972 switch (opcode) 11973 { 11974 case N_MNEM_vbic: 11975 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11976 break; 11977 11978 case N_MNEM_vorr: 11979 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11980 break; 11981 11982 case N_MNEM_vand: 11983 /* Pseudo-instruction for VBIC. */ 11984 neon_invert_size (&immbits, 0, et.size); 11985 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11986 break; 11987 11988 case N_MNEM_vorn: 11989 /* Pseudo-instruction for VORR. */ 11990 neon_invert_size (&immbits, 0, et.size); 11991 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11992 break; 11993 11994 default: 11995 abort (); 11996 } 11997 11998 if (cmode == FAIL) 11999 return; 12000 12001 inst.instruction |= neon_quad (rs) << 6; 12002 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12003 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12004 inst.instruction |= cmode << 8; 12005 neon_write_immbits (immbits); 12006 12007 inst.instruction = neon_dp_fixup (inst.instruction); 12008 } 12009} 12010 12011static void 12012do_neon_bitfield (void) 12013{ 12014 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12015 neon_check_type (3, rs, N_IGNORE_TYPE); 12016 neon_three_same (neon_quad (rs), 0, -1); 12017} 12018 12019static void 12020neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, 12021 unsigned destbits) 12022{ 12023 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12024 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, 12025 types | N_KEY); 12026 if (et.type == NT_float) 12027 { 12028 inst.instruction = NEON_ENC_FLOAT (inst.instruction); 12029 neon_three_same (neon_quad (rs), 0, -1); 12030 } 12031 else 12032 { 12033 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12034 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); 12035 } 12036} 12037 12038static void 12039do_neon_dyadic_if_su (void) 12040{ 12041 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12042} 12043 12044static void 12045do_neon_dyadic_if_su_d (void) 12046{ 12047 /* This version only allow D registers, but that constraint is enforced during 12048 operand parsing so we don't need to do anything extra here. */ 12049 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12050} 12051 12052static void 12053do_neon_dyadic_if_i_d (void) 12054{ 12055 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12056 affected if we specify unsigned args. */ 12057 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12058} 12059 12060enum vfp_or_neon_is_neon_bits 12061{ 12062 NEON_CHECK_CC = 1, 12063 NEON_CHECK_ARCH = 2 12064}; 12065 12066/* Call this function if an instruction which may have belonged to the VFP or 12067 Neon instruction sets, but turned out to be a Neon instruction (due to the 12068 operand types involved, etc.). We have to check and/or fix-up a couple of 12069 things: 12070 12071 - Make sure the user hasn't attempted to make a Neon instruction 12072 conditional. 12073 - Alter the value in the condition code field if necessary. 12074 - Make sure that the arch supports Neon instructions. 12075 12076 Which of these operations take place depends on bits from enum 12077 vfp_or_neon_is_neon_bits. 12078 12079 WARNING: This function has side effects! If NEON_CHECK_CC is used and the 12080 current instruction's condition is COND_ALWAYS, the condition field is 12081 changed to inst.uncond_value. This is necessary because instructions shared 12082 between VFP and Neon may be conditional for the VFP variants only, and the 12083 unconditional Neon version must have, e.g., 0xF in the condition field. */ 12084 12085static int 12086vfp_or_neon_is_neon (unsigned check) 12087{ 12088 /* Conditions are always legal in Thumb mode (IT blocks). */ 12089 if (!thumb_mode && (check & NEON_CHECK_CC)) 12090 { 12091 if (inst.cond != COND_ALWAYS) 12092 { 12093 first_error (_(BAD_COND)); 12094 return FAIL; 12095 } 12096 if (inst.uncond_value != -1) 12097 inst.instruction |= inst.uncond_value << 28; 12098 } 12099 12100 if ((check & NEON_CHECK_ARCH) 12101 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) 12102 { 12103 first_error (_(BAD_FPU)); 12104 return FAIL; 12105 } 12106 12107 return SUCCESS; 12108} 12109 12110static void 12111do_neon_addsub_if_i (void) 12112{ 12113 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) 12114 return; 12115 12116 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12117 return; 12118 12119 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12120 affected if we specify unsigned args. */ 12121 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); 12122} 12123 12124/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the 12125 result to be: 12126 V<op> A,B (A is operand 0, B is operand 2) 12127 to mean: 12128 V<op> A,B,A 12129 not: 12130 V<op> A,B,B 12131 so handle that case specially. */ 12132 12133static void 12134neon_exchange_operands (void) 12135{ 12136 void *scratch = alloca (sizeof (inst.operands[0])); 12137 if (inst.operands[1].present) 12138 { 12139 /* Swap operands[1] and operands[2]. */ 12140 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); 12141 inst.operands[1] = inst.operands[2]; 12142 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); 12143 } 12144 else 12145 { 12146 inst.operands[1] = inst.operands[2]; 12147 inst.operands[2] = inst.operands[0]; 12148 } 12149} 12150 12151static void 12152neon_compare (unsigned regtypes, unsigned immtypes, int invert) 12153{ 12154 if (inst.operands[2].isreg) 12155 { 12156 if (invert) 12157 neon_exchange_operands (); 12158 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); 12159 } 12160 else 12161 { 12162 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12163 struct neon_type_el et = neon_check_type (2, rs, 12164 N_EQK | N_SIZ, immtypes | N_KEY); 12165 12166 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12167 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12168 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12169 inst.instruction |= LOW4 (inst.operands[1].reg); 12170 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12171 inst.instruction |= neon_quad (rs) << 6; 12172 inst.instruction |= (et.type == NT_float) << 10; 12173 inst.instruction |= neon_logbits (et.size) << 18; 12174 12175 inst.instruction = neon_dp_fixup (inst.instruction); 12176 } 12177} 12178 12179static void 12180do_neon_cmp (void) 12181{ 12182 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); 12183} 12184 12185static void 12186do_neon_cmp_inv (void) 12187{ 12188 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); 12189} 12190 12191static void 12192do_neon_ceq (void) 12193{ 12194 neon_compare (N_IF_32, N_IF_32, FALSE); 12195} 12196 12197/* For multiply instructions, we have the possibility of 16-bit or 32-bit 12198 scalars, which are encoded in 5 bits, M : Rm. 12199 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in 12200 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the 12201 index in M. */ 12202 12203static unsigned 12204neon_scalar_for_mul (unsigned scalar, unsigned elsize) 12205{ 12206 unsigned regno = NEON_SCALAR_REG (scalar); 12207 unsigned elno = NEON_SCALAR_INDEX (scalar); 12208 12209 switch (elsize) 12210 { 12211 case 16: 12212 if (regno > 7 || elno > 3) 12213 goto bad_scalar; 12214 return regno | (elno << 3); 12215 12216 case 32: 12217 if (regno > 15 || elno > 1) 12218 goto bad_scalar; 12219 return regno | (elno << 4); 12220 12221 default: 12222 bad_scalar: 12223 first_error (_("scalar out of range for multiply instruction")); 12224 } 12225 12226 return 0; 12227} 12228 12229/* Encode multiply / multiply-accumulate scalar instructions. */ 12230 12231static void 12232neon_mul_mac (struct neon_type_el et, int ubit) 12233{ 12234 unsigned scalar; 12235 12236 /* Give a more helpful error message if we have an invalid type. */ 12237 if (et.type == NT_invtype) 12238 return; 12239 12240 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); 12241 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12242 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12243 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12244 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12245 inst.instruction |= LOW4 (scalar); 12246 inst.instruction |= HI1 (scalar) << 5; 12247 inst.instruction |= (et.type == NT_float) << 8; 12248 inst.instruction |= neon_logbits (et.size) << 20; 12249 inst.instruction |= (ubit != 0) << 24; 12250 12251 inst.instruction = neon_dp_fixup (inst.instruction); 12252} 12253 12254static void 12255do_neon_mac_maybe_scalar (void) 12256{ 12257 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) 12258 return; 12259 12260 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12261 return; 12262 12263 if (inst.operands[2].isscalar) 12264 { 12265 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12266 struct neon_type_el et = neon_check_type (3, rs, 12267 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); 12268 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12269 neon_mul_mac (et, neon_quad (rs)); 12270 } 12271 else 12272 { 12273 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12274 affected if we specify unsigned args. */ 12275 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12276 } 12277} 12278 12279static void 12280do_neon_tst (void) 12281{ 12282 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12283 struct neon_type_el et = neon_check_type (3, rs, 12284 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); 12285 neon_three_same (neon_quad (rs), 0, et.size); 12286} 12287 12288/* VMUL with 3 registers allows the P8 type. The scalar version supports the 12289 same types as the MAC equivalents. The polynomial type for this instruction 12290 is encoded the same as the integer type. */ 12291 12292static void 12293do_neon_mul (void) 12294{ 12295 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) 12296 return; 12297 12298 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12299 return; 12300 12301 if (inst.operands[2].isscalar) 12302 do_neon_mac_maybe_scalar (); 12303 else 12304 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); 12305} 12306 12307static void 12308do_neon_qdmulh (void) 12309{ 12310 if (inst.operands[2].isscalar) 12311 { 12312 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12313 struct neon_type_el et = neon_check_type (3, rs, 12314 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12315 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12316 neon_mul_mac (et, neon_quad (rs)); 12317 } 12318 else 12319 { 12320 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12321 struct neon_type_el et = neon_check_type (3, rs, 12322 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12323 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12324 /* The U bit (rounding) comes from bit mask. */ 12325 neon_three_same (neon_quad (rs), 0, et.size); 12326 } 12327} 12328 12329static void 12330do_neon_fcmp_absolute (void) 12331{ 12332 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12333 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12334 /* Size field comes from bit mask. */ 12335 neon_three_same (neon_quad (rs), 1, -1); 12336} 12337 12338static void 12339do_neon_fcmp_absolute_inv (void) 12340{ 12341 neon_exchange_operands (); 12342 do_neon_fcmp_absolute (); 12343} 12344 12345static void 12346do_neon_step (void) 12347{ 12348 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12349 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12350 neon_three_same (neon_quad (rs), 0, -1); 12351} 12352 12353static void 12354do_neon_abs_neg (void) 12355{ 12356 enum neon_shape rs; 12357 struct neon_type_el et; 12358 12359 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) 12360 return; 12361 12362 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12363 return; 12364 12365 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12366 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); 12367 12368 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12369 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12370 inst.instruction |= LOW4 (inst.operands[1].reg); 12371 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12372 inst.instruction |= neon_quad (rs) << 6; 12373 inst.instruction |= (et.type == NT_float) << 10; 12374 inst.instruction |= neon_logbits (et.size) << 18; 12375 12376 inst.instruction = neon_dp_fixup (inst.instruction); 12377} 12378 12379static void 12380do_neon_sli (void) 12381{ 12382 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12383 struct neon_type_el et = neon_check_type (2, rs, 12384 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12385 int imm = inst.operands[2].imm; 12386 constraint (imm < 0 || (unsigned)imm >= et.size, 12387 _("immediate out of range for insert")); 12388 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12389} 12390 12391static void 12392do_neon_sri (void) 12393{ 12394 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12395 struct neon_type_el et = neon_check_type (2, rs, 12396 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12397 int imm = inst.operands[2].imm; 12398 constraint (imm < 1 || (unsigned)imm > et.size, 12399 _("immediate out of range for insert")); 12400 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); 12401} 12402 12403static void 12404do_neon_qshlu_imm (void) 12405{ 12406 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12407 struct neon_type_el et = neon_check_type (2, rs, 12408 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); 12409 int imm = inst.operands[2].imm; 12410 constraint (imm < 0 || (unsigned)imm >= et.size, 12411 _("immediate out of range for shift")); 12412 /* Only encodes the 'U present' variant of the instruction. 12413 In this case, signed types have OP (bit 8) set to 0. 12414 Unsigned types have OP set to 1. */ 12415 inst.instruction |= (et.type == NT_unsigned) << 8; 12416 /* The rest of the bits are the same as other immediate shifts. */ 12417 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12418} 12419 12420static void 12421do_neon_qmovn (void) 12422{ 12423 struct neon_type_el et = neon_check_type (2, NS_DQ, 12424 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12425 /* Saturating move where operands can be signed or unsigned, and the 12426 destination has the same signedness. */ 12427 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12428 if (et.type == NT_unsigned) 12429 inst.instruction |= 0xc0; 12430 else 12431 inst.instruction |= 0x80; 12432 neon_two_same (0, 1, et.size / 2); 12433} 12434 12435static void 12436do_neon_qmovun (void) 12437{ 12438 struct neon_type_el et = neon_check_type (2, NS_DQ, 12439 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12440 /* Saturating move with unsigned results. Operands must be signed. */ 12441 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12442 neon_two_same (0, 1, et.size / 2); 12443} 12444 12445static void 12446do_neon_rshift_sat_narrow (void) 12447{ 12448 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12449 or unsigned. If operands are unsigned, results must also be unsigned. */ 12450 struct neon_type_el et = neon_check_type (2, NS_DQI, 12451 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12452 int imm = inst.operands[2].imm; 12453 /* This gets the bounds check, size encoding and immediate bits calculation 12454 right. */ 12455 et.size /= 2; 12456 12457 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for 12458 VQMOVN.I<size> <Dd>, <Qm>. */ 12459 if (imm == 0) 12460 { 12461 inst.operands[2].present = 0; 12462 inst.instruction = N_MNEM_vqmovn; 12463 do_neon_qmovn (); 12464 return; 12465 } 12466 12467 constraint (imm < 1 || (unsigned)imm > et.size, 12468 _("immediate out of range")); 12469 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); 12470} 12471 12472static void 12473do_neon_rshift_sat_narrow_u (void) 12474{ 12475 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12476 or unsigned. If operands are unsigned, results must also be unsigned. */ 12477 struct neon_type_el et = neon_check_type (2, NS_DQI, 12478 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12479 int imm = inst.operands[2].imm; 12480 /* This gets the bounds check, size encoding and immediate bits calculation 12481 right. */ 12482 et.size /= 2; 12483 12484 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for 12485 VQMOVUN.I<size> <Dd>, <Qm>. */ 12486 if (imm == 0) 12487 { 12488 inst.operands[2].present = 0; 12489 inst.instruction = N_MNEM_vqmovun; 12490 do_neon_qmovun (); 12491 return; 12492 } 12493 12494 constraint (imm < 1 || (unsigned)imm > et.size, 12495 _("immediate out of range")); 12496 /* FIXME: The manual is kind of unclear about what value U should have in 12497 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it 12498 must be 1. */ 12499 neon_imm_shift (TRUE, 1, 0, et, et.size - imm); 12500} 12501 12502static void 12503do_neon_movn (void) 12504{ 12505 struct neon_type_el et = neon_check_type (2, NS_DQ, 12506 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12507 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12508 neon_two_same (0, 1, et.size / 2); 12509} 12510 12511static void 12512do_neon_rshift_narrow (void) 12513{ 12514 struct neon_type_el et = neon_check_type (2, NS_DQI, 12515 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12516 int imm = inst.operands[2].imm; 12517 /* This gets the bounds check, size encoding and immediate bits calculation 12518 right. */ 12519 et.size /= 2; 12520 12521 /* If immediate is zero then we are a pseudo-instruction for 12522 VMOVN.I<size> <Dd>, <Qm> */ 12523 if (imm == 0) 12524 { 12525 inst.operands[2].present = 0; 12526 inst.instruction = N_MNEM_vmovn; 12527 do_neon_movn (); 12528 return; 12529 } 12530 12531 constraint (imm < 1 || (unsigned)imm > et.size, 12532 _("immediate out of range for narrowing operation")); 12533 neon_imm_shift (FALSE, 0, 0, et, et.size - imm); 12534} 12535 12536static void 12537do_neon_shll (void) 12538{ 12539 /* FIXME: Type checking when lengthening. */ 12540 struct neon_type_el et = neon_check_type (2, NS_QDI, 12541 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); 12542 unsigned imm = inst.operands[2].imm; 12543 12544 if (imm == et.size) 12545 { 12546 /* Maximum shift variant. */ 12547 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12548 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12549 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12550 inst.instruction |= LOW4 (inst.operands[1].reg); 12551 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12552 inst.instruction |= neon_logbits (et.size) << 18; 12553 12554 inst.instruction = neon_dp_fixup (inst.instruction); 12555 } 12556 else 12557 { 12558 /* A more-specific type check for non-max versions. */ 12559 et = neon_check_type (2, NS_QDI, 12560 N_EQK | N_DBL, N_SU_32 | N_KEY); 12561 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12562 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); 12563 } 12564} 12565 12566/* Check the various types for the VCVT instruction, and return which version 12567 the current instruction is. */ 12568 12569static int 12570neon_cvt_flavour (enum neon_shape rs) 12571{ 12572#define CVT_VAR(C,X,Y) \ 12573 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ 12574 if (et.type != NT_invtype) \ 12575 { \ 12576 inst.error = NULL; \ 12577 return (C); \ 12578 } 12579 struct neon_type_el et; 12580 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF 12581 || rs == NS_FF) ? N_VFP : 0; 12582 /* The instruction versions which take an immediate take one register 12583 argument, which is extended to the width of the full register. Thus the 12584 "source" and "destination" registers must have the same width. Hack that 12585 here by making the size equal to the key (wider, in this case) operand. */ 12586 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; 12587 12588 CVT_VAR (0, N_S32, N_F32); 12589 CVT_VAR (1, N_U32, N_F32); 12590 CVT_VAR (2, N_F32, N_S32); 12591 CVT_VAR (3, N_F32, N_U32); 12592 12593 whole_reg = N_VFP; 12594 12595 /* VFP instructions. */ 12596 CVT_VAR (4, N_F32, N_F64); 12597 CVT_VAR (5, N_F64, N_F32); 12598 CVT_VAR (6, N_S32, N_F64 | key); 12599 CVT_VAR (7, N_U32, N_F64 | key); 12600 CVT_VAR (8, N_F64 | key, N_S32); 12601 CVT_VAR (9, N_F64 | key, N_U32); 12602 /* VFP instructions with bitshift. */ 12603 CVT_VAR (10, N_F32 | key, N_S16); 12604 CVT_VAR (11, N_F32 | key, N_U16); 12605 CVT_VAR (12, N_F64 | key, N_S16); 12606 CVT_VAR (13, N_F64 | key, N_U16); 12607 CVT_VAR (14, N_S16, N_F32 | key); 12608 CVT_VAR (15, N_U16, N_F32 | key); 12609 CVT_VAR (16, N_S16, N_F64 | key); 12610 CVT_VAR (17, N_U16, N_F64 | key); 12611 12612 return -1; 12613#undef CVT_VAR 12614} 12615 12616/* Neon-syntax VFP conversions. */ 12617 12618static void 12619do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) 12620{ 12621 const char *opname = 0; 12622 12623 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) 12624 { 12625 /* Conversions with immediate bitshift. */ 12626 const char *enc[] = 12627 { 12628 "ftosls", 12629 "ftouls", 12630 "fsltos", 12631 "fultos", 12632 NULL, 12633 NULL, 12634 "ftosld", 12635 "ftould", 12636 "fsltod", 12637 "fultod", 12638 "fshtos", 12639 "fuhtos", 12640 "fshtod", 12641 "fuhtod", 12642 "ftoshs", 12643 "ftouhs", 12644 "ftoshd", 12645 "ftouhd" 12646 }; 12647 12648 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12649 { 12650 opname = enc[flavour]; 12651 constraint (inst.operands[0].reg != inst.operands[1].reg, 12652 _("operands 0 and 1 must be the same register")); 12653 inst.operands[1] = inst.operands[2]; 12654 memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); 12655 } 12656 } 12657 else 12658 { 12659 /* Conversions without bitshift. */ 12660 const char *enc[] = 12661 { 12662 "ftosis", 12663 "ftouis", 12664 "fsitos", 12665 "fuitos", 12666 "fcvtsd", 12667 "fcvtds", 12668 "ftosid", 12669 "ftouid", 12670 "fsitod", 12671 "fuitod" 12672 }; 12673 12674 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12675 opname = enc[flavour]; 12676 } 12677 12678 if (opname) 12679 do_vfp_nsyn_opcode (opname); 12680} 12681 12682static void 12683do_vfp_nsyn_cvtz (void) 12684{ 12685 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); 12686 int flavour = neon_cvt_flavour (rs); 12687 const char *enc[] = 12688 { 12689 "ftosizs", 12690 "ftouizs", 12691 NULL, 12692 NULL, 12693 NULL, 12694 NULL, 12695 "ftosizd", 12696 "ftouizd" 12697 }; 12698 12699 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) 12700 do_vfp_nsyn_opcode (enc[flavour]); 12701} 12702 12703static void 12704do_neon_cvt (void) 12705{ 12706 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, 12707 NS_FD, NS_DF, NS_FF, NS_NULL); 12708 int flavour = neon_cvt_flavour (rs); 12709 12710 /* VFP rather than Neon conversions. */ 12711 if (flavour >= 4) 12712 { 12713 do_vfp_nsyn_cvt (rs, flavour); 12714 return; 12715 } 12716 12717 switch (rs) 12718 { 12719 case NS_DDI: 12720 case NS_QQI: 12721 { 12722 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12723 return; 12724 12725 /* Fixed-point conversion with #0 immediate is encoded as an 12726 integer conversion. */ 12727 if (inst.operands[2].present && inst.operands[2].imm == 0) 12728 goto int_encode; 12729 unsigned immbits = 32 - inst.operands[2].imm; 12730 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; 12731 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12732 if (flavour != -1) 12733 inst.instruction |= enctab[flavour]; 12734 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12735 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12736 inst.instruction |= LOW4 (inst.operands[1].reg); 12737 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12738 inst.instruction |= neon_quad (rs) << 6; 12739 inst.instruction |= 1 << 21; 12740 inst.instruction |= immbits << 16; 12741 12742 inst.instruction = neon_dp_fixup (inst.instruction); 12743 } 12744 break; 12745 12746 case NS_DD: 12747 case NS_QQ: 12748 int_encode: 12749 { 12750 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; 12751 12752 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12753 12754 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12755 return; 12756 12757 if (flavour != -1) 12758 inst.instruction |= enctab[flavour]; 12759 12760 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12761 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12762 inst.instruction |= LOW4 (inst.operands[1].reg); 12763 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12764 inst.instruction |= neon_quad (rs) << 6; 12765 inst.instruction |= 2 << 18; 12766 12767 inst.instruction = neon_dp_fixup (inst.instruction); 12768 } 12769 break; 12770 12771 default: 12772 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ 12773 do_vfp_nsyn_cvt (rs, flavour); 12774 } 12775} 12776 12777static void 12778neon_move_immediate (void) 12779{ 12780 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 12781 struct neon_type_el et = neon_check_type (2, rs, 12782 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 12783 unsigned immlo, immhi = 0, immbits; 12784 int op, cmode, float_p; 12785 12786 constraint (et.type == NT_invtype, 12787 _("operand size must be specified for immediate VMOV")); 12788 12789 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ 12790 op = (inst.instruction & (1 << 5)) != 0; 12791 12792 immlo = inst.operands[1].imm; 12793 if (inst.operands[1].regisimm) 12794 immhi = inst.operands[1].reg; 12795 12796 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, 12797 _("immediate has bits set outside the operand size")); 12798 12799 float_p = inst.operands[1].immisfloat; 12800 12801 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, 12802 et.size, et.type)) == FAIL) 12803 { 12804 /* Invert relevant bits only. */ 12805 neon_invert_size (&immlo, &immhi, et.size); 12806 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable 12807 with one or the other; those cases are caught by 12808 neon_cmode_for_move_imm. */ 12809 op = !op; 12810 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, 12811 &op, et.size, et.type)) == FAIL) 12812 { 12813 first_error (_("immediate out of range")); 12814 return; 12815 } 12816 } 12817 12818 inst.instruction &= ~(1 << 5); 12819 inst.instruction |= op << 5; 12820 12821 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12822 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12823 inst.instruction |= neon_quad (rs) << 6; 12824 inst.instruction |= cmode << 8; 12825 12826 neon_write_immbits (immbits); 12827} 12828 12829static void 12830do_neon_mvn (void) 12831{ 12832 if (inst.operands[1].isreg) 12833 { 12834 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12835 12836 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12837 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12838 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12839 inst.instruction |= LOW4 (inst.operands[1].reg); 12840 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12841 inst.instruction |= neon_quad (rs) << 6; 12842 } 12843 else 12844 { 12845 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12846 neon_move_immediate (); 12847 } 12848 12849 inst.instruction = neon_dp_fixup (inst.instruction); 12850} 12851 12852/* Encode instructions of form: 12853 12854 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| 12855 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | 12856 12857*/ 12858 12859static void 12860neon_mixed_length (struct neon_type_el et, unsigned size) 12861{ 12862 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12863 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12864 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12865 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12866 inst.instruction |= LOW4 (inst.operands[2].reg); 12867 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12868 inst.instruction |= (et.type == NT_unsigned) << 24; 12869 inst.instruction |= neon_logbits (size) << 20; 12870 12871 inst.instruction = neon_dp_fixup (inst.instruction); 12872} 12873 12874static void 12875do_neon_dyadic_long (void) 12876{ 12877 /* FIXME: Type checking for lengthening op. */ 12878 struct neon_type_el et = neon_check_type (3, NS_QDD, 12879 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); 12880 neon_mixed_length (et, et.size); 12881} 12882 12883static void 12884do_neon_abal (void) 12885{ 12886 struct neon_type_el et = neon_check_type (3, NS_QDD, 12887 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); 12888 neon_mixed_length (et, et.size); 12889} 12890 12891static void 12892neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) 12893{ 12894 if (inst.operands[2].isscalar) 12895 { 12896 struct neon_type_el et = neon_check_type (3, NS_QDS, 12897 N_EQK | N_DBL, N_EQK, regtypes | N_KEY); 12898 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12899 neon_mul_mac (et, et.type == NT_unsigned); 12900 } 12901 else 12902 { 12903 struct neon_type_el et = neon_check_type (3, NS_QDD, 12904 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); 12905 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12906 neon_mixed_length (et, et.size); 12907 } 12908} 12909 12910static void 12911do_neon_mac_maybe_scalar_long (void) 12912{ 12913 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); 12914} 12915 12916static void 12917do_neon_dyadic_wide (void) 12918{ 12919 struct neon_type_el et = neon_check_type (3, NS_QQD, 12920 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); 12921 neon_mixed_length (et, et.size); 12922} 12923 12924static void 12925do_neon_dyadic_narrow (void) 12926{ 12927 struct neon_type_el et = neon_check_type (3, NS_QDD, 12928 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); 12929 /* Operand sign is unimportant, and the U bit is part of the opcode, 12930 so force the operand type to integer. */ 12931 et.type = NT_integer; 12932 neon_mixed_length (et, et.size / 2); 12933} 12934 12935static void 12936do_neon_mul_sat_scalar_long (void) 12937{ 12938 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); 12939} 12940 12941static void 12942do_neon_vmull (void) 12943{ 12944 if (inst.operands[2].isscalar) 12945 do_neon_mac_maybe_scalar_long (); 12946 else 12947 { 12948 struct neon_type_el et = neon_check_type (3, NS_QDD, 12949 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); 12950 if (et.type == NT_poly) 12951 inst.instruction = NEON_ENC_POLY (inst.instruction); 12952 else 12953 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12954 /* For polynomial encoding, size field must be 0b00 and the U bit must be 12955 zero. Should be OK as-is. */ 12956 neon_mixed_length (et, et.size); 12957 } 12958} 12959 12960static void 12961do_neon_ext (void) 12962{ 12963 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); 12964 struct neon_type_el et = neon_check_type (3, rs, 12965 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12966 unsigned imm = (inst.operands[3].imm * et.size) / 8; 12967 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range")); 12968 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12969 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12970 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12971 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12972 inst.instruction |= LOW4 (inst.operands[2].reg); 12973 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12974 inst.instruction |= neon_quad (rs) << 6; 12975 inst.instruction |= imm << 8; 12976 12977 inst.instruction = neon_dp_fixup (inst.instruction); 12978} 12979 12980static void 12981do_neon_rev (void) 12982{ 12983 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12984 struct neon_type_el et = neon_check_type (2, rs, 12985 N_EQK, N_8 | N_16 | N_32 | N_KEY); 12986 unsigned op = (inst.instruction >> 7) & 3; 12987 /* N (width of reversed regions) is encoded as part of the bitmask. We 12988 extract it here to check the elements to be reversed are smaller. 12989 Otherwise we'd get a reserved instruction. */ 12990 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; 12991 assert (elsize != 0); 12992 constraint (et.size >= elsize, 12993 _("elements must be smaller than reversal region")); 12994 neon_two_same (neon_quad (rs), 1, et.size); 12995} 12996 12997static void 12998do_neon_dup (void) 12999{ 13000 if (inst.operands[1].isscalar) 13001 { 13002 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); 13003 struct neon_type_el et = neon_check_type (2, rs, 13004 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13005 unsigned sizebits = et.size >> 3; 13006 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); 13007 int logsize = neon_logbits (et.size); 13008 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; 13009 13010 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) 13011 return; 13012 13013 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 13014 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13015 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13016 inst.instruction |= LOW4 (dm); 13017 inst.instruction |= HI1 (dm) << 5; 13018 inst.instruction |= neon_quad (rs) << 6; 13019 inst.instruction |= x << 17; 13020 inst.instruction |= sizebits << 16; 13021 13022 inst.instruction = neon_dp_fixup (inst.instruction); 13023 } 13024 else 13025 { 13026 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); 13027 struct neon_type_el et = neon_check_type (2, rs, 13028 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13029 /* Duplicate ARM register to lanes of vector. */ 13030 inst.instruction = NEON_ENC_ARMREG (inst.instruction); 13031 switch (et.size) 13032 { 13033 case 8: inst.instruction |= 0x400000; break; 13034 case 16: inst.instruction |= 0x000020; break; 13035 case 32: inst.instruction |= 0x000000; break; 13036 default: break; 13037 } 13038 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13039 inst.instruction |= LOW4 (inst.operands[0].reg) << 16; 13040 inst.instruction |= HI1 (inst.operands[0].reg) << 7; 13041 inst.instruction |= neon_quad (rs) << 21; 13042 /* The encoding for this instruction is identical for the ARM and Thumb 13043 variants, except for the condition field. */ 13044 do_vfp_cond_or_thumb (); 13045 } 13046} 13047 13048/* VMOV has particularly many variations. It can be one of: 13049 0. VMOV<c><q> <Qd>, <Qm> 13050 1. VMOV<c><q> <Dd>, <Dm> 13051 (Register operations, which are VORR with Rm = Rn.) 13052 2. VMOV<c><q>.<dt> <Qd>, #<imm> 13053 3. VMOV<c><q>.<dt> <Dd>, #<imm> 13054 (Immediate loads.) 13055 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> 13056 (ARM register to scalar.) 13057 5. VMOV<c><q> <Dm>, <Rd>, <Rn> 13058 (Two ARM registers to vector.) 13059 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> 13060 (Scalar to ARM register.) 13061 7. VMOV<c><q> <Rd>, <Rn>, <Dm> 13062 (Vector to two ARM registers.) 13063 8. VMOV.F32 <Sd>, <Sm> 13064 9. VMOV.F64 <Dd>, <Dm> 13065 (VFP register moves.) 13066 10. VMOV.F32 <Sd>, #imm 13067 11. VMOV.F64 <Dd>, #imm 13068 (VFP float immediate load.) 13069 12. VMOV <Rd>, <Sm> 13070 (VFP single to ARM reg.) 13071 13. VMOV <Sd>, <Rm> 13072 (ARM reg to VFP single.) 13073 14. VMOV <Rd>, <Re>, <Sn>, <Sm> 13074 (Two ARM regs to two VFP singles.) 13075 15. VMOV <Sd>, <Se>, <Rn>, <Rm> 13076 (Two VFP singles to two ARM regs.) 13077 13078 These cases can be disambiguated using neon_select_shape, except cases 1/9 13079 and 3/11 which depend on the operand type too. 13080 13081 All the encoded bits are hardcoded by this function. 13082 13083 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). 13084 Cases 5, 7 may be used with VFPv2 and above. 13085 13086 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you 13087 can specify a type where it doesn't make sense to, and is ignored). 13088*/ 13089 13090static void 13091do_neon_mov (void) 13092{ 13093 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, 13094 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, 13095 NS_NULL); 13096 struct neon_type_el et; 13097 const char *ldconst = 0; 13098 13099 switch (rs) 13100 { 13101 case NS_DD: /* case 1/9. */ 13102 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13103 /* It is not an error here if no type is given. */ 13104 inst.error = NULL; 13105 if (et.type == NT_float && et.size == 64) 13106 { 13107 do_vfp_nsyn_opcode ("fcpyd"); 13108 break; 13109 } 13110 /* fall through. */ 13111 13112 case NS_QQ: /* case 0/1. */ 13113 { 13114 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13115 return; 13116 /* The architecture manual I have doesn't explicitly state which 13117 value the U bit should have for register->register moves, but 13118 the equivalent VORR instruction has U = 0, so do that. */ 13119 inst.instruction = 0x0200110; 13120 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13121 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13122 inst.instruction |= LOW4 (inst.operands[1].reg); 13123 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13124 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13125 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13126 inst.instruction |= neon_quad (rs) << 6; 13127 13128 inst.instruction = neon_dp_fixup (inst.instruction); 13129 } 13130 break; 13131 13132 case NS_DI: /* case 3/11. */ 13133 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13134 inst.error = NULL; 13135 if (et.type == NT_float && et.size == 64) 13136 { 13137 /* case 11 (fconstd). */ 13138 ldconst = "fconstd"; 13139 goto encode_fconstd; 13140 } 13141 /* fall through. */ 13142 13143 case NS_QI: /* case 2/3. */ 13144 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13145 return; 13146 inst.instruction = 0x0800010; 13147 neon_move_immediate (); 13148 inst.instruction = neon_dp_fixup (inst.instruction); 13149 break; 13150 13151 case NS_SR: /* case 4. */ 13152 { 13153 unsigned bcdebits = 0; 13154 struct neon_type_el et = neon_check_type (2, NS_NULL, 13155 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13156 int logsize = neon_logbits (et.size); 13157 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); 13158 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); 13159 13160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13161 _(BAD_FPU)); 13162 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13163 && et.size != 32, _(BAD_FPU)); 13164 constraint (et.type == NT_invtype, _("bad type for scalar")); 13165 constraint (x >= 64 / et.size, _("scalar index out of range")); 13166 13167 switch (et.size) 13168 { 13169 case 8: bcdebits = 0x8; break; 13170 case 16: bcdebits = 0x1; break; 13171 case 32: bcdebits = 0x0; break; 13172 default: ; 13173 } 13174 13175 bcdebits |= x << logsize; 13176 13177 inst.instruction = 0xe000b10; 13178 do_vfp_cond_or_thumb (); 13179 inst.instruction |= LOW4 (dn) << 16; 13180 inst.instruction |= HI1 (dn) << 7; 13181 inst.instruction |= inst.operands[1].reg << 12; 13182 inst.instruction |= (bcdebits & 3) << 5; 13183 inst.instruction |= (bcdebits >> 2) << 21; 13184 } 13185 break; 13186 13187 case NS_DRR: /* case 5 (fmdrr). */ 13188 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13189 _(BAD_FPU)); 13190 13191 inst.instruction = 0xc400b10; 13192 do_vfp_cond_or_thumb (); 13193 inst.instruction |= LOW4 (inst.operands[0].reg); 13194 inst.instruction |= HI1 (inst.operands[0].reg) << 5; 13195 inst.instruction |= inst.operands[1].reg << 12; 13196 inst.instruction |= inst.operands[2].reg << 16; 13197 break; 13198 13199 case NS_RS: /* case 6. */ 13200 { 13201 struct neon_type_el et = neon_check_type (2, NS_NULL, 13202 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); 13203 unsigned logsize = neon_logbits (et.size); 13204 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); 13205 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); 13206 unsigned abcdebits = 0; 13207 13208 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13209 _(BAD_FPU)); 13210 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13211 && et.size != 32, _(BAD_FPU)); 13212 constraint (et.type == NT_invtype, _("bad type for scalar")); 13213 constraint (x >= 64 / et.size, _("scalar index out of range")); 13214 13215 switch (et.size) 13216 { 13217 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; 13218 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; 13219 case 32: abcdebits = 0x00; break; 13220 default: ; 13221 } 13222 13223 abcdebits |= x << logsize; 13224 inst.instruction = 0xe100b10; 13225 do_vfp_cond_or_thumb (); 13226 inst.instruction |= LOW4 (dn) << 16; 13227 inst.instruction |= HI1 (dn) << 7; 13228 inst.instruction |= inst.operands[0].reg << 12; 13229 inst.instruction |= (abcdebits & 3) << 5; 13230 inst.instruction |= (abcdebits >> 2) << 21; 13231 } 13232 break; 13233 13234 case NS_RRD: /* case 7 (fmrrd). */ 13235 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13236 _(BAD_FPU)); 13237 13238 inst.instruction = 0xc500b10; 13239 do_vfp_cond_or_thumb (); 13240 inst.instruction |= inst.operands[0].reg << 12; 13241 inst.instruction |= inst.operands[1].reg << 16; 13242 inst.instruction |= LOW4 (inst.operands[2].reg); 13243 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13244 break; 13245 13246 case NS_FF: /* case 8 (fcpys). */ 13247 do_vfp_nsyn_opcode ("fcpys"); 13248 break; 13249 13250 case NS_FI: /* case 10 (fconsts). */ 13251 ldconst = "fconsts"; 13252 encode_fconstd: 13253 if (is_quarter_float (inst.operands[1].imm)) 13254 { 13255 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); 13256 do_vfp_nsyn_opcode (ldconst); 13257 } 13258 else 13259 first_error (_("immediate out of range")); 13260 break; 13261 13262 case NS_RF: /* case 12 (fmrs). */ 13263 do_vfp_nsyn_opcode ("fmrs"); 13264 break; 13265 13266 case NS_FR: /* case 13 (fmsr). */ 13267 do_vfp_nsyn_opcode ("fmsr"); 13268 break; 13269 13270 /* The encoders for the fmrrs and fmsrr instructions expect three operands 13271 (one of which is a list), but we have parsed four. Do some fiddling to 13272 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 13273 expect. */ 13274 case NS_RRFF: /* case 14 (fmrrs). */ 13275 constraint (inst.operands[3].reg != inst.operands[2].reg + 1, 13276 _("VFP registers must be adjacent")); 13277 inst.operands[2].imm = 2; 13278 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13279 do_vfp_nsyn_opcode ("fmrrs"); 13280 break; 13281 13282 case NS_FFRR: /* case 15 (fmsrr). */ 13283 constraint (inst.operands[1].reg != inst.operands[0].reg + 1, 13284 _("VFP registers must be adjacent")); 13285 inst.operands[1] = inst.operands[2]; 13286 inst.operands[2] = inst.operands[3]; 13287 inst.operands[0].imm = 2; 13288 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13289 do_vfp_nsyn_opcode ("fmsrr"); 13290 break; 13291 13292 default: 13293 abort (); 13294 } 13295} 13296 13297static void 13298do_neon_rshift_round_imm (void) 13299{ 13300 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13301 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 13302 int imm = inst.operands[2].imm; 13303 13304 /* imm == 0 case is encoded as VMOV for V{R}SHR. */ 13305 if (imm == 0) 13306 { 13307 inst.operands[2].present = 0; 13308 do_neon_mov (); 13309 return; 13310 } 13311 13312 constraint (imm < 1 || (unsigned)imm > et.size, 13313 _("immediate out of range for shift")); 13314 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 13315 et.size - imm); 13316} 13317 13318static void 13319do_neon_movl (void) 13320{ 13321 struct neon_type_el et = neon_check_type (2, NS_QD, 13322 N_EQK | N_DBL, N_SU_32 | N_KEY); 13323 unsigned sizebits = et.size >> 3; 13324 inst.instruction |= sizebits << 19; 13325 neon_two_same (0, et.type == NT_unsigned, -1); 13326} 13327 13328static void 13329do_neon_trn (void) 13330{ 13331 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13332 struct neon_type_el et = neon_check_type (2, rs, 13333 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13334 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 13335 neon_two_same (neon_quad (rs), 1, et.size); 13336} 13337 13338static void 13339do_neon_zip_uzp (void) 13340{ 13341 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13342 struct neon_type_el et = neon_check_type (2, rs, 13343 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13344 if (rs == NS_DD && et.size == 32) 13345 { 13346 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ 13347 inst.instruction = N_MNEM_vtrn; 13348 do_neon_trn (); 13349 return; 13350 } 13351 neon_two_same (neon_quad (rs), 1, et.size); 13352} 13353 13354static void 13355do_neon_sat_abs_neg (void) 13356{ 13357 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13358 struct neon_type_el et = neon_check_type (2, rs, 13359 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13360 neon_two_same (neon_quad (rs), 1, et.size); 13361} 13362 13363static void 13364do_neon_pair_long (void) 13365{ 13366 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13367 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); 13368 /* Unsigned is encoded in OP field (bit 7) for these instruction. */ 13369 inst.instruction |= (et.type == NT_unsigned) << 7; 13370 neon_two_same (neon_quad (rs), 1, et.size); 13371} 13372 13373static void 13374do_neon_recip_est (void) 13375{ 13376 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13377 struct neon_type_el et = neon_check_type (2, rs, 13378 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); 13379 inst.instruction |= (et.type == NT_float) << 8; 13380 neon_two_same (neon_quad (rs), 1, et.size); 13381} 13382 13383static void 13384do_neon_cls (void) 13385{ 13386 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13387 struct neon_type_el et = neon_check_type (2, rs, 13388 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13389 neon_two_same (neon_quad (rs), 1, et.size); 13390} 13391 13392static void 13393do_neon_clz (void) 13394{ 13395 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13396 struct neon_type_el et = neon_check_type (2, rs, 13397 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); 13398 neon_two_same (neon_quad (rs), 1, et.size); 13399} 13400 13401static void 13402do_neon_cnt (void) 13403{ 13404 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13405 struct neon_type_el et = neon_check_type (2, rs, 13406 N_EQK | N_INT, N_8 | N_KEY); 13407 neon_two_same (neon_quad (rs), 1, et.size); 13408} 13409 13410static void 13411do_neon_swp (void) 13412{ 13413 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13414 neon_two_same (neon_quad (rs), 1, -1); 13415} 13416 13417static void 13418do_neon_tbl_tbx (void) 13419{ 13420 unsigned listlenbits; 13421 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); 13422 13423 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) 13424 { 13425 first_error (_("bad list length for table lookup")); 13426 return; 13427 } 13428 13429 listlenbits = inst.operands[1].imm - 1; 13430 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13431 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13432 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13433 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13434 inst.instruction |= LOW4 (inst.operands[2].reg); 13435 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13436 inst.instruction |= listlenbits << 8; 13437 13438 inst.instruction = neon_dp_fixup (inst.instruction); 13439} 13440 13441static void 13442do_neon_ldm_stm (void) 13443{ 13444 /* P, U and L bits are part of bitmask. */ 13445 int is_dbmode = (inst.instruction & (1 << 24)) != 0; 13446 unsigned offsetbits = inst.operands[1].imm * 2; 13447 13448 if (inst.operands[1].issingle) 13449 { 13450 do_vfp_nsyn_ldm_stm (is_dbmode); 13451 return; 13452 } 13453 13454 constraint (is_dbmode && !inst.operands[0].writeback, 13455 _("writeback (!) must be used for VLDMDB and VSTMDB")); 13456 13457 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, 13458 _("register list must contain at least 1 and at most 16 " 13459 "registers")); 13460 13461 inst.instruction |= inst.operands[0].reg << 16; 13462 inst.instruction |= inst.operands[0].writeback << 21; 13463 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13464 inst.instruction |= HI1 (inst.operands[1].reg) << 22; 13465 13466 inst.instruction |= offsetbits; 13467 13468 do_vfp_cond_or_thumb (); 13469} 13470 13471static void 13472do_neon_ldr_str (void) 13473{ 13474 int is_ldr = (inst.instruction & (1 << 20)) != 0; 13475 13476 if (inst.operands[0].issingle) 13477 { 13478 if (is_ldr) 13479 do_vfp_nsyn_opcode ("flds"); 13480 else 13481 do_vfp_nsyn_opcode ("fsts"); 13482 } 13483 else 13484 { 13485 if (is_ldr) 13486 do_vfp_nsyn_opcode ("fldd"); 13487 else 13488 do_vfp_nsyn_opcode ("fstd"); 13489 } 13490} 13491 13492/* "interleave" version also handles non-interleaving register VLD1/VST1 13493 instructions. */ 13494 13495static void 13496do_neon_ld_st_interleave (void) 13497{ 13498 struct neon_type_el et = neon_check_type (1, NS_NULL, 13499 N_8 | N_16 | N_32 | N_64); 13500 unsigned alignbits = 0; 13501 unsigned idx; 13502 /* The bits in this table go: 13503 0: register stride of one (0) or two (1) 13504 1,2: register list length, minus one (1, 2, 3, 4). 13505 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). 13506 We use -1 for invalid entries. */ 13507 const int typetable[] = 13508 { 13509 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ 13510 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ 13511 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ 13512 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ 13513 }; 13514 int typebits; 13515 13516 if (et.type == NT_invtype) 13517 return; 13518 13519 if (inst.operands[1].immisalign) 13520 switch (inst.operands[1].imm >> 8) 13521 { 13522 case 64: alignbits = 1; break; 13523 case 128: 13524 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13525 goto bad_alignment; 13526 alignbits = 2; 13527 break; 13528 case 256: 13529 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13530 goto bad_alignment; 13531 alignbits = 3; 13532 break; 13533 default: 13534 bad_alignment: 13535 first_error (_("bad alignment")); 13536 return; 13537 } 13538 13539 inst.instruction |= alignbits << 4; 13540 inst.instruction |= neon_logbits (et.size) << 6; 13541 13542 /* Bits [4:6] of the immediate in a list specifier encode register stride 13543 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of 13544 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look 13545 up the right value for "type" in a table based on this value and the given 13546 list style, then stick it back. */ 13547 idx = ((inst.operands[0].imm >> 4) & 7) 13548 | (((inst.instruction >> 8) & 3) << 3); 13549 13550 typebits = typetable[idx]; 13551 13552 constraint (typebits == -1, _("bad list type for instruction")); 13553 13554 inst.instruction &= ~0xf00; 13555 inst.instruction |= typebits << 8; 13556} 13557 13558/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. 13559 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 13560 otherwise. The variable arguments are a list of pairs of legal (size, align) 13561 values, terminated with -1. */ 13562 13563static int 13564neon_alignment_bit (int size, int align, int *do_align, ...) 13565{ 13566 va_list ap; 13567 int result = FAIL, thissize, thisalign; 13568 13569 if (!inst.operands[1].immisalign) 13570 { 13571 *do_align = 0; 13572 return SUCCESS; 13573 } 13574 13575 va_start (ap, do_align); 13576 13577 do 13578 { 13579 thissize = va_arg (ap, int); 13580 if (thissize == -1) 13581 break; 13582 thisalign = va_arg (ap, int); 13583 13584 if (size == thissize && align == thisalign) 13585 result = SUCCESS; 13586 } 13587 while (result != SUCCESS); 13588 13589 va_end (ap); 13590 13591 if (result == SUCCESS) 13592 *do_align = 1; 13593 else 13594 first_error (_("unsupported alignment for instruction")); 13595 13596 return result; 13597} 13598 13599static void 13600do_neon_ld_st_lane (void) 13601{ 13602 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13603 int align_good, do_align = 0; 13604 int logsize = neon_logbits (et.size); 13605 int align = inst.operands[1].imm >> 8; 13606 int n = (inst.instruction >> 8) & 3; 13607 int max_el = 64 / et.size; 13608 13609 if (et.type == NT_invtype) 13610 return; 13611 13612 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, 13613 _("bad list length")); 13614 constraint (NEON_LANE (inst.operands[0].imm) >= max_el, 13615 _("scalar index out of range")); 13616 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 13617 && et.size == 8, 13618 _("stride of 2 unavailable when element size is 8")); 13619 13620 switch (n) 13621 { 13622 case 0: /* VLD1 / VST1. */ 13623 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, 13624 32, 32, -1); 13625 if (align_good == FAIL) 13626 return; 13627 if (do_align) 13628 { 13629 unsigned alignbits = 0; 13630 switch (et.size) 13631 { 13632 case 16: alignbits = 0x1; break; 13633 case 32: alignbits = 0x3; break; 13634 default: ; 13635 } 13636 inst.instruction |= alignbits << 4; 13637 } 13638 break; 13639 13640 case 1: /* VLD2 / VST2. */ 13641 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, 13642 32, 64, -1); 13643 if (align_good == FAIL) 13644 return; 13645 if (do_align) 13646 inst.instruction |= 1 << 4; 13647 break; 13648 13649 case 2: /* VLD3 / VST3. */ 13650 constraint (inst.operands[1].immisalign, 13651 _("can't use alignment with this instruction")); 13652 break; 13653 13654 case 3: /* VLD4 / VST4. */ 13655 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13656 16, 64, 32, 64, 32, 128, -1); 13657 if (align_good == FAIL) 13658 return; 13659 if (do_align) 13660 { 13661 unsigned alignbits = 0; 13662 switch (et.size) 13663 { 13664 case 8: alignbits = 0x1; break; 13665 case 16: alignbits = 0x1; break; 13666 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; 13667 default: ; 13668 } 13669 inst.instruction |= alignbits << 4; 13670 } 13671 break; 13672 13673 default: ; 13674 } 13675 13676 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ 13677 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13678 inst.instruction |= 1 << (4 + logsize); 13679 13680 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); 13681 inst.instruction |= logsize << 10; 13682} 13683 13684/* Encode single n-element structure to all lanes VLD<n> instructions. */ 13685 13686static void 13687do_neon_ld_dup (void) 13688{ 13689 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13690 int align_good, do_align = 0; 13691 13692 if (et.type == NT_invtype) 13693 return; 13694 13695 switch ((inst.instruction >> 8) & 3) 13696 { 13697 case 0: /* VLD1. */ 13698 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); 13699 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13700 &do_align, 16, 16, 32, 32, -1); 13701 if (align_good == FAIL) 13702 return; 13703 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) 13704 { 13705 case 1: break; 13706 case 2: inst.instruction |= 1 << 5; break; 13707 default: first_error (_("bad list length")); return; 13708 } 13709 inst.instruction |= neon_logbits (et.size) << 6; 13710 break; 13711 13712 case 1: /* VLD2. */ 13713 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13714 &do_align, 8, 16, 16, 32, 32, 64, -1); 13715 if (align_good == FAIL) 13716 return; 13717 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, 13718 _("bad list length")); 13719 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13720 inst.instruction |= 1 << 5; 13721 inst.instruction |= neon_logbits (et.size) << 6; 13722 break; 13723 13724 case 2: /* VLD3. */ 13725 constraint (inst.operands[1].immisalign, 13726 _("can't use alignment with this instruction")); 13727 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, 13728 _("bad list length")); 13729 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13730 inst.instruction |= 1 << 5; 13731 inst.instruction |= neon_logbits (et.size) << 6; 13732 break; 13733 13734 case 3: /* VLD4. */ 13735 { 13736 int align = inst.operands[1].imm >> 8; 13737 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13738 16, 64, 32, 64, 32, 128, -1); 13739 if (align_good == FAIL) 13740 return; 13741 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, 13742 _("bad list length")); 13743 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13744 inst.instruction |= 1 << 5; 13745 if (et.size == 32 && align == 128) 13746 inst.instruction |= 0x3 << 6; 13747 else 13748 inst.instruction |= neon_logbits (et.size) << 6; 13749 } 13750 break; 13751 13752 default: ; 13753 } 13754 13755 inst.instruction |= do_align << 4; 13756} 13757 13758/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those 13759 apart from bits [11:4]. */ 13760 13761static void 13762do_neon_ldx_stx (void) 13763{ 13764 switch (NEON_LANE (inst.operands[0].imm)) 13765 { 13766 case NEON_INTERLEAVE_LANES: 13767 inst.instruction = NEON_ENC_INTERLV (inst.instruction); 13768 do_neon_ld_st_interleave (); 13769 break; 13770 13771 case NEON_ALL_LANES: 13772 inst.instruction = NEON_ENC_DUP (inst.instruction); 13773 do_neon_ld_dup (); 13774 break; 13775 13776 default: 13777 inst.instruction = NEON_ENC_LANE (inst.instruction); 13778 do_neon_ld_st_lane (); 13779 } 13780 13781 /* L bit comes from bit mask. */ 13782 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13783 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13784 inst.instruction |= inst.operands[1].reg << 16; 13785 13786 if (inst.operands[1].postind) 13787 { 13788 int postreg = inst.operands[1].imm & 0xf; 13789 constraint (!inst.operands[1].immisreg, 13790 _("post-index must be a register")); 13791 constraint (postreg == 0xd || postreg == 0xf, 13792 _("bad register for post-index")); 13793 inst.instruction |= postreg; 13794 } 13795 else if (inst.operands[1].writeback) 13796 { 13797 inst.instruction |= 0xd; 13798 } 13799 else 13800 inst.instruction |= 0xf; 13801 13802 if (thumb_mode) 13803 inst.instruction |= 0xf9000000; 13804 else 13805 inst.instruction |= 0xf4000000; 13806} 13807 13808 13809/* Overall per-instruction processing. */ 13810 13811/* We need to be able to fix up arbitrary expressions in some statements. 13812 This is so that we can handle symbols that are an arbitrary distance from 13813 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), 13814 which returns part of an address in a form which will be valid for 13815 a data instruction. We do this by pushing the expression into a symbol 13816 in the expr_section, and creating a fix for that. */ 13817 13818static void 13819fix_new_arm (fragS * frag, 13820 int where, 13821 short int size, 13822 expressionS * exp, 13823 int pc_rel, 13824 int reloc) 13825{ 13826 fixS * new_fix; 13827 13828 switch (exp->X_op) 13829 { 13830 case O_constant: 13831 case O_symbol: 13832 case O_add: 13833 case O_subtract: 13834 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); 13835 break; 13836 13837 default: 13838 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, 13839 pc_rel, reloc); 13840 break; 13841 } 13842 13843 /* Mark whether the fix is to a THUMB instruction, or an ARM 13844 instruction. */ 13845 new_fix->tc_fix_data = thumb_mode; 13846} 13847 13848/* Create a frg for an instruction requiring relaxation. */ 13849static void 13850output_relax_insn (void) 13851{ 13852 char * to; 13853 symbolS *sym; 13854 int offset; 13855 13856 /* The size of the instruction is unknown, so tie the debug info to the 13857 start of the instruction. */ 13858 dwarf2_emit_insn (0); 13859 13860 switch (inst.reloc.exp.X_op) 13861 { 13862 case O_symbol: 13863 sym = inst.reloc.exp.X_add_symbol; 13864 offset = inst.reloc.exp.X_add_number; 13865 break; 13866 case O_constant: 13867 sym = NULL; 13868 offset = inst.reloc.exp.X_add_number; 13869 break; 13870 default: 13871 sym = make_expr_symbol (&inst.reloc.exp); 13872 offset = 0; 13873 break; 13874 } 13875 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, 13876 inst.relax, sym, offset, NULL/*offset, opcode*/); 13877 md_number_to_chars (to, inst.instruction, THUMB_SIZE); 13878} 13879 13880/* Write a 32-bit thumb instruction to buf. */ 13881static void 13882put_thumb32_insn (char * buf, unsigned long insn) 13883{ 13884 md_number_to_chars (buf, insn >> 16, THUMB_SIZE); 13885 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); 13886} 13887 13888static void 13889output_inst (const char * str) 13890{ 13891 char * to = NULL; 13892 13893 if (inst.error) 13894 { 13895 as_bad ("%s -- `%s'", inst.error, str); 13896 return; 13897 } 13898 if (inst.relax) { 13899 output_relax_insn(); 13900 return; 13901 } 13902 if (inst.size == 0) 13903 return; 13904 13905 to = frag_more (inst.size); 13906 13907 if (thumb_mode && (inst.size > THUMB_SIZE)) 13908 { 13909 assert (inst.size == (2 * THUMB_SIZE)); 13910 put_thumb32_insn (to, inst.instruction); 13911 } 13912 else if (inst.size > INSN_SIZE) 13913 { 13914 assert (inst.size == (2 * INSN_SIZE)); 13915 md_number_to_chars (to, inst.instruction, INSN_SIZE); 13916 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); 13917 } 13918 else 13919 md_number_to_chars (to, inst.instruction, inst.size); 13920 13921 if (inst.reloc.type != BFD_RELOC_UNUSED) 13922 fix_new_arm (frag_now, to - frag_now->fr_literal, 13923 inst.size, & inst.reloc.exp, inst.reloc.pc_rel, 13924 inst.reloc.type); 13925 13926 dwarf2_emit_insn (inst.size); 13927} 13928 13929/* Tag values used in struct asm_opcode's tag field. */ 13930enum opcode_tag 13931{ 13932 OT_unconditional, /* Instruction cannot be conditionalized. 13933 The ARM condition field is still 0xE. */ 13934 OT_unconditionalF, /* Instruction cannot be conditionalized 13935 and carries 0xF in its ARM condition field. */ 13936 OT_csuffix, /* Instruction takes a conditional suffix. */ 13937 OT_csuffixF, /* Some forms of the instruction take a conditional 13938 suffix, others place 0xF where the condition field 13939 would be. */ 13940 OT_cinfix3, /* Instruction takes a conditional infix, 13941 beginning at character index 3. (In 13942 unified mode, it becomes a suffix.) */ 13943 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for 13944 tsts, cmps, cmns, and teqs. */ 13945 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at 13946 character index 3, even in unified mode. Used for 13947 legacy instructions where suffix and infix forms 13948 may be ambiguous. */ 13949 OT_csuf_or_in3, /* Instruction takes either a conditional 13950 suffix or an infix at character index 3. */ 13951 OT_odd_infix_unc, /* This is the unconditional variant of an 13952 instruction that takes a conditional infix 13953 at an unusual position. In unified mode, 13954 this variant will accept a suffix. */ 13955 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 13956 are the conditional variants of instructions that 13957 take conditional infixes in unusual positions. 13958 The infix appears at character index 13959 (tag - OT_odd_infix_0). These are not accepted 13960 in unified mode. */ 13961}; 13962 13963/* Subroutine of md_assemble, responsible for looking up the primary 13964 opcode from the mnemonic the user wrote. STR points to the 13965 beginning of the mnemonic. 13966 13967 This is not simply a hash table lookup, because of conditional 13968 variants. Most instructions have conditional variants, which are 13969 expressed with a _conditional affix_ to the mnemonic. If we were 13970 to encode each conditional variant as a literal string in the opcode 13971 table, it would have approximately 20,000 entries. 13972 13973 Most mnemonics take this affix as a suffix, and in unified syntax, 13974 'most' is upgraded to 'all'. However, in the divided syntax, some 13975 instructions take the affix as an infix, notably the s-variants of 13976 the arithmetic instructions. Of those instructions, all but six 13977 have the infix appear after the third character of the mnemonic. 13978 13979 Accordingly, the algorithm for looking up primary opcodes given 13980 an identifier is: 13981 13982 1. Look up the identifier in the opcode table. 13983 If we find a match, go to step U. 13984 13985 2. Look up the last two characters of the identifier in the 13986 conditions table. If we find a match, look up the first N-2 13987 characters of the identifier in the opcode table. If we 13988 find a match, go to step CE. 13989 13990 3. Look up the fourth and fifth characters of the identifier in 13991 the conditions table. If we find a match, extract those 13992 characters from the identifier, and look up the remaining 13993 characters in the opcode table. If we find a match, go 13994 to step CM. 13995 13996 4. Fail. 13997 13998 U. Examine the tag field of the opcode structure, in case this is 13999 one of the six instructions with its conditional infix in an 14000 unusual place. If it is, the tag tells us where to find the 14001 infix; look it up in the conditions table and set inst.cond 14002 accordingly. Otherwise, this is an unconditional instruction. 14003 Again set inst.cond accordingly. Return the opcode structure. 14004 14005 CE. Examine the tag field to make sure this is an instruction that 14006 should receive a conditional suffix. If it is not, fail. 14007 Otherwise, set inst.cond from the suffix we already looked up, 14008 and return the opcode structure. 14009 14010 CM. Examine the tag field to make sure this is an instruction that 14011 should receive a conditional infix after the third character. 14012 If it is not, fail. Otherwise, undo the edits to the current 14013 line of input and proceed as for case CE. */ 14014 14015static const struct asm_opcode * 14016opcode_lookup (char **str) 14017{ 14018 char *end, *base; 14019 char *affix; 14020 const struct asm_opcode *opcode; 14021 const struct asm_cond *cond; 14022 char save[2]; 14023 bfd_boolean neon_supported; 14024 14025 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1); 14026 14027 /* Scan up to the end of the mnemonic, which must end in white space, 14028 '.' (in unified mode, or for Neon instructions), or end of string. */ 14029 for (base = end = *str; *end != '\0'; end++) 14030 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.')) 14031 break; 14032 14033 if (end == base) 14034 return 0; 14035 14036 /* Handle a possible width suffix and/or Neon type suffix. */ 14037 if (end[0] == '.') 14038 { 14039 int offset = 2; 14040 14041 /* The .w and .n suffixes are only valid if the unified syntax is in 14042 use. */ 14043 if (unified_syntax && end[1] == 'w') 14044 inst.size_req = 4; 14045 else if (unified_syntax && end[1] == 'n') 14046 inst.size_req = 2; 14047 else 14048 offset = 0; 14049 14050 inst.vectype.elems = 0; 14051 14052 *str = end + offset; 14053 14054 if (end[offset] == '.') 14055 { 14056 /* See if we have a Neon type suffix (possible in either unified or 14057 non-unified ARM syntax mode). */ 14058 if (parse_neon_type (&inst.vectype, str) == FAIL) 14059 return 0; 14060 } 14061 else if (end[offset] != '\0' && end[offset] != ' ') 14062 return 0; 14063 } 14064 else 14065 *str = end; 14066 14067 /* Look for unaffixed or special-case affixed mnemonic. */ 14068 opcode = hash_find_n (arm_ops_hsh, base, end - base); 14069 if (opcode) 14070 { 14071 /* step U */ 14072 if (opcode->tag < OT_odd_infix_0) 14073 { 14074 inst.cond = COND_ALWAYS; 14075 return opcode; 14076 } 14077 14078 if (unified_syntax) 14079 as_warn (_("conditional infixes are deprecated in unified syntax")); 14080 affix = base + (opcode->tag - OT_odd_infix_0); 14081 cond = hash_find_n (arm_cond_hsh, affix, 2); 14082 assert (cond); 14083 14084 inst.cond = cond->value; 14085 return opcode; 14086 } 14087 14088 /* Cannot have a conditional suffix on a mnemonic of less than two 14089 characters. */ 14090 if (end - base < 3) 14091 return 0; 14092 14093 /* Look for suffixed mnemonic. */ 14094 affix = end - 2; 14095 cond = hash_find_n (arm_cond_hsh, affix, 2); 14096 opcode = hash_find_n (arm_ops_hsh, base, affix - base); 14097 if (opcode && cond) 14098 { 14099 /* step CE */ 14100 switch (opcode->tag) 14101 { 14102 case OT_cinfix3_legacy: 14103 /* Ignore conditional suffixes matched on infix only mnemonics. */ 14104 break; 14105 14106 case OT_cinfix3: 14107 case OT_cinfix3_deprecated: 14108 case OT_odd_infix_unc: 14109 if (!unified_syntax) 14110 return 0; 14111 /* else fall through */ 14112 14113 case OT_csuffix: 14114 case OT_csuffixF: 14115 case OT_csuf_or_in3: 14116 inst.cond = cond->value; 14117 return opcode; 14118 14119 case OT_unconditional: 14120 case OT_unconditionalF: 14121 if (thumb_mode) 14122 { 14123 inst.cond = cond->value; 14124 } 14125 else 14126 { 14127 /* delayed diagnostic */ 14128 inst.error = BAD_COND; 14129 inst.cond = COND_ALWAYS; 14130 } 14131 return opcode; 14132 14133 default: 14134 return 0; 14135 } 14136 } 14137 14138 /* Cannot have a usual-position infix on a mnemonic of less than 14139 six characters (five would be a suffix). */ 14140 if (end - base < 6) 14141 return 0; 14142 14143 /* Look for infixed mnemonic in the usual position. */ 14144 affix = base + 3; 14145 cond = hash_find_n (arm_cond_hsh, affix, 2); 14146 if (!cond) 14147 return 0; 14148 14149 memcpy (save, affix, 2); 14150 memmove (affix, affix + 2, (end - affix) - 2); 14151 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); 14152 memmove (affix + 2, affix, (end - affix) - 2); 14153 memcpy (affix, save, 2); 14154 14155 if (opcode 14156 && (opcode->tag == OT_cinfix3 14157 || opcode->tag == OT_cinfix3_deprecated 14158 || opcode->tag == OT_csuf_or_in3 14159 || opcode->tag == OT_cinfix3_legacy)) 14160 { 14161 /* step CM */ 14162 if (unified_syntax 14163 && (opcode->tag == OT_cinfix3 14164 || opcode->tag == OT_cinfix3_deprecated)) 14165 as_warn (_("conditional infixes are deprecated in unified syntax")); 14166 14167 inst.cond = cond->value; 14168 return opcode; 14169 } 14170 14171 return 0; 14172} 14173 14174void 14175md_assemble (char *str) 14176{ 14177 char *p = str; 14178 const struct asm_opcode * opcode; 14179 14180 /* Align the previous label if needed. */ 14181 if (last_label_seen != NULL) 14182 { 14183 symbol_set_frag (last_label_seen, frag_now); 14184 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); 14185 S_SET_SEGMENT (last_label_seen, now_seg); 14186 } 14187 14188 memset (&inst, '\0', sizeof (inst)); 14189 inst.reloc.type = BFD_RELOC_UNUSED; 14190 14191 opcode = opcode_lookup (&p); 14192 if (!opcode) 14193 { 14194 /* It wasn't an instruction, but it might be a register alias of 14195 the form alias .req reg, or a Neon .dn/.qn directive. */ 14196 if (!create_register_alias (str, p) 14197 && !create_neon_reg_alias (str, p)) 14198 as_bad (_("bad instruction `%s'"), str); 14199 14200 return; 14201 } 14202 14203 if (opcode->tag == OT_cinfix3_deprecated) 14204 as_warn (_("s suffix on comparison instruction is deprecated")); 14205 14206 /* The value which unconditional instructions should have in place of the 14207 condition field. */ 14208 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; 14209 14210 if (thumb_mode) 14211 { 14212 arm_feature_set variant; 14213 14214 variant = cpu_variant; 14215 /* Only allow coprocessor instructions on Thumb-2 capable devices. */ 14216 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) 14217 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); 14218 /* Check that this instruction is supported for this CPU. */ 14219 if (!opcode->tvariant 14220 || (thumb_mode == 1 14221 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) 14222 { 14223 as_bad (_("selected processor does not support `%s'"), str); 14224 return; 14225 } 14226 if (inst.cond != COND_ALWAYS && !unified_syntax 14227 && opcode->tencode != do_t_branch) 14228 { 14229 as_bad (_("Thumb does not support conditional execution")); 14230 return; 14231 } 14232 14233 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req) 14234 { 14235 /* Implicit require narrow instructions on Thumb-1. This avoids 14236 relaxation accidentally introducing Thumb-2 instructions. */ 14237 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23) 14238 inst.size_req = 2; 14239 } 14240 14241 /* Check conditional suffixes. */ 14242 if (current_it_mask) 14243 { 14244 int cond; 14245 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; 14246 current_it_mask <<= 1; 14247 current_it_mask &= 0x1f; 14248 /* The BKPT instruction is unconditional even in an IT block. */ 14249 if (!inst.error 14250 && cond != inst.cond && opcode->tencode != do_t_bkpt) 14251 { 14252 as_bad (_("incorrect condition in IT block")); 14253 return; 14254 } 14255 } 14256 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) 14257 { 14258 as_bad (_("thumb conditional instrunction not in IT block")); 14259 return; 14260 } 14261 14262 mapping_state (MAP_THUMB); 14263 inst.instruction = opcode->tvalue; 14264 14265 if (!parse_operands (p, opcode->operands)) 14266 opcode->tencode (); 14267 14268 /* Clear current_it_mask at the end of an IT block. */ 14269 if (current_it_mask == 0x10) 14270 current_it_mask = 0; 14271 14272 if (!(inst.error || inst.relax)) 14273 { 14274 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); 14275 inst.size = (inst.instruction > 0xffff ? 4 : 2); 14276 if (inst.size_req && inst.size_req != inst.size) 14277 { 14278 as_bad (_("cannot honor width suffix -- `%s'"), str); 14279 return; 14280 } 14281 } 14282 14283 /* Something has gone badly wrong if we try to relax a fixed size 14284 instruction. */ 14285 assert (inst.size_req == 0 || !inst.relax); 14286 14287 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14288 *opcode->tvariant); 14289 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly 14290 set those bits when Thumb-2 32-bit instructions are seen. ie. 14291 anything other than bl/blx. 14292 This is overly pessimistic for relaxable instructions. */ 14293 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) 14294 || inst.relax) 14295 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14296 arm_ext_v6t2); 14297 } 14298 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 14299 { 14300 /* Check that this instruction is supported for this CPU. */ 14301 if (!opcode->avariant || 14302 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) 14303 { 14304 as_bad (_("selected processor does not support `%s'"), str); 14305 return; 14306 } 14307 if (inst.size_req) 14308 { 14309 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); 14310 return; 14311 } 14312 14313 mapping_state (MAP_ARM); 14314 inst.instruction = opcode->avalue; 14315 if (opcode->tag == OT_unconditionalF) 14316 inst.instruction |= 0xF << 28; 14317 else 14318 inst.instruction |= inst.cond << 28; 14319 inst.size = INSN_SIZE; 14320 if (!parse_operands (p, opcode->operands)) 14321 opcode->aencode (); 14322 /* Arm mode bx is marked as both v4T and v5 because it's still required 14323 on a hypothetical non-thumb v5 core. */ 14324 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) 14325 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) 14326 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); 14327 else 14328 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 14329 *opcode->avariant); 14330 } 14331 else 14332 { 14333 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " 14334 "-- `%s'"), str); 14335 return; 14336 } 14337 output_inst (str); 14338} 14339 14340/* Various frobbings of labels and their addresses. */ 14341 14342void 14343arm_start_line_hook (void) 14344{ 14345 last_label_seen = NULL; 14346} 14347 14348void 14349arm_frob_label (symbolS * sym) 14350{ 14351 last_label_seen = sym; 14352 14353 ARM_SET_THUMB (sym, thumb_mode); 14354 14355#if defined OBJ_COFF || defined OBJ_ELF 14356 ARM_SET_INTERWORK (sym, support_interwork); 14357#endif 14358 14359 /* Note - do not allow local symbols (.Lxxx) to be labeled 14360 as Thumb functions. This is because these labels, whilst 14361 they exist inside Thumb code, are not the entry points for 14362 possible ARM->Thumb calls. Also, these labels can be used 14363 as part of a computed goto or switch statement. eg gcc 14364 can generate code that looks like this: 14365 14366 ldr r2, [pc, .Laaa] 14367 lsl r3, r3, #2 14368 ldr r2, [r3, r2] 14369 mov pc, r2 14370 14371 .Lbbb: .word .Lxxx 14372 .Lccc: .word .Lyyy 14373 ..etc... 14374 .Laaa: .word Lbbb 14375 14376 The first instruction loads the address of the jump table. 14377 The second instruction converts a table index into a byte offset. 14378 The third instruction gets the jump address out of the table. 14379 The fourth instruction performs the jump. 14380 14381 If the address stored at .Laaa is that of a symbol which has the 14382 Thumb_Func bit set, then the linker will arrange for this address 14383 to have the bottom bit set, which in turn would mean that the 14384 address computation performed by the third instruction would end 14385 up with the bottom bit set. Since the ARM is capable of unaligned 14386 word loads, the instruction would then load the incorrect address 14387 out of the jump table, and chaos would ensue. */ 14388 if (label_is_thumb_function_name 14389 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') 14390 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) 14391 { 14392 /* When the address of a Thumb function is taken the bottom 14393 bit of that address should be set. This will allow 14394 interworking between Arm and Thumb functions to work 14395 correctly. */ 14396 14397 THUMB_SET_FUNC (sym, 1); 14398 14399 label_is_thumb_function_name = FALSE; 14400 } 14401 14402 dwarf2_emit_label (sym); 14403} 14404 14405int 14406arm_data_in_code (void) 14407{ 14408 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) 14409 { 14410 *input_line_pointer = '/'; 14411 input_line_pointer += 5; 14412 *input_line_pointer = 0; 14413 return 1; 14414 } 14415 14416 return 0; 14417} 14418 14419char * 14420arm_canonicalize_symbol_name (char * name) 14421{ 14422 int len; 14423 14424 if (thumb_mode && (len = strlen (name)) > 5 14425 && streq (name + len - 5, "/data")) 14426 *(name + len - 5) = 0; 14427 14428 return name; 14429} 14430 14431/* Table of all register names defined by default. The user can 14432 define additional names with .req. Note that all register names 14433 should appear in both upper and lowercase variants. Some registers 14434 also have mixed-case names. */ 14435 14436#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } 14437#define REGNUM(p,n,t) REGDEF(p##n, n, t) 14438#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) 14439#define REGSET(p,t) \ 14440 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ 14441 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ 14442 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ 14443 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) 14444#define REGSETH(p,t) \ 14445 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ 14446 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ 14447 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ 14448 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) 14449#define REGSET2(p,t) \ 14450 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ 14451 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ 14452 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ 14453 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) 14454 14455static const struct reg_entry reg_names[] = 14456{ 14457 /* ARM integer registers. */ 14458 REGSET(r, RN), REGSET(R, RN), 14459 14460 /* ATPCS synonyms. */ 14461 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), 14462 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), 14463 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), 14464 14465 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), 14466 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), 14467 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), 14468 14469 /* Well-known aliases. */ 14470 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), 14471 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), 14472 14473 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), 14474 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), 14475 14476 /* Coprocessor numbers. */ 14477 REGSET(p, CP), REGSET(P, CP), 14478 14479 /* Coprocessor register numbers. The "cr" variants are for backward 14480 compatibility. */ 14481 REGSET(c, CN), REGSET(C, CN), 14482 REGSET(cr, CN), REGSET(CR, CN), 14483 14484 /* FPA registers. */ 14485 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), 14486 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), 14487 14488 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), 14489 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), 14490 14491 /* VFP SP registers. */ 14492 REGSET(s,VFS), REGSET(S,VFS), 14493 REGSETH(s,VFS), REGSETH(S,VFS), 14494 14495 /* VFP DP Registers. */ 14496 REGSET(d,VFD), REGSET(D,VFD), 14497 /* Extra Neon DP registers. */ 14498 REGSETH(d,VFD), REGSETH(D,VFD), 14499 14500 /* Neon QP registers. */ 14501 REGSET2(q,NQ), REGSET2(Q,NQ), 14502 14503 /* VFP control registers. */ 14504 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), 14505 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), 14506 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), 14507 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), 14508 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), 14509 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), 14510 14511 /* Maverick DSP coprocessor registers. */ 14512 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), 14513 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), 14514 14515 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), 14516 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), 14517 REGDEF(dspsc,0,DSPSC), 14518 14519 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), 14520 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), 14521 REGDEF(DSPSC,0,DSPSC), 14522 14523 /* iWMMXt data registers - p0, c0-15. */ 14524 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), 14525 14526 /* iWMMXt control registers - p1, c0-3. */ 14527 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), 14528 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), 14529 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), 14530 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), 14531 14532 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ 14533 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), 14534 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), 14535 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), 14536 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), 14537 14538 /* XScale accumulator registers. */ 14539 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), 14540}; 14541#undef REGDEF 14542#undef REGNUM 14543#undef REGSET 14544 14545/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled 14546 within psr_required_here. */ 14547static const struct asm_psr psrs[] = 14548{ 14549 /* Backward compatibility notation. Note that "all" is no longer 14550 truly all possible PSR bits. */ 14551 {"all", PSR_c | PSR_f}, 14552 {"flg", PSR_f}, 14553 {"ctl", PSR_c}, 14554 14555 /* Individual flags. */ 14556 {"f", PSR_f}, 14557 {"c", PSR_c}, 14558 {"x", PSR_x}, 14559 {"s", PSR_s}, 14560 /* Combinations of flags. */ 14561 {"fs", PSR_f | PSR_s}, 14562 {"fx", PSR_f | PSR_x}, 14563 {"fc", PSR_f | PSR_c}, 14564 {"sf", PSR_s | PSR_f}, 14565 {"sx", PSR_s | PSR_x}, 14566 {"sc", PSR_s | PSR_c}, 14567 {"xf", PSR_x | PSR_f}, 14568 {"xs", PSR_x | PSR_s}, 14569 {"xc", PSR_x | PSR_c}, 14570 {"cf", PSR_c | PSR_f}, 14571 {"cs", PSR_c | PSR_s}, 14572 {"cx", PSR_c | PSR_x}, 14573 {"fsx", PSR_f | PSR_s | PSR_x}, 14574 {"fsc", PSR_f | PSR_s | PSR_c}, 14575 {"fxs", PSR_f | PSR_x | PSR_s}, 14576 {"fxc", PSR_f | PSR_x | PSR_c}, 14577 {"fcs", PSR_f | PSR_c | PSR_s}, 14578 {"fcx", PSR_f | PSR_c | PSR_x}, 14579 {"sfx", PSR_s | PSR_f | PSR_x}, 14580 {"sfc", PSR_s | PSR_f | PSR_c}, 14581 {"sxf", PSR_s | PSR_x | PSR_f}, 14582 {"sxc", PSR_s | PSR_x | PSR_c}, 14583 {"scf", PSR_s | PSR_c | PSR_f}, 14584 {"scx", PSR_s | PSR_c | PSR_x}, 14585 {"xfs", PSR_x | PSR_f | PSR_s}, 14586 {"xfc", PSR_x | PSR_f | PSR_c}, 14587 {"xsf", PSR_x | PSR_s | PSR_f}, 14588 {"xsc", PSR_x | PSR_s | PSR_c}, 14589 {"xcf", PSR_x | PSR_c | PSR_f}, 14590 {"xcs", PSR_x | PSR_c | PSR_s}, 14591 {"cfs", PSR_c | PSR_f | PSR_s}, 14592 {"cfx", PSR_c | PSR_f | PSR_x}, 14593 {"csf", PSR_c | PSR_s | PSR_f}, 14594 {"csx", PSR_c | PSR_s | PSR_x}, 14595 {"cxf", PSR_c | PSR_x | PSR_f}, 14596 {"cxs", PSR_c | PSR_x | PSR_s}, 14597 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, 14598 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, 14599 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, 14600 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, 14601 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, 14602 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, 14603 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, 14604 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, 14605 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, 14606 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, 14607 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, 14608 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, 14609 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, 14610 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, 14611 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, 14612 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, 14613 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, 14614 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, 14615 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, 14616 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, 14617 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, 14618 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, 14619 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, 14620 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, 14621}; 14622 14623/* Table of V7M psr names. */ 14624static const struct asm_psr v7m_psrs[] = 14625{ 14626 {"apsr", 0 }, {"APSR", 0 }, 14627 {"iapsr", 1 }, {"IAPSR", 1 }, 14628 {"eapsr", 2 }, {"EAPSR", 2 }, 14629 {"psr", 3 }, {"PSR", 3 }, 14630 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, 14631 {"ipsr", 5 }, {"IPSR", 5 }, 14632 {"epsr", 6 }, {"EPSR", 6 }, 14633 {"iepsr", 7 }, {"IEPSR", 7 }, 14634 {"msp", 8 }, {"MSP", 8 }, 14635 {"psp", 9 }, {"PSP", 9 }, 14636 {"primask", 16}, {"PRIMASK", 16}, 14637 {"basepri", 17}, {"BASEPRI", 17}, 14638 {"basepri_max", 18}, {"BASEPRI_MAX", 18}, 14639 {"faultmask", 19}, {"FAULTMASK", 19}, 14640 {"control", 20}, {"CONTROL", 20} 14641}; 14642 14643/* Table of all shift-in-operand names. */ 14644static const struct asm_shift_name shift_names [] = 14645{ 14646 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, 14647 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, 14648 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, 14649 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, 14650 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, 14651 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } 14652}; 14653 14654/* Table of all explicit relocation names. */ 14655#ifdef OBJ_ELF 14656static struct reloc_entry reloc_names[] = 14657{ 14658 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, 14659 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, 14660 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, 14661 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, 14662 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, 14663 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, 14664 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, 14665 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, 14666 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, 14667 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, 14668 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} 14669}; 14670#endif 14671 14672/* Table of all conditional affixes. 0xF is not defined as a condition code. */ 14673static const struct asm_cond conds[] = 14674{ 14675 {"eq", 0x0}, 14676 {"ne", 0x1}, 14677 {"cs", 0x2}, {"hs", 0x2}, 14678 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, 14679 {"mi", 0x4}, 14680 {"pl", 0x5}, 14681 {"vs", 0x6}, 14682 {"vc", 0x7}, 14683 {"hi", 0x8}, 14684 {"ls", 0x9}, 14685 {"ge", 0xa}, 14686 {"lt", 0xb}, 14687 {"gt", 0xc}, 14688 {"le", 0xd}, 14689 {"al", 0xe} 14690}; 14691 14692static struct asm_barrier_opt barrier_opt_names[] = 14693{ 14694 { "sy", 0xf }, 14695 { "un", 0x7 }, 14696 { "st", 0xe }, 14697 { "unst", 0x6 } 14698}; 14699 14700/* Table of ARM-format instructions. */ 14701 14702/* Macros for gluing together operand strings. N.B. In all cases 14703 other than OPS0, the trailing OP_stop comes from default 14704 zero-initialization of the unspecified elements of the array. */ 14705#define OPS0() { OP_stop, } 14706#define OPS1(a) { OP_##a, } 14707#define OPS2(a,b) { OP_##a,OP_##b, } 14708#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } 14709#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } 14710#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } 14711#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } 14712 14713/* These macros abstract out the exact format of the mnemonic table and 14714 save some repeated characters. */ 14715 14716/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ 14717#define TxCE(mnem, op, top, nops, ops, ae, te) \ 14718 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ 14719 THUMB_VARIANT, do_##ae, do_##te } 14720 14721/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for 14722 a T_MNEM_xyz enumerator. */ 14723#define TCE(mnem, aop, top, nops, ops, ae, te) \ 14724 TxCE(mnem, aop, 0x##top, nops, ops, ae, te) 14725#define tCE(mnem, aop, top, nops, ops, ae, te) \ 14726 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14727 14728/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional 14729 infix after the third character. */ 14730#define TxC3(mnem, op, top, nops, ops, ae, te) \ 14731 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ 14732 THUMB_VARIANT, do_##ae, do_##te } 14733#define TxC3w(mnem, op, top, nops, ops, ae, te) \ 14734 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ 14735 THUMB_VARIANT, do_##ae, do_##te } 14736#define TC3(mnem, aop, top, nops, ops, ae, te) \ 14737 TxC3(mnem, aop, 0x##top, nops, ops, ae, te) 14738#define TC3w(mnem, aop, top, nops, ops, ae, te) \ 14739 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te) 14740#define tC3(mnem, aop, top, nops, ops, ae, te) \ 14741 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14742#define tC3w(mnem, aop, top, nops, ops, ae, te) \ 14743 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14744 14745/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to 14746 appear in the condition table. */ 14747#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ 14748 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14749 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } 14750 14751#define TxCM(m1, m2, op, top, nops, ops, ae, te) \ 14752 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ 14753 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ 14754 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ 14755 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ 14756 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ 14757 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ 14758 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ 14759 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ 14760 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ 14761 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ 14762 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ 14763 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ 14764 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ 14765 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ 14766 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ 14767 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ 14768 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ 14769 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ 14770 TxCM_(m1, al, m2, op, top, nops, ops, ae, te) 14771 14772#define TCM(m1,m2, aop, top, nops, ops, ae, te) \ 14773 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) 14774#define tCM(m1,m2, aop, top, nops, ops, ae, te) \ 14775 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) 14776 14777/* Mnemonic that cannot be conditionalized. The ARM condition-code 14778 field is still 0xE. Many of the Thumb variants can be executed 14779 conditionally, so this is checked separately. */ 14780#define TUE(mnem, op, top, nops, ops, ae, te) \ 14781 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ 14782 THUMB_VARIANT, do_##ae, do_##te } 14783 14784/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM 14785 condition code field. */ 14786#define TUF(mnem, op, top, nops, ops, ae, te) \ 14787 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ 14788 THUMB_VARIANT, do_##ae, do_##te } 14789 14790/* ARM-only variants of all the above. */ 14791#define CE(mnem, op, nops, ops, ae) \ 14792 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14793 14794#define C3(mnem, op, nops, ops, ae) \ 14795 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14796 14797/* Legacy mnemonics that always have conditional infix after the third 14798 character. */ 14799#define CL(mnem, op, nops, ops, ae) \ 14800 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14801 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14802 14803/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ 14804#define cCE(mnem, op, nops, ops, ae) \ 14805 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14806 14807/* Legacy coprocessor instructions where conditional infix and conditional 14808 suffix are ambiguous. For consistency this includes all FPA instructions, 14809 not just the potentially ambiguous ones. */ 14810#define cCL(mnem, op, nops, ops, ae) \ 14811 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14812 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14813 14814/* Coprocessor, takes either a suffix or a position-3 infix 14815 (for an FPA corner case). */ 14816#define C3E(mnem, op, nops, ops, ae) \ 14817 { #mnem, OPS##nops ops, OT_csuf_or_in3, \ 14818 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14819 14820#define xCM_(m1, m2, m3, op, nops, ops, ae) \ 14821 { #m1 #m2 #m3, OPS##nops ops, \ 14822 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14823 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14824 14825#define CM(m1, m2, op, nops, ops, ae) \ 14826 xCM_(m1, , m2, op, nops, ops, ae), \ 14827 xCM_(m1, eq, m2, op, nops, ops, ae), \ 14828 xCM_(m1, ne, m2, op, nops, ops, ae), \ 14829 xCM_(m1, cs, m2, op, nops, ops, ae), \ 14830 xCM_(m1, hs, m2, op, nops, ops, ae), \ 14831 xCM_(m1, cc, m2, op, nops, ops, ae), \ 14832 xCM_(m1, ul, m2, op, nops, ops, ae), \ 14833 xCM_(m1, lo, m2, op, nops, ops, ae), \ 14834 xCM_(m1, mi, m2, op, nops, ops, ae), \ 14835 xCM_(m1, pl, m2, op, nops, ops, ae), \ 14836 xCM_(m1, vs, m2, op, nops, ops, ae), \ 14837 xCM_(m1, vc, m2, op, nops, ops, ae), \ 14838 xCM_(m1, hi, m2, op, nops, ops, ae), \ 14839 xCM_(m1, ls, m2, op, nops, ops, ae), \ 14840 xCM_(m1, ge, m2, op, nops, ops, ae), \ 14841 xCM_(m1, lt, m2, op, nops, ops, ae), \ 14842 xCM_(m1, gt, m2, op, nops, ops, ae), \ 14843 xCM_(m1, le, m2, op, nops, ops, ae), \ 14844 xCM_(m1, al, m2, op, nops, ops, ae) 14845 14846#define UE(mnem, op, nops, ops, ae) \ 14847 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14848 14849#define UF(mnem, op, nops, ops, ae) \ 14850 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14851 14852/* Neon data-processing. ARM versions are unconditional with cond=0xf. 14853 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we 14854 use the same encoding function for each. */ 14855#define NUF(mnem, op, nops, ops, enc) \ 14856 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ 14857 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14858 14859/* Neon data processing, version which indirects through neon_enc_tab for 14860 the various overloaded versions of opcodes. */ 14861#define nUF(mnem, op, nops, ops, enc) \ 14862 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ 14863 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14864 14865/* Neon insn with conditional suffix for the ARM version, non-overloaded 14866 version. */ 14867#define NCE_tag(mnem, op, nops, ops, enc, tag) \ 14868 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ 14869 THUMB_VARIANT, do_##enc, do_##enc } 14870 14871#define NCE(mnem, op, nops, ops, enc) \ 14872 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14873 14874#define NCEF(mnem, op, nops, ops, enc) \ 14875 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14876 14877/* Neon insn with conditional suffix for the ARM version, overloaded types. */ 14878#define nCE_tag(mnem, op, nops, ops, enc, tag) \ 14879 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ 14880 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14881 14882#define nCE(mnem, op, nops, ops, enc) \ 14883 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14884 14885#define nCEF(mnem, op, nops, ops, enc) \ 14886 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14887 14888#define do_0 0 14889 14890/* Thumb-only, unconditional. */ 14891#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) 14892 14893static const struct asm_opcode insns[] = 14894{ 14895#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ 14896#define THUMB_VARIANT &arm_ext_v4t 14897 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), 14898 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), 14899 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), 14900 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), 14901 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), 14902 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), 14903 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), 14904 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), 14905 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), 14906 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), 14907 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), 14908 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), 14909 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), 14910 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), 14911 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), 14912 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), 14913 14914 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism 14915 for setting PSR flag bits. They are obsolete in V6 and do not 14916 have Thumb equivalents. */ 14917 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14918 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14919 CL(tstp, 110f000, 2, (RR, SH), cmp), 14920 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14921 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14922 CL(cmpp, 150f000, 2, (RR, SH), cmp), 14923 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14924 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14925 CL(cmnp, 170f000, 2, (RR, SH), cmp), 14926 14927 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), 14928 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), 14929 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), 14930 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), 14931 14932 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), 14933 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14934 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), 14935 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14936 14937 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14938 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14939 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14940 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14941 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14942 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14943 14944 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), 14945 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), 14946 tCE(b, a000000, b, 1, (EXPr), branch, t_branch), 14947 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), 14948 14949 /* Pseudo ops. */ 14950 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), 14951 C3(adrl, 28f0000, 2, (RR, EXP), adrl), 14952 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), 14953 14954 /* Thumb-compatibility pseudo ops. */ 14955 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), 14956 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), 14957 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), 14958 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), 14959 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), 14960 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), 14961 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), 14962 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), 14963 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), 14964 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), 14965 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), 14966 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), 14967 14968 /* These may simplify to neg. */ 14969 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), 14970 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), 14971 14972 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm), 14973 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm), 14974 14975#undef THUMB_VARIANT 14976#define THUMB_VARIANT &arm_ext_v6 14977 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), 14978 14979 /* V1 instructions with no Thumb analogue prior to V6T2. */ 14980#undef THUMB_VARIANT 14981#define THUMB_VARIANT &arm_ext_v6t2 14982 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 14983 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 14984 CL(teqp, 130f000, 2, (RR, SH), cmp), 14985 14986 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), 14987 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), 14988 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), 14989 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), 14990 14991 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14992 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14993 14994 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14995 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14996 14997 /* V1 instructions with no Thumb analogue at all. */ 14998 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), 14999 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), 15000 15001 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), 15002 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), 15003 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), 15004 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), 15005 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), 15006 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), 15007 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), 15008 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), 15009 15010#undef ARM_VARIANT 15011#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ 15012#undef THUMB_VARIANT 15013#define THUMB_VARIANT &arm_ext_v4t 15014 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15015 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15016 15017#undef THUMB_VARIANT 15018#define THUMB_VARIANT &arm_ext_v6t2 15019 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15020 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), 15021 15022 /* Generic coprocessor instructions. */ 15023 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15024 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15025 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15026 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15027 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15028 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15029 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15030 15031#undef ARM_VARIANT 15032#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ 15033 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15034 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15035 15036#undef ARM_VARIANT 15037#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ 15038 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), 15039 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), 15040 15041#undef ARM_VARIANT 15042#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ 15043 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15044 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15045 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15046 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15047 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15048 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15049 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15050 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15051 15052#undef ARM_VARIANT 15053#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ 15054#undef THUMB_VARIANT 15055#define THUMB_VARIANT &arm_ext_v4t 15056 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15057 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15058 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15059 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15060 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15061 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15062 15063#undef ARM_VARIANT 15064#define ARM_VARIANT &arm_ext_v4t_5 15065 /* ARM Architecture 4T. */ 15066 /* Note: bx (and blx) are required on V5, even if the processor does 15067 not support Thumb. */ 15068 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), 15069 15070#undef ARM_VARIANT 15071#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ 15072#undef THUMB_VARIANT 15073#define THUMB_VARIANT &arm_ext_v5t 15074 /* Note: blx has 2 variants; the .value coded here is for 15075 BLX(2). Only this variant has conditional execution. */ 15076 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), 15077 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), 15078 15079#undef THUMB_VARIANT 15080#define THUMB_VARIANT &arm_ext_v6t2 15081 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), 15082 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15083 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15084 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15085 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15086 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15087 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15088 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15089 15090#undef ARM_VARIANT 15091#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ 15092 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15093 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15094 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15095 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15096 15097 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15098 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15099 15100 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15101 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15102 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15103 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15104 15105 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15106 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15107 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15108 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15109 15110 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15111 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15112 15113 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15114 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15115 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15116 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15117 15118#undef ARM_VARIANT 15119#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ 15120 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), 15121 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15122 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15123 15124 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15125 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15126 15127#undef ARM_VARIANT 15128#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ 15129 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), 15130 15131#undef ARM_VARIANT 15132#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ 15133#undef THUMB_VARIANT 15134#define THUMB_VARIANT &arm_ext_v6 15135 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), 15136 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), 15137 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15138 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15139 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15140 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15141 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15142 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15143 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15144 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), 15145 15146#undef THUMB_VARIANT 15147#define THUMB_VARIANT &arm_ext_v6t2 15148 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), 15149 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), 15150 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15151 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15152 15153 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), 15154 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), 15155 15156/* ARM V6 not included in V7M (eg. integer SIMD). */ 15157#undef THUMB_VARIANT 15158#define THUMB_VARIANT &arm_ext_v6_notm 15159 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), 15160 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), 15161 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), 15162 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15163 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15164 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15165 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15166 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15167 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15168 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15169 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15170 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15171 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15172 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15173 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15174 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15175 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15176 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15177 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15178 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15179 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15180 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15181 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15182 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15183 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15184 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15185 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15186 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15187 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15188 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15189 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15190 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15191 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15192 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15193 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15194 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15195 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15196 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15197 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15198 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15199 UF(rfeib, 9900a00, 1, (RRw), rfe), 15200 UF(rfeda, 8100a00, 1, (RRw), rfe), 15201 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15202 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15203 UF(rfefa, 9900a00, 1, (RRw), rfe), 15204 UF(rfeea, 8100a00, 1, (RRw), rfe), 15205 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15206 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15207 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15208 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15209 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15210 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15211 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15212 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15213 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15214 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15215 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15216 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15217 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15218 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15219 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15220 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15221 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15222 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15223 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15224 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15225 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15226 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15227 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15228 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15229 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15230 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15231 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15232 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15233 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), 15234 UF(srsib, 9c00500, 2, (oRRw, I31w), srs), 15235 UF(srsda, 8400500, 2, (oRRw, I31w), srs), 15236 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs), 15237 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), 15238 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), 15239 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15240 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15241 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), 15242 15243#undef ARM_VARIANT 15244#define ARM_VARIANT &arm_ext_v6k 15245#undef THUMB_VARIANT 15246#define THUMB_VARIANT &arm_ext_v6k 15247 tCE(yield, 320f001, yield, 0, (), noargs, t_hint), 15248 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), 15249 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), 15250 tCE(sev, 320f004, sev, 0, (), noargs, t_hint), 15251 15252#undef THUMB_VARIANT 15253#define THUMB_VARIANT &arm_ext_v6_notm 15254 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), 15255 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), 15256 15257#undef THUMB_VARIANT 15258#define THUMB_VARIANT &arm_ext_v6t2 15259 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15260 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15261 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15262 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15263 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), 15264 15265#undef ARM_VARIANT 15266#define ARM_VARIANT &arm_ext_v6z 15267 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), 15268 15269#undef ARM_VARIANT 15270#define ARM_VARIANT &arm_ext_v6t2 15271 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), 15272 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), 15273 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15274 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15275 15276 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15277 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), 15278 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), 15279 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), 15280 15281 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15282 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15283 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15284 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15285 15286 UT(cbnz, b900, 2, (RR, EXP), t_cbz), 15287 UT(cbz, b100, 2, (RR, EXP), t_cbz), 15288 /* ARM does not really have an IT instruction, so always allow it. */ 15289#undef ARM_VARIANT 15290#define ARM_VARIANT &arm_ext_v1 15291 TUE(it, 0, bf08, 1, (COND), it, t_it), 15292 TUE(itt, 0, bf0c, 1, (COND), it, t_it), 15293 TUE(ite, 0, bf04, 1, (COND), it, t_it), 15294 TUE(ittt, 0, bf0e, 1, (COND), it, t_it), 15295 TUE(itet, 0, bf06, 1, (COND), it, t_it), 15296 TUE(itte, 0, bf0a, 1, (COND), it, t_it), 15297 TUE(itee, 0, bf02, 1, (COND), it, t_it), 15298 TUE(itttt, 0, bf0f, 1, (COND), it, t_it), 15299 TUE(itett, 0, bf07, 1, (COND), it, t_it), 15300 TUE(ittet, 0, bf0b, 1, (COND), it, t_it), 15301 TUE(iteet, 0, bf03, 1, (COND), it, t_it), 15302 TUE(ittte, 0, bf0d, 1, (COND), it, t_it), 15303 TUE(itete, 0, bf05, 1, (COND), it, t_it), 15304 TUE(ittee, 0, bf09, 1, (COND), it, t_it), 15305 TUE(iteee, 0, bf01, 1, (COND), it, t_it), 15306 15307 /* Thumb2 only instructions. */ 15308#undef ARM_VARIANT 15309#define ARM_VARIANT NULL 15310 15311 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15312 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15313 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), 15314 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), 15315 15316 /* Thumb-2 hardware division instructions (R and M profiles only). */ 15317#undef THUMB_VARIANT 15318#define THUMB_VARIANT &arm_ext_div 15319 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), 15320 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), 15321 15322 /* ARM V7 instructions. */ 15323#undef ARM_VARIANT 15324#define ARM_VARIANT &arm_ext_v7 15325#undef THUMB_VARIANT 15326#define THUMB_VARIANT &arm_ext_v7 15327 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), 15328 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), 15329 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), 15330 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), 15331 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), 15332 15333#undef ARM_VARIANT 15334#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ 15335 cCE(wfs, e200110, 1, (RR), rd), 15336 cCE(rfs, e300110, 1, (RR), rd), 15337 cCE(wfc, e400110, 1, (RR), rd), 15338 cCE(rfc, e500110, 1, (RR), rd), 15339 15340 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), 15341 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), 15342 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), 15343 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), 15344 15345 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), 15346 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), 15347 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), 15348 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), 15349 15350 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), 15351 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), 15352 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), 15353 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), 15354 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), 15355 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), 15356 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), 15357 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), 15358 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), 15359 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), 15360 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), 15361 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), 15362 15363 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), 15364 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), 15365 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), 15366 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), 15367 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), 15368 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), 15369 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), 15370 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), 15371 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), 15372 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), 15373 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), 15374 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), 15375 15376 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), 15377 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), 15378 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), 15379 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), 15380 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), 15381 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), 15382 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), 15383 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), 15384 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), 15385 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), 15386 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), 15387 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), 15388 15389 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), 15390 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), 15391 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), 15392 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), 15393 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), 15394 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), 15395 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), 15396 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), 15397 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), 15398 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), 15399 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), 15400 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), 15401 15402 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), 15403 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), 15404 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), 15405 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), 15406 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), 15407 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), 15408 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), 15409 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), 15410 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), 15411 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), 15412 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), 15413 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), 15414 15415 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), 15416 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), 15417 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), 15418 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), 15419 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), 15420 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), 15421 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), 15422 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), 15423 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), 15424 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), 15425 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), 15426 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), 15427 15428 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), 15429 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), 15430 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), 15431 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), 15432 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), 15433 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), 15434 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), 15435 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), 15436 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), 15437 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), 15438 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), 15439 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), 15440 15441 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), 15442 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), 15443 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), 15444 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), 15445 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), 15446 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), 15447 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), 15448 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), 15449 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), 15450 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), 15451 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), 15452 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), 15453 15454 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), 15455 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), 15456 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), 15457 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), 15458 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), 15459 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), 15460 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), 15461 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), 15462 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), 15463 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), 15464 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), 15465 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), 15466 15467 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), 15468 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), 15469 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), 15470 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), 15471 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), 15472 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), 15473 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), 15474 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), 15475 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), 15476 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), 15477 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), 15478 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), 15479 15480 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), 15481 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), 15482 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), 15483 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), 15484 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), 15485 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), 15486 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), 15487 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), 15488 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), 15489 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), 15490 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), 15491 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), 15492 15493 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), 15494 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), 15495 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), 15496 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), 15497 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), 15498 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), 15499 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), 15500 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), 15501 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), 15502 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), 15503 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), 15504 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), 15505 15506 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), 15507 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), 15508 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), 15509 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), 15510 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), 15511 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), 15512 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), 15513 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), 15514 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), 15515 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), 15516 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), 15517 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), 15518 15519 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), 15520 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), 15521 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), 15522 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), 15523 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), 15524 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), 15525 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), 15526 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), 15527 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), 15528 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), 15529 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), 15530 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), 15531 15532 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), 15533 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), 15534 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), 15535 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), 15536 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), 15537 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), 15538 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), 15539 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), 15540 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), 15541 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), 15542 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), 15543 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), 15544 15545 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), 15546 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), 15547 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), 15548 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), 15549 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), 15550 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), 15551 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), 15552 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), 15553 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), 15554 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), 15555 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), 15556 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), 15557 15558 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), 15559 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), 15560 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), 15561 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), 15562 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), 15563 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15564 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15565 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15566 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), 15567 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), 15568 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), 15569 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), 15570 15571 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), 15572 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), 15573 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), 15574 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), 15575 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), 15576 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15577 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15578 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15579 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), 15580 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), 15581 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), 15582 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), 15583 15584 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), 15585 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), 15586 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), 15587 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), 15588 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), 15589 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15590 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15591 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15592 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), 15593 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), 15594 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), 15595 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), 15596 15597 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), 15598 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), 15599 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), 15600 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), 15601 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), 15602 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15603 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15604 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15605 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), 15606 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), 15607 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), 15608 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), 15609 15610 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), 15611 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), 15612 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), 15613 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), 15614 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), 15615 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15616 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15617 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15618 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), 15619 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), 15620 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), 15621 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), 15622 15623 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), 15624 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), 15625 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), 15626 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), 15627 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), 15628 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15629 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15630 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15631 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), 15632 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), 15633 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), 15634 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), 15635 15636 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), 15637 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), 15638 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), 15639 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), 15640 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), 15641 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15642 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15643 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15644 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), 15645 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), 15646 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), 15647 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), 15648 15649 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), 15650 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), 15651 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), 15652 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), 15653 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), 15654 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15655 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15656 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15657 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), 15658 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), 15659 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), 15660 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), 15661 15662 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), 15663 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), 15664 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), 15665 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), 15666 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), 15667 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15668 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15669 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15670 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), 15671 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), 15672 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), 15673 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), 15674 15675 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), 15676 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), 15677 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), 15678 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), 15679 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), 15680 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15681 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15682 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15683 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), 15684 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), 15685 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), 15686 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), 15687 15688 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15689 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15690 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15691 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15692 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15693 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15694 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15695 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15696 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15697 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15698 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15699 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15700 15701 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15702 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15703 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15704 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15705 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15706 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15707 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15708 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15709 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15710 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15711 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15712 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15713 15714 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15715 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15716 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15717 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15718 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15719 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15720 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15721 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15722 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15723 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15724 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15725 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15726 15727 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), 15728 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), 15729 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), 15730 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), 15731 15732 cCL(flts, e000110, 2, (RF, RR), rn_rd), 15733 cCL(fltsp, e000130, 2, (RF, RR), rn_rd), 15734 cCL(fltsm, e000150, 2, (RF, RR), rn_rd), 15735 cCL(fltsz, e000170, 2, (RF, RR), rn_rd), 15736 cCL(fltd, e000190, 2, (RF, RR), rn_rd), 15737 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), 15738 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), 15739 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), 15740 cCL(flte, e080110, 2, (RF, RR), rn_rd), 15741 cCL(fltep, e080130, 2, (RF, RR), rn_rd), 15742 cCL(fltem, e080150, 2, (RF, RR), rn_rd), 15743 cCL(fltez, e080170, 2, (RF, RR), rn_rd), 15744 15745 /* The implementation of the FIX instruction is broken on some 15746 assemblers, in that it accepts a precision specifier as well as a 15747 rounding specifier, despite the fact that this is meaningless. 15748 To be more compatible, we accept it as well, though of course it 15749 does not set any bits. */ 15750 cCE(fix, e100110, 2, (RR, RF), rd_rm), 15751 cCL(fixp, e100130, 2, (RR, RF), rd_rm), 15752 cCL(fixm, e100150, 2, (RR, RF), rd_rm), 15753 cCL(fixz, e100170, 2, (RR, RF), rd_rm), 15754 cCL(fixsp, e100130, 2, (RR, RF), rd_rm), 15755 cCL(fixsm, e100150, 2, (RR, RF), rd_rm), 15756 cCL(fixsz, e100170, 2, (RR, RF), rd_rm), 15757 cCL(fixdp, e100130, 2, (RR, RF), rd_rm), 15758 cCL(fixdm, e100150, 2, (RR, RF), rd_rm), 15759 cCL(fixdz, e100170, 2, (RR, RF), rd_rm), 15760 cCL(fixep, e100130, 2, (RR, RF), rd_rm), 15761 cCL(fixem, e100150, 2, (RR, RF), rd_rm), 15762 cCL(fixez, e100170, 2, (RR, RF), rd_rm), 15763 15764 /* Instructions that were new with the real FPA, call them V2. */ 15765#undef ARM_VARIANT 15766#define ARM_VARIANT &fpu_fpa_ext_v2 15767 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15768 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15769 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15770 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15771 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15772 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15773 15774#undef ARM_VARIANT 15775#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ 15776 /* Moves and type conversions. */ 15777 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), 15778 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), 15779 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), 15780 cCE(fmstat, ef1fa10, 0, (), noargs), 15781 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), 15782 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), 15783 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), 15784 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15785 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), 15786 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15787 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), 15788 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), 15789 cCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vfp_vmrs), 15790 cCE(vmsr, ee00a10, 2, (RVC, RR), vfp_vmsr), 15791 15792 /* Memory operations. */ 15793 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15794 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15795 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15796 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15797 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15798 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15799 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15800 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15801 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15802 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15803 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15804 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15805 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15806 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15807 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15808 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15809 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15810 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15811 15812 /* Monadic operations. */ 15813 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), 15814 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), 15815 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), 15816 15817 /* Dyadic operations. */ 15818 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15819 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15820 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15821 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15822 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15823 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15824 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15825 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15826 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15827 15828 /* Comparisons. */ 15829 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), 15830 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), 15831 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), 15832 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), 15833 15834#undef ARM_VARIANT 15835#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ 15836 /* Moves and type conversions. */ 15837 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15838 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15839 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15840 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), 15841 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), 15842 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), 15843 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), 15844 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15845 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), 15846 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15847 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15848 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15849 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15850 15851 /* Memory operations. */ 15852 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15853 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15854 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15855 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15856 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15857 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15858 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15859 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15860 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15861 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15862 15863 /* Monadic operations. */ 15864 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15865 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15866 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15867 15868 /* Dyadic operations. */ 15869 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15870 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15871 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15872 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15873 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15874 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15875 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15876 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15877 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15878 15879 /* Comparisons. */ 15880 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15881 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), 15882 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15883 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), 15884 15885#undef ARM_VARIANT 15886#define ARM_VARIANT &fpu_vfp_ext_v2 15887 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), 15888 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), 15889 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), 15890 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), 15891 15892/* Instructions which may belong to either the Neon or VFP instruction sets. 15893 Individual encoder functions perform additional architecture checks. */ 15894#undef ARM_VARIANT 15895#define ARM_VARIANT &fpu_vfp_ext_v1xd 15896#undef THUMB_VARIANT 15897#define THUMB_VARIANT &fpu_vfp_ext_v1xd 15898 /* These mnemonics are unique to VFP. */ 15899 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), 15900 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), 15901 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15902 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15903 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15904 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15905 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15906 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), 15907 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), 15908 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), 15909 15910 /* Mnemonics shared by Neon and VFP. */ 15911 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), 15912 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15913 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15914 15915 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15916 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15917 15918 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15919 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15920 15921 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15922 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15923 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15924 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15925 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15926 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15927 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15928 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15929 15930 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), 15931 15932 /* NOTE: All VMOV encoding is special-cased! */ 15933 NCE(vmov, 0, 1, (VMOV), neon_mov), 15934 NCE(vmovq, 0, 1, (VMOV), neon_mov), 15935 15936#undef THUMB_VARIANT 15937#define THUMB_VARIANT &fpu_neon_ext_v1 15938#undef ARM_VARIANT 15939#define ARM_VARIANT &fpu_neon_ext_v1 15940 /* Data processing with three registers of the same length. */ 15941 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ 15942 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), 15943 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), 15944 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15945 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15946 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15947 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15948 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15949 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15950 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ 15951 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15952 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15953 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15954 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15955 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15956 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15957 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15958 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15959 /* If not immediate, fall back to neon_dyadic_i64_su. 15960 shl_imm should accept I8 I16 I32 I64, 15961 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ 15962 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), 15963 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), 15964 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), 15965 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), 15966 /* Logic ops, types optional & ignored. */ 15967 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), 15968 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), 15969 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), 15970 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), 15971 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), 15972 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), 15973 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), 15974 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), 15975 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), 15976 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), 15977 /* Bitfield ops, untyped. */ 15978 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15979 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15980 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15981 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15982 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15983 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15984 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ 15985 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15986 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15987 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15988 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15989 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15990 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15991 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall 15992 back to neon_dyadic_if_su. */ 15993 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 15994 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 15995 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 15996 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 15997 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 15998 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 15999 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16000 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16001 /* Comparison. Type I8 I16 I32 F32. */ 16002 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), 16003 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), 16004 /* As above, D registers only. */ 16005 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16006 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16007 /* Int and float variants, signedness unimportant. */ 16008 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16009 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16010 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), 16011 /* Add/sub take types I8 I16 I32 I64 F32. */ 16012 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16013 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16014 /* vtst takes sizes 8, 16, 32. */ 16015 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), 16016 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), 16017 /* VMUL takes I8 I16 I32 F32 P8. */ 16018 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), 16019 /* VQD{R}MULH takes S16 S32. */ 16020 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16021 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16022 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16023 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16024 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16025 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16026 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16027 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16028 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16029 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16030 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16031 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16032 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16033 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16034 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16035 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16036 16037 /* Two address, int/float. Types S8 S16 S32 F32. */ 16038 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), 16039 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), 16040 16041 /* Data processing with two registers and a shift amount. */ 16042 /* Right shifts, and variants with rounding. 16043 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ 16044 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16045 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16046 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16047 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16048 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16049 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16050 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16051 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16052 /* Shift and insert. Sizes accepted 8 16 32 64. */ 16053 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), 16054 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), 16055 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), 16056 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), 16057 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ 16058 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), 16059 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), 16060 /* Right shift immediate, saturating & narrowing, with rounding variants. 16061 Types accepted S16 S32 S64 U16 U32 U64. */ 16062 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16063 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16064 /* As above, unsigned. Types accepted S16 S32 S64. */ 16065 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16066 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16067 /* Right shift narrowing. Types accepted I16 I32 I64. */ 16068 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16069 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16070 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ 16071 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), 16072 /* CVT with optional immediate for fixed-point variant. */ 16073 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), 16074 16075 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), 16076 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), 16077 16078 /* Data processing, three registers of different lengths. */ 16079 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ 16080 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), 16081 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), 16082 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), 16083 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), 16084 /* If not scalar, fall back to neon_dyadic_long. 16085 Vector types as above, scalar types S16 S32 U16 U32. */ 16086 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16087 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16088 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ 16089 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16090 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16091 /* Dyadic, narrowing insns. Types I16 I32 I64. */ 16092 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16093 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16094 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16095 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16096 /* Saturating doubling multiplies. Types S16 S32. */ 16097 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16098 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16099 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16100 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types 16101 S16 S32 U16 U32. */ 16102 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), 16103 16104 /* Extract. Size 8. */ 16105 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), 16106 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), 16107 16108 /* Two registers, miscellaneous. */ 16109 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ 16110 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), 16111 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), 16112 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), 16113 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), 16114 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), 16115 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), 16116 /* Vector replicate. Sizes 8 16 32. */ 16117 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), 16118 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), 16119 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ 16120 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), 16121 /* VMOVN. Types I16 I32 I64. */ 16122 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), 16123 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ 16124 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), 16125 /* VQMOVUN. Types S16 S32 S64. */ 16126 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), 16127 /* VZIP / VUZP. Sizes 8 16 32. */ 16128 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), 16129 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), 16130 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), 16131 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), 16132 /* VQABS / VQNEG. Types S8 S16 S32. */ 16133 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16134 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), 16135 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16136 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), 16137 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ 16138 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), 16139 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), 16140 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), 16141 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), 16142 /* Reciprocal estimates. Types U32 F32. */ 16143 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), 16144 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), 16145 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), 16146 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), 16147 /* VCLS. Types S8 S16 S32. */ 16148 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), 16149 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), 16150 /* VCLZ. Types I8 I16 I32. */ 16151 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), 16152 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), 16153 /* VCNT. Size 8. */ 16154 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), 16155 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), 16156 /* Two address, untyped. */ 16157 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), 16158 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), 16159 /* VTRN. Sizes 8 16 32. */ 16160 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), 16161 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), 16162 16163 /* Table lookup. Size 8. */ 16164 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16165 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16166 16167#undef THUMB_VARIANT 16168#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext 16169#undef ARM_VARIANT 16170#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext 16171 /* Neon element/structure load/store. */ 16172 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16173 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16174 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16175 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16176 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16177 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16178 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16179 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16180 16181#undef THUMB_VARIANT 16182#define THUMB_VARIANT &fpu_vfp_ext_v3 16183#undef ARM_VARIANT 16184#define ARM_VARIANT &fpu_vfp_ext_v3 16185 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), 16186 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), 16187 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16188 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16189 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16190 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16191 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16192 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16193 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16194 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16195 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16196 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16197 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16198 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16199 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16200 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16201 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16202 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16203 16204#undef THUMB_VARIANT 16205#undef ARM_VARIANT 16206#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ 16207 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16208 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16209 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16210 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16211 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16212 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16213 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), 16214 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), 16215 16216#undef ARM_VARIANT 16217#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ 16218 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), 16219 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), 16220 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), 16221 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), 16222 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), 16223 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), 16224 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), 16225 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), 16226 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), 16227 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16228 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16229 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16230 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16231 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16232 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16233 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16234 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16235 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16236 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), 16237 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), 16238 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16239 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16240 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16241 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16242 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16243 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16244 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), 16245 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), 16246 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), 16247 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), 16248 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), 16249 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), 16250 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), 16251 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), 16252 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), 16253 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), 16254 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), 16255 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16256 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16257 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16258 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16259 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16260 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16261 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16262 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16263 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16264 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), 16265 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16266 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16267 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16268 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16269 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16270 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16271 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16272 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16273 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16274 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16275 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16276 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16277 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16278 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16279 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16280 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16281 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16282 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16283 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16284 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16285 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16286 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16287 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16288 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16289 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16290 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16291 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16292 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16293 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16294 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16295 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16296 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16297 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16298 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16299 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16300 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16301 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16302 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16303 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16304 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16305 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16306 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), 16307 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16308 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16309 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16310 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16311 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16312 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16313 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16314 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16315 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16316 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16317 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16318 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16319 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16320 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16321 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16322 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16323 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16324 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16325 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16326 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16327 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16328 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), 16329 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16330 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16331 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16332 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16333 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16334 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16335 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16336 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16337 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16338 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16339 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16340 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16341 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16342 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16343 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16344 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16345 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16346 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16347 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16348 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16349 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16350 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16351 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16352 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16353 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16354 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16355 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16356 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16357 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16358 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16359 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16360 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), 16361 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), 16362 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), 16363 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), 16364 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), 16365 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), 16366 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16367 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16368 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16369 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), 16370 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), 16371 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), 16372 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), 16373 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), 16374 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), 16375 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16376 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16377 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16378 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16379 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), 16380 16381#undef ARM_VARIANT 16382#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ 16383 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc), 16384 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc), 16385 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc), 16386 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn), 16387 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn), 16388 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn), 16389 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16390 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16391 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16392 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16393 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16394 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16395 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16396 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16397 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16398 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16399 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16400 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16401 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16402 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16403 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), 16404 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16405 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16406 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16407 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16408 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16409 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16410 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16411 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16412 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16413 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16414 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16415 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16416 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16417 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16418 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16419 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16420 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16421 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16422 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16423 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16424 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16425 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16426 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16427 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16428 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16429 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16430 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16431 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16432 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16433 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16434 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16435 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16436 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16437 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16438 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16439 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16440 16441#undef ARM_VARIANT 16442#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ 16443 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16444 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16445 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16446 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16447 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16448 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16449 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16450 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16451 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), 16452 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), 16453 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), 16454 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), 16455 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), 16456 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), 16457 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), 16458 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), 16459 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), 16460 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), 16461 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), 16462 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), 16463 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), 16464 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), 16465 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), 16466 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), 16467 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), 16468 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), 16469 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), 16470 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), 16471 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), 16472 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), 16473 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), 16474 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), 16475 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), 16476 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), 16477 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), 16478 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), 16479 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), 16480 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), 16481 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), 16482 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), 16483 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), 16484 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), 16485 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), 16486 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), 16487 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), 16488 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), 16489 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), 16490 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), 16491 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), 16492 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), 16493 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), 16494 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), 16495 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), 16496 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), 16497 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), 16498 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), 16499 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), 16500 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), 16501 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), 16502 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), 16503 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), 16504 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), 16505 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), 16506 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), 16507 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16508 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16509 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16510 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16511 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16512 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16513 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16514 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16515 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16516 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16517 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16518 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16519}; 16520#undef ARM_VARIANT 16521#undef THUMB_VARIANT 16522#undef TCE 16523#undef TCM 16524#undef TUE 16525#undef TUF 16526#undef TCC 16527#undef cCE 16528#undef cCL 16529#undef C3E 16530#undef CE 16531#undef CM 16532#undef UE 16533#undef UF 16534#undef UT 16535#undef NUF 16536#undef nUF 16537#undef NCE 16538#undef nCE 16539#undef OPS0 16540#undef OPS1 16541#undef OPS2 16542#undef OPS3 16543#undef OPS4 16544#undef OPS5 16545#undef OPS6 16546#undef do_0 16547 16548/* MD interface: bits in the object file. */ 16549 16550/* Turn an integer of n bytes (in val) into a stream of bytes appropriate 16551 for use in the a.out file, and stores them in the array pointed to by buf. 16552 This knows about the endian-ness of the target machine and does 16553 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) 16554 2 (short) and 4 (long) Floating numbers are put out as a series of 16555 LITTLENUMS (shorts, here at least). */ 16556 16557void 16558md_number_to_chars (char * buf, valueT val, int n) 16559{ 16560 if (target_big_endian) 16561 number_to_chars_bigendian (buf, val, n); 16562 else 16563 number_to_chars_littleendian (buf, val, n); 16564} 16565 16566static valueT 16567md_chars_to_number (char * buf, int n) 16568{ 16569 valueT result = 0; 16570 unsigned char * where = (unsigned char *) buf; 16571 16572 if (target_big_endian) 16573 { 16574 while (n--) 16575 { 16576 result <<= 8; 16577 result |= (*where++ & 255); 16578 } 16579 } 16580 else 16581 { 16582 while (n--) 16583 { 16584 result <<= 8; 16585 result |= (where[n] & 255); 16586 } 16587 } 16588 16589 return result; 16590} 16591 16592/* MD interface: Sections. */ 16593 16594/* Estimate the size of a frag before relaxing. Assume everything fits in 16595 2 bytes. */ 16596 16597int 16598md_estimate_size_before_relax (fragS * fragp, 16599 segT segtype ATTRIBUTE_UNUSED) 16600{ 16601 fragp->fr_var = 2; 16602 return 2; 16603} 16604 16605/* Convert a machine dependent frag. */ 16606 16607void 16608md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) 16609{ 16610 unsigned long insn; 16611 unsigned long old_op; 16612 char *buf; 16613 expressionS exp; 16614 fixS *fixp; 16615 int reloc_type; 16616 int pc_rel; 16617 int opcode; 16618 16619 buf = fragp->fr_literal + fragp->fr_fix; 16620 16621 old_op = bfd_get_16(abfd, buf); 16622 if (fragp->fr_symbol) { 16623 exp.X_op = O_symbol; 16624 exp.X_add_symbol = fragp->fr_symbol; 16625 } else { 16626 exp.X_op = O_constant; 16627 } 16628 exp.X_add_number = fragp->fr_offset; 16629 opcode = fragp->fr_subtype; 16630 switch (opcode) 16631 { 16632 case T_MNEM_ldr_pc: 16633 case T_MNEM_ldr_pc2: 16634 case T_MNEM_ldr_sp: 16635 case T_MNEM_str_sp: 16636 case T_MNEM_ldr: 16637 case T_MNEM_ldrb: 16638 case T_MNEM_ldrh: 16639 case T_MNEM_str: 16640 case T_MNEM_strb: 16641 case T_MNEM_strh: 16642 if (fragp->fr_var == 4) 16643 { 16644 insn = THUMB_OP32(opcode); 16645 if ((old_op >> 12) == 4 || (old_op >> 12) == 9) 16646 { 16647 insn |= (old_op & 0x700) << 4; 16648 } 16649 else 16650 { 16651 insn |= (old_op & 7) << 12; 16652 insn |= (old_op & 0x38) << 13; 16653 } 16654 insn |= 0x00000c00; 16655 put_thumb32_insn (buf, insn); 16656 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; 16657 } 16658 else 16659 { 16660 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; 16661 } 16662 pc_rel = (opcode == T_MNEM_ldr_pc2); 16663 break; 16664 case T_MNEM_adr: 16665 if (fragp->fr_var == 4) 16666 { 16667 insn = THUMB_OP32 (opcode); 16668 insn |= (old_op & 0xf0) << 4; 16669 put_thumb32_insn (buf, insn); 16670 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; 16671 } 16672 else 16673 { 16674 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16675 exp.X_add_number -= 4; 16676 } 16677 pc_rel = 1; 16678 break; 16679 case T_MNEM_mov: 16680 case T_MNEM_movs: 16681 case T_MNEM_cmp: 16682 case T_MNEM_cmn: 16683 if (fragp->fr_var == 4) 16684 { 16685 int r0off = (opcode == T_MNEM_mov 16686 || opcode == T_MNEM_movs) ? 0 : 8; 16687 insn = THUMB_OP32 (opcode); 16688 insn = (insn & 0xe1ffffff) | 0x10000000; 16689 insn |= (old_op & 0x700) << r0off; 16690 put_thumb32_insn (buf, insn); 16691 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16692 } 16693 else 16694 { 16695 reloc_type = BFD_RELOC_ARM_THUMB_IMM; 16696 } 16697 pc_rel = 0; 16698 break; 16699 case T_MNEM_b: 16700 if (fragp->fr_var == 4) 16701 { 16702 insn = THUMB_OP32(opcode); 16703 put_thumb32_insn (buf, insn); 16704 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; 16705 } 16706 else 16707 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; 16708 pc_rel = 1; 16709 break; 16710 case T_MNEM_bcond: 16711 if (fragp->fr_var == 4) 16712 { 16713 insn = THUMB_OP32(opcode); 16714 insn |= (old_op & 0xf00) << 14; 16715 put_thumb32_insn (buf, insn); 16716 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; 16717 } 16718 else 16719 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; 16720 pc_rel = 1; 16721 break; 16722 case T_MNEM_add_sp: 16723 case T_MNEM_add_pc: 16724 case T_MNEM_inc_sp: 16725 case T_MNEM_dec_sp: 16726 if (fragp->fr_var == 4) 16727 { 16728 /* ??? Choose between add and addw. */ 16729 insn = THUMB_OP32 (opcode); 16730 insn |= (old_op & 0xf0) << 4; 16731 put_thumb32_insn (buf, insn); 16732 if (opcode == T_MNEM_add_pc) 16733 reloc_type = BFD_RELOC_ARM_T32_IMM12; 16734 else 16735 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16736 } 16737 else 16738 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16739 pc_rel = 0; 16740 break; 16741 16742 case T_MNEM_addi: 16743 case T_MNEM_addis: 16744 case T_MNEM_subi: 16745 case T_MNEM_subis: 16746 if (fragp->fr_var == 4) 16747 { 16748 insn = THUMB_OP32 (opcode); 16749 insn |= (old_op & 0xf0) << 4; 16750 insn |= (old_op & 0xf) << 16; 16751 put_thumb32_insn (buf, insn); 16752 if (insn & (1 << 20)) 16753 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16754 else 16755 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16756 } 16757 else 16758 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16759 pc_rel = 0; 16760 break; 16761 default: 16762 abort(); 16763 } 16764 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, 16765 reloc_type); 16766 fixp->fx_file = fragp->fr_file; 16767 fixp->fx_line = fragp->fr_line; 16768 fragp->fr_fix += fragp->fr_var; 16769} 16770 16771/* Return the size of a relaxable immediate operand instruction. 16772 SHIFT and SIZE specify the form of the allowable immediate. */ 16773static int 16774relax_immediate (fragS *fragp, int size, int shift) 16775{ 16776 offsetT offset; 16777 offsetT mask; 16778 offsetT low; 16779 16780 /* ??? Should be able to do better than this. */ 16781 if (fragp->fr_symbol) 16782 return 4; 16783 16784 low = (1 << shift) - 1; 16785 mask = (1 << (shift + size)) - (1 << shift); 16786 offset = fragp->fr_offset; 16787 /* Force misaligned offsets to 32-bit variant. */ 16788 if (offset & low) 16789 return 4; 16790 if (offset & ~mask) 16791 return 4; 16792 return 2; 16793} 16794 16795/* Get the address of a symbol during relaxation. */ 16796static addressT 16797relaxed_symbol_addr(fragS *fragp, long stretch) 16798{ 16799 fragS *sym_frag; 16800 addressT addr; 16801 symbolS *sym; 16802 16803 sym = fragp->fr_symbol; 16804 sym_frag = symbol_get_frag (sym); 16805 know (S_GET_SEGMENT (sym) != absolute_section 16806 || sym_frag == &zero_address_frag); 16807 addr = S_GET_VALUE (sym) + fragp->fr_offset; 16808 16809 /* If frag has yet to be reached on this pass, assume it will 16810 move by STRETCH just as we did. If this is not so, it will 16811 be because some frag between grows, and that will force 16812 another pass. */ 16813 16814 if (stretch != 0 16815 && sym_frag->relax_marker != fragp->relax_marker) 16816 addr += stretch; 16817 16818 return addr; 16819} 16820 16821/* Return the size of a relaxable adr pseudo-instruction or PC-relative 16822 load. */ 16823static int 16824relax_adr (fragS *fragp, asection *sec, long stretch) 16825{ 16826 addressT addr; 16827 offsetT val; 16828 16829 /* Assume worst case for symbols not known to be in the same section. */ 16830 if (!S_IS_DEFINED(fragp->fr_symbol) 16831 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16832 return 4; 16833 16834 val = relaxed_symbol_addr(fragp, stretch); 16835 addr = fragp->fr_address + fragp->fr_fix; 16836 addr = (addr + 4) & ~3; 16837 /* Force misaligned targets to 32-bit variant. */ 16838 if (val & 3) 16839 return 4; 16840 val -= addr; 16841 if (val < 0 || val > 1020) 16842 return 4; 16843 return 2; 16844} 16845 16846/* Return the size of a relaxable add/sub immediate instruction. */ 16847static int 16848relax_addsub (fragS *fragp, asection *sec) 16849{ 16850 char *buf; 16851 int op; 16852 16853 buf = fragp->fr_literal + fragp->fr_fix; 16854 op = bfd_get_16(sec->owner, buf); 16855 if ((op & 0xf) == ((op >> 4) & 0xf)) 16856 return relax_immediate (fragp, 8, 0); 16857 else 16858 return relax_immediate (fragp, 3, 0); 16859} 16860 16861 16862/* Return the size of a relaxable branch instruction. BITS is the 16863 size of the offset field in the narrow instruction. */ 16864 16865static int 16866relax_branch (fragS *fragp, asection *sec, int bits, long stretch) 16867{ 16868 addressT addr; 16869 offsetT val; 16870 offsetT limit; 16871 16872 /* Assume worst case for symbols not known to be in the same section. */ 16873 if (!S_IS_DEFINED(fragp->fr_symbol) 16874 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16875 return 4; 16876 16877 val = relaxed_symbol_addr(fragp, stretch); 16878 addr = fragp->fr_address + fragp->fr_fix + 4; 16879 val -= addr; 16880 16881 /* Offset is a signed value *2 */ 16882 limit = 1 << bits; 16883 if (val >= limit || val < -limit) 16884 return 4; 16885 return 2; 16886} 16887 16888 16889/* Relax a machine dependent frag. This returns the amount by which 16890 the current size of the frag should change. */ 16891 16892int 16893arm_relax_frag (asection *sec, fragS *fragp, long stretch) 16894{ 16895 int oldsize; 16896 int newsize; 16897 16898 oldsize = fragp->fr_var; 16899 switch (fragp->fr_subtype) 16900 { 16901 case T_MNEM_ldr_pc2: 16902 newsize = relax_adr(fragp, sec, stretch); 16903 break; 16904 case T_MNEM_ldr_pc: 16905 case T_MNEM_ldr_sp: 16906 case T_MNEM_str_sp: 16907 newsize = relax_immediate(fragp, 8, 2); 16908 break; 16909 case T_MNEM_ldr: 16910 case T_MNEM_str: 16911 newsize = relax_immediate(fragp, 5, 2); 16912 break; 16913 case T_MNEM_ldrh: 16914 case T_MNEM_strh: 16915 newsize = relax_immediate(fragp, 5, 1); 16916 break; 16917 case T_MNEM_ldrb: 16918 case T_MNEM_strb: 16919 newsize = relax_immediate(fragp, 5, 0); 16920 break; 16921 case T_MNEM_adr: 16922 newsize = relax_adr(fragp, sec, stretch); 16923 break; 16924 case T_MNEM_mov: 16925 case T_MNEM_movs: 16926 case T_MNEM_cmp: 16927 case T_MNEM_cmn: 16928 newsize = relax_immediate(fragp, 8, 0); 16929 break; 16930 case T_MNEM_b: 16931 newsize = relax_branch(fragp, sec, 11, stretch); 16932 break; 16933 case T_MNEM_bcond: 16934 newsize = relax_branch(fragp, sec, 8, stretch); 16935 break; 16936 case T_MNEM_add_sp: 16937 case T_MNEM_add_pc: 16938 newsize = relax_immediate (fragp, 8, 2); 16939 break; 16940 case T_MNEM_inc_sp: 16941 case T_MNEM_dec_sp: 16942 newsize = relax_immediate (fragp, 7, 2); 16943 break; 16944 case T_MNEM_addi: 16945 case T_MNEM_addis: 16946 case T_MNEM_subi: 16947 case T_MNEM_subis: 16948 newsize = relax_addsub (fragp, sec); 16949 break; 16950 default: 16951 abort(); 16952 } 16953 16954 fragp->fr_var = newsize; 16955 /* Freeze wide instructions that are at or before the same location as 16956 in the previous pass. This avoids infinite loops. 16957 Don't freeze them unconditionally because targets may be artificialy 16958 misaligned by the expansion of preceeding frags. */ 16959 if (stretch <= 0 && newsize > 2) 16960 { 16961 md_convert_frag (sec->owner, sec, fragp); 16962 frag_wane(fragp); 16963 } 16964 16965 return newsize - oldsize; 16966} 16967 16968/* Round up a section size to the appropriate boundary. */ 16969 16970valueT 16971md_section_align (segT segment ATTRIBUTE_UNUSED, 16972 valueT size) 16973{ 16974#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 16975 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 16976 { 16977 /* For a.out, force the section size to be aligned. If we don't do 16978 this, BFD will align it for us, but it will not write out the 16979 final bytes of the section. This may be a bug in BFD, but it is 16980 easier to fix it here since that is how the other a.out targets 16981 work. */ 16982 int align; 16983 16984 align = bfd_get_section_alignment (stdoutput, segment); 16985 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 16986 } 16987#endif 16988 16989 return size; 16990} 16991 16992/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 16993 of an rs_align_code fragment. */ 16994 16995void 16996arm_handle_align (fragS * fragP) 16997{ 16998 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; 16999 static char const thumb_noop[2] = { 0xc0, 0x46 }; 17000 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; 17001 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; 17002 17003 int bytes, fix, noop_size; 17004 char * p; 17005 const char * noop; 17006 17007 if (fragP->fr_type != rs_align_code) 17008 return; 17009 17010 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 17011 p = fragP->fr_literal + fragP->fr_fix; 17012 fix = 0; 17013 17014 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) 17015 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; 17016 17017 if (fragP->tc_frag_data) 17018 { 17019 if (target_big_endian) 17020 noop = thumb_bigend_noop; 17021 else 17022 noop = thumb_noop; 17023 noop_size = sizeof (thumb_noop); 17024 } 17025 else 17026 { 17027 if (target_big_endian) 17028 noop = arm_bigend_noop; 17029 else 17030 noop = arm_noop; 17031 noop_size = sizeof (arm_noop); 17032 } 17033 17034 if (bytes & (noop_size - 1)) 17035 { 17036 fix = bytes & (noop_size - 1); 17037 memset (p, 0, fix); 17038 p += fix; 17039 bytes -= fix; 17040 } 17041 17042 while (bytes >= noop_size) 17043 { 17044 memcpy (p, noop, noop_size); 17045 p += noop_size; 17046 bytes -= noop_size; 17047 fix += noop_size; 17048 } 17049 17050 fragP->fr_fix += fix; 17051 fragP->fr_var = noop_size; 17052} 17053 17054/* Called from md_do_align. Used to create an alignment 17055 frag in a code section. */ 17056 17057void 17058arm_frag_align_code (int n, int max) 17059{ 17060 char * p; 17061 17062 /* We assume that there will never be a requirement 17063 to support alignments greater than 32 bytes. */ 17064 if (max > MAX_MEM_FOR_RS_ALIGN_CODE) 17065 as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); 17066 17067 p = frag_var (rs_align_code, 17068 MAX_MEM_FOR_RS_ALIGN_CODE, 17069 1, 17070 (relax_substateT) max, 17071 (symbolS *) NULL, 17072 (offsetT) n, 17073 (char *) NULL); 17074 *p = 0; 17075} 17076 17077/* Perform target specific initialisation of a frag. */ 17078 17079void 17080arm_init_frag (fragS * fragP) 17081{ 17082 /* Record whether this frag is in an ARM or a THUMB area. */ 17083 fragP->tc_frag_data = thumb_mode; 17084} 17085 17086#ifdef OBJ_ELF 17087/* When we change sections we need to issue a new mapping symbol. */ 17088 17089void 17090arm_elf_change_section (void) 17091{ 17092 flagword flags; 17093 segment_info_type *seginfo; 17094 17095 /* Link an unlinked unwind index table section to the .text section. */ 17096 if (elf_section_type (now_seg) == SHT_ARM_EXIDX 17097 && elf_linked_to_section (now_seg) == NULL) 17098 elf_linked_to_section (now_seg) = text_section; 17099 17100 if (!SEG_NORMAL (now_seg)) 17101 return; 17102 17103 flags = bfd_get_section_flags (stdoutput, now_seg); 17104 17105 /* We can ignore sections that only contain debug info. */ 17106 if ((flags & SEC_ALLOC) == 0) 17107 return; 17108 17109 seginfo = seg_info (now_seg); 17110 mapstate = seginfo->tc_segment_info_data.mapstate; 17111 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; 17112} 17113 17114int 17115arm_elf_section_type (const char * str, size_t len) 17116{ 17117 if (len == 5 && strncmp (str, "exidx", 5) == 0) 17118 return SHT_ARM_EXIDX; 17119 17120 return -1; 17121} 17122 17123/* Code to deal with unwinding tables. */ 17124 17125static void add_unwind_adjustsp (offsetT); 17126 17127/* Cenerate and deferred unwind frame offset. */ 17128 17129static void 17130flush_pending_unwind (void) 17131{ 17132 offsetT offset; 17133 17134 offset = unwind.pending_offset; 17135 unwind.pending_offset = 0; 17136 if (offset != 0) 17137 add_unwind_adjustsp (offset); 17138} 17139 17140/* Add an opcode to this list for this function. Two-byte opcodes should 17141 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse 17142 order. */ 17143 17144static void 17145add_unwind_opcode (valueT op, int length) 17146{ 17147 /* Add any deferred stack adjustment. */ 17148 if (unwind.pending_offset) 17149 flush_pending_unwind (); 17150 17151 unwind.sp_restored = 0; 17152 17153 if (unwind.opcode_count + length > unwind.opcode_alloc) 17154 { 17155 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; 17156 if (unwind.opcodes) 17157 unwind.opcodes = xrealloc (unwind.opcodes, 17158 unwind.opcode_alloc); 17159 else 17160 unwind.opcodes = xmalloc (unwind.opcode_alloc); 17161 } 17162 while (length > 0) 17163 { 17164 length--; 17165 unwind.opcodes[unwind.opcode_count] = op & 0xff; 17166 op >>= 8; 17167 unwind.opcode_count++; 17168 } 17169} 17170 17171/* Add unwind opcodes to adjust the stack pointer. */ 17172 17173static void 17174add_unwind_adjustsp (offsetT offset) 17175{ 17176 valueT op; 17177 17178 if (offset > 0x200) 17179 { 17180 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ 17181 char bytes[5]; 17182 int n; 17183 valueT o; 17184 17185 /* Long form: 0xb2, uleb128. */ 17186 /* This might not fit in a word so add the individual bytes, 17187 remembering the list is built in reverse order. */ 17188 o = (valueT) ((offset - 0x204) >> 2); 17189 if (o == 0) 17190 add_unwind_opcode (0, 1); 17191 17192 /* Calculate the uleb128 encoding of the offset. */ 17193 n = 0; 17194 while (o) 17195 { 17196 bytes[n] = o & 0x7f; 17197 o >>= 7; 17198 if (o) 17199 bytes[n] |= 0x80; 17200 n++; 17201 } 17202 /* Add the insn. */ 17203 for (; n; n--) 17204 add_unwind_opcode (bytes[n - 1], 1); 17205 add_unwind_opcode (0xb2, 1); 17206 } 17207 else if (offset > 0x100) 17208 { 17209 /* Two short opcodes. */ 17210 add_unwind_opcode (0x3f, 1); 17211 op = (offset - 0x104) >> 2; 17212 add_unwind_opcode (op, 1); 17213 } 17214 else if (offset > 0) 17215 { 17216 /* Short opcode. */ 17217 op = (offset - 4) >> 2; 17218 add_unwind_opcode (op, 1); 17219 } 17220 else if (offset < 0) 17221 { 17222 offset = -offset; 17223 while (offset > 0x100) 17224 { 17225 add_unwind_opcode (0x7f, 1); 17226 offset -= 0x100; 17227 } 17228 op = ((offset - 4) >> 2) | 0x40; 17229 add_unwind_opcode (op, 1); 17230 } 17231} 17232 17233/* Finish the list of unwind opcodes for this function. */ 17234static void 17235finish_unwind_opcodes (void) 17236{ 17237 valueT op; 17238 17239 if (unwind.fp_used) 17240 { 17241 /* Adjust sp as necessary. */ 17242 unwind.pending_offset += unwind.fp_offset - unwind.frame_size; 17243 flush_pending_unwind (); 17244 17245 /* After restoring sp from the frame pointer. */ 17246 op = 0x90 | unwind.fp_reg; 17247 add_unwind_opcode (op, 1); 17248 } 17249 else 17250 flush_pending_unwind (); 17251} 17252 17253 17254/* Start an exception table entry. If idx is nonzero this is an index table 17255 entry. */ 17256 17257static void 17258start_unwind_section (const segT text_seg, int idx) 17259{ 17260 const char * text_name; 17261 const char * prefix; 17262 const char * prefix_once; 17263 const char * group_name; 17264 size_t prefix_len; 17265 size_t text_len; 17266 char * sec_name; 17267 size_t sec_name_len; 17268 int type; 17269 int flags; 17270 int linkonce; 17271 17272 if (idx) 17273 { 17274 prefix = ELF_STRING_ARM_unwind; 17275 prefix_once = ELF_STRING_ARM_unwind_once; 17276 type = SHT_ARM_EXIDX; 17277 } 17278 else 17279 { 17280 prefix = ELF_STRING_ARM_unwind_info; 17281 prefix_once = ELF_STRING_ARM_unwind_info_once; 17282 type = SHT_PROGBITS; 17283 } 17284 17285 text_name = segment_name (text_seg); 17286 if (streq (text_name, ".text")) 17287 text_name = ""; 17288 17289 if (strncmp (text_name, ".gnu.linkonce.t.", 17290 strlen (".gnu.linkonce.t.")) == 0) 17291 { 17292 prefix = prefix_once; 17293 text_name += strlen (".gnu.linkonce.t."); 17294 } 17295 17296 prefix_len = strlen (prefix); 17297 text_len = strlen (text_name); 17298 sec_name_len = prefix_len + text_len; 17299 sec_name = xmalloc (sec_name_len + 1); 17300 memcpy (sec_name, prefix, prefix_len); 17301 memcpy (sec_name + prefix_len, text_name, text_len); 17302 sec_name[prefix_len + text_len] = '\0'; 17303 17304 flags = SHF_ALLOC; 17305 linkonce = 0; 17306 group_name = 0; 17307 17308 /* Handle COMDAT group. */ 17309 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) 17310 { 17311 group_name = elf_group_name (text_seg); 17312 if (group_name == NULL) 17313 { 17314 as_bad ("Group section `%s' has no group signature", 17315 segment_name (text_seg)); 17316 ignore_rest_of_line (); 17317 return; 17318 } 17319 flags |= SHF_GROUP; 17320 linkonce = 1; 17321 } 17322 17323 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); 17324 17325 /* Set the setion link for index tables. */ 17326 if (idx) 17327 elf_linked_to_section (now_seg) = text_seg; 17328} 17329 17330 17331/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional 17332 personality routine data. Returns zero, or the index table value for 17333 and inline entry. */ 17334 17335static valueT 17336create_unwind_entry (int have_data) 17337{ 17338 int size; 17339 addressT where; 17340 char *ptr; 17341 /* The current word of data. */ 17342 valueT data; 17343 /* The number of bytes left in this word. */ 17344 int n; 17345 17346 finish_unwind_opcodes (); 17347 17348 /* Remember the current text section. */ 17349 unwind.saved_seg = now_seg; 17350 unwind.saved_subseg = now_subseg; 17351 17352 start_unwind_section (now_seg, 0); 17353 17354 if (unwind.personality_routine == NULL) 17355 { 17356 if (unwind.personality_index == -2) 17357 { 17358 if (have_data) 17359 as_bad (_("handerdata in cantunwind frame")); 17360 return 1; /* EXIDX_CANTUNWIND. */ 17361 } 17362 17363 /* Use a default personality routine if none is specified. */ 17364 if (unwind.personality_index == -1) 17365 { 17366 if (unwind.opcode_count > 3) 17367 unwind.personality_index = 1; 17368 else 17369 unwind.personality_index = 0; 17370 } 17371 17372 /* Space for the personality routine entry. */ 17373 if (unwind.personality_index == 0) 17374 { 17375 if (unwind.opcode_count > 3) 17376 as_bad (_("too many unwind opcodes for personality routine 0")); 17377 17378 if (!have_data) 17379 { 17380 /* All the data is inline in the index table. */ 17381 data = 0x80; 17382 n = 3; 17383 while (unwind.opcode_count > 0) 17384 { 17385 unwind.opcode_count--; 17386 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17387 n--; 17388 } 17389 17390 /* Pad with "finish" opcodes. */ 17391 while (n--) 17392 data = (data << 8) | 0xb0; 17393 17394 return data; 17395 } 17396 size = 0; 17397 } 17398 else 17399 /* We get two opcodes "free" in the first word. */ 17400 size = unwind.opcode_count - 2; 17401 } 17402 else 17403 /* An extra byte is required for the opcode count. */ 17404 size = unwind.opcode_count + 1; 17405 17406 size = (size + 3) >> 2; 17407 if (size > 0xff) 17408 as_bad (_("too many unwind opcodes")); 17409 17410 frag_align (2, 0, 0); 17411 record_alignment (now_seg, 2); 17412 unwind.table_entry = expr_build_dot (); 17413 17414 /* Allocate the table entry. */ 17415 ptr = frag_more ((size << 2) + 4); 17416 memset(ptr, 0, (size << 2) + 4); 17417 where = frag_now_fix () - ((size << 2) + 4); 17418 17419 switch (unwind.personality_index) 17420 { 17421 case -1: 17422 /* ??? Should this be a PLT generating relocation? */ 17423 /* Custom personality routine. */ 17424 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, 17425 BFD_RELOC_ARM_PREL31); 17426 17427 where += 4; 17428 ptr += 4; 17429 17430 /* Set the first byte to the number of additional words. */ 17431 data = size - 1; 17432 n = 3; 17433 break; 17434 17435 /* ABI defined personality routines. */ 17436 case 0: 17437 /* Three opcodes bytes are packed into the first word. */ 17438 data = 0x80; 17439 n = 3; 17440 break; 17441 17442 case 1: 17443 case 2: 17444 /* The size and first two opcode bytes go in the first word. */ 17445 data = ((0x80 + unwind.personality_index) << 8) | size; 17446 n = 2; 17447 break; 17448 17449 default: 17450 /* Should never happen. */ 17451 abort (); 17452 } 17453 17454 /* Pack the opcodes into words (MSB first), reversing the list at the same 17455 time. */ 17456 while (unwind.opcode_count > 0) 17457 { 17458 if (n == 0) 17459 { 17460 md_number_to_chars (ptr, data, 4); 17461 ptr += 4; 17462 n = 4; 17463 data = 0; 17464 } 17465 unwind.opcode_count--; 17466 n--; 17467 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17468 } 17469 17470 /* Finish off the last word. */ 17471 if (n < 4) 17472 { 17473 /* Pad with "finish" opcodes. */ 17474 while (n--) 17475 data = (data << 8) | 0xb0; 17476 17477 md_number_to_chars (ptr, data, 4); 17478 } 17479 17480 if (!have_data) 17481 { 17482 /* Add an empty descriptor if there is no user-specified data. */ 17483 ptr = frag_more (4); 17484 md_number_to_chars (ptr, 0, 4); 17485 } 17486 17487 return 0; 17488} 17489 17490 17491/* Initialize the DWARF-2 unwind information for this procedure. */ 17492 17493void 17494tc_arm_frame_initial_instructions (void) 17495{ 17496 cfi_add_CFA_def_cfa (REG_SP, 0); 17497} 17498#endif /* OBJ_ELF */ 17499 17500/* Convert REGNAME to a DWARF-2 register number. */ 17501 17502int 17503tc_arm_regname_to_dw2regnum (char *regname) 17504{ 17505 int reg = arm_reg_parse (®name, REG_TYPE_RN); 17506 17507 if (reg == FAIL) 17508 return -1; 17509 17510 return reg; 17511} 17512 17513#ifdef TE_PE 17514void 17515tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 17516{ 17517 expressionS expr; 17518 17519 expr.X_op = O_secrel; 17520 expr.X_add_symbol = symbol; 17521 expr.X_add_number = 0; 17522 emit_expr (&expr, size); 17523} 17524#endif 17525 17526/* MD interface: Symbol and relocation handling. */ 17527 17528/* Return the address within the segment that a PC-relative fixup is 17529 relative to. For ARM, PC-relative fixups applied to instructions 17530 are generally relative to the location of the fixup plus 8 bytes. 17531 Thumb branches are offset by 4, and Thumb loads relative to PC 17532 require special handling. */ 17533 17534long 17535md_pcrel_from_section (fixS * fixP, segT seg) 17536{ 17537 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; 17538 17539 /* If this is pc-relative and we are going to emit a relocation 17540 then we just want to put out any pipeline compensation that the linker 17541 will need. Otherwise we want to use the calculated base. 17542 For WinCE we skip the bias for externals as well, since this 17543 is how the MS ARM-CE assembler behaves and we want to be compatible. */ 17544 if (fixP->fx_pcrel 17545 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) 17546 || (arm_force_relocation (fixP) 17547#ifdef TE_WINCE 17548 && !S_IS_EXTERNAL (fixP->fx_addsy) 17549#endif 17550 ))) 17551 base = 0; 17552 17553 switch (fixP->fx_r_type) 17554 { 17555 /* PC relative addressing on the Thumb is slightly odd as the 17556 bottom two bits of the PC are forced to zero for the 17557 calculation. This happens *after* application of the 17558 pipeline offset. However, Thumb adrl already adjusts for 17559 this, so we need not do it again. */ 17560 case BFD_RELOC_ARM_THUMB_ADD: 17561 return base & ~3; 17562 17563 case BFD_RELOC_ARM_THUMB_OFFSET: 17564 case BFD_RELOC_ARM_T32_OFFSET_IMM: 17565 case BFD_RELOC_ARM_T32_ADD_PC12: 17566 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 17567 return (base + 4) & ~3; 17568 17569 /* Thumb branches are simply offset by +4. */ 17570 case BFD_RELOC_THUMB_PCREL_BRANCH7: 17571 case BFD_RELOC_THUMB_PCREL_BRANCH9: 17572 case BFD_RELOC_THUMB_PCREL_BRANCH12: 17573 case BFD_RELOC_THUMB_PCREL_BRANCH20: 17574 case BFD_RELOC_THUMB_PCREL_BRANCH23: 17575 case BFD_RELOC_THUMB_PCREL_BRANCH25: 17576 case BFD_RELOC_THUMB_PCREL_BLX: 17577 return base + 4; 17578 17579 /* ARM mode branches are offset by +8. However, the Windows CE 17580 loader expects the relocation not to take this into account. */ 17581 case BFD_RELOC_ARM_PCREL_BRANCH: 17582 case BFD_RELOC_ARM_PCREL_CALL: 17583 case BFD_RELOC_ARM_PCREL_JUMP: 17584 case BFD_RELOC_ARM_PCREL_BLX: 17585 case BFD_RELOC_ARM_PLT32: 17586#ifdef TE_WINCE 17587 /* When handling fixups immediately, because we have already 17588 discovered the value of a symbol, or the address of the frag involved 17589 we must account for the offset by +8, as the OS loader will never see the reloc. 17590 see fixup_segment() in write.c 17591 The S_IS_EXTERNAL test handles the case of global symbols. 17592 Those need the calculated base, not just the pipe compensation the linker will need. */ 17593 if (fixP->fx_pcrel 17594 && fixP->fx_addsy != NULL 17595 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 17596 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) 17597 return base + 8; 17598 return base; 17599#else 17600 return base + 8; 17601#endif 17602 17603 /* ARM mode loads relative to PC are also offset by +8. Unlike 17604 branches, the Windows CE loader *does* expect the relocation 17605 to take this into account. */ 17606 case BFD_RELOC_ARM_OFFSET_IMM: 17607 case BFD_RELOC_ARM_OFFSET_IMM8: 17608 case BFD_RELOC_ARM_HWLITERAL: 17609 case BFD_RELOC_ARM_LITERAL: 17610 case BFD_RELOC_ARM_CP_OFF_IMM: 17611 return base + 8; 17612 17613 17614 /* Other PC-relative relocations are un-offset. */ 17615 default: 17616 return base; 17617 } 17618} 17619 17620/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. 17621 Otherwise we have no need to default values of symbols. */ 17622 17623symbolS * 17624md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 17625{ 17626#ifdef OBJ_ELF 17627 if (name[0] == '_' && name[1] == 'G' 17628 && streq (name, GLOBAL_OFFSET_TABLE_NAME)) 17629 { 17630 if (!GOT_symbol) 17631 { 17632 if (symbol_find (name)) 17633 as_bad ("GOT already in the symbol table"); 17634 17635 GOT_symbol = symbol_new (name, undefined_section, 17636 (valueT) 0, & zero_address_frag); 17637 } 17638 17639 return GOT_symbol; 17640 } 17641#endif 17642 17643 return 0; 17644} 17645 17646/* Subroutine of md_apply_fix. Check to see if an immediate can be 17647 computed as two separate immediate values, added together. We 17648 already know that this value cannot be computed by just one ARM 17649 instruction. */ 17650 17651static unsigned int 17652validate_immediate_twopart (unsigned int val, 17653 unsigned int * highpart) 17654{ 17655 unsigned int a; 17656 unsigned int i; 17657 17658 for (i = 0; i < 32; i += 2) 17659 if (((a = rotate_left (val, i)) & 0xff) != 0) 17660 { 17661 if (a & 0xff00) 17662 { 17663 if (a & ~ 0xffff) 17664 continue; 17665 * highpart = (a >> 8) | ((i + 24) << 7); 17666 } 17667 else if (a & 0xff0000) 17668 { 17669 if (a & 0xff000000) 17670 continue; 17671 * highpart = (a >> 16) | ((i + 16) << 7); 17672 } 17673 else 17674 { 17675 assert (a & 0xff000000); 17676 * highpart = (a >> 24) | ((i + 8) << 7); 17677 } 17678 17679 return (a & 0xff) | (i << 7); 17680 } 17681 17682 return FAIL; 17683} 17684 17685static int 17686validate_offset_imm (unsigned int val, int hwse) 17687{ 17688 if ((hwse && val > 255) || val > 4095) 17689 return FAIL; 17690 return val; 17691} 17692 17693/* Subroutine of md_apply_fix. Do those data_ops which can take a 17694 negative immediate constant by altering the instruction. A bit of 17695 a hack really. 17696 MOV <-> MVN 17697 AND <-> BIC 17698 ADC <-> SBC 17699 by inverting the second operand, and 17700 ADD <-> SUB 17701 CMP <-> CMN 17702 by negating the second operand. */ 17703 17704static int 17705negate_data_op (unsigned long * instruction, 17706 unsigned long value) 17707{ 17708 int op, new_inst; 17709 unsigned long negated, inverted; 17710 17711 negated = encode_arm_immediate (-value); 17712 inverted = encode_arm_immediate (~value); 17713 17714 op = (*instruction >> DATA_OP_SHIFT) & 0xf; 17715 switch (op) 17716 { 17717 /* First negates. */ 17718 case OPCODE_SUB: /* ADD <-> SUB */ 17719 new_inst = OPCODE_ADD; 17720 value = negated; 17721 break; 17722 17723 case OPCODE_ADD: 17724 new_inst = OPCODE_SUB; 17725 value = negated; 17726 break; 17727 17728 case OPCODE_CMP: /* CMP <-> CMN */ 17729 new_inst = OPCODE_CMN; 17730 value = negated; 17731 break; 17732 17733 case OPCODE_CMN: 17734 new_inst = OPCODE_CMP; 17735 value = negated; 17736 break; 17737 17738 /* Now Inverted ops. */ 17739 case OPCODE_MOV: /* MOV <-> MVN */ 17740 new_inst = OPCODE_MVN; 17741 value = inverted; 17742 break; 17743 17744 case OPCODE_MVN: 17745 new_inst = OPCODE_MOV; 17746 value = inverted; 17747 break; 17748 17749 case OPCODE_AND: /* AND <-> BIC */ 17750 new_inst = OPCODE_BIC; 17751 value = inverted; 17752 break; 17753 17754 case OPCODE_BIC: 17755 new_inst = OPCODE_AND; 17756 value = inverted; 17757 break; 17758 17759 case OPCODE_ADC: /* ADC <-> SBC */ 17760 new_inst = OPCODE_SBC; 17761 value = inverted; 17762 break; 17763 17764 case OPCODE_SBC: 17765 new_inst = OPCODE_ADC; 17766 value = inverted; 17767 break; 17768 17769 /* We cannot do anything. */ 17770 default: 17771 return FAIL; 17772 } 17773 17774 if (value == (unsigned) FAIL) 17775 return FAIL; 17776 17777 *instruction &= OPCODE_MASK; 17778 *instruction |= new_inst << DATA_OP_SHIFT; 17779 return value; 17780} 17781 17782/* Like negate_data_op, but for Thumb-2. */ 17783 17784static unsigned int 17785thumb32_negate_data_op (offsetT *instruction, unsigned int value) 17786{ 17787 int op, new_inst; 17788 int rd; 17789 unsigned int negated, inverted; 17790 17791 negated = encode_thumb32_immediate (-value); 17792 inverted = encode_thumb32_immediate (~value); 17793 17794 rd = (*instruction >> 8) & 0xf; 17795 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; 17796 switch (op) 17797 { 17798 /* ADD <-> SUB. Includes CMP <-> CMN. */ 17799 case T2_OPCODE_SUB: 17800 new_inst = T2_OPCODE_ADD; 17801 value = negated; 17802 break; 17803 17804 case T2_OPCODE_ADD: 17805 new_inst = T2_OPCODE_SUB; 17806 value = negated; 17807 break; 17808 17809 /* ORR <-> ORN. Includes MOV <-> MVN. */ 17810 case T2_OPCODE_ORR: 17811 new_inst = T2_OPCODE_ORN; 17812 value = inverted; 17813 break; 17814 17815 case T2_OPCODE_ORN: 17816 new_inst = T2_OPCODE_ORR; 17817 value = inverted; 17818 break; 17819 17820 /* AND <-> BIC. TST has no inverted equivalent. */ 17821 case T2_OPCODE_AND: 17822 new_inst = T2_OPCODE_BIC; 17823 if (rd == 15) 17824 value = FAIL; 17825 else 17826 value = inverted; 17827 break; 17828 17829 case T2_OPCODE_BIC: 17830 new_inst = T2_OPCODE_AND; 17831 value = inverted; 17832 break; 17833 17834 /* ADC <-> SBC */ 17835 case T2_OPCODE_ADC: 17836 new_inst = T2_OPCODE_SBC; 17837 value = inverted; 17838 break; 17839 17840 case T2_OPCODE_SBC: 17841 new_inst = T2_OPCODE_ADC; 17842 value = inverted; 17843 break; 17844 17845 /* We cannot do anything. */ 17846 default: 17847 return FAIL; 17848 } 17849 17850 if (value == (unsigned int)FAIL) 17851 return FAIL; 17852 17853 *instruction &= T2_OPCODE_MASK; 17854 *instruction |= new_inst << T2_DATA_OP_SHIFT; 17855 return value; 17856} 17857 17858/* Read a 32-bit thumb instruction from buf. */ 17859static unsigned long 17860get_thumb32_insn (char * buf) 17861{ 17862 unsigned long insn; 17863 insn = md_chars_to_number (buf, THUMB_SIZE) << 16; 17864 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 17865 17866 return insn; 17867} 17868 17869 17870/* We usually want to set the low bit on the address of thumb function 17871 symbols. In particular .word foo - . should have the low bit set. 17872 Generic code tries to fold the difference of two symbols to 17873 a constant. Prevent this and force a relocation when the first symbols 17874 is a thumb function. */ 17875int 17876arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) 17877{ 17878 if (op == O_subtract 17879 && l->X_op == O_symbol 17880 && r->X_op == O_symbol 17881 && THUMB_IS_FUNC (l->X_add_symbol)) 17882 { 17883 l->X_op = O_subtract; 17884 l->X_op_symbol = r->X_add_symbol; 17885 l->X_add_number -= r->X_add_number; 17886 return 1; 17887 } 17888 /* Process as normal. */ 17889 return 0; 17890} 17891 17892void 17893md_apply_fix (fixS * fixP, 17894 valueT * valP, 17895 segT seg) 17896{ 17897 offsetT value = * valP; 17898 offsetT newval; 17899 unsigned int newimm; 17900 unsigned long temp; 17901 int sign; 17902 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; 17903 17904 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); 17905 17906 /* Note whether this will delete the relocation. */ 17907 17908 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 17909 fixP->fx_done = 1; 17910 17911 /* On a 64-bit host, silently truncate 'value' to 32 bits for 17912 consistency with the behavior on 32-bit hosts. Remember value 17913 for emit_reloc. */ 17914 value &= 0xffffffff; 17915 value ^= 0x80000000; 17916 value -= 0x80000000; 17917 17918 *valP = value; 17919 fixP->fx_addnumber = value; 17920 17921 /* Same treatment for fixP->fx_offset. */ 17922 fixP->fx_offset &= 0xffffffff; 17923 fixP->fx_offset ^= 0x80000000; 17924 fixP->fx_offset -= 0x80000000; 17925 17926 switch (fixP->fx_r_type) 17927 { 17928 case BFD_RELOC_NONE: 17929 /* This will need to go in the object file. */ 17930 fixP->fx_done = 0; 17931 break; 17932 17933 case BFD_RELOC_ARM_IMMEDIATE: 17934 /* We claim that this fixup has been processed here, 17935 even if in fact we generate an error because we do 17936 not have a reloc for it, so tc_gen_reloc will reject it. */ 17937 fixP->fx_done = 1; 17938 17939 if (fixP->fx_addsy 17940 && ! S_IS_DEFINED (fixP->fx_addsy)) 17941 { 17942 as_bad_where (fixP->fx_file, fixP->fx_line, 17943 _("undefined symbol %s used as an immediate value"), 17944 S_GET_NAME (fixP->fx_addsy)); 17945 break; 17946 } 17947 17948 newimm = encode_arm_immediate (value); 17949 temp = md_chars_to_number (buf, INSN_SIZE); 17950 17951 /* If the instruction will fail, see if we can fix things up by 17952 changing the opcode. */ 17953 if (newimm == (unsigned int) FAIL 17954 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) 17955 { 17956 as_bad_where (fixP->fx_file, fixP->fx_line, 17957 _("invalid constant (%lx) after fixup"), 17958 (unsigned long) value); 17959 break; 17960 } 17961 17962 newimm |= (temp & 0xfffff000); 17963 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 17964 break; 17965 17966 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 17967 { 17968 unsigned int highpart = 0; 17969 unsigned int newinsn = 0xe1a00000; /* nop. */ 17970 17971 newimm = encode_arm_immediate (value); 17972 temp = md_chars_to_number (buf, INSN_SIZE); 17973 17974 /* If the instruction will fail, see if we can fix things up by 17975 changing the opcode. */ 17976 if (newimm == (unsigned int) FAIL 17977 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) 17978 { 17979 /* No ? OK - try using two ADD instructions to generate 17980 the value. */ 17981 newimm = validate_immediate_twopart (value, & highpart); 17982 17983 /* Yes - then make sure that the second instruction is 17984 also an add. */ 17985 if (newimm != (unsigned int) FAIL) 17986 newinsn = temp; 17987 /* Still No ? Try using a negated value. */ 17988 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) 17989 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; 17990 /* Otherwise - give up. */ 17991 else 17992 { 17993 as_bad_where (fixP->fx_file, fixP->fx_line, 17994 _("unable to compute ADRL instructions for PC offset of 0x%lx"), 17995 (long) value); 17996 break; 17997 } 17998 17999 /* Replace the first operand in the 2nd instruction (which 18000 is the PC) with the destination register. We have 18001 already added in the PC in the first instruction and we 18002 do not want to do it again. */ 18003 newinsn &= ~ 0xf0000; 18004 newinsn |= ((newinsn & 0x0f000) << 4); 18005 } 18006 18007 newimm |= (temp & 0xfffff000); 18008 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 18009 18010 highpart |= (newinsn & 0xfffff000); 18011 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); 18012 } 18013 break; 18014 18015 case BFD_RELOC_ARM_OFFSET_IMM: 18016 if (!fixP->fx_done && seg->use_rela_p) 18017 value = 0; 18018 18019 case BFD_RELOC_ARM_LITERAL: 18020 sign = value >= 0; 18021 18022 if (value < 0) 18023 value = - value; 18024 18025 if (validate_offset_imm (value, 0) == FAIL) 18026 { 18027 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) 18028 as_bad_where (fixP->fx_file, fixP->fx_line, 18029 _("invalid literal constant: pool needs to be closer")); 18030 else 18031 as_bad_where (fixP->fx_file, fixP->fx_line, 18032 _("bad immediate value for offset (%ld)"), 18033 (long) value); 18034 break; 18035 } 18036 18037 newval = md_chars_to_number (buf, INSN_SIZE); 18038 newval &= 0xff7ff000; 18039 newval |= value | (sign ? INDEX_UP : 0); 18040 md_number_to_chars (buf, newval, INSN_SIZE); 18041 break; 18042 18043 case BFD_RELOC_ARM_OFFSET_IMM8: 18044 case BFD_RELOC_ARM_HWLITERAL: 18045 sign = value >= 0; 18046 18047 if (value < 0) 18048 value = - value; 18049 18050 if (validate_offset_imm (value, 1) == FAIL) 18051 { 18052 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) 18053 as_bad_where (fixP->fx_file, fixP->fx_line, 18054 _("invalid literal constant: pool needs to be closer")); 18055 else 18056 as_bad (_("bad immediate value for 8-bit offset (%ld)"), 18057 (long) value); 18058 break; 18059 } 18060 18061 newval = md_chars_to_number (buf, INSN_SIZE); 18062 newval &= 0xff7ff0f0; 18063 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); 18064 md_number_to_chars (buf, newval, INSN_SIZE); 18065 break; 18066 18067 case BFD_RELOC_ARM_T32_OFFSET_U8: 18068 if (value < 0 || value > 1020 || value % 4 != 0) 18069 as_bad_where (fixP->fx_file, fixP->fx_line, 18070 _("bad immediate value for offset (%ld)"), (long) value); 18071 value /= 4; 18072 18073 newval = md_chars_to_number (buf+2, THUMB_SIZE); 18074 newval |= value; 18075 md_number_to_chars (buf+2, newval, THUMB_SIZE); 18076 break; 18077 18078 case BFD_RELOC_ARM_T32_OFFSET_IMM: 18079 /* This is a complicated relocation used for all varieties of Thumb32 18080 load/store instruction with immediate offset: 18081 18082 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, 18083 *4, optional writeback(W) 18084 (doubleword load/store) 18085 18086 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel 18087 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit 18088 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) 18089 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit 18090 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit 18091 18092 Uppercase letters indicate bits that are already encoded at 18093 this point. Lowercase letters are our problem. For the 18094 second block of instructions, the secondary opcode nybble 18095 (bits 8..11) is present, and bit 23 is zero, even if this is 18096 a PC-relative operation. */ 18097 newval = md_chars_to_number (buf, THUMB_SIZE); 18098 newval <<= 16; 18099 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); 18100 18101 if ((newval & 0xf0000000) == 0xe0000000) 18102 { 18103 /* Doubleword load/store: 8-bit offset, scaled by 4. */ 18104 if (value >= 0) 18105 newval |= (1 << 23); 18106 else 18107 value = -value; 18108 if (value % 4 != 0) 18109 { 18110 as_bad_where (fixP->fx_file, fixP->fx_line, 18111 _("offset not a multiple of 4")); 18112 break; 18113 } 18114 value /= 4; 18115 if (value > 0xff) 18116 { 18117 as_bad_where (fixP->fx_file, fixP->fx_line, 18118 _("offset out of range")); 18119 break; 18120 } 18121 newval &= ~0xff; 18122 } 18123 else if ((newval & 0x000f0000) == 0x000f0000) 18124 { 18125 /* PC-relative, 12-bit offset. */ 18126 if (value >= 0) 18127 newval |= (1 << 23); 18128 else 18129 value = -value; 18130 if (value > 0xfff) 18131 { 18132 as_bad_where (fixP->fx_file, fixP->fx_line, 18133 _("offset out of range")); 18134 break; 18135 } 18136 newval &= ~0xfff; 18137 } 18138 else if ((newval & 0x00000100) == 0x00000100) 18139 { 18140 /* Writeback: 8-bit, +/- offset. */ 18141 if (value >= 0) 18142 newval |= (1 << 9); 18143 else 18144 value = -value; 18145 if (value > 0xff) 18146 { 18147 as_bad_where (fixP->fx_file, fixP->fx_line, 18148 _("offset out of range")); 18149 break; 18150 } 18151 newval &= ~0xff; 18152 } 18153 else if ((newval & 0x00000f00) == 0x00000e00) 18154 { 18155 /* T-instruction: positive 8-bit offset. */ 18156 if (value < 0 || value > 0xff) 18157 { 18158 as_bad_where (fixP->fx_file, fixP->fx_line, 18159 _("offset out of range")); 18160 break; 18161 } 18162 newval &= ~0xff; 18163 newval |= value; 18164 } 18165 else 18166 { 18167 /* Positive 12-bit or negative 8-bit offset. */ 18168 int limit; 18169 if (value >= 0) 18170 { 18171 newval |= (1 << 23); 18172 limit = 0xfff; 18173 } 18174 else 18175 { 18176 value = -value; 18177 limit = 0xff; 18178 } 18179 if (value > limit) 18180 { 18181 as_bad_where (fixP->fx_file, fixP->fx_line, 18182 _("offset out of range")); 18183 break; 18184 } 18185 newval &= ~limit; 18186 } 18187 18188 newval |= value; 18189 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); 18190 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); 18191 break; 18192 18193 case BFD_RELOC_ARM_SHIFT_IMM: 18194 newval = md_chars_to_number (buf, INSN_SIZE); 18195 if (((unsigned long) value) > 32 18196 || (value == 32 18197 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) 18198 { 18199 as_bad_where (fixP->fx_file, fixP->fx_line, 18200 _("shift expression is too large")); 18201 break; 18202 } 18203 18204 if (value == 0) 18205 /* Shifts of zero must be done as lsl. */ 18206 newval &= ~0x60; 18207 else if (value == 32) 18208 value = 0; 18209 newval &= 0xfffff07f; 18210 newval |= (value & 0x1f) << 7; 18211 md_number_to_chars (buf, newval, INSN_SIZE); 18212 break; 18213 18214 case BFD_RELOC_ARM_T32_IMMEDIATE: 18215 case BFD_RELOC_ARM_T32_ADD_IMM: 18216 case BFD_RELOC_ARM_T32_IMM12: 18217 case BFD_RELOC_ARM_T32_ADD_PC12: 18218 /* We claim that this fixup has been processed here, 18219 even if in fact we generate an error because we do 18220 not have a reloc for it, so tc_gen_reloc will reject it. */ 18221 fixP->fx_done = 1; 18222 18223 if (fixP->fx_addsy 18224 && ! S_IS_DEFINED (fixP->fx_addsy)) 18225 { 18226 as_bad_where (fixP->fx_file, fixP->fx_line, 18227 _("undefined symbol %s used as an immediate value"), 18228 S_GET_NAME (fixP->fx_addsy)); 18229 break; 18230 } 18231 18232 newval = md_chars_to_number (buf, THUMB_SIZE); 18233 newval <<= 16; 18234 newval |= md_chars_to_number (buf+2, THUMB_SIZE); 18235 18236 newimm = FAIL; 18237 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 18238 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18239 { 18240 newimm = encode_thumb32_immediate (value); 18241 if (newimm == (unsigned int) FAIL) 18242 newimm = thumb32_negate_data_op (&newval, value); 18243 } 18244 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE 18245 && newimm == (unsigned int) FAIL) 18246 { 18247 /* Turn add/sum into addw/subw. */ 18248 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18249 newval = (newval & 0xfeffffff) | 0x02000000; 18250 18251 /* 12 bit immediate for addw/subw. */ 18252 if (value < 0) 18253 { 18254 value = -value; 18255 newval ^= 0x00a00000; 18256 } 18257 if (value > 0xfff) 18258 newimm = (unsigned int) FAIL; 18259 else 18260 newimm = value; 18261 } 18262 18263 if (newimm == (unsigned int)FAIL) 18264 { 18265 as_bad_where (fixP->fx_file, fixP->fx_line, 18266 _("invalid constant (%lx) after fixup"), 18267 (unsigned long) value); 18268 break; 18269 } 18270 18271 newval |= (newimm & 0x800) << 15; 18272 newval |= (newimm & 0x700) << 4; 18273 newval |= (newimm & 0x0ff); 18274 18275 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); 18276 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); 18277 break; 18278 18279 case BFD_RELOC_ARM_SMC: 18280 if (((unsigned long) value) > 0xffff) 18281 as_bad_where (fixP->fx_file, fixP->fx_line, 18282 _("invalid smc expression")); 18283 newval = md_chars_to_number (buf, INSN_SIZE); 18284 newval |= (value & 0xf) | ((value & 0xfff0) << 4); 18285 md_number_to_chars (buf, newval, INSN_SIZE); 18286 break; 18287 18288 case BFD_RELOC_ARM_SWI: 18289 if (fixP->tc_fix_data != 0) 18290 { 18291 if (((unsigned long) value) > 0xff) 18292 as_bad_where (fixP->fx_file, fixP->fx_line, 18293 _("invalid swi expression")); 18294 newval = md_chars_to_number (buf, THUMB_SIZE); 18295 newval |= value; 18296 md_number_to_chars (buf, newval, THUMB_SIZE); 18297 } 18298 else 18299 { 18300 if (((unsigned long) value) > 0x00ffffff) 18301 as_bad_where (fixP->fx_file, fixP->fx_line, 18302 _("invalid swi expression")); 18303 newval = md_chars_to_number (buf, INSN_SIZE); 18304 newval |= value; 18305 md_number_to_chars (buf, newval, INSN_SIZE); 18306 } 18307 break; 18308 18309 case BFD_RELOC_ARM_MULTI: 18310 if (((unsigned long) value) > 0xffff) 18311 as_bad_where (fixP->fx_file, fixP->fx_line, 18312 _("invalid expression in load/store multiple")); 18313 newval = value | md_chars_to_number (buf, INSN_SIZE); 18314 md_number_to_chars (buf, newval, INSN_SIZE); 18315 break; 18316 18317#ifdef OBJ_ELF 18318 case BFD_RELOC_ARM_PCREL_CALL: 18319 newval = md_chars_to_number (buf, INSN_SIZE); 18320 if ((newval & 0xf0000000) == 0xf0000000) 18321 temp = 1; 18322 else 18323 temp = 3; 18324 goto arm_branch_common; 18325 18326 case BFD_RELOC_ARM_PCREL_JUMP: 18327 case BFD_RELOC_ARM_PLT32: 18328#endif 18329 case BFD_RELOC_ARM_PCREL_BRANCH: 18330 temp = 3; 18331 goto arm_branch_common; 18332 18333 case BFD_RELOC_ARM_PCREL_BLX: 18334 temp = 1; 18335 arm_branch_common: 18336 /* We are going to store value (shifted right by two) in the 18337 instruction, in a 24 bit, signed field. Bits 26 through 32 either 18338 all clear or all set and bit 0 must be clear. For B/BL bit 1 must 18339 also be be clear. */ 18340 if (value & temp) 18341 as_bad_where (fixP->fx_file, fixP->fx_line, 18342 _("misaligned branch destination")); 18343 if ((value & (offsetT)0xfe000000) != (offsetT)0 18344 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) 18345 as_bad_where (fixP->fx_file, fixP->fx_line, 18346 _("branch out of range")); 18347 18348 if (fixP->fx_done || !seg->use_rela_p) 18349 { 18350 newval = md_chars_to_number (buf, INSN_SIZE); 18351 newval |= (value >> 2) & 0x00ffffff; 18352 /* Set the H bit on BLX instructions. */ 18353 if (temp == 1) 18354 { 18355 if (value & 2) 18356 newval |= 0x01000000; 18357 else 18358 newval &= ~0x01000000; 18359 } 18360 md_number_to_chars (buf, newval, INSN_SIZE); 18361 } 18362 break; 18363 18364 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ 18365 /* CBZ can only branch forward. */ 18366 18367 /* Attempts to use CBZ to branch to the next instruction 18368 (which, strictly speaking, are prohibited) will be turned into 18369 no-ops. 18370 18371 FIXME: It may be better to remove the instruction completely and 18372 perform relaxation. */ 18373 if (value == -2) 18374 { 18375 newval = md_chars_to_number (buf, THUMB_SIZE); 18376 newval = 0xbf00; /* NOP encoding T1 */ 18377 md_number_to_chars (buf, newval, THUMB_SIZE); 18378 } 18379 else 18380 { 18381 if (value & ~0x7e) 18382 as_bad_where (fixP->fx_file, fixP->fx_line, 18383 _("branch out of range")); 18384 18385 if (fixP->fx_done || !seg->use_rela_p) 18386 { 18387 newval = md_chars_to_number (buf, THUMB_SIZE); 18388 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); 18389 md_number_to_chars (buf, newval, THUMB_SIZE); 18390 } 18391 } 18392 break; 18393 18394 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ 18395 if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) 18396 as_bad_where (fixP->fx_file, fixP->fx_line, 18397 _("branch out of range")); 18398 18399 if (fixP->fx_done || !seg->use_rela_p) 18400 { 18401 newval = md_chars_to_number (buf, THUMB_SIZE); 18402 newval |= (value & 0x1ff) >> 1; 18403 md_number_to_chars (buf, newval, THUMB_SIZE); 18404 } 18405 break; 18406 18407 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ 18408 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) 18409 as_bad_where (fixP->fx_file, fixP->fx_line, 18410 _("branch out of range")); 18411 18412 if (fixP->fx_done || !seg->use_rela_p) 18413 { 18414 newval = md_chars_to_number (buf, THUMB_SIZE); 18415 newval |= (value & 0xfff) >> 1; 18416 md_number_to_chars (buf, newval, THUMB_SIZE); 18417 } 18418 break; 18419 18420 case BFD_RELOC_THUMB_PCREL_BRANCH20: 18421 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) 18422 as_bad_where (fixP->fx_file, fixP->fx_line, 18423 _("conditional branch out of range")); 18424 18425 if (fixP->fx_done || !seg->use_rela_p) 18426 { 18427 offsetT newval2; 18428 addressT S, J1, J2, lo, hi; 18429 18430 S = (value & 0x00100000) >> 20; 18431 J2 = (value & 0x00080000) >> 19; 18432 J1 = (value & 0x00040000) >> 18; 18433 hi = (value & 0x0003f000) >> 12; 18434 lo = (value & 0x00000ffe) >> 1; 18435 18436 newval = md_chars_to_number (buf, THUMB_SIZE); 18437 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18438 newval |= (S << 10) | hi; 18439 newval2 |= (J1 << 13) | (J2 << 11) | lo; 18440 md_number_to_chars (buf, newval, THUMB_SIZE); 18441 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18442 } 18443 break; 18444 18445 case BFD_RELOC_THUMB_PCREL_BLX: 18446 case BFD_RELOC_THUMB_PCREL_BRANCH23: 18447 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) 18448 as_bad_where (fixP->fx_file, fixP->fx_line, 18449 _("branch out of range")); 18450 18451 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) 18452 /* For a BLX instruction, make sure that the relocation is rounded up 18453 to a word boundary. This follows the semantics of the instruction 18454 which specifies that bit 1 of the target address will come from bit 18455 1 of the base address. */ 18456 value = (value + 1) & ~ 1; 18457 18458 if (fixP->fx_done || !seg->use_rela_p) 18459 { 18460 offsetT newval2; 18461 18462 newval = md_chars_to_number (buf, THUMB_SIZE); 18463 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18464 newval |= (value & 0x7fffff) >> 12; 18465 newval2 |= (value & 0xfff) >> 1; 18466 md_number_to_chars (buf, newval, THUMB_SIZE); 18467 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18468 } 18469 break; 18470 18471 case BFD_RELOC_THUMB_PCREL_BRANCH25: 18472 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) 18473 as_bad_where (fixP->fx_file, fixP->fx_line, 18474 _("branch out of range")); 18475 18476 if (fixP->fx_done || !seg->use_rela_p) 18477 { 18478 offsetT newval2; 18479 addressT S, I1, I2, lo, hi; 18480 18481 S = (value & 0x01000000) >> 24; 18482 I1 = (value & 0x00800000) >> 23; 18483 I2 = (value & 0x00400000) >> 22; 18484 hi = (value & 0x003ff000) >> 12; 18485 lo = (value & 0x00000ffe) >> 1; 18486 18487 I1 = !(I1 ^ S); 18488 I2 = !(I2 ^ S); 18489 18490 newval = md_chars_to_number (buf, THUMB_SIZE); 18491 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18492 newval |= (S << 10) | hi; 18493 newval2 |= (I1 << 13) | (I2 << 11) | lo; 18494 md_number_to_chars (buf, newval, THUMB_SIZE); 18495 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18496 } 18497 break; 18498 18499 case BFD_RELOC_8: 18500 if (fixP->fx_done || !seg->use_rela_p) 18501 md_number_to_chars (buf, value, 1); 18502 break; 18503 18504 case BFD_RELOC_16: 18505 if (fixP->fx_done || !seg->use_rela_p) 18506 md_number_to_chars (buf, value, 2); 18507 break; 18508 18509#ifdef OBJ_ELF 18510 case BFD_RELOC_ARM_TLS_GD32: 18511 case BFD_RELOC_ARM_TLS_LE32: 18512 case BFD_RELOC_ARM_TLS_IE32: 18513 case BFD_RELOC_ARM_TLS_LDM32: 18514 case BFD_RELOC_ARM_TLS_LDO32: 18515 S_SET_THREAD_LOCAL (fixP->fx_addsy); 18516 /* fall through */ 18517 18518 case BFD_RELOC_ARM_GOT32: 18519 case BFD_RELOC_ARM_GOTOFF: 18520 case BFD_RELOC_ARM_TARGET2: 18521 if (fixP->fx_done || !seg->use_rela_p) 18522 md_number_to_chars (buf, 0, 4); 18523 break; 18524#endif 18525 18526 case BFD_RELOC_RVA: 18527 case BFD_RELOC_32: 18528 case BFD_RELOC_ARM_TARGET1: 18529 case BFD_RELOC_ARM_ROSEGREL32: 18530 case BFD_RELOC_ARM_SBREL32: 18531 case BFD_RELOC_32_PCREL: 18532#ifdef TE_PE 18533 case BFD_RELOC_32_SECREL: 18534#endif 18535 if (fixP->fx_done || !seg->use_rela_p) 18536#ifdef TE_WINCE 18537 /* For WinCE we only do this for pcrel fixups. */ 18538 if (fixP->fx_done || fixP->fx_pcrel) 18539#endif 18540 md_number_to_chars (buf, value, 4); 18541 break; 18542 18543#ifdef OBJ_ELF 18544 case BFD_RELOC_ARM_PREL31: 18545 if (fixP->fx_done || !seg->use_rela_p) 18546 { 18547 newval = md_chars_to_number (buf, 4) & 0x80000000; 18548 if ((value ^ (value >> 1)) & 0x40000000) 18549 { 18550 as_bad_where (fixP->fx_file, fixP->fx_line, 18551 _("rel31 relocation overflow")); 18552 } 18553 newval |= value & 0x7fffffff; 18554 md_number_to_chars (buf, newval, 4); 18555 } 18556 break; 18557#endif 18558 18559 case BFD_RELOC_ARM_CP_OFF_IMM: 18560 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 18561 if (value < -1023 || value > 1023 || (value & 3)) 18562 as_bad_where (fixP->fx_file, fixP->fx_line, 18563 _("co-processor offset out of range")); 18564 cp_off_common: 18565 sign = value >= 0; 18566 if (value < 0) 18567 value = -value; 18568 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18569 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18570 newval = md_chars_to_number (buf, INSN_SIZE); 18571 else 18572 newval = get_thumb32_insn (buf); 18573 newval &= 0xff7fff00; 18574 newval |= (value >> 2) | (sign ? INDEX_UP : 0); 18575 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18576 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18577 md_number_to_chars (buf, newval, INSN_SIZE); 18578 else 18579 put_thumb32_insn (buf, newval); 18580 break; 18581 18582 case BFD_RELOC_ARM_CP_OFF_IMM_S2: 18583 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: 18584 if (value < -255 || value > 255) 18585 as_bad_where (fixP->fx_file, fixP->fx_line, 18586 _("co-processor offset out of range")); 18587 value *= 4; 18588 goto cp_off_common; 18589 18590 case BFD_RELOC_ARM_THUMB_OFFSET: 18591 newval = md_chars_to_number (buf, THUMB_SIZE); 18592 /* Exactly what ranges, and where the offset is inserted depends 18593 on the type of instruction, we can establish this from the 18594 top 4 bits. */ 18595 switch (newval >> 12) 18596 { 18597 case 4: /* PC load. */ 18598 /* Thumb PC loads are somewhat odd, bit 1 of the PC is 18599 forced to zero for these loads; md_pcrel_from has already 18600 compensated for this. */ 18601 if (value & 3) 18602 as_bad_where (fixP->fx_file, fixP->fx_line, 18603 _("invalid offset, target not word aligned (0x%08lX)"), 18604 (((unsigned long) fixP->fx_frag->fr_address 18605 + (unsigned long) fixP->fx_where) & ~3) 18606 + (unsigned long) value); 18607 18608 if (value & ~0x3fc) 18609 as_bad_where (fixP->fx_file, fixP->fx_line, 18610 _("invalid offset, value too big (0x%08lX)"), 18611 (long) value); 18612 18613 newval |= value >> 2; 18614 break; 18615 18616 case 9: /* SP load/store. */ 18617 if (value & ~0x3fc) 18618 as_bad_where (fixP->fx_file, fixP->fx_line, 18619 _("invalid offset, value too big (0x%08lX)"), 18620 (long) value); 18621 newval |= value >> 2; 18622 break; 18623 18624 case 6: /* Word load/store. */ 18625 if (value & ~0x7c) 18626 as_bad_where (fixP->fx_file, fixP->fx_line, 18627 _("invalid offset, value too big (0x%08lX)"), 18628 (long) value); 18629 newval |= value << 4; /* 6 - 2. */ 18630 break; 18631 18632 case 7: /* Byte load/store. */ 18633 if (value & ~0x1f) 18634 as_bad_where (fixP->fx_file, fixP->fx_line, 18635 _("invalid offset, value too big (0x%08lX)"), 18636 (long) value); 18637 newval |= value << 6; 18638 break; 18639 18640 case 8: /* Halfword load/store. */ 18641 if (value & ~0x3e) 18642 as_bad_where (fixP->fx_file, fixP->fx_line, 18643 _("invalid offset, value too big (0x%08lX)"), 18644 (long) value); 18645 newval |= value << 5; /* 6 - 1. */ 18646 break; 18647 18648 default: 18649 as_bad_where (fixP->fx_file, fixP->fx_line, 18650 "Unable to process relocation for thumb opcode: %lx", 18651 (unsigned long) newval); 18652 break; 18653 } 18654 md_number_to_chars (buf, newval, THUMB_SIZE); 18655 break; 18656 18657 case BFD_RELOC_ARM_THUMB_ADD: 18658 /* This is a complicated relocation, since we use it for all of 18659 the following immediate relocations: 18660 18661 3bit ADD/SUB 18662 8bit ADD/SUB 18663 9bit ADD/SUB SP word-aligned 18664 10bit ADD PC/SP word-aligned 18665 18666 The type of instruction being processed is encoded in the 18667 instruction field: 18668 18669 0x8000 SUB 18670 0x00F0 Rd 18671 0x000F Rs 18672 */ 18673 newval = md_chars_to_number (buf, THUMB_SIZE); 18674 { 18675 int rd = (newval >> 4) & 0xf; 18676 int rs = newval & 0xf; 18677 int subtract = !!(newval & 0x8000); 18678 18679 /* Check for HI regs, only very restricted cases allowed: 18680 Adjusting SP, and using PC or SP to get an address. */ 18681 if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) 18682 || (rs > 7 && rs != REG_SP && rs != REG_PC)) 18683 as_bad_where (fixP->fx_file, fixP->fx_line, 18684 _("invalid Hi register with immediate")); 18685 18686 /* If value is negative, choose the opposite instruction. */ 18687 if (value < 0) 18688 { 18689 value = -value; 18690 subtract = !subtract; 18691 if (value < 0) 18692 as_bad_where (fixP->fx_file, fixP->fx_line, 18693 _("immediate value out of range")); 18694 } 18695 18696 if (rd == REG_SP) 18697 { 18698 if (value & ~0x1fc) 18699 as_bad_where (fixP->fx_file, fixP->fx_line, 18700 _("invalid immediate for stack address calculation")); 18701 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; 18702 newval |= value >> 2; 18703 } 18704 else if (rs == REG_PC || rs == REG_SP) 18705 { 18706 if (subtract || value & ~0x3fc) 18707 as_bad_where (fixP->fx_file, fixP->fx_line, 18708 _("invalid immediate for address calculation (value = 0x%08lX)"), 18709 (unsigned long) value); 18710 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); 18711 newval |= rd << 8; 18712 newval |= value >> 2; 18713 } 18714 else if (rs == rd) 18715 { 18716 if (value & ~0xff) 18717 as_bad_where (fixP->fx_file, fixP->fx_line, 18718 _("immediate value out of range")); 18719 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; 18720 newval |= (rd << 8) | value; 18721 } 18722 else 18723 { 18724 if (value & ~0x7) 18725 as_bad_where (fixP->fx_file, fixP->fx_line, 18726 _("immediate value out of range")); 18727 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; 18728 newval |= rd | (rs << 3) | (value << 6); 18729 } 18730 } 18731 md_number_to_chars (buf, newval, THUMB_SIZE); 18732 break; 18733 18734 case BFD_RELOC_ARM_THUMB_IMM: 18735 newval = md_chars_to_number (buf, THUMB_SIZE); 18736 if (value < 0 || value > 255) 18737 as_bad_where (fixP->fx_file, fixP->fx_line, 18738 _("invalid immediate: %ld is too large"), 18739 (long) value); 18740 newval |= value; 18741 md_number_to_chars (buf, newval, THUMB_SIZE); 18742 break; 18743 18744 case BFD_RELOC_ARM_THUMB_SHIFT: 18745 /* 5bit shift value (0..32). LSL cannot take 32. */ 18746 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; 18747 temp = newval & 0xf800; 18748 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) 18749 as_bad_where (fixP->fx_file, fixP->fx_line, 18750 _("invalid shift value: %ld"), (long) value); 18751 /* Shifts of zero must be encoded as LSL. */ 18752 if (value == 0) 18753 newval = (newval & 0x003f) | T_OPCODE_LSL_I; 18754 /* Shifts of 32 are encoded as zero. */ 18755 else if (value == 32) 18756 value = 0; 18757 newval |= value << 6; 18758 md_number_to_chars (buf, newval, THUMB_SIZE); 18759 break; 18760 18761 case BFD_RELOC_VTABLE_INHERIT: 18762 case BFD_RELOC_VTABLE_ENTRY: 18763 fixP->fx_done = 0; 18764 return; 18765 18766 case BFD_RELOC_ARM_MOVW: 18767 case BFD_RELOC_ARM_MOVT: 18768 case BFD_RELOC_ARM_THUMB_MOVW: 18769 case BFD_RELOC_ARM_THUMB_MOVT: 18770 if (fixP->fx_done || !seg->use_rela_p) 18771 { 18772 /* REL format relocations are limited to a 16-bit addend. */ 18773 if (!fixP->fx_done) 18774 { 18775 if (value < -0x1000 || value > 0xffff) 18776 as_bad_where (fixP->fx_file, fixP->fx_line, 18777 _("offset too big")); 18778 } 18779 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT 18780 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18781 { 18782 value >>= 16; 18783 } 18784 18785 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 18786 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18787 { 18788 newval = get_thumb32_insn (buf); 18789 newval &= 0xfbf08f00; 18790 newval |= (value & 0xf000) << 4; 18791 newval |= (value & 0x0800) << 15; 18792 newval |= (value & 0x0700) << 4; 18793 newval |= (value & 0x00ff); 18794 put_thumb32_insn (buf, newval); 18795 } 18796 else 18797 { 18798 newval = md_chars_to_number (buf, 4); 18799 newval &= 0xfff0f000; 18800 newval |= value & 0x0fff; 18801 newval |= (value & 0xf000) << 4; 18802 md_number_to_chars (buf, newval, 4); 18803 } 18804 } 18805 return; 18806 18807 case BFD_RELOC_ARM_ALU_PC_G0_NC: 18808 case BFD_RELOC_ARM_ALU_PC_G0: 18809 case BFD_RELOC_ARM_ALU_PC_G1_NC: 18810 case BFD_RELOC_ARM_ALU_PC_G1: 18811 case BFD_RELOC_ARM_ALU_PC_G2: 18812 case BFD_RELOC_ARM_ALU_SB_G0_NC: 18813 case BFD_RELOC_ARM_ALU_SB_G0: 18814 case BFD_RELOC_ARM_ALU_SB_G1_NC: 18815 case BFD_RELOC_ARM_ALU_SB_G1: 18816 case BFD_RELOC_ARM_ALU_SB_G2: 18817 assert (!fixP->fx_done); 18818 if (!seg->use_rela_p) 18819 { 18820 bfd_vma insn; 18821 bfd_vma encoded_addend; 18822 bfd_vma addend_abs = abs (value); 18823 18824 /* Check that the absolute value of the addend can be 18825 expressed as an 8-bit constant plus a rotation. */ 18826 encoded_addend = encode_arm_immediate (addend_abs); 18827 if (encoded_addend == (unsigned int) FAIL) 18828 as_bad_where (fixP->fx_file, fixP->fx_line, 18829 _("the offset 0x%08lX is not representable"), 18830 (unsigned long) addend_abs); 18831 18832 /* Extract the instruction. */ 18833 insn = md_chars_to_number (buf, INSN_SIZE); 18834 18835 /* If the addend is positive, use an ADD instruction. 18836 Otherwise use a SUB. Take care not to destroy the S bit. */ 18837 insn &= 0xff1fffff; 18838 if (value < 0) 18839 insn |= 1 << 22; 18840 else 18841 insn |= 1 << 23; 18842 18843 /* Place the encoded addend into the first 12 bits of the 18844 instruction. */ 18845 insn &= 0xfffff000; 18846 insn |= encoded_addend; 18847 18848 /* Update the instruction. */ 18849 md_number_to_chars (buf, insn, INSN_SIZE); 18850 } 18851 break; 18852 18853 case BFD_RELOC_ARM_LDR_PC_G0: 18854 case BFD_RELOC_ARM_LDR_PC_G1: 18855 case BFD_RELOC_ARM_LDR_PC_G2: 18856 case BFD_RELOC_ARM_LDR_SB_G0: 18857 case BFD_RELOC_ARM_LDR_SB_G1: 18858 case BFD_RELOC_ARM_LDR_SB_G2: 18859 assert (!fixP->fx_done); 18860 if (!seg->use_rela_p) 18861 { 18862 bfd_vma insn; 18863 bfd_vma addend_abs = abs (value); 18864 18865 /* Check that the absolute value of the addend can be 18866 encoded in 12 bits. */ 18867 if (addend_abs >= 0x1000) 18868 as_bad_where (fixP->fx_file, fixP->fx_line, 18869 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), 18870 (unsigned long) addend_abs); 18871 18872 /* Extract the instruction. */ 18873 insn = md_chars_to_number (buf, INSN_SIZE); 18874 18875 /* If the addend is negative, clear bit 23 of the instruction. 18876 Otherwise set it. */ 18877 if (value < 0) 18878 insn &= ~(1 << 23); 18879 else 18880 insn |= 1 << 23; 18881 18882 /* Place the absolute value of the addend into the first 12 bits 18883 of the instruction. */ 18884 insn &= 0xfffff000; 18885 insn |= addend_abs; 18886 18887 /* Update the instruction. */ 18888 md_number_to_chars (buf, insn, INSN_SIZE); 18889 } 18890 break; 18891 18892 case BFD_RELOC_ARM_LDRS_PC_G0: 18893 case BFD_RELOC_ARM_LDRS_PC_G1: 18894 case BFD_RELOC_ARM_LDRS_PC_G2: 18895 case BFD_RELOC_ARM_LDRS_SB_G0: 18896 case BFD_RELOC_ARM_LDRS_SB_G1: 18897 case BFD_RELOC_ARM_LDRS_SB_G2: 18898 assert (!fixP->fx_done); 18899 if (!seg->use_rela_p) 18900 { 18901 bfd_vma insn; 18902 bfd_vma addend_abs = abs (value); 18903 18904 /* Check that the absolute value of the addend can be 18905 encoded in 8 bits. */ 18906 if (addend_abs >= 0x100) 18907 as_bad_where (fixP->fx_file, fixP->fx_line, 18908 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), 18909 (unsigned long) addend_abs); 18910 18911 /* Extract the instruction. */ 18912 insn = md_chars_to_number (buf, INSN_SIZE); 18913 18914 /* If the addend is negative, clear bit 23 of the instruction. 18915 Otherwise set it. */ 18916 if (value < 0) 18917 insn &= ~(1 << 23); 18918 else 18919 insn |= 1 << 23; 18920 18921 /* Place the first four bits of the absolute value of the addend 18922 into the first 4 bits of the instruction, and the remaining 18923 four into bits 8 .. 11. */ 18924 insn &= 0xfffff0f0; 18925 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); 18926 18927 /* Update the instruction. */ 18928 md_number_to_chars (buf, insn, INSN_SIZE); 18929 } 18930 break; 18931 18932 case BFD_RELOC_ARM_LDC_PC_G0: 18933 case BFD_RELOC_ARM_LDC_PC_G1: 18934 case BFD_RELOC_ARM_LDC_PC_G2: 18935 case BFD_RELOC_ARM_LDC_SB_G0: 18936 case BFD_RELOC_ARM_LDC_SB_G1: 18937 case BFD_RELOC_ARM_LDC_SB_G2: 18938 assert (!fixP->fx_done); 18939 if (!seg->use_rela_p) 18940 { 18941 bfd_vma insn; 18942 bfd_vma addend_abs = abs (value); 18943 18944 /* Check that the absolute value of the addend is a multiple of 18945 four and, when divided by four, fits in 8 bits. */ 18946 if (addend_abs & 0x3) 18947 as_bad_where (fixP->fx_file, fixP->fx_line, 18948 _("bad offset 0x%08lX (must be word-aligned)"), 18949 (unsigned long) addend_abs); 18950 18951 if ((addend_abs >> 2) > 0xff) 18952 as_bad_where (fixP->fx_file, fixP->fx_line, 18953 _("bad offset 0x%08lX (must be an 8-bit number of words)"), 18954 (unsigned long) addend_abs); 18955 18956 /* Extract the instruction. */ 18957 insn = md_chars_to_number (buf, INSN_SIZE); 18958 18959 /* If the addend is negative, clear bit 23 of the instruction. 18960 Otherwise set it. */ 18961 if (value < 0) 18962 insn &= ~(1 << 23); 18963 else 18964 insn |= 1 << 23; 18965 18966 /* Place the addend (divided by four) into the first eight 18967 bits of the instruction. */ 18968 insn &= 0xfffffff0; 18969 insn |= addend_abs >> 2; 18970 18971 /* Update the instruction. */ 18972 md_number_to_chars (buf, insn, INSN_SIZE); 18973 } 18974 break; 18975 18976 case BFD_RELOC_UNUSED: 18977 default: 18978 as_bad_where (fixP->fx_file, fixP->fx_line, 18979 _("bad relocation fixup type (%d)"), fixP->fx_r_type); 18980 } 18981} 18982 18983/* Translate internal representation of relocation info to BFD target 18984 format. */ 18985 18986arelent * 18987tc_gen_reloc (asection *section, fixS *fixp) 18988{ 18989 arelent * reloc; 18990 bfd_reloc_code_real_type code; 18991 18992 reloc = xmalloc (sizeof (arelent)); 18993 18994 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 18995 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 18996 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 18997 18998 if (fixp->fx_pcrel) 18999 { 19000 if (section->use_rela_p) 19001 fixp->fx_offset -= md_pcrel_from_section (fixp, section); 19002 else 19003 fixp->fx_offset = reloc->address; 19004 } 19005 reloc->addend = fixp->fx_offset; 19006 19007 switch (fixp->fx_r_type) 19008 { 19009 case BFD_RELOC_8: 19010 if (fixp->fx_pcrel) 19011 { 19012 code = BFD_RELOC_8_PCREL; 19013 break; 19014 } 19015 19016 case BFD_RELOC_16: 19017 if (fixp->fx_pcrel) 19018 { 19019 code = BFD_RELOC_16_PCREL; 19020 break; 19021 } 19022 19023 case BFD_RELOC_32: 19024 if (fixp->fx_pcrel) 19025 { 19026 code = BFD_RELOC_32_PCREL; 19027 break; 19028 } 19029 19030 case BFD_RELOC_ARM_MOVW: 19031 if (fixp->fx_pcrel) 19032 { 19033 code = BFD_RELOC_ARM_MOVW_PCREL; 19034 break; 19035 } 19036 19037 case BFD_RELOC_ARM_MOVT: 19038 if (fixp->fx_pcrel) 19039 { 19040 code = BFD_RELOC_ARM_MOVT_PCREL; 19041 break; 19042 } 19043 19044 case BFD_RELOC_ARM_THUMB_MOVW: 19045 if (fixp->fx_pcrel) 19046 { 19047 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; 19048 break; 19049 } 19050 19051 case BFD_RELOC_ARM_THUMB_MOVT: 19052 if (fixp->fx_pcrel) 19053 { 19054 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; 19055 break; 19056 } 19057 19058 case BFD_RELOC_NONE: 19059 case BFD_RELOC_ARM_PCREL_BRANCH: 19060 case BFD_RELOC_ARM_PCREL_BLX: 19061 case BFD_RELOC_RVA: 19062 case BFD_RELOC_THUMB_PCREL_BRANCH7: 19063 case BFD_RELOC_THUMB_PCREL_BRANCH9: 19064 case BFD_RELOC_THUMB_PCREL_BRANCH12: 19065 case BFD_RELOC_THUMB_PCREL_BRANCH20: 19066 case BFD_RELOC_THUMB_PCREL_BRANCH23: 19067 case BFD_RELOC_THUMB_PCREL_BRANCH25: 19068 case BFD_RELOC_THUMB_PCREL_BLX: 19069 case BFD_RELOC_VTABLE_ENTRY: 19070 case BFD_RELOC_VTABLE_INHERIT: 19071#ifdef TE_PE 19072 case BFD_RELOC_32_SECREL: 19073#endif 19074 code = fixp->fx_r_type; 19075 break; 19076 19077 case BFD_RELOC_ARM_LITERAL: 19078 case BFD_RELOC_ARM_HWLITERAL: 19079 /* If this is called then the a literal has 19080 been referenced across a section boundary. */ 19081 as_bad_where (fixp->fx_file, fixp->fx_line, 19082 _("literal referenced across section boundary")); 19083 return NULL; 19084 19085#ifdef OBJ_ELF 19086 case BFD_RELOC_ARM_GOT32: 19087 case BFD_RELOC_ARM_GOTOFF: 19088 case BFD_RELOC_ARM_PLT32: 19089 case BFD_RELOC_ARM_TARGET1: 19090 case BFD_RELOC_ARM_ROSEGREL32: 19091 case BFD_RELOC_ARM_SBREL32: 19092 case BFD_RELOC_ARM_PREL31: 19093 case BFD_RELOC_ARM_TARGET2: 19094 case BFD_RELOC_ARM_TLS_LE32: 19095 case BFD_RELOC_ARM_TLS_LDO32: 19096 case BFD_RELOC_ARM_PCREL_CALL: 19097 case BFD_RELOC_ARM_PCREL_JUMP: 19098 case BFD_RELOC_ARM_ALU_PC_G0_NC: 19099 case BFD_RELOC_ARM_ALU_PC_G0: 19100 case BFD_RELOC_ARM_ALU_PC_G1_NC: 19101 case BFD_RELOC_ARM_ALU_PC_G1: 19102 case BFD_RELOC_ARM_ALU_PC_G2: 19103 case BFD_RELOC_ARM_LDR_PC_G0: 19104 case BFD_RELOC_ARM_LDR_PC_G1: 19105 case BFD_RELOC_ARM_LDR_PC_G2: 19106 case BFD_RELOC_ARM_LDRS_PC_G0: 19107 case BFD_RELOC_ARM_LDRS_PC_G1: 19108 case BFD_RELOC_ARM_LDRS_PC_G2: 19109 case BFD_RELOC_ARM_LDC_PC_G0: 19110 case BFD_RELOC_ARM_LDC_PC_G1: 19111 case BFD_RELOC_ARM_LDC_PC_G2: 19112 case BFD_RELOC_ARM_ALU_SB_G0_NC: 19113 case BFD_RELOC_ARM_ALU_SB_G0: 19114 case BFD_RELOC_ARM_ALU_SB_G1_NC: 19115 case BFD_RELOC_ARM_ALU_SB_G1: 19116 case BFD_RELOC_ARM_ALU_SB_G2: 19117 case BFD_RELOC_ARM_LDR_SB_G0: 19118 case BFD_RELOC_ARM_LDR_SB_G1: 19119 case BFD_RELOC_ARM_LDR_SB_G2: 19120 case BFD_RELOC_ARM_LDRS_SB_G0: 19121 case BFD_RELOC_ARM_LDRS_SB_G1: 19122 case BFD_RELOC_ARM_LDRS_SB_G2: 19123 case BFD_RELOC_ARM_LDC_SB_G0: 19124 case BFD_RELOC_ARM_LDC_SB_G1: 19125 case BFD_RELOC_ARM_LDC_SB_G2: 19126 code = fixp->fx_r_type; 19127 break; 19128 19129 case BFD_RELOC_ARM_TLS_GD32: 19130 case BFD_RELOC_ARM_TLS_IE32: 19131 case BFD_RELOC_ARM_TLS_LDM32: 19132 /* BFD will include the symbol's address in the addend. 19133 But we don't want that, so subtract it out again here. */ 19134 if (!S_IS_COMMON (fixp->fx_addsy)) 19135 reloc->addend -= (*reloc->sym_ptr_ptr)->value; 19136 code = fixp->fx_r_type; 19137 break; 19138#endif 19139 19140 case BFD_RELOC_ARM_IMMEDIATE: 19141 as_bad_where (fixp->fx_file, fixp->fx_line, 19142 _("internal relocation (type: IMMEDIATE) not fixed up")); 19143 return NULL; 19144 19145 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 19146 as_bad_where (fixp->fx_file, fixp->fx_line, 19147 _("ADRL used for a symbol not defined in the same file")); 19148 return NULL; 19149 19150 case BFD_RELOC_ARM_OFFSET_IMM: 19151 if (section->use_rela_p) 19152 { 19153 code = fixp->fx_r_type; 19154 break; 19155 } 19156 19157 if (fixp->fx_addsy != NULL 19158 && !S_IS_DEFINED (fixp->fx_addsy) 19159 && S_IS_LOCAL (fixp->fx_addsy)) 19160 { 19161 as_bad_where (fixp->fx_file, fixp->fx_line, 19162 _("undefined local label `%s'"), 19163 S_GET_NAME (fixp->fx_addsy)); 19164 return NULL; 19165 } 19166 19167 as_bad_where (fixp->fx_file, fixp->fx_line, 19168 _("internal_relocation (type: OFFSET_IMM) not fixed up")); 19169 return NULL; 19170 19171 default: 19172 { 19173 char * type; 19174 19175 switch (fixp->fx_r_type) 19176 { 19177 case BFD_RELOC_NONE: type = "NONE"; break; 19178 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; 19179 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; 19180 case BFD_RELOC_ARM_SMC: type = "SMC"; break; 19181 case BFD_RELOC_ARM_SWI: type = "SWI"; break; 19182 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; 19183 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; 19184 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; 19185 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; 19186 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; 19187 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; 19188 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; 19189 default: type = _("<unknown>"); break; 19190 } 19191 as_bad_where (fixp->fx_file, fixp->fx_line, 19192 _("cannot represent %s relocation in this object file format"), 19193 type); 19194 return NULL; 19195 } 19196 } 19197 19198#ifdef OBJ_ELF 19199 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) 19200 && GOT_symbol 19201 && fixp->fx_addsy == GOT_symbol) 19202 { 19203 code = BFD_RELOC_ARM_GOTPC; 19204 reloc->addend = fixp->fx_offset = reloc->address; 19205 } 19206#endif 19207 19208 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 19209 19210 if (reloc->howto == NULL) 19211 { 19212 as_bad_where (fixp->fx_file, fixp->fx_line, 19213 _("cannot represent %s relocation in this object file format"), 19214 bfd_get_reloc_code_name (code)); 19215 return NULL; 19216 } 19217 19218 /* HACK: Since arm ELF uses Rel instead of Rela, encode the 19219 vtable entry to be used in the relocation's section offset. */ 19220 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19221 reloc->address = fixp->fx_offset; 19222 19223 return reloc; 19224} 19225 19226/* This fix_new is called by cons via TC_CONS_FIX_NEW. */ 19227 19228void 19229cons_fix_new_arm (fragS * frag, 19230 int where, 19231 int size, 19232 expressionS * exp) 19233{ 19234 bfd_reloc_code_real_type type; 19235 int pcrel = 0; 19236 19237 /* Pick a reloc. 19238 FIXME: @@ Should look at CPU word size. */ 19239 switch (size) 19240 { 19241 case 1: 19242 type = BFD_RELOC_8; 19243 break; 19244 case 2: 19245 type = BFD_RELOC_16; 19246 break; 19247 case 4: 19248 default: 19249 type = BFD_RELOC_32; 19250 break; 19251 case 8: 19252 type = BFD_RELOC_64; 19253 break; 19254 } 19255 19256#ifdef TE_PE 19257 if (exp->X_op == O_secrel) 19258 { 19259 exp->X_op = O_symbol; 19260 type = BFD_RELOC_32_SECREL; 19261 } 19262#endif 19263 19264 fix_new_exp (frag, where, (int) size, exp, pcrel, type); 19265} 19266 19267#if defined OBJ_COFF || defined OBJ_ELF 19268void 19269arm_validate_fix (fixS * fixP) 19270{ 19271 /* If the destination of the branch is a defined symbol which does not have 19272 the THUMB_FUNC attribute, then we must be calling a function which has 19273 the (interfacearm) attribute. We look for the Thumb entry point to that 19274 function and change the branch to refer to that function instead. */ 19275 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 19276 && fixP->fx_addsy != NULL 19277 && S_IS_DEFINED (fixP->fx_addsy) 19278 && ! THUMB_IS_FUNC (fixP->fx_addsy)) 19279 { 19280 fixP->fx_addsy = find_real_start (fixP->fx_addsy); 19281 } 19282} 19283#endif 19284 19285int 19286arm_force_relocation (struct fix * fixp) 19287{ 19288#if defined (OBJ_COFF) && defined (TE_PE) 19289 if (fixp->fx_r_type == BFD_RELOC_RVA) 19290 return 1; 19291#endif 19292 19293 /* Resolve these relocations even if the symbol is extern or weak. */ 19294 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE 19295 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM 19296 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE 19297 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM 19298 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 19299 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 19300 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) 19301 return 0; 19302 19303 /* Always leave these relocations for the linker. */ 19304 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19305 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19306 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19307 return 1; 19308 19309 /* Always generate relocations against function symbols. */ 19310 if (fixp->fx_r_type == BFD_RELOC_32 19311 && fixp->fx_addsy 19312 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) 19313 return 1; 19314 19315 return generic_force_reloc (fixp); 19316} 19317 19318#if defined (OBJ_ELF) || defined (OBJ_COFF) 19319/* Relocations against function names must be left unadjusted, 19320 so that the linker can use this information to generate interworking 19321 stubs. The MIPS version of this function 19322 also prevents relocations that are mips-16 specific, but I do not 19323 know why it does this. 19324 19325 FIXME: 19326 There is one other problem that ought to be addressed here, but 19327 which currently is not: Taking the address of a label (rather 19328 than a function) and then later jumping to that address. Such 19329 addresses also ought to have their bottom bit set (assuming that 19330 they reside in Thumb code), but at the moment they will not. */ 19331 19332bfd_boolean 19333arm_fix_adjustable (fixS * fixP) 19334{ 19335 if (fixP->fx_addsy == NULL) 19336 return 1; 19337 19338 /* Preserve relocations against symbols with function type. */ 19339 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) 19340 return 0; 19341 19342 if (THUMB_IS_FUNC (fixP->fx_addsy) 19343 && fixP->fx_subsy == NULL) 19344 return 0; 19345 19346 /* We need the symbol name for the VTABLE entries. */ 19347 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 19348 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19349 return 0; 19350 19351 /* Don't allow symbols to be discarded on GOT related relocs. */ 19352 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 19353 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 19354 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF 19355 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 19356 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 19357 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 19358 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 19359 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 19360 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) 19361 return 0; 19362 19363 /* Similarly for group relocations. */ 19364 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19365 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19366 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19367 return 0; 19368 19369 return 1; 19370} 19371#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ 19372 19373#ifdef OBJ_ELF 19374 19375const char * 19376elf32_arm_target_format (void) 19377{ 19378#ifdef TE_SYMBIAN 19379 return (target_big_endian 19380 ? "elf32-bigarm-symbian" 19381 : "elf32-littlearm-symbian"); 19382#elif defined (TE_VXWORKS) 19383 return (target_big_endian 19384 ? "elf32-bigarm-vxworks" 19385 : "elf32-littlearm-vxworks"); 19386#else 19387 if (target_big_endian) 19388 return "elf32-bigarm"; 19389 else 19390 return "elf32-littlearm"; 19391#endif 19392} 19393 19394void 19395armelf_frob_symbol (symbolS * symp, 19396 int * puntp) 19397{ 19398 elf_frob_symbol (symp, puntp); 19399} 19400#endif 19401 19402/* MD interface: Finalization. */ 19403 19404/* A good place to do this, although this was probably not intended 19405 for this kind of use. We need to dump the literal pool before 19406 references are made to a null symbol pointer. */ 19407 19408void 19409arm_cleanup (void) 19410{ 19411 literal_pool * pool; 19412 19413 for (pool = list_of_pools; pool; pool = pool->next) 19414 { 19415 /* Put it at the end of the relevent section. */ 19416 subseg_set (pool->section, pool->sub_section); 19417#ifdef OBJ_ELF 19418 arm_elf_change_section (); 19419#endif 19420 s_ltorg (0); 19421 } 19422} 19423 19424/* Adjust the symbol table. This marks Thumb symbols as distinct from 19425 ARM ones. */ 19426 19427void 19428arm_adjust_symtab (void) 19429{ 19430#ifdef OBJ_COFF 19431 symbolS * sym; 19432 19433 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19434 { 19435 if (ARM_IS_THUMB (sym)) 19436 { 19437 if (THUMB_IS_FUNC (sym)) 19438 { 19439 /* Mark the symbol as a Thumb function. */ 19440 if ( S_GET_STORAGE_CLASS (sym) == C_STAT 19441 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ 19442 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); 19443 19444 else if (S_GET_STORAGE_CLASS (sym) == C_EXT) 19445 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); 19446 else 19447 as_bad (_("%s: unexpected function type: %d"), 19448 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); 19449 } 19450 else switch (S_GET_STORAGE_CLASS (sym)) 19451 { 19452 case C_EXT: 19453 S_SET_STORAGE_CLASS (sym, C_THUMBEXT); 19454 break; 19455 case C_STAT: 19456 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); 19457 break; 19458 case C_LABEL: 19459 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); 19460 break; 19461 default: 19462 /* Do nothing. */ 19463 break; 19464 } 19465 } 19466 19467 if (ARM_IS_INTERWORK (sym)) 19468 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; 19469 } 19470#endif 19471#ifdef OBJ_ELF 19472 symbolS * sym; 19473 char bind; 19474 19475 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19476 { 19477 if (ARM_IS_THUMB (sym)) 19478 { 19479 elf_symbol_type * elf_sym; 19480 19481 elf_sym = elf_symbol (symbol_get_bfdsym (sym)); 19482 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); 19483 19484 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, 19485 BFD_ARM_SPECIAL_SYM_TYPE_ANY)) 19486 { 19487 /* If it's a .thumb_func, declare it as so, 19488 otherwise tag label as .code 16. */ 19489 if (THUMB_IS_FUNC (sym)) 19490 elf_sym->internal_elf_sym.st_info = 19491 ELF_ST_INFO (bind, STT_ARM_TFUNC); 19492 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 19493 elf_sym->internal_elf_sym.st_info = 19494 ELF_ST_INFO (bind, STT_ARM_16BIT); 19495 } 19496 } 19497 } 19498#endif 19499} 19500 19501/* MD interface: Initialization. */ 19502 19503static void 19504set_constant_flonums (void) 19505{ 19506 int i; 19507 19508 for (i = 0; i < NUM_FLOAT_VALS; i++) 19509 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) 19510 abort (); 19511} 19512 19513/* Auto-select Thumb mode if it's the only available instruction set for the 19514 given architecture. */ 19515 19516static void 19517autoselect_thumb_from_cpu_variant (void) 19518{ 19519 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 19520 opcode_select (16); 19521} 19522 19523void 19524md_begin (void) 19525{ 19526 unsigned mach; 19527 unsigned int i; 19528 19529 if ( (arm_ops_hsh = hash_new ()) == NULL 19530 || (arm_cond_hsh = hash_new ()) == NULL 19531 || (arm_shift_hsh = hash_new ()) == NULL 19532 || (arm_psr_hsh = hash_new ()) == NULL 19533 || (arm_v7m_psr_hsh = hash_new ()) == NULL 19534 || (arm_reg_hsh = hash_new ()) == NULL 19535 || (arm_reloc_hsh = hash_new ()) == NULL 19536 || (arm_barrier_opt_hsh = hash_new ()) == NULL) 19537 as_fatal (_("virtual memory exhausted")); 19538 19539 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) 19540 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); 19541 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) 19542 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); 19543 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) 19544 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); 19545 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) 19546 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); 19547 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) 19548 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i)); 19549 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) 19550 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); 19551 for (i = 0; 19552 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); 19553 i++) 19554 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, 19555 (PTR) (barrier_opt_names + i)); 19556#ifdef OBJ_ELF 19557 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) 19558 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); 19559#endif 19560 19561 set_constant_flonums (); 19562 19563 /* Set the cpu variant based on the command-line options. We prefer 19564 -mcpu= over -march= if both are set (as for GCC); and we prefer 19565 -mfpu= over any other way of setting the floating point unit. 19566 Use of legacy options with new options are faulted. */ 19567 if (legacy_cpu) 19568 { 19569 if (mcpu_cpu_opt || march_cpu_opt) 19570 as_bad (_("use of old and new-style options to set CPU type")); 19571 19572 mcpu_cpu_opt = legacy_cpu; 19573 } 19574 else if (!mcpu_cpu_opt) 19575 mcpu_cpu_opt = march_cpu_opt; 19576 19577 if (legacy_fpu) 19578 { 19579 if (mfpu_opt) 19580 as_bad (_("use of old and new-style options to set FPU type")); 19581 19582 mfpu_opt = legacy_fpu; 19583 } 19584 else if (!mfpu_opt) 19585 { 19586#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) 19587 /* Some environments specify a default FPU. If they don't, infer it 19588 from the processor. */ 19589 if (mcpu_fpu_opt) 19590 mfpu_opt = mcpu_fpu_opt; 19591 else 19592 mfpu_opt = march_fpu_opt; 19593#else 19594 mfpu_opt = &fpu_default; 19595#endif 19596 } 19597 19598 if (!mfpu_opt) 19599 { 19600 if (mcpu_cpu_opt != NULL) 19601 mfpu_opt = &fpu_default; 19602 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) 19603 mfpu_opt = &fpu_arch_vfp_v2; 19604 else 19605 mfpu_opt = &fpu_arch_fpa; 19606 } 19607 19608#ifdef CPU_DEFAULT 19609 if (!mcpu_cpu_opt) 19610 { 19611 mcpu_cpu_opt = &cpu_default; 19612 selected_cpu = cpu_default; 19613 } 19614#else 19615 if (mcpu_cpu_opt) 19616 selected_cpu = *mcpu_cpu_opt; 19617 else 19618 mcpu_cpu_opt = &arm_arch_any; 19619#endif 19620 19621 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 19622 19623 autoselect_thumb_from_cpu_variant (); 19624 19625 arm_arch_used = thumb_arch_used = arm_arch_none; 19626 19627#if defined OBJ_COFF || defined OBJ_ELF 19628 { 19629 unsigned int flags = 0; 19630 19631#if defined OBJ_ELF 19632 flags = meabi_flags; 19633 19634 switch (meabi_flags) 19635 { 19636 case EF_ARM_EABI_UNKNOWN: 19637#endif 19638 /* Set the flags in the private structure. */ 19639 if (uses_apcs_26) flags |= F_APCS26; 19640 if (support_interwork) flags |= F_INTERWORK; 19641 if (uses_apcs_float) flags |= F_APCS_FLOAT; 19642 if (pic_code) flags |= F_PIC; 19643 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) 19644 flags |= F_SOFT_FLOAT; 19645 19646 switch (mfloat_abi_opt) 19647 { 19648 case ARM_FLOAT_ABI_SOFT: 19649 case ARM_FLOAT_ABI_SOFTFP: 19650 flags |= F_SOFT_FLOAT; 19651 break; 19652 19653 case ARM_FLOAT_ABI_HARD: 19654 if (flags & F_SOFT_FLOAT) 19655 as_bad (_("hard-float conflicts with specified fpu")); 19656 break; 19657 } 19658 19659 /* Using pure-endian doubles (even if soft-float). */ 19660 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 19661 flags |= F_VFP_FLOAT; 19662 19663#if defined OBJ_ELF 19664 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) 19665 flags |= EF_ARM_MAVERICK_FLOAT; 19666 break; 19667 19668 case EF_ARM_EABI_VER4: 19669 case EF_ARM_EABI_VER5: 19670 /* No additional flags to set. */ 19671 break; 19672 19673 default: 19674 abort (); 19675 } 19676#endif 19677 bfd_set_private_flags (stdoutput, flags); 19678 19679 /* We have run out flags in the COFF header to encode the 19680 status of ATPCS support, so instead we create a dummy, 19681 empty, debug section called .arm.atpcs. */ 19682 if (atpcs) 19683 { 19684 asection * sec; 19685 19686 sec = bfd_make_section (stdoutput, ".arm.atpcs"); 19687 19688 if (sec != NULL) 19689 { 19690 bfd_set_section_flags 19691 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); 19692 bfd_set_section_size (stdoutput, sec, 0); 19693 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); 19694 } 19695 } 19696 } 19697#endif 19698 19699 /* Record the CPU type as well. */ 19700 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) 19701 mach = bfd_mach_arm_iWMMXt2; 19702 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) 19703 mach = bfd_mach_arm_iWMMXt; 19704 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) 19705 mach = bfd_mach_arm_XScale; 19706 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) 19707 mach = bfd_mach_arm_ep9312; 19708 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) 19709 mach = bfd_mach_arm_5TE; 19710 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) 19711 { 19712 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19713 mach = bfd_mach_arm_5T; 19714 else 19715 mach = bfd_mach_arm_5; 19716 } 19717 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) 19718 { 19719 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19720 mach = bfd_mach_arm_4T; 19721 else 19722 mach = bfd_mach_arm_4; 19723 } 19724 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) 19725 mach = bfd_mach_arm_3M; 19726 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) 19727 mach = bfd_mach_arm_3; 19728 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) 19729 mach = bfd_mach_arm_2a; 19730 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) 19731 mach = bfd_mach_arm_2; 19732 else 19733 mach = bfd_mach_arm_unknown; 19734 19735 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); 19736} 19737 19738/* Command line processing. */ 19739 19740/* md_parse_option 19741 Invocation line includes a switch not recognized by the base assembler. 19742 See if it's a processor-specific option. 19743 19744 This routine is somewhat complicated by the need for backwards 19745 compatibility (since older releases of gcc can't be changed). 19746 The new options try to make the interface as compatible as 19747 possible with GCC. 19748 19749 New options (supported) are: 19750 19751 -mcpu=<cpu name> Assemble for selected processor 19752 -march=<architecture name> Assemble for selected architecture 19753 -mfpu=<fpu architecture> Assemble for selected FPU. 19754 -EB/-mbig-endian Big-endian 19755 -EL/-mlittle-endian Little-endian 19756 -k Generate PIC code 19757 -mthumb Start in Thumb mode 19758 -mthumb-interwork Code supports ARM/Thumb interworking 19759 19760 For now we will also provide support for: 19761 19762 -mapcs-32 32-bit Program counter 19763 -mapcs-26 26-bit Program counter 19764 -macps-float Floats passed in FP registers 19765 -mapcs-reentrant Reentrant code 19766 -matpcs 19767 (sometime these will probably be replaced with -mapcs=<list of options> 19768 and -matpcs=<list of options>) 19769 19770 The remaining options are only supported for back-wards compatibility. 19771 Cpu variants, the arm part is optional: 19772 -m[arm]1 Currently not supported. 19773 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor 19774 -m[arm]3 Arm 3 processor 19775 -m[arm]6[xx], Arm 6 processors 19776 -m[arm]7[xx][t][[d]m] Arm 7 processors 19777 -m[arm]8[10] Arm 8 processors 19778 -m[arm]9[20][tdmi] Arm 9 processors 19779 -mstrongarm[110[0]] StrongARM processors 19780 -mxscale XScale processors 19781 -m[arm]v[2345[t[e]]] Arm architectures 19782 -mall All (except the ARM1) 19783 FP variants: 19784 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions 19785 -mfpe-old (No float load/store multiples) 19786 -mvfpxd VFP Single precision 19787 -mvfp All VFP 19788 -mno-fpu Disable all floating point instructions 19789 19790 The following CPU names are recognized: 19791 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, 19792 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, 19793 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, 19794 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, 19795 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, 19796 arm10t arm10e, arm1020t, arm1020e, arm10200e, 19797 strongarm, strongarm110, strongarm1100, strongarm1110, xscale. 19798 19799 */ 19800 19801const char * md_shortopts = "m:k"; 19802 19803#ifdef ARM_BI_ENDIAN 19804#define OPTION_EB (OPTION_MD_BASE + 0) 19805#define OPTION_EL (OPTION_MD_BASE + 1) 19806#else 19807#if TARGET_BYTES_BIG_ENDIAN 19808#define OPTION_EB (OPTION_MD_BASE + 0) 19809#else 19810#define OPTION_EL (OPTION_MD_BASE + 1) 19811#endif 19812#endif 19813 19814struct option md_longopts[] = 19815{ 19816#ifdef OPTION_EB 19817 {"EB", no_argument, NULL, OPTION_EB}, 19818#endif 19819#ifdef OPTION_EL 19820 {"EL", no_argument, NULL, OPTION_EL}, 19821#endif 19822 {NULL, no_argument, NULL, 0} 19823}; 19824 19825size_t md_longopts_size = sizeof (md_longopts); 19826 19827struct arm_option_table 19828{ 19829 char *option; /* Option name to match. */ 19830 char *help; /* Help information. */ 19831 int *var; /* Variable to change. */ 19832 int value; /* What to change it to. */ 19833 char *deprecated; /* If non-null, print this message. */ 19834}; 19835 19836struct arm_option_table arm_opts[] = 19837{ 19838 {"k", N_("generate PIC code"), &pic_code, 1, NULL}, 19839 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, 19840 {"mthumb-interwork", N_("support ARM/Thumb interworking"), 19841 &support_interwork, 1, NULL}, 19842 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, 19843 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, 19844 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, 19845 1, NULL}, 19846 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, 19847 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, 19848 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, 19849 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, 19850 NULL}, 19851 19852 /* These are recognized by the assembler, but have no affect on code. */ 19853 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, 19854 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, 19855 {NULL, NULL, NULL, 0, NULL} 19856}; 19857 19858struct arm_legacy_option_table 19859{ 19860 char *option; /* Option name to match. */ 19861 const arm_feature_set **var; /* Variable to change. */ 19862 const arm_feature_set value; /* What to change it to. */ 19863 char *deprecated; /* If non-null, print this message. */ 19864}; 19865 19866const struct arm_legacy_option_table arm_legacy_opts[] = 19867{ 19868 /* DON'T add any new processors to this list -- we want the whole list 19869 to go away... Add them to the processors table instead. */ 19870 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19871 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19872 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19873 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19874 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19875 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19876 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19877 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19878 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19879 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19880 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19881 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19882 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19883 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19884 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19885 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19886 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19887 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19888 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19889 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19890 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19891 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19892 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19893 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19894 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19895 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19896 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19897 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19898 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19899 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19900 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19901 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19902 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19903 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19904 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19905 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19906 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19907 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19908 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19909 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19910 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19911 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19912 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19913 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19914 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19915 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19916 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19917 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19918 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19919 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19920 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19921 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19922 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19923 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19924 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19925 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19926 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19927 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19928 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19929 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19930 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19931 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19932 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19933 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19934 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19935 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19936 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19937 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19938 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, 19939 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, 19940 N_("use -mcpu=strongarm110")}, 19941 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, 19942 N_("use -mcpu=strongarm1100")}, 19943 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, 19944 N_("use -mcpu=strongarm1110")}, 19945 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, 19946 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, 19947 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, 19948 19949 /* Architecture variants -- don't add any more to this list either. */ 19950 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19951 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19952 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19953 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19954 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 19955 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 19956 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 19957 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 19958 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 19959 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 19960 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 19961 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 19962 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 19963 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 19964 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 19965 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 19966 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 19967 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 19968 19969 /* Floating point variants -- don't add any more to this list either. */ 19970 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, 19971 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, 19972 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, 19973 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, 19974 N_("use either -mfpu=softfpa or -mfpu=softvfp")}, 19975 19976 {NULL, NULL, ARM_ARCH_NONE, NULL} 19977}; 19978 19979struct arm_cpu_option_table 19980{ 19981 char *name; 19982 const arm_feature_set value; 19983 /* For some CPUs we assume an FPU unless the user explicitly sets 19984 -mfpu=... */ 19985 const arm_feature_set default_fpu; 19986 /* The canonical name of the CPU, or NULL to use NAME converted to upper 19987 case. */ 19988 const char *canonical_name; 19989}; 19990 19991/* This list should, at a minimum, contain all the cpu names 19992 recognized by GCC. */ 19993static const struct arm_cpu_option_table arm_cpus[] = 19994{ 19995 {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, 19996 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, 19997 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, 19998 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 19999 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20000 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20001 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20002 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20003 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20004 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20005 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20006 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20007 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20008 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20009 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20010 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20011 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20012 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20013 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20014 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20015 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20016 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20017 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20018 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20019 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20020 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20021 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20022 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20023 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20024 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20025 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20026 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20027 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20028 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20029 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20030 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20031 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20032 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20033 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20034 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, 20035 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20036 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20037 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20038 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20039 /* For V5 or later processors we default to using VFP; but the user 20040 should really set the FPU type explicitly. */ 20041 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20042 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20043 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20044 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20045 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20046 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20047 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, 20048 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20049 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20050 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, 20051 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20052 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20053 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20054 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20055 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20056 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, 20057 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20058 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20059 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20060 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, 20061 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20062 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, 20063 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, 20064 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, 20065 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, 20066 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, 20067 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, 20068 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, 20069 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, 20070 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, 20071 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, 20072 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20073 | FPU_NEON_EXT_V1), 20074 NULL}, 20075 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20076 | FPU_NEON_EXT_V1), 20077 NULL}, 20078 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, 20079 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, 20080 /* ??? XSCALE is really an architecture. */ 20081 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20082 /* ??? iwmmxt is not a processor. */ 20083 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, 20084 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, 20085 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20086 /* Maverick */ 20087 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, 20088 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} 20089}; 20090 20091struct arm_arch_option_table 20092{ 20093 char *name; 20094 const arm_feature_set value; 20095 const arm_feature_set default_fpu; 20096}; 20097 20098/* This list should, at a minimum, contain all the architecture names 20099 recognized by GCC. */ 20100static const struct arm_arch_option_table arm_archs[] = 20101{ 20102 {"all", ARM_ANY, FPU_ARCH_FPA}, 20103 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, 20104 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, 20105 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20106 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20107 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, 20108 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, 20109 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, 20110 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, 20111 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, 20112 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, 20113 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, 20114 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, 20115 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, 20116 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, 20117 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, 20118 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, 20119 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, 20120 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, 20121 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, 20122 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, 20123 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, 20124 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, 20125 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, 20126 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, 20127 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, 20128 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, 20129 /* The official spelling of the ARMv7 profile variants is the dashed form. 20130 Accept the non-dashed form for compatibility with old toolchains. */ 20131 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20132 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20133 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20134 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20135 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20136 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20137 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, 20138 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, 20139 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, 20140 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} 20141}; 20142 20143/* ISA extensions in the co-processor space. */ 20144struct arm_option_cpu_value_table 20145{ 20146 char *name; 20147 const arm_feature_set value; 20148}; 20149 20150static const struct arm_option_cpu_value_table arm_extensions[] = 20151{ 20152 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, 20153 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, 20154 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, 20155 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, 20156 {NULL, ARM_ARCH_NONE} 20157}; 20158 20159/* This list should, at a minimum, contain all the fpu names 20160 recognized by GCC. */ 20161static const struct arm_option_cpu_value_table arm_fpus[] = 20162{ 20163 {"softfpa", FPU_NONE}, 20164 {"fpe", FPU_ARCH_FPE}, 20165 {"fpe2", FPU_ARCH_FPE}, 20166 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ 20167 {"fpa", FPU_ARCH_FPA}, 20168 {"fpa10", FPU_ARCH_FPA}, 20169 {"fpa11", FPU_ARCH_FPA}, 20170 {"arm7500fe", FPU_ARCH_FPA}, 20171 {"softvfp", FPU_ARCH_VFP}, 20172 {"softvfp+vfp", FPU_ARCH_VFP_V2}, 20173 {"vfp", FPU_ARCH_VFP_V2}, 20174 {"vfpv2", FPU_ARCH_VFP_V2}, 20175 {"vfp9", FPU_ARCH_VFP_V2}, 20176 {"vfp3", FPU_ARCH_VFP_V3}, 20177 {"vfpv3", FPU_ARCH_VFP_V3}, 20178 {"vfp10", FPU_ARCH_VFP_V2}, 20179 {"vfp10-r0", FPU_ARCH_VFP_V1}, 20180 {"vfpxd", FPU_ARCH_VFP_V1xD}, 20181 {"arm1020t", FPU_ARCH_VFP_V1}, 20182 {"arm1020e", FPU_ARCH_VFP_V2}, 20183 {"arm1136jfs", FPU_ARCH_VFP_V2}, 20184 {"arm1136jf-s", FPU_ARCH_VFP_V2}, 20185 {"maverick", FPU_ARCH_MAVERICK}, 20186 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, 20187 {NULL, ARM_ARCH_NONE} 20188}; 20189 20190struct arm_option_value_table 20191{ 20192 char *name; 20193 long value; 20194}; 20195 20196static const struct arm_option_value_table arm_float_abis[] = 20197{ 20198 {"hard", ARM_FLOAT_ABI_HARD}, 20199 {"softfp", ARM_FLOAT_ABI_SOFTFP}, 20200 {"soft", ARM_FLOAT_ABI_SOFT}, 20201 {NULL, 0} 20202}; 20203 20204#ifdef OBJ_ELF 20205/* We only know how to output GNU and ver 4/5 (AAELF) formats. */ 20206static const struct arm_option_value_table arm_eabis[] = 20207{ 20208 {"gnu", EF_ARM_EABI_UNKNOWN}, 20209 {"4", EF_ARM_EABI_VER4}, 20210 {"5", EF_ARM_EABI_VER5}, 20211 {NULL, 0} 20212}; 20213#endif 20214 20215struct arm_long_option_table 20216{ 20217 char * option; /* Substring to match. */ 20218 char * help; /* Help information. */ 20219 int (* func) (char * subopt); /* Function to decode sub-option. */ 20220 char * deprecated; /* If non-null, print this message. */ 20221}; 20222 20223static int 20224arm_parse_extension (char * str, const arm_feature_set **opt_p) 20225{ 20226 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); 20227 20228 /* Copy the feature set, so that we can modify it. */ 20229 *ext_set = **opt_p; 20230 *opt_p = ext_set; 20231 20232 while (str != NULL && *str != 0) 20233 { 20234 const struct arm_option_cpu_value_table * opt; 20235 char * ext; 20236 int optlen; 20237 20238 if (*str != '+') 20239 { 20240 as_bad (_("invalid architectural extension")); 20241 return 0; 20242 } 20243 20244 str++; 20245 ext = strchr (str, '+'); 20246 20247 if (ext != NULL) 20248 optlen = ext - str; 20249 else 20250 optlen = strlen (str); 20251 20252 if (optlen == 0) 20253 { 20254 as_bad (_("missing architectural extension")); 20255 return 0; 20256 } 20257 20258 for (opt = arm_extensions; opt->name != NULL; opt++) 20259 if (strncmp (opt->name, str, optlen) == 0) 20260 { 20261 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); 20262 break; 20263 } 20264 20265 if (opt->name == NULL) 20266 { 20267 as_bad (_("unknown architectural extnsion `%s'"), str); 20268 return 0; 20269 } 20270 20271 str = ext; 20272 }; 20273 20274 return 1; 20275} 20276 20277static int 20278arm_parse_cpu (char * str) 20279{ 20280 const struct arm_cpu_option_table * opt; 20281 char * ext = strchr (str, '+'); 20282 int optlen; 20283 20284 if (ext != NULL) 20285 optlen = ext - str; 20286 else 20287 optlen = strlen (str); 20288 20289 if (optlen == 0) 20290 { 20291 as_bad (_("missing cpu name `%s'"), str); 20292 return 0; 20293 } 20294 20295 for (opt = arm_cpus; opt->name != NULL; opt++) 20296 if (strncmp (opt->name, str, optlen) == 0) 20297 { 20298 mcpu_cpu_opt = &opt->value; 20299 mcpu_fpu_opt = &opt->default_fpu; 20300 if (opt->canonical_name) 20301 strcpy(selected_cpu_name, opt->canonical_name); 20302 else 20303 { 20304 int i; 20305 for (i = 0; i < optlen; i++) 20306 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20307 selected_cpu_name[i] = 0; 20308 } 20309 20310 if (ext != NULL) 20311 return arm_parse_extension (ext, &mcpu_cpu_opt); 20312 20313 return 1; 20314 } 20315 20316 as_bad (_("unknown cpu `%s'"), str); 20317 return 0; 20318} 20319 20320static int 20321arm_parse_arch (char * str) 20322{ 20323 const struct arm_arch_option_table *opt; 20324 char *ext = strchr (str, '+'); 20325 int optlen; 20326 20327 if (ext != NULL) 20328 optlen = ext - str; 20329 else 20330 optlen = strlen (str); 20331 20332 if (optlen == 0) 20333 { 20334 as_bad (_("missing architecture name `%s'"), str); 20335 return 0; 20336 } 20337 20338 for (opt = arm_archs; opt->name != NULL; opt++) 20339 if (streq (opt->name, str)) 20340 { 20341 march_cpu_opt = &opt->value; 20342 march_fpu_opt = &opt->default_fpu; 20343 strcpy(selected_cpu_name, opt->name); 20344 20345 if (ext != NULL) 20346 return arm_parse_extension (ext, &march_cpu_opt); 20347 20348 return 1; 20349 } 20350 20351 as_bad (_("unknown architecture `%s'\n"), str); 20352 return 0; 20353} 20354 20355static int 20356arm_parse_fpu (char * str) 20357{ 20358 const struct arm_option_cpu_value_table * opt; 20359 20360 for (opt = arm_fpus; opt->name != NULL; opt++) 20361 if (streq (opt->name, str)) 20362 { 20363 mfpu_opt = &opt->value; 20364 return 1; 20365 } 20366 20367 as_bad (_("unknown floating point format `%s'\n"), str); 20368 return 0; 20369} 20370 20371static int 20372arm_parse_float_abi (char * str) 20373{ 20374 const struct arm_option_value_table * opt; 20375 20376 for (opt = arm_float_abis; opt->name != NULL; opt++) 20377 if (streq (opt->name, str)) 20378 { 20379 mfloat_abi_opt = opt->value; 20380 return 1; 20381 } 20382 20383 as_bad (_("unknown floating point abi `%s'\n"), str); 20384 return 0; 20385} 20386 20387#ifdef OBJ_ELF 20388static int 20389arm_parse_eabi (char * str) 20390{ 20391 const struct arm_option_value_table *opt; 20392 20393 for (opt = arm_eabis; opt->name != NULL; opt++) 20394 if (streq (opt->name, str)) 20395 { 20396 meabi_flags = opt->value; 20397 return 1; 20398 } 20399 as_bad (_("unknown EABI `%s'\n"), str); 20400 return 0; 20401} 20402#endif 20403 20404struct arm_long_option_table arm_long_opts[] = 20405{ 20406 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), 20407 arm_parse_cpu, NULL}, 20408 {"march=", N_("<arch name>\t assemble for architecture <arch name>"), 20409 arm_parse_arch, NULL}, 20410 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), 20411 arm_parse_fpu, NULL}, 20412 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), 20413 arm_parse_float_abi, NULL}, 20414#ifdef OBJ_ELF 20415 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), 20416 arm_parse_eabi, NULL}, 20417#endif 20418 {NULL, NULL, 0, NULL} 20419}; 20420 20421int 20422md_parse_option (int c, char * arg) 20423{ 20424 struct arm_option_table *opt; 20425 const struct arm_legacy_option_table *fopt; 20426 struct arm_long_option_table *lopt; 20427 20428 switch (c) 20429 { 20430#ifdef OPTION_EB 20431 case OPTION_EB: 20432 target_big_endian = 1; 20433 break; 20434#endif 20435 20436#ifdef OPTION_EL 20437 case OPTION_EL: 20438 target_big_endian = 0; 20439 break; 20440#endif 20441 20442 case 'a': 20443 /* Listing option. Just ignore these, we don't support additional 20444 ones. */ 20445 return 0; 20446 20447 default: 20448 for (opt = arm_opts; opt->option != NULL; opt++) 20449 { 20450 if (c == opt->option[0] 20451 && ((arg == NULL && opt->option[1] == 0) 20452 || streq (arg, opt->option + 1))) 20453 { 20454#if WARN_DEPRECATED 20455 /* If the option is deprecated, tell the user. */ 20456 if (opt->deprecated != NULL) 20457 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20458 arg ? arg : "", _(opt->deprecated)); 20459#endif 20460 20461 if (opt->var != NULL) 20462 *opt->var = opt->value; 20463 20464 return 1; 20465 } 20466 } 20467 20468 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) 20469 { 20470 if (c == fopt->option[0] 20471 && ((arg == NULL && fopt->option[1] == 0) 20472 || streq (arg, fopt->option + 1))) 20473 { 20474#if WARN_DEPRECATED 20475 /* If the option is deprecated, tell the user. */ 20476 if (fopt->deprecated != NULL) 20477 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20478 arg ? arg : "", _(fopt->deprecated)); 20479#endif 20480 20481 if (fopt->var != NULL) 20482 *fopt->var = &fopt->value; 20483 20484 return 1; 20485 } 20486 } 20487 20488 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20489 { 20490 /* These options are expected to have an argument. */ 20491 if (c == lopt->option[0] 20492 && arg != NULL 20493 && strncmp (arg, lopt->option + 1, 20494 strlen (lopt->option + 1)) == 0) 20495 { 20496#if WARN_DEPRECATED 20497 /* If the option is deprecated, tell the user. */ 20498 if (lopt->deprecated != NULL) 20499 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, 20500 _(lopt->deprecated)); 20501#endif 20502 20503 /* Call the sup-option parser. */ 20504 return lopt->func (arg + strlen (lopt->option) - 1); 20505 } 20506 } 20507 20508 return 0; 20509 } 20510 20511 return 1; 20512} 20513 20514void 20515md_show_usage (FILE * fp) 20516{ 20517 struct arm_option_table *opt; 20518 struct arm_long_option_table *lopt; 20519 20520 fprintf (fp, _(" ARM-specific assembler options:\n")); 20521 20522 for (opt = arm_opts; opt->option != NULL; opt++) 20523 if (opt->help != NULL) 20524 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); 20525 20526 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20527 if (lopt->help != NULL) 20528 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); 20529 20530#ifdef OPTION_EB 20531 fprintf (fp, _("\ 20532 -EB assemble code for a big-endian cpu\n")); 20533#endif 20534 20535#ifdef OPTION_EL 20536 fprintf (fp, _("\ 20537 -EL assemble code for a little-endian cpu\n")); 20538#endif 20539} 20540 20541 20542#ifdef OBJ_ELF 20543typedef struct 20544{ 20545 int val; 20546 arm_feature_set flags; 20547} cpu_arch_ver_table; 20548 20549/* Mapping from CPU features to EABI CPU arch values. Table must be sorted 20550 least features first. */ 20551static const cpu_arch_ver_table cpu_arch_ver[] = 20552{ 20553 {1, ARM_ARCH_V4}, 20554 {2, ARM_ARCH_V4T}, 20555 {3, ARM_ARCH_V5}, 20556 {4, ARM_ARCH_V5TE}, 20557 {5, ARM_ARCH_V5TEJ}, 20558 {6, ARM_ARCH_V6}, 20559 {7, ARM_ARCH_V6Z}, 20560 {8, ARM_ARCH_V6K}, 20561 {9, ARM_ARCH_V6T2}, 20562 {10, ARM_ARCH_V7A}, 20563 {10, ARM_ARCH_V7R}, 20564 {10, ARM_ARCH_V7M}, 20565 {0, ARM_ARCH_NONE} 20566}; 20567 20568/* Set the public EABI object attributes. */ 20569static void 20570aeabi_set_public_attributes (void) 20571{ 20572 int arch; 20573 arm_feature_set flags; 20574 arm_feature_set tmp; 20575 const cpu_arch_ver_table *p; 20576 20577 /* Choose the architecture based on the capabilities of the requested cpu 20578 (if any) and/or the instructions actually used. */ 20579 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); 20580 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); 20581 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); 20582 /*Allow the user to override the reported architecture. */ 20583 if (object_arch) 20584 { 20585 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); 20586 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); 20587 } 20588 20589 tmp = flags; 20590 arch = 0; 20591 for (p = cpu_arch_ver; p->val; p++) 20592 { 20593 if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) 20594 { 20595 arch = p->val; 20596 ARM_CLEAR_FEATURE (tmp, tmp, p->flags); 20597 } 20598 } 20599 20600 /* Tag_CPU_name. */ 20601 if (selected_cpu_name[0]) 20602 { 20603 char *p; 20604 20605 p = selected_cpu_name; 20606 if (strncmp(p, "armv", 4) == 0) 20607 { 20608 int i; 20609 20610 p += 4; 20611 for (i = 0; p[i]; i++) 20612 p[i] = TOUPPER (p[i]); 20613 } 20614 bfd_elf_add_proc_attr_string (stdoutput, 5, p); 20615 } 20616 /* Tag_CPU_arch. */ 20617 bfd_elf_add_proc_attr_int (stdoutput, 6, arch); 20618 /* Tag_CPU_arch_profile. */ 20619 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) 20620 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A'); 20621 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) 20622 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R'); 20623 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)) 20624 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M'); 20625 /* Tag_ARM_ISA_use. */ 20626 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) 20627 bfd_elf_add_proc_attr_int (stdoutput, 8, 1); 20628 /* Tag_THUMB_ISA_use. */ 20629 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) 20630 bfd_elf_add_proc_attr_int (stdoutput, 9, 20631 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); 20632 /* Tag_VFP_arch. */ 20633 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3) 20634 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3)) 20635 bfd_elf_add_proc_attr_int (stdoutput, 10, 3); 20636 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2) 20637 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2)) 20638 bfd_elf_add_proc_attr_int (stdoutput, 10, 2); 20639 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1) 20640 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1) 20641 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd) 20642 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd)) 20643 bfd_elf_add_proc_attr_int (stdoutput, 10, 1); 20644 /* Tag_WMMX_arch. */ 20645 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) 20646 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) 20647 bfd_elf_add_proc_attr_int (stdoutput, 11, 1); 20648 /* Tag_NEON_arch. */ 20649 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1) 20650 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1)) 20651 bfd_elf_add_proc_attr_int (stdoutput, 12, 1); 20652} 20653 20654/* Add the default contents for the .ARM.attributes section. */ 20655void 20656arm_md_end (void) 20657{ 20658 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 20659 return; 20660 20661 aeabi_set_public_attributes (); 20662} 20663#endif /* OBJ_ELF */ 20664 20665 20666/* Parse a .cpu directive. */ 20667 20668static void 20669s_arm_cpu (int ignored ATTRIBUTE_UNUSED) 20670{ 20671 const struct arm_cpu_option_table *opt; 20672 char *name; 20673 char saved_char; 20674 20675 name = input_line_pointer; 20676 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20677 input_line_pointer++; 20678 saved_char = *input_line_pointer; 20679 *input_line_pointer = 0; 20680 20681 /* Skip the first "all" entry. */ 20682 for (opt = arm_cpus + 1; opt->name != NULL; opt++) 20683 if (streq (opt->name, name)) 20684 { 20685 mcpu_cpu_opt = &opt->value; 20686 selected_cpu = opt->value; 20687 if (opt->canonical_name) 20688 strcpy(selected_cpu_name, opt->canonical_name); 20689 else 20690 { 20691 int i; 20692 for (i = 0; opt->name[i]; i++) 20693 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20694 selected_cpu_name[i] = 0; 20695 } 20696 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20697 *input_line_pointer = saved_char; 20698 demand_empty_rest_of_line (); 20699 return; 20700 } 20701 as_bad (_("unknown cpu `%s'"), name); 20702 *input_line_pointer = saved_char; 20703 ignore_rest_of_line (); 20704} 20705 20706 20707/* Parse a .arch directive. */ 20708 20709static void 20710s_arm_arch (int ignored ATTRIBUTE_UNUSED) 20711{ 20712 const struct arm_arch_option_table *opt; 20713 char saved_char; 20714 char *name; 20715 20716 name = input_line_pointer; 20717 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20718 input_line_pointer++; 20719 saved_char = *input_line_pointer; 20720 *input_line_pointer = 0; 20721 20722 /* Skip the first "all" entry. */ 20723 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20724 if (streq (opt->name, name)) 20725 { 20726 mcpu_cpu_opt = &opt->value; 20727 selected_cpu = opt->value; 20728 strcpy(selected_cpu_name, opt->name); 20729 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20730 *input_line_pointer = saved_char; 20731 demand_empty_rest_of_line (); 20732 return; 20733 } 20734 20735 as_bad (_("unknown architecture `%s'\n"), name); 20736 *input_line_pointer = saved_char; 20737 ignore_rest_of_line (); 20738} 20739 20740 20741/* Parse a .object_arch directive. */ 20742 20743static void 20744s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) 20745{ 20746 const struct arm_arch_option_table *opt; 20747 char saved_char; 20748 char *name; 20749 20750 name = input_line_pointer; 20751 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20752 input_line_pointer++; 20753 saved_char = *input_line_pointer; 20754 *input_line_pointer = 0; 20755 20756 /* Skip the first "all" entry. */ 20757 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20758 if (streq (opt->name, name)) 20759 { 20760 object_arch = &opt->value; 20761 *input_line_pointer = saved_char; 20762 demand_empty_rest_of_line (); 20763 return; 20764 } 20765 20766 as_bad (_("unknown architecture `%s'\n"), name); 20767 *input_line_pointer = saved_char; 20768 ignore_rest_of_line (); 20769} 20770 20771 20772/* Parse a .fpu directive. */ 20773 20774static void 20775s_arm_fpu (int ignored ATTRIBUTE_UNUSED) 20776{ 20777 const struct arm_option_cpu_value_table *opt; 20778 char saved_char; 20779 char *name; 20780 20781 name = input_line_pointer; 20782 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20783 input_line_pointer++; 20784 saved_char = *input_line_pointer; 20785 *input_line_pointer = 0; 20786 20787 for (opt = arm_fpus; opt->name != NULL; opt++) 20788 if (streq (opt->name, name)) 20789 { 20790 mfpu_opt = &opt->value; 20791 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20792 *input_line_pointer = saved_char; 20793 demand_empty_rest_of_line (); 20794 return; 20795 } 20796 20797 as_bad (_("unknown floating point format `%s'\n"), name); 20798 *input_line_pointer = saved_char; 20799 ignore_rest_of_line (); 20800} 20801 20802/* Copy symbol information. */ 20803void 20804arm_copy_symbol_attributes (symbolS *dest, symbolS *src) 20805{ 20806 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); 20807} 20808