cap.c revision 240474
1/*- 2 * Copyright (c) 2007 Yahoo!, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#ifndef lint 32static const char rcsid[] = 33 "$FreeBSD: head/usr.sbin/pciconf/cap.c 240474 2012-09-13 19:08:31Z jhb $"; 34#endif /* not lint */ 35 36#include <sys/types.h> 37 38#include <err.h> 39#include <stdio.h> 40#include <sys/agpio.h> 41#include <sys/pciio.h> 42 43#include <dev/agp/agpreg.h> 44#include <dev/pci/pcireg.h> 45 46#include "pciconf.h" 47 48static void list_ecaps(int fd, struct pci_conf *p); 49 50static void 51cap_power(int fd, struct pci_conf *p, uint8_t ptr) 52{ 53 uint16_t cap, status; 54 55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 56 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 57 printf("powerspec %d supports D0%s%s D3 current D%d", 58 cap & PCIM_PCAP_SPEC, 59 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 60 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 61 status & PCIM_PSTAT_DMASK); 62} 63 64static void 65cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 66{ 67 uint32_t status, command; 68 69 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 70 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 71 printf("AGP "); 72 if (AGP_MODE_GET_MODE_3(status)) { 73 printf("v3 "); 74 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 75 printf("8x "); 76 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 77 printf("4x "); 78 } else { 79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 80 printf("4x "); 81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 82 printf("2x "); 83 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 84 printf("1x "); 85 } 86 if (AGP_MODE_GET_SBA(status)) 87 printf("SBA "); 88 if (AGP_MODE_GET_AGP(command)) { 89 printf("enabled at "); 90 if (AGP_MODE_GET_MODE_3(command)) { 91 printf("v3 "); 92 switch (AGP_MODE_GET_RATE(command)) { 93 case AGP_MODE_V3_RATE_8x: 94 printf("8x "); 95 break; 96 case AGP_MODE_V3_RATE_4x: 97 printf("4x "); 98 break; 99 } 100 } else 101 switch (AGP_MODE_GET_RATE(command)) { 102 case AGP_MODE_V2_RATE_4x: 103 printf("4x "); 104 break; 105 case AGP_MODE_V2_RATE_2x: 106 printf("2x "); 107 break; 108 case AGP_MODE_V2_RATE_1x: 109 printf("1x "); 110 break; 111 } 112 if (AGP_MODE_GET_SBA(command)) 113 printf("SBA "); 114 } else 115 printf("disabled"); 116} 117 118static void 119cap_vpd(int fd, struct pci_conf *p, uint8_t ptr) 120{ 121 122 printf("VPD"); 123} 124 125static void 126cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 127{ 128 uint16_t ctrl; 129 int msgnum; 130 131 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 132 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 133 printf("MSI supports %d message%s%s%s ", msgnum, 134 (msgnum == 1) ? "" : "s", 135 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 136 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 137 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 138 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 139 printf("enabled with %d message%s", msgnum, 140 (msgnum == 1) ? "" : "s"); 141 } 142} 143 144static void 145cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 146{ 147 uint32_t status; 148 int comma, max_splits, max_burst_read; 149 150 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 151 printf("PCI-X "); 152 if (status & PCIXM_STATUS_64BIT) 153 printf("64-bit "); 154 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 155 printf("bridge "); 156 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 157 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 158 printf("supports"); 159 comma = 0; 160 if (status & PCIXM_STATUS_133CAP) { 161 printf("%s 133MHz", comma ? "," : ""); 162 comma = 1; 163 } 164 if (status & PCIXM_STATUS_266CAP) { 165 printf("%s 266MHz", comma ? "," : ""); 166 comma = 1; 167 } 168 if (status & PCIXM_STATUS_533CAP) { 169 printf("%s 533MHz", comma ? "," : ""); 170 comma = 1; 171 } 172 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 173 return; 174 switch (status & PCIXM_STATUS_MAX_READ) { 175 case PCIXM_STATUS_MAX_READ_512: 176 max_burst_read = 512; 177 break; 178 case PCIXM_STATUS_MAX_READ_1024: 179 max_burst_read = 1024; 180 break; 181 case PCIXM_STATUS_MAX_READ_2048: 182 max_burst_read = 2048; 183 break; 184 case PCIXM_STATUS_MAX_READ_4096: 185 max_burst_read = 4096; 186 break; 187 } 188 switch (status & PCIXM_STATUS_MAX_SPLITS) { 189 case PCIXM_STATUS_MAX_SPLITS_1: 190 max_splits = 1; 191 break; 192 case PCIXM_STATUS_MAX_SPLITS_2: 193 max_splits = 2; 194 break; 195 case PCIXM_STATUS_MAX_SPLITS_3: 196 max_splits = 3; 197 break; 198 case PCIXM_STATUS_MAX_SPLITS_4: 199 max_splits = 4; 200 break; 201 case PCIXM_STATUS_MAX_SPLITS_8: 202 max_splits = 8; 203 break; 204 case PCIXM_STATUS_MAX_SPLITS_12: 205 max_splits = 12; 206 break; 207 case PCIXM_STATUS_MAX_SPLITS_16: 208 max_splits = 16; 209 break; 210 case PCIXM_STATUS_MAX_SPLITS_32: 211 max_splits = 32; 212 break; 213 } 214 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 215 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 216} 217 218static void 219cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 220{ 221 uint32_t reg; 222 uint16_t command; 223 224 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 225 printf("HT "); 226 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 227 printf("slave"); 228 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 229 printf("host"); 230 else 231 switch (command & PCIM_HTCMD_CAP_MASK) { 232 case PCIM_HTCAP_SWITCH: 233 printf("switch"); 234 break; 235 case PCIM_HTCAP_INTERRUPT: 236 printf("interrupt"); 237 break; 238 case PCIM_HTCAP_REVISION_ID: 239 printf("revision ID"); 240 break; 241 case PCIM_HTCAP_UNITID_CLUMPING: 242 printf("unit ID clumping"); 243 break; 244 case PCIM_HTCAP_EXT_CONFIG_SPACE: 245 printf("extended config space"); 246 break; 247 case PCIM_HTCAP_ADDRESS_MAPPING: 248 printf("address mapping"); 249 break; 250 case PCIM_HTCAP_MSI_MAPPING: 251 printf("MSI %saddress window %s at 0x", 252 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 253 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 254 "disabled"); 255 if (command & PCIM_HTCMD_MSI_FIXED) 256 printf("fee00000"); 257 else { 258 reg = read_config(fd, &p->pc_sel, 259 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 260 if (reg != 0) 261 printf("%08x", reg); 262 reg = read_config(fd, &p->pc_sel, 263 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 264 printf("%08x", reg); 265 } 266 break; 267 case PCIM_HTCAP_DIRECT_ROUTE: 268 printf("direct route"); 269 break; 270 case PCIM_HTCAP_VCSET: 271 printf("VC set"); 272 break; 273 case PCIM_HTCAP_RETRY_MODE: 274 printf("retry mode"); 275 break; 276 case PCIM_HTCAP_X86_ENCODING: 277 printf("X86 encoding"); 278 break; 279 default: 280 printf("unknown %02x", command); 281 break; 282 } 283} 284 285static void 286cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 287{ 288 uint8_t length; 289 290 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 291 printf("vendor (length %d)", length); 292 if (p->pc_vendor == 0x8086) { 293 /* Intel */ 294 uint8_t version; 295 296 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 297 1); 298 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 299 if (version >> 4 == 1 && length == 12) { 300 /* Feature Detection */ 301 uint32_t fvec; 302 int comma; 303 304 comma = 0; 305 fvec = read_config(fd, &p->pc_sel, ptr + 306 PCIR_VENDOR_DATA + 5, 4); 307 printf("\n\t\t features:"); 308 if (fvec & (1 << 0)) { 309 printf(" AMT"); 310 comma = 1; 311 } 312 fvec = read_config(fd, &p->pc_sel, ptr + 313 PCIR_VENDOR_DATA + 1, 4); 314 if (fvec & (1 << 21)) { 315 printf("%s Quick Resume", comma ? "," : ""); 316 comma = 1; 317 } 318 if (fvec & (1 << 18)) { 319 printf("%s SATA RAID-5", comma ? "," : ""); 320 comma = 1; 321 } 322 if (fvec & (1 << 9)) { 323 printf("%s Mobile", comma ? "," : ""); 324 comma = 1; 325 } 326 if (fvec & (1 << 7)) { 327 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 328 comma = 1; 329 } else { 330 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 331 comma = 1; 332 } 333 if (fvec & (1 << 5)) { 334 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 335 comma = 1; 336 } 337 if (fvec & (1 << 3)) { 338 printf("%s SATA AHCI", comma ? "," : ""); 339 comma = 1; 340 } 341 } 342 } 343} 344 345static void 346cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 347{ 348 uint16_t debug_port; 349 350 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 351 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 352 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 353} 354 355static void 356cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 357{ 358 uint32_t id; 359 360 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 361 printf("PCI Bridge card=0x%08x", id); 362} 363 364#define MAX_PAYLOAD(field) (128 << (field)) 365 366static void 367cap_express(int fd, struct pci_conf *p, uint8_t ptr) 368{ 369 uint32_t val; 370 uint16_t flags; 371 372 flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2); 373 printf("PCI-Express %d ", flags & PCIM_EXP_FLAGS_VERSION); 374 switch (flags & PCIM_EXP_FLAGS_TYPE) { 375 case PCIM_EXP_TYPE_ENDPOINT: 376 printf("endpoint"); 377 break; 378 case PCIM_EXP_TYPE_LEGACY_ENDPOINT: 379 printf("legacy endpoint"); 380 break; 381 case PCIM_EXP_TYPE_ROOT_PORT: 382 printf("root port"); 383 break; 384 case PCIM_EXP_TYPE_UPSTREAM_PORT: 385 printf("upstream port"); 386 break; 387 case PCIM_EXP_TYPE_DOWNSTREAM_PORT: 388 printf("downstream port"); 389 break; 390 case PCIM_EXP_TYPE_PCI_BRIDGE: 391 printf("PCI bridge"); 392 break; 393 case PCIM_EXP_TYPE_PCIE_BRIDGE: 394 printf("PCI to PCIe bridge"); 395 break; 396 case PCIM_EXP_TYPE_ROOT_INT_EP: 397 printf("root endpoint"); 398 break; 399 case PCIM_EXP_TYPE_ROOT_EC: 400 printf("event collector"); 401 break; 402 default: 403 printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 4); 404 break; 405 } 406 if (flags & PCIM_EXP_FLAGS_SLOT) 407 printf(" slot"); 408 if (flags & PCIM_EXP_FLAGS_IRQ) 409 printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 9); 410 val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CAP, 4); 411 flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CTL, 2); 412 printf(" max data %d(%d)", 413 MAX_PAYLOAD((flags & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5), 414 MAX_PAYLOAD(val & PCIM_EXP_CAP_MAX_PAYLOAD)); 415 if (val & PCIM_EXP_CAP_FLR) 416 printf(" FLR"); 417 val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_LINK_CAP, 4); 418 flags = read_config(fd, &p->pc_sel, ptr+ PCIR_EXPRESS_LINK_STA, 2); 419 printf(" link x%d(x%d)", (flags & PCIM_LINK_STA_WIDTH) >> 4, 420 (val & PCIM_LINK_CAP_MAX_WIDTH) >> 4); 421} 422 423static void 424cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 425{ 426 uint32_t val; 427 uint16_t ctrl; 428 int msgnum, table_bar, pba_bar; 429 430 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 431 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 432 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 433 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 434 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 435 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 436 printf("MSI-X supports %d message%s ", msgnum, 437 (msgnum == 1) ? "" : "s"); 438 if (table_bar == pba_bar) 439 printf("in map 0x%x", table_bar); 440 else 441 printf("in maps 0x%x and 0x%x", table_bar, pba_bar); 442 if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) 443 printf(" enabled"); 444} 445 446static void 447cap_sata(int fd, struct pci_conf *p, uint8_t ptr) 448{ 449 450 printf("SATA Index-Data Pair"); 451} 452 453static void 454cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 455{ 456 uint8_t cap; 457 458 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 459 printf("PCI Advanced Features:%s%s", 460 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 461 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 462} 463 464void 465list_caps(int fd, struct pci_conf *p) 466{ 467 int express; 468 uint16_t sta; 469 uint8_t ptr, cap; 470 471 /* Are capabilities present for this device? */ 472 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 473 if (!(sta & PCIM_STATUS_CAPPRESENT)) 474 return; 475 476 switch (p->pc_hdr & PCIM_HDRTYPE) { 477 case PCIM_HDRTYPE_NORMAL: 478 case PCIM_HDRTYPE_BRIDGE: 479 ptr = PCIR_CAP_PTR; 480 break; 481 case PCIM_HDRTYPE_CARDBUS: 482 ptr = PCIR_CAP_PTR_2; 483 break; 484 default: 485 errx(1, "list_caps: bad header type"); 486 } 487 488 /* Walk the capability list. */ 489 express = 0; 490 ptr = read_config(fd, &p->pc_sel, ptr, 1); 491 while (ptr != 0 && ptr != 0xff) { 492 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 493 printf(" cap %02x[%02x] = ", cap, ptr); 494 switch (cap) { 495 case PCIY_PMG: 496 cap_power(fd, p, ptr); 497 break; 498 case PCIY_AGP: 499 cap_agp(fd, p, ptr); 500 break; 501 case PCIY_VPD: 502 cap_vpd(fd, p, ptr); 503 break; 504 case PCIY_MSI: 505 cap_msi(fd, p, ptr); 506 break; 507 case PCIY_PCIX: 508 cap_pcix(fd, p, ptr); 509 break; 510 case PCIY_HT: 511 cap_ht(fd, p, ptr); 512 break; 513 case PCIY_VENDOR: 514 cap_vendor(fd, p, ptr); 515 break; 516 case PCIY_DEBUG: 517 cap_debug(fd, p, ptr); 518 break; 519 case PCIY_SUBVENDOR: 520 cap_subvendor(fd, p, ptr); 521 break; 522 case PCIY_EXPRESS: 523 express = 1; 524 cap_express(fd, p, ptr); 525 break; 526 case PCIY_MSIX: 527 cap_msix(fd, p, ptr); 528 break; 529 case PCIY_SATA: 530 cap_sata(fd, p, ptr); 531 break; 532 case PCIY_PCIAF: 533 cap_pciaf(fd, p, ptr); 534 break; 535 default: 536 printf("unknown"); 537 break; 538 } 539 printf("\n"); 540 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 541 } 542 543 if (express) 544 list_ecaps(fd, p); 545} 546 547/* From <sys/systm.h>. */ 548static __inline uint32_t 549bitcount32(uint32_t x) 550{ 551 552 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 553 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 554 x = (x + (x >> 4)) & 0x0f0f0f0f; 555 x = (x + (x >> 8)); 556 x = (x + (x >> 16)) & 0x000000ff; 557 return (x); 558} 559 560static void 561ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 562{ 563 uint32_t sta, mask; 564 565 printf("AER %d", ver); 566 if (ver < 1) 567 return; 568 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 569 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 570 printf(" %d fatal", bitcount32(sta & mask)); 571 printf(" %d non-fatal", bitcount32(sta & ~mask)); 572 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 573 printf(" %d corrected", bitcount32(sta)); 574} 575 576static void 577ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 578{ 579 uint32_t cap1; 580 581 printf("VC %d", ver); 582 if (ver < 1) 583 return; 584 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 585 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 586 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 587 printf(" lowpri VC0-VC%d", 588 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 589} 590 591static void 592ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 593{ 594 uint32_t high, low; 595 596 printf("Serial %d", ver); 597 if (ver < 1) 598 return; 599 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 600 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 601 printf(" %08x%08x", high, low); 602} 603 604static void 605ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 606{ 607 uint32_t val; 608 609 printf("Vendor %d", ver); 610 if (ver < 1) 611 return; 612 val = read_config(fd, &p->pc_sel, ptr + 4, 4); 613 printf(" ID %d", val & 0xffff); 614} 615 616static void 617ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 618{ 619 uint32_t val; 620 621 printf("PCIe Sec %d", ver); 622 if (ver < 1) 623 return; 624 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 625 printf(" lane errors %#x", val); 626} 627 628struct { 629 uint16_t id; 630 const char *name; 631} ecap_names[] = { 632 { PCIZ_PWRBDGT, "Power Budgeting" }, 633 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 634 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 635 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 636 { PCIZ_MFVC, "MFVC" }, 637 { PCIZ_RCRB, "RCRB" }, 638 { PCIZ_ACS, "ACS" }, 639 { PCIZ_ARI, "ARI" }, 640 { PCIZ_ATS, "ATS" }, 641 { PCIZ_SRIOV, "SRIOV" }, 642 { PCIZ_MULTICAST, "Multicast" }, 643 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 644 { PCIZ_DPA, "DPA" }, 645 { PCIZ_TPH_REQ, "TPH Requester" }, 646 { PCIZ_LTR, "LTR" }, 647 { 0, NULL } 648}; 649 650static void 651list_ecaps(int fd, struct pci_conf *p) 652{ 653 const char *name; 654 uint32_t ecap; 655 uint16_t ptr; 656 int i; 657 658 ptr = PCIR_EXTCAP; 659 ecap = read_config(fd, &p->pc_sel, ptr, 4); 660 if (ecap == 0xffffffff || ecap == 0) 661 return; 662 for (;;) { 663 printf("ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 664 switch (PCI_EXTCAP_ID(ecap)) { 665 case PCIZ_AER: 666 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 667 break; 668 case PCIZ_VC: 669 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 670 break; 671 case PCIZ_SERNUM: 672 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 673 break; 674 case PCIZ_VENDOR: 675 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 676 break; 677 case PCIZ_SEC_PCIE: 678 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 679 break; 680 default: 681 name = "unknown"; 682 for (i = 0; ecap_names[i].name != NULL; i++) 683 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 684 name = ecap_names[i].name; 685 break; 686 } 687 printf("%s %d", name, PCI_EXTCAP_VER(ecap)); 688 break; 689 } 690 printf("\n"); 691 ptr = PCI_EXTCAP_NEXTPTR(ecap); 692 if (ptr == 0) 693 break; 694 ecap = read_config(fd, &p->pc_sel, ptr, 4); 695 } 696} 697 698/* Find offset of a specific capability. Returns 0 on failure. */ 699uint8_t 700pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 701{ 702 uint16_t sta; 703 uint8_t ptr, cap; 704 705 /* Are capabilities present for this device? */ 706 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 707 if (!(sta & PCIM_STATUS_CAPPRESENT)) 708 return (0); 709 710 switch (p->pc_hdr & PCIM_HDRTYPE) { 711 case PCIM_HDRTYPE_NORMAL: 712 case PCIM_HDRTYPE_BRIDGE: 713 ptr = PCIR_CAP_PTR; 714 break; 715 case PCIM_HDRTYPE_CARDBUS: 716 ptr = PCIR_CAP_PTR_2; 717 break; 718 default: 719 return (0); 720 } 721 722 ptr = read_config(fd, &p->pc_sel, ptr, 1); 723 while (ptr != 0 && ptr != 0xff) { 724 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 725 if (cap == id) 726 return (ptr); 727 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 728 } 729 return (0); 730} 731 732/* Find offset of a specific extended capability. Returns 0 on failure. */ 733uint16_t 734pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 735{ 736 uint32_t ecap; 737 uint16_t ptr; 738 739 ptr = PCIR_EXTCAP; 740 ecap = read_config(fd, &p->pc_sel, ptr, 4); 741 if (ecap == 0xffffffff || ecap == 0) 742 return (0); 743 for (;;) { 744 if (PCI_EXTCAP_ID(ecap) == id) 745 return (ptr); 746 ptr = PCI_EXTCAP_NEXTPTR(ecap); 747 if (ptr == 0) 748 break; 749 ecap = read_config(fd, &p->pc_sel, ptr, 4); 750 } 751 return (0); 752} 753