1221828Sgrehan/*-
2221828Sgrehan * Copyright (c) 2011 NetApp, Inc.
3221828Sgrehan * All rights reserved.
4221828Sgrehan *
5221828Sgrehan * Redistribution and use in source and binary forms, with or without
6221828Sgrehan * modification, are permitted provided that the following conditions
7221828Sgrehan * are met:
8221828Sgrehan * 1. Redistributions of source code must retain the above copyright
9221828Sgrehan *    notice, this list of conditions and the following disclaimer.
10221828Sgrehan * 2. Redistributions in binary form must reproduce the above copyright
11221828Sgrehan *    notice, this list of conditions and the following disclaimer in the
12221828Sgrehan *    documentation and/or other materials provided with the distribution.
13221828Sgrehan *
14221828Sgrehan * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15221828Sgrehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16221828Sgrehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17221828Sgrehan * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18221828Sgrehan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19221828Sgrehan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20221828Sgrehan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21221828Sgrehan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22221828Sgrehan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23221828Sgrehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24221828Sgrehan * SUCH DAMAGE.
25221828Sgrehan *
26221828Sgrehan * $FreeBSD$
27221828Sgrehan */
28221828Sgrehan
29221828Sgrehan#include <sys/cdefs.h>
30221828Sgrehan__FBSDID("$FreeBSD$");
31221828Sgrehan
32221828Sgrehan#include <sys/types.h>
33221828Sgrehan
34221828Sgrehan#include "inout.h"
35221828Sgrehan
36221828Sgrehan/*
37221828Sgrehan * EISA interrupt Level Control Register.
38221828Sgrehan *
39221828Sgrehan * This is a 16-bit register with one bit for each of the IRQ0 through IRQ15.
40221828Sgrehan * A level triggered irq is indicated by setting the corresponding bit to '1'.
41221828Sgrehan */
42221828Sgrehan#define	ELCR_PORT	0x4d0
43221828Sgrehan
44221828Sgrehanstatic uint8_t elcr[2] = { 0x00, 0x00 };
45221828Sgrehan
46221828Sgrehanstatic int
47221828Sgrehanelcr_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
48221828Sgrehan	     uint32_t *eax, void *arg)
49221828Sgrehan{
50221828Sgrehan	int idx;
51221828Sgrehan
52221828Sgrehan	if (bytes != 1)
53221828Sgrehan		return (-1);
54221828Sgrehan
55221828Sgrehan	idx = port - ELCR_PORT;
56221828Sgrehan
57221828Sgrehan	if (in)
58221828Sgrehan		*eax = elcr[idx];
59221828Sgrehan	else
60221828Sgrehan		elcr[idx] = *eax;
61221828Sgrehan
62221828Sgrehan	return (0);
63221828Sgrehan}
64221828SgrehanINOUT_PORT(elcr, ELCR_PORT + 0, IOPORT_F_INOUT, elcr_handler);
65221828SgrehanINOUT_PORT(elcr, ELCR_PORT + 1, IOPORT_F_INOUT, elcr_handler);
66