pci_fdt.c revision 218075
1/*- 2 * Copyright 2006-2007 by Juniper Networks. 3 * Copyright 2008 Semihalf. 4 * Copyright 2010 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Semihalf 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 34 */ 35 36#include <sys/cdefs.h> 37__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/pci_fdt.c 218075 2011-01-29 20:58:38Z marcel $"); 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/ktr.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <sys/socket.h> 48#include <sys/queue.h> 49#include <sys/bus.h> 50#include <sys/lock.h> 51#include <sys/mutex.h> 52#include <sys/rman.h> 53#include <sys/endian.h> 54 55#include <vm/vm.h> 56#include <vm/pmap.h> 57 58#include <dev/fdt/fdt_common.h> 59#include <dev/ofw/ofw_bus.h> 60#include <dev/ofw/ofw_bus_subr.h> 61#include <dev/pci/pcivar.h> 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcib_private.h> 64 65#include "ofw_bus_if.h" 66#include "pcib_if.h" 67 68#include <machine/resource.h> 69#include <machine/bus.h> 70#include <machine/intr_machdep.h> 71 72#include <powerpc/mpc85xx/mpc85xx.h> 73 74#define REG_CFG_ADDR 0x0000 75#define CONFIG_ACCESS_ENABLE 0x80000000 76 77#define REG_CFG_DATA 0x0004 78#define REG_INT_ACK 0x0008 79 80#define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 81#define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 82#define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 83#define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 84 85#define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 86#define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 87#define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 88#define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 89 90#define REG_PEX_MES_DR 0x0020 91#define REG_PEX_MES_IER 0x0028 92#define REG_PEX_ERR_DR 0x0e00 93#define REG_PEX_ERR_EN 0x0e08 94 95#define PCIR_LTSSM 0x404 96#define LTSSM_STAT_L0 0x16 97 98#define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 99 100struct fsl_pcib_softc { 101 device_t sc_dev; 102 103 struct rman sc_iomem; 104 bus_addr_t sc_iomem_va; /* Virtual mapping. */ 105 bus_addr_t sc_iomem_size; 106 bus_addr_t sc_iomem_alloc; /* Next allocation. */ 107 int sc_iomem_target; 108 struct rman sc_ioport; 109 bus_addr_t sc_ioport_va; /* Virtual mapping. */ 110 bus_addr_t sc_ioport_size; 111 bus_addr_t sc_ioport_alloc; /* Next allocation. */ 112 int sc_ioport_target; 113 114 struct resource *sc_res; 115 bus_space_handle_t sc_bsh; 116 bus_space_tag_t sc_bst; 117 int sc_rid; 118 119 int sc_busnr; 120 int sc_pcie; 121 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 122 123 /* Devices that need special attention. */ 124 int sc_devfn_tundra; 125 int sc_devfn_via_ide; 126 127 struct fdt_pci_intr sc_intr_info; 128}; 129 130/* Local forward declerations. */ 131static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 132 u_int, int); 133static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 134 u_int, uint32_t, int); 135static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 136static void fsl_pcib_err_init(device_t); 137static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long, 138 u_long, u_long); 139static int fsl_pcib_init(struct fsl_pcib_softc *, int, int); 140static int fsl_pcib_intr_info(phandle_t, struct fsl_pcib_softc *); 141static int fsl_pcib_set_range(struct fsl_pcib_softc *, int, int, u_long, 142 u_long); 143static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, u_long, 144 u_long, u_long); 145 146/* Forward declerations. */ 147static int fsl_pcib_attach(device_t); 148static int fsl_pcib_detach(device_t); 149static int fsl_pcib_probe(device_t); 150 151static struct resource *fsl_pcib_alloc_resource(device_t, device_t, int, int *, 152 u_long, u_long, u_long, u_int); 153static int fsl_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 154static int fsl_pcib_release_resource(device_t, device_t, int, int, 155 struct resource *); 156static int fsl_pcib_write_ivar(device_t, device_t, int, uintptr_t); 157 158static int fsl_pcib_maxslots(device_t); 159static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 160static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 161 uint32_t, int); 162 163/* Configuration r/w mutex. */ 164struct mtx pcicfg_mtx; 165static int mtx_initialized = 0; 166 167/* 168 * Bus interface definitions. 169 */ 170static device_method_t fsl_pcib_methods[] = { 171 /* Device interface */ 172 DEVMETHOD(device_probe, fsl_pcib_probe), 173 DEVMETHOD(device_attach, fsl_pcib_attach), 174 DEVMETHOD(device_detach, fsl_pcib_detach), 175 176 /* Bus interface */ 177 DEVMETHOD(bus_print_child, bus_generic_print_child), 178 DEVMETHOD(bus_read_ivar, fsl_pcib_read_ivar), 179 DEVMETHOD(bus_write_ivar, fsl_pcib_write_ivar), 180 DEVMETHOD(bus_alloc_resource, fsl_pcib_alloc_resource), 181 DEVMETHOD(bus_release_resource, fsl_pcib_release_resource), 182 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 183 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 184 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 185 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 186 187 /* pcib interface */ 188 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 189 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 190 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 191 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 192 193 /* OFW bus interface */ 194 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 195 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 196 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 197 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 198 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 199 200 { 0, 0 } 201}; 202 203static driver_t fsl_pcib_driver = { 204 "pcib", 205 fsl_pcib_methods, 206 sizeof(struct fsl_pcib_softc), 207}; 208 209devclass_t pcib_devclass; 210 211DRIVER_MODULE(pcib, fdtbus, fsl_pcib_driver, pcib_devclass, 0, 0); 212 213static int 214fsl_pcib_probe(device_t dev) 215{ 216 phandle_t node; 217 218 node = ofw_bus_get_node(dev); 219 if (!fdt_is_type(node, "pci")) 220 return (ENXIO); 221 222 if (!(fdt_is_compatible(node, "fsl,mpc8540-pci") || 223 fdt_is_compatible(node, "fsl,mpc8548-pcie"))) 224 return (ENXIO); 225 226 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 227 return (BUS_PROBE_DEFAULT); 228} 229 230static int 231fsl_pcib_attach(device_t dev) 232{ 233 struct fsl_pcib_softc *sc; 234 phandle_t node; 235 uint32_t cfgreg; 236 int maxslot; 237 uint8_t ltssm, capptr; 238 239 sc = device_get_softc(dev); 240 sc->sc_dev = dev; 241 242 sc->sc_rid = 0; 243 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 244 RF_ACTIVE); 245 if (sc->sc_res == NULL) { 246 device_printf(dev, "could not map I/O memory\n"); 247 return (ENXIO); 248 } 249 sc->sc_bst = rman_get_bustag(sc->sc_res); 250 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 251 sc->sc_busnr = 0; 252 253 if (!mtx_initialized) { 254 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 255 mtx_initialized = 1; 256 } 257 258 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 259 if (cfgreg != 0x1057 && cfgreg != 0x1957) 260 goto err; 261 262 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 263 while (capptr != 0) { 264 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 265 switch (cfgreg & 0xff) { 266 case PCIY_PCIX: 267 break; 268 case PCIY_EXPRESS: 269 sc->sc_pcie = 1; 270 sc->sc_pcie_capreg = capptr; 271 break; 272 } 273 capptr = (cfgreg >> 8) & 0xff; 274 } 275 276 node = ofw_bus_get_node(dev); 277 /* 278 * Get PCI interrupt info. 279 */ 280 if (fsl_pcib_intr_info(node, sc) != 0) { 281 device_printf(dev, "could not retrieve interrupt info\n"); 282 goto err; 283 } 284 285 /* 286 * Configure decode windows for PCI(E) access. 287 */ 288 if (fsl_pcib_decode_win(node, sc) != 0) 289 goto err; 290 291 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 292 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 293 PCIM_CMD_PORTEN; 294 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 295 296 sc->sc_devfn_tundra = -1; 297 sc->sc_devfn_via_ide = -1; 298 299 300 /* 301 * Scan bus using firmware configured, 0 based bus numbering. 302 */ 303 sc->sc_busnr = 0; 304 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX; 305 fsl_pcib_init(sc, sc->sc_busnr, maxslot); 306 307 if (sc->sc_pcie) { 308 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 309 if (ltssm < LTSSM_STAT_L0) { 310 if (bootverbose) 311 printf("PCI %d: no PCIE link, skipping\n", 312 device_get_unit(dev)); 313 return (0); 314 } 315 } 316 317 fsl_pcib_err_init(dev); 318 319 device_add_child(dev, "pci", -1); 320 return (bus_generic_attach(dev)); 321 322err: 323 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res); 324 return (ENXIO); 325} 326 327static uint32_t 328fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 329 u_int reg, int bytes) 330{ 331 uint32_t addr, data; 332 333 if (bus == sc->sc_busnr - 1) 334 bus = 0; 335 336 addr = CONFIG_ACCESS_ENABLE; 337 addr |= (bus & 0xff) << 16; 338 addr |= (slot & 0x1f) << 11; 339 addr |= (func & 0x7) << 8; 340 addr |= reg & 0xfc; 341 if (sc->sc_pcie) 342 addr |= (reg & 0xf00) << 16; 343 344 mtx_lock_spin(&pcicfg_mtx); 345 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 346 347 switch (bytes) { 348 case 1: 349 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 350 REG_CFG_DATA + (reg & 3)); 351 break; 352 case 2: 353 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 354 REG_CFG_DATA + (reg & 2))); 355 break; 356 case 4: 357 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 358 REG_CFG_DATA)); 359 break; 360 default: 361 data = ~0; 362 break; 363 } 364 mtx_unlock_spin(&pcicfg_mtx); 365 return (data); 366} 367 368static void 369fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 370 u_int reg, uint32_t data, int bytes) 371{ 372 uint32_t addr; 373 374 if (bus == sc->sc_busnr - 1) 375 bus = 0; 376 377 addr = CONFIG_ACCESS_ENABLE; 378 addr |= (bus & 0xff) << 16; 379 addr |= (slot & 0x1f) << 11; 380 addr |= (func & 0x7) << 8; 381 addr |= reg & 0xfc; 382 if (sc->sc_pcie) 383 addr |= (reg & 0xf00) << 16; 384 385 mtx_lock_spin(&pcicfg_mtx); 386 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 387 388 switch (bytes) { 389 case 1: 390 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 391 REG_CFG_DATA + (reg & 3), data); 392 break; 393 case 2: 394 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 395 REG_CFG_DATA + (reg & 2), htole16(data)); 396 break; 397 case 4: 398 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 399 REG_CFG_DATA, htole32(data)); 400 break; 401 } 402 mtx_unlock_spin(&pcicfg_mtx); 403} 404 405#if 0 406static void 407dump(struct fsl_pcib_softc *sc) 408{ 409 unsigned int i; 410 411#define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 412 for (i = 0; i < 5; i++) { 413 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 414 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 415 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 416 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 417 } 418 printf("\n"); 419 for (i = 1; i < 4; i++) { 420 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 421 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 422 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 423 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 424 } 425 printf("\n"); 426#undef RD 427 428 for (i = 0; i < 0x48; i += 4) { 429 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 430 i, 4)); 431 } 432} 433#endif 434 435static int 436fsl_pcib_maxslots(device_t dev) 437{ 438 struct fsl_pcib_softc *sc = device_get_softc(dev); 439 440 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 441} 442 443static uint32_t 444fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 445 u_int reg, int bytes) 446{ 447 struct fsl_pcib_softc *sc = device_get_softc(dev); 448 u_int devfn; 449 450 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 451 return (~0); 452 devfn = DEVFN(bus, slot, func); 453 if (devfn == sc->sc_devfn_tundra) 454 return (~0); 455 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 456 return (1); 457 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 458} 459 460static void 461fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 462 u_int reg, uint32_t val, int bytes) 463{ 464 struct fsl_pcib_softc *sc = device_get_softc(dev); 465 466 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 467 return; 468 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 469} 470 471static void 472fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus, 473 int slot, int fn) 474{ 475 476 if (device == 0x0686) { 477 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 478 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 479 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 480 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 481 } else if (device == 0x0571) { 482 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 483 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 484 } 485} 486 487static int 488fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func, 489 int barno) 490{ 491 bus_addr_t *allocp; 492 uint32_t addr, mask, size; 493 int reg, width; 494 495 reg = PCIR_BAR(barno); 496 497 if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) { 498 switch (barno) { 499 case 0: addr = 0x1f0; break; 500 case 1: addr = 0x3f4; break; 501 case 2: addr = 0x170; break; 502 case 3: addr = 0x374; break; 503 case 4: addr = 0xcc0; break; 504 default: return (1); 505 } 506 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 507 return (1); 508 } 509 510 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 511 size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 512 if (size == 0) 513 return (1); 514 width = ((size & 7) == 4) ? 2 : 1; 515 516 if (size & 1) { /* I/O port */ 517 allocp = &sc->sc_ioport_alloc; 518 size &= ~3; 519 if ((size & 0xffff0000) == 0) 520 size |= 0xffff0000; 521 } else { /* memory */ 522 allocp = &sc->sc_iomem_alloc; 523 size &= ~15; 524 } 525 mask = ~size; 526 size = mask + 1; 527 /* Sanity check (must be a power of 2). */ 528 if (size & mask) 529 return (width); 530 531 addr = (*allocp + mask) & ~mask; 532 *allocp = addr + size; 533 534 if (bootverbose) 535 printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n", 536 device_get_unit(sc->sc_dev), bus, slot, func, reg, 537 size, addr); 538 539 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 540 if (width == 2) 541 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 542 0, 4); 543 return (width); 544} 545 546static u_int 547fsl_pcib_route_int(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 548 u_int intpin) 549{ 550 int err, unit; 551 u_int devfn, intline; 552 553 unit = device_get_unit(sc->sc_dev); 554 555 devfn = DEVFN(bus, slot, func); 556 if (devfn == sc->sc_devfn_via_ide) 557 intline = INTR_VEC(0, 14); 558 else if (devfn == sc->sc_devfn_via_ide + 1) 559 intline = INTR_VEC(0, 10); 560 else if (devfn == sc->sc_devfn_via_ide + 2) 561 intline = INTR_VEC(0, 10); 562 else { 563 if (intpin != 0) 564 err = fdt_pci_route_intr(bus, slot, func, intpin, 565 &sc->sc_intr_info, &intline); 566 else 567 intline = 0xff; 568 } 569 570 if (bootverbose) 571 printf("PCI %u:%u:%u:%u: intpin %u: intline=%u\n", 572 unit, bus, slot, func, intpin, intline); 573 574 return (intline); 575} 576 577static int 578fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot) 579{ 580 int secbus; 581 int old_pribus, old_secbus, old_subbus; 582 int new_pribus, new_secbus, new_subbus; 583 int slot, func, maxfunc; 584 int bar, maxbar; 585 uint16_t vendor, device; 586 uint8_t command, hdrtype, class, subclass; 587 uint8_t intline, intpin; 588 589 secbus = bus; 590 for (slot = 0; slot <= maxslot; slot++) { 591 maxfunc = 0; 592 for (func = 0; func <= maxfunc; func++) { 593 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot, 594 func, PCIR_HDRTYPE, 1); 595 596 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 597 continue; 598 599 if (func == 0 && (hdrtype & PCIM_MFDEV)) 600 maxfunc = PCI_FUNCMAX; 601 602 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot, 603 func, PCIR_VENDOR, 2); 604 device = fsl_pcib_read_config(sc->sc_dev, bus, slot, 605 func, PCIR_DEVICE, 2); 606 607 if (vendor == 0x1957 && device == 0x3fff) { 608 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 609 continue; 610 } 611 612 command = fsl_pcib_read_config(sc->sc_dev, bus, slot, 613 func, PCIR_COMMAND, 1); 614 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 615 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 616 PCIR_COMMAND, command, 1); 617 618 if (vendor == 0x1106) 619 fsl_pcib_init_via(sc, device, bus, slot, func); 620 621 /* Program the base address registers. */ 622 maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6; 623 bar = 0; 624 while (bar < maxbar) 625 bar += fsl_pcib_init_bar(sc, bus, slot, func, 626 bar); 627 628 /* Perform interrupt routing. */ 629 intpin = fsl_pcib_read_config(sc->sc_dev, bus, slot, 630 func, PCIR_INTPIN, 1); 631 intline = fsl_pcib_route_int(sc, bus, slot, func, 632 intpin); 633 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 634 PCIR_INTLINE, intline, 1); 635 636 command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 637 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 638 PCIR_COMMAND, command, 1); 639 640 /* 641 * Handle PCI-PCI bridges 642 */ 643 class = fsl_pcib_read_config(sc->sc_dev, bus, slot, 644 func, PCIR_CLASS, 1); 645 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot, 646 func, PCIR_SUBCLASS, 1); 647 648 /* Allow only proper PCI-PCI briges */ 649 if (class != PCIC_BRIDGE) 650 continue; 651 if (subclass != PCIS_BRIDGE_PCI) 652 continue; 653 654 secbus++; 655 656 /* Program I/O decoder. */ 657 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 658 PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1); 659 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 660 PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1); 661 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 662 PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2); 663 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 664 PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2); 665 666 /* Program (non-prefetchable) memory decoder. */ 667 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 668 PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2); 669 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 670 PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2); 671 672 /* Program prefetchable memory decoder. */ 673 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 674 PCIR_PMBASEL_1, 0x0010, 2); 675 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 676 PCIR_PMLIMITL_1, 0x000f, 2); 677 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 678 PCIR_PMBASEH_1, 0x00000000, 4); 679 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 680 PCIR_PMLIMITH_1, 0x00000000, 4); 681 682 /* Read currect bus register configuration */ 683 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus, 684 slot, func, PCIR_PRIBUS_1, 1); 685 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus, 686 slot, func, PCIR_SECBUS_1, 1); 687 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus, 688 slot, func, PCIR_SUBBUS_1, 1); 689 690 if (bootverbose) 691 printf("PCI: reading firmware bus numbers for " 692 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n", 693 secbus, old_pribus, old_secbus, old_subbus); 694 695 new_pribus = bus; 696 new_secbus = secbus; 697 698 secbus = fsl_pcib_init(sc, secbus, 699 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0); 700 701 new_subbus = secbus; 702 703 if (bootverbose) 704 printf("PCI: translate firmware bus numbers " 705 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n", 706 secbus, old_pribus, old_secbus, old_subbus, 707 new_pribus, new_secbus, new_subbus); 708 709 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 710 PCIR_PRIBUS_1, new_pribus, 1); 711 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 712 PCIR_SECBUS_1, new_secbus, 1); 713 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 714 PCIR_SUBBUS_1, new_subbus, 1); 715 } 716 } 717 718 return (secbus); 719} 720 721static void 722fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, u_long start, 723 u_long size, u_long pci_start) 724{ 725 uint32_t attr, bar, tar; 726 727 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 728 729 switch (tgt) { 730 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ 731 case OCP85XX_TGTIF_RAM1: 732 attr = 0xa0f55000 | (ffsl(size) - 2); 733 break; 734 default: 735 attr = 0; 736 break; 737 } 738 tar = start >> 12; 739 bar = pci_start >> 12; 740 741 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 742 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 743 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 744 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 745} 746 747static void 748fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, u_long start, 749 u_long size, u_long pci_start) 750{ 751 uint32_t attr, bar, tar; 752 753 switch (res) { 754 case SYS_RES_MEMORY: 755 attr = 0x80044000 | (ffsl(size) - 2); 756 break; 757 case SYS_RES_IOPORT: 758 attr = 0x80088000 | (ffsl(size) - 2); 759 break; 760 default: 761 attr = 0x0004401f; 762 break; 763 } 764 bar = start >> 12; 765 tar = pci_start >> 12; 766 767 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 768 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 769 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 770 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 771} 772 773static int 774fsl_pcib_set_range(struct fsl_pcib_softc *sc, int type, int wnd, u_long start, 775 u_long size) 776{ 777 struct rman *rm; 778 u_long end, alloc; 779 bus_addr_t pci_start, pci_end; 780 bus_addr_t *vap, *allocp; 781 int error; 782 783 end = start + size - 1; 784 785 switch (type) { 786 case SYS_RES_IOPORT: 787 rm = &sc->sc_ioport; 788 pci_start = 0x0000; 789 pci_end = 0xffff; 790 alloc = 0x1000; 791 vap = &sc->sc_ioport_va; 792 allocp = &sc->sc_ioport_alloc; 793 break; 794 case SYS_RES_MEMORY: 795 rm = &sc->sc_iomem; 796 pci_start = start; 797 pci_end = end; 798 alloc = 0; 799 vap = &sc->sc_iomem_va; 800 allocp = &sc->sc_iomem_alloc; 801 break; 802 default: 803 return (EINVAL); 804 } 805 806 rm->rm_type = RMAN_ARRAY; 807 rm->rm_start = pci_start; 808 rm->rm_end = pci_end; 809 error = rman_init(rm); 810 if (error) 811 return (error); 812 813 error = rman_manage_region(rm, pci_start, pci_end); 814 if (error) { 815 rman_fini(rm); 816 return (error); 817 } 818 819 *allocp = pci_start + alloc; 820 *vap = (uintptr_t)pmap_mapdev(start, size); 821 fsl_pcib_outbound(sc, wnd, type, start, size, pci_start); 822 return (0); 823} 824 825static void 826fsl_pcib_err_init(device_t dev) 827{ 828 struct fsl_pcib_softc *sc; 829 uint16_t sec_stat, dsr; 830 uint32_t dcr, err_en; 831 832 sc = device_get_softc(dev); 833 834 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 835 if (sec_stat) 836 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 837 if (sc->sc_pcie) { 838 /* Clear error bits */ 839 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 840 0xffffffff); 841 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 842 0xffffffff); 843 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 844 0xffffffff); 845 846 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 847 sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA, 2); 848 if (dsr) 849 fsl_pcib_cfgwrite(sc, 0, 0, 0, 850 sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA, 851 0xffff, 2); 852 853 /* Enable all errors reporting */ 854 err_en = 0x00bfff00; 855 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 856 err_en); 857 858 /* Enable error reporting: URR, FER, NFER */ 859 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 860 sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, 4); 861 dcr |= PCIM_EXP_CTL_URR_ENABLE | PCIM_EXP_CTL_FER_ENABLE | 862 PCIM_EXP_CTL_NFER_ENABLE; 863 fsl_pcib_cfgwrite(sc, 0, 0, 0, 864 sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, dcr, 4); 865 } 866} 867 868static int 869fsl_pcib_detach(device_t dev) 870{ 871 872 if (mtx_initialized) { 873 mtx_destroy(&pcicfg_mtx); 874 mtx_initialized = 0; 875 } 876 return (bus_generic_detach(dev)); 877} 878 879static struct resource * 880fsl_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 881 u_long start, u_long end, u_long count, u_int flags) 882{ 883 struct fsl_pcib_softc *sc = device_get_softc(dev); 884 struct rman *rm; 885 struct resource *res; 886 bus_addr_t va; 887 888 switch (type) { 889 case SYS_RES_IOPORT: 890 rm = &sc->sc_ioport; 891 va = sc->sc_ioport_va; 892 break; 893 case SYS_RES_MEMORY: 894 rm = &sc->sc_iomem; 895 va = sc->sc_iomem_va; 896 break; 897 case SYS_RES_IRQ: 898 if (start < 16) { 899 device_printf(dev, "%s requested ISA interrupt %lu\n", 900 device_get_nameunit(child), start); 901 } 902 flags |= RF_SHAREABLE; 903 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 904 type, rid, start, end, count, flags)); 905 default: 906 return (NULL); 907 } 908 909 res = rman_reserve_resource(rm, start, end, count, flags, child); 910 if (res == NULL) 911 return (NULL); 912 913 rman_set_bustag(res, &bs_le_tag); 914 rman_set_bushandle(res, va + rman_get_start(res) - rm->rm_start); 915 return (res); 916} 917 918static int 919fsl_pcib_release_resource(device_t dev, device_t child, int type, int rid, 920 struct resource *res) 921{ 922 923 return (rman_release_resource(res)); 924} 925 926static int 927fsl_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 928{ 929 struct fsl_pcib_softc *sc = device_get_softc(dev); 930 931 switch (which) { 932 case PCIB_IVAR_BUS: 933 *result = sc->sc_busnr; 934 return (0); 935 case PCIB_IVAR_DOMAIN: 936 *result = device_get_unit(dev); 937 return (0); 938 } 939 return (ENOENT); 940} 941 942static int 943fsl_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 944{ 945 struct fsl_pcib_softc *sc = device_get_softc(dev); 946 947 switch (which) { 948 case PCIB_IVAR_BUS: 949 sc->sc_busnr = value; 950 return (0); 951 } 952 return (ENOENT); 953} 954 955static int 956fsl_pcib_intr_info(phandle_t node, struct fsl_pcib_softc *sc) 957{ 958 int error; 959 960 if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0) 961 return (error); 962 963 return (0); 964} 965 966static int 967fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 968{ 969 struct fdt_pci_range io_space, mem_space; 970 device_t dev; 971 int error; 972 973 dev = sc->sc_dev; 974 975 if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) { 976 device_printf(dev, "could not retrieve 'ranges' data\n"); 977 return (error); 978 } 979 980 /* 981 * Configure LAW decode windows. 982 */ 983 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 984 &sc->sc_ioport_target); 985 if (error != 0) { 986 device_printf(dev, "could not retrieve PCI LAW target info\n"); 987 return (error); 988 } 989 error = law_enable(sc->sc_iomem_target, mem_space.base_parent, 990 mem_space.len); 991 if (error != 0) { 992 device_printf(dev, "could not program LAW for PCI MEM range\n"); 993 return (error); 994 } 995 error = law_enable(sc->sc_ioport_target, io_space.base_parent, 996 io_space.len); 997 if (error != 0) { 998 device_printf(dev, "could not program LAW for PCI IO range\n"); 999 return (error); 1000 } 1001 1002 /* 1003 * Set outbout and inbound windows. 1004 */ 1005 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 1006 if ((error = fsl_pcib_set_range(sc, SYS_RES_MEMORY, 1, 1007 mem_space.base_parent, mem_space.len)) != 0) 1008 return (error); 1009 if ((error = fsl_pcib_set_range(sc, SYS_RES_IOPORT, 2, 1010 io_space.base_parent, io_space.len)) != 0) 1011 return (error); 1012 1013 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 1014 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 1015 1016 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 1017 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 1018 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 1019 2U * 1024U * 1024U * 1024U, 0); 1020 1021 return (0); 1022} 1023