195719Sbenno/* $FreeBSD$ */ 295719Sbenno/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 395719Sbenno 4139825Simp/*- 595719Sbenno * Copyright (C) 1995, 1996 Wolfgang Solfrank. 695719Sbenno * Copyright (C) 1995, 1996 TooLs GmbH. 795719Sbenno * All rights reserved. 895719Sbenno * 995719Sbenno * Redistribution and use in source and binary forms, with or without 1095719Sbenno * modification, are permitted provided that the following conditions 1195719Sbenno * are met: 1295719Sbenno * 1. Redistributions of source code must retain the above copyright 1395719Sbenno * notice, this list of conditions and the following disclaimer. 1495719Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1595719Sbenno * notice, this list of conditions and the following disclaimer in the 1695719Sbenno * documentation and/or other materials provided with the distribution. 1795719Sbenno * 3. All advertising materials mentioning features or use of this software 1895719Sbenno * must display the following acknowledgement: 1995719Sbenno * This product includes software developed by TooLs GmbH. 2095719Sbenno * 4. The name of TooLs GmbH may not be used to endorse or promote products 2195719Sbenno * derived from this software without specific prior written permission. 2295719Sbenno * 2395719Sbenno * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 2495719Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2595719Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2695719Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2795719Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2895719Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2995719Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 3095719Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 3195719Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 3295719Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3395719Sbenno */ 3495719Sbenno 3595719Sbenno/* 3695719Sbenno * NOTICE: This is not a standalone file. to use it, #include it in 3795719Sbenno * your port's locore.S, like so: 3895719Sbenno * 39174599Smarcel * #include <powerpc/aim/trap_subr.S> 4095719Sbenno */ 4195719Sbenno 4295719Sbenno/* 43125441Sgrehan * Save/restore segment registers 4495719Sbenno */ 45125441Sgrehan#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46125441Sgrehan lwz sr,1*4(pmap); mtsr 1,sr; \ 47125441Sgrehan lwz sr,2*4(pmap); mtsr 2,sr; \ 48125441Sgrehan lwz sr,3*4(pmap); mtsr 3,sr; \ 49125441Sgrehan lwz sr,4*4(pmap); mtsr 4,sr; \ 50125441Sgrehan lwz sr,5*4(pmap); mtsr 5,sr; \ 51125441Sgrehan lwz sr,6*4(pmap); mtsr 6,sr; \ 52125441Sgrehan lwz sr,7*4(pmap); mtsr 7,sr; \ 53125441Sgrehan lwz sr,8*4(pmap); mtsr 8,sr; \ 54125441Sgrehan lwz sr,9*4(pmap); mtsr 9,sr; \ 55125441Sgrehan lwz sr,10*4(pmap); mtsr 10,sr; \ 56125441Sgrehan lwz sr,11*4(pmap); mtsr 11,sr; \ 57214574Snwhitehorn /* Skip segment 12 (USER_SR), which is restored differently */ \ 58125441Sgrehan lwz sr,13*4(pmap); mtsr 13,sr; \ 59125441Sgrehan lwz sr,14*4(pmap); mtsr 14,sr; \ 60125441Sgrehan lwz sr,15*4(pmap); mtsr 15,sr; isync; 6195719Sbenno 6295719Sbenno/* 63125441Sgrehan * User SRs are loaded through a pointer to the current pmap. 6495719Sbenno */ 65125441Sgrehan#define RESTORE_USER_SRS(pmap,sr) \ 66125441Sgrehan GET_CPUINFO(pmap); \ 67125441Sgrehan lwz pmap,PC_CURPMAP(pmap); \ 68125441Sgrehan lwzu sr,PM_SR(pmap); \ 69214574Snwhitehorn RESTORE_SRS(pmap,sr) \ 70214574Snwhitehorn /* Restore SR 12 */ \ 71214574Snwhitehorn lwz sr,12*4(pmap); mtsr 12,sr 7295719Sbenno 7395719Sbenno/* 74125441Sgrehan * Kernel SRs are loaded directly from kernel_pmap_ 7595719Sbenno */ 76125441Sgrehan#define RESTORE_KERN_SRS(pmap,sr) \ 77125441Sgrehan lis pmap,CNAME(kernel_pmap_store)@ha; \ 78125441Sgrehan lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \ 79125441Sgrehan RESTORE_SRS(pmap,sr) 8095719Sbenno 81125441Sgrehan/* 82125441Sgrehan * FRAME_SETUP assumes: 83125441Sgrehan * SPRG1 SP (1) 84188860Snwhitehorn * SPRG3 trap type 85125441Sgrehan * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 86125441Sgrehan * r28 LR 87125441Sgrehan * r29 CR 88125441Sgrehan * r30 scratch 89125441Sgrehan * r31 scratch 90125441Sgrehan * r1 kernel stack 91125441Sgrehan * SRR0/1 as at start of trap 92125441Sgrehan */ 93125441Sgrehan#define FRAME_SETUP(savearea) \ 94125441Sgrehan/* Have to enable translation to allow access of kernel stack: */ \ 95125441Sgrehan GET_CPUINFO(%r31); \ 96125441Sgrehan mfsrr0 %r30; \ 97125441Sgrehan stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 98125441Sgrehan mfsrr1 %r30; \ 99125441Sgrehan stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 100125441Sgrehan mfmsr %r30; \ 101125441Sgrehan ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 102125441Sgrehan mtmsr %r30; /* stack can now be accessed */ \ 103125441Sgrehan isync; \ 104125441Sgrehan mfsprg1 %r31; /* get saved SP */ \ 105125441Sgrehan stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 106125441Sgrehan stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 107125441Sgrehan stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 108125441Sgrehan stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 109125441Sgrehan stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 110125441Sgrehan stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 111125441Sgrehan GET_CPUINFO(%r2); \ 112125441Sgrehan lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 113125441Sgrehan lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 114125441Sgrehan lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 115125441Sgrehan lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 116125441Sgrehan stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 117125441Sgrehan stw %r4, FRAME_4+8(%r1); \ 118125441Sgrehan stw %r5, FRAME_5+8(%r1); \ 119125441Sgrehan stw %r6, FRAME_6+8(%r1); \ 120125441Sgrehan stw %r7, FRAME_7+8(%r1); \ 121125441Sgrehan stw %r8, FRAME_8+8(%r1); \ 122125441Sgrehan stw %r9, FRAME_9+8(%r1); \ 123125441Sgrehan stw %r10, FRAME_10+8(%r1); \ 124125441Sgrehan stw %r11, FRAME_11+8(%r1); \ 125125441Sgrehan stw %r12, FRAME_12+8(%r1); \ 126125441Sgrehan stw %r13, FRAME_13+8(%r1); \ 127125441Sgrehan stw %r14, FRAME_14+8(%r1); \ 128125441Sgrehan stw %r15, FRAME_15+8(%r1); \ 129125441Sgrehan stw %r16, FRAME_16+8(%r1); \ 130125441Sgrehan stw %r17, FRAME_17+8(%r1); \ 131125441Sgrehan stw %r18, FRAME_18+8(%r1); \ 132125441Sgrehan stw %r19, FRAME_19+8(%r1); \ 133125441Sgrehan stw %r20, FRAME_20+8(%r1); \ 134125441Sgrehan stw %r21, FRAME_21+8(%r1); \ 135125441Sgrehan stw %r22, FRAME_22+8(%r1); \ 136125441Sgrehan stw %r23, FRAME_23+8(%r1); \ 137125441Sgrehan stw %r24, FRAME_24+8(%r1); \ 138125441Sgrehan stw %r25, FRAME_25+8(%r1); \ 139125441Sgrehan stw %r26, FRAME_26+8(%r1); \ 140125441Sgrehan stw %r27, FRAME_27+8(%r1); \ 141125441Sgrehan stw %r28, FRAME_28+8(%r1); \ 142125441Sgrehan stw %r29, FRAME_29+8(%r1); \ 143125441Sgrehan stw %r30, FRAME_30+8(%r1); \ 144125441Sgrehan stw %r31, FRAME_31+8(%r1); \ 145176742Sraj lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 146176742Sraj lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 147125441Sgrehan lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 148125441Sgrehan lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 149125441Sgrehan mfxer %r3; \ 150125441Sgrehan mfctr %r4; \ 151188860Snwhitehorn mfsprg3 %r5; \ 152125441Sgrehan stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 153125441Sgrehan stw %r4, FRAME_CTR+8(1); \ 154125441Sgrehan stw %r5, FRAME_EXC+8(1); \ 155176742Sraj stw %r28,FRAME_AIM_DAR+8(1); \ 156176742Sraj stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 157125441Sgrehan stw %r30,FRAME_SRR0+8(1); \ 158223485Snwhitehorn stw %r31,FRAME_SRR1+8(1); \ 159223485Snwhitehorn lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */ 16095719Sbenno 161125441Sgrehan#define FRAME_LEAVE(savearea) \ 162223485Snwhitehorn/* Disable exceptions: */ \ 163223485Snwhitehorn mfmsr %r2; \ 164223485Snwhitehorn andi. %r2,%r2,~PSL_EE@l; \ 165223485Snwhitehorn mtmsr %r2; \ 166223485Snwhitehorn isync; \ 167125441Sgrehan/* Now restore regs: */ \ 168125441Sgrehan lwz %r2,FRAME_SRR0+8(%r1); \ 169125441Sgrehan lwz %r3,FRAME_SRR1+8(%r1); \ 170125441Sgrehan lwz %r4,FRAME_CTR+8(%r1); \ 171125441Sgrehan lwz %r5,FRAME_XER+8(%r1); \ 172125441Sgrehan lwz %r6,FRAME_LR+8(%r1); \ 173125441Sgrehan GET_CPUINFO(%r7); \ 174125441Sgrehan stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 175125441Sgrehan stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 176125441Sgrehan lwz %r7,FRAME_CR+8(%r1); \ 177125441Sgrehan mtctr %r4; \ 178125441Sgrehan mtxer %r5; \ 179125441Sgrehan mtlr %r6; \ 180125441Sgrehan mtsprg1 %r7; /* save cr */ \ 181125441Sgrehan lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 182125441Sgrehan lwz %r30,FRAME_30+8(%r1); \ 183125441Sgrehan lwz %r29,FRAME_29+8(%r1); \ 184125441Sgrehan lwz %r28,FRAME_28+8(%r1); \ 185125441Sgrehan lwz %r27,FRAME_27+8(%r1); \ 186125441Sgrehan lwz %r26,FRAME_26+8(%r1); \ 187125441Sgrehan lwz %r25,FRAME_25+8(%r1); \ 188125441Sgrehan lwz %r24,FRAME_24+8(%r1); \ 189125441Sgrehan lwz %r23,FRAME_23+8(%r1); \ 190125441Sgrehan lwz %r22,FRAME_22+8(%r1); \ 191125441Sgrehan lwz %r21,FRAME_21+8(%r1); \ 192125441Sgrehan lwz %r20,FRAME_20+8(%r1); \ 193125441Sgrehan lwz %r19,FRAME_19+8(%r1); \ 194125441Sgrehan lwz %r18,FRAME_18+8(%r1); \ 195125441Sgrehan lwz %r17,FRAME_17+8(%r1); \ 196125441Sgrehan lwz %r16,FRAME_16+8(%r1); \ 197125441Sgrehan lwz %r15,FRAME_15+8(%r1); \ 198125441Sgrehan lwz %r14,FRAME_14+8(%r1); \ 199125441Sgrehan lwz %r13,FRAME_13+8(%r1); \ 200125441Sgrehan lwz %r12,FRAME_12+8(%r1); \ 201125441Sgrehan lwz %r11,FRAME_11+8(%r1); \ 202125441Sgrehan lwz %r10,FRAME_10+8(%r1); \ 203125441Sgrehan lwz %r9, FRAME_9+8(%r1); \ 204125441Sgrehan lwz %r8, FRAME_8+8(%r1); \ 205125441Sgrehan lwz %r7, FRAME_7+8(%r1); \ 206125441Sgrehan lwz %r6, FRAME_6+8(%r1); \ 207125441Sgrehan lwz %r5, FRAME_5+8(%r1); \ 208125441Sgrehan lwz %r4, FRAME_4+8(%r1); \ 209125441Sgrehan lwz %r3, FRAME_3+8(%r1); \ 210125441Sgrehan lwz %r2, FRAME_2+8(%r1); \ 211125441Sgrehan lwz %r0, FRAME_0+8(%r1); \ 212125441Sgrehan lwz %r1, FRAME_1+8(%r1); \ 213125441Sgrehan/* Can't touch %r1 from here on */ \ 214125441Sgrehan mtsprg2 %r2; /* save r2 & r3 */ \ 215125441Sgrehan mtsprg3 %r3; \ 216125441Sgrehan/* Disable translation, machine check and recoverability: */ \ 217125441Sgrehan mfmsr %r2; \ 218223485Snwhitehorn andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 219125441Sgrehan mtmsr %r2; \ 220125441Sgrehan isync; \ 221125441Sgrehan/* Decide whether we return to user mode: */ \ 222125441Sgrehan GET_CPUINFO(%r2); \ 223125441Sgrehan lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 224125441Sgrehan mtcr %r3; \ 225125441Sgrehan bf 17,1f; /* branch if PSL_PR is false */ \ 226125441Sgrehan/* Restore user SRs */ \ 227125441Sgrehan RESTORE_USER_SRS(%r2,%r3); \ 228125441Sgrehan1: mfsprg1 %r2; /* restore cr */ \ 229125441Sgrehan mtcr %r2; \ 230125441Sgrehan GET_CPUINFO(%r2); \ 231125441Sgrehan lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 232125441Sgrehan mtsrr0 %r3; \ 233125441Sgrehan lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 234190681Snwhitehorn \ 235190681Snwhitehorn /* Make sure HV bit of MSR propagated to SRR1 */ \ 236190681Snwhitehorn mfmsr %r2; \ 237190681Snwhitehorn or %r3,%r2,%r3; \ 238190681Snwhitehorn \ 239125441Sgrehan mtsrr1 %r3; \ 240125441Sgrehan mfsprg2 %r2; /* restore r2 & r3 */ \ 241125441Sgrehan mfsprg3 %r3 24295719Sbenno 243242723Sjhibbits#ifdef KDTRACE_HOOKS 244242723Sjhibbits .data 245242723Sjhibbits .globl dtrace_invop_calltrap_addr 246242723Sjhibbits .align 4 247242723Sjhibbits .type dtrace_invop_calltrap_addr, @object 248242723Sjhibbits .size dtrace_invop_calltrap_addr, 4 249242723Sjhibbitsdtrace_invop_calltrap_addr: 250242723Sjhibbits .word 0 251242723Sjhibbits .word 0 252242723Sjhibbits 253242723Sjhibbits .text 254242723Sjhibbits#endif 255242723Sjhibbits 256190681Snwhitehorn/* 257190681Snwhitehorn * The next two routines are 64-bit glue code. The first is used to test if 258190681Snwhitehorn * we are on a 64-bit system. By copying it to the illegal instruction 259190681Snwhitehorn * handler, we can test for 64-bit mode by trying to execute a 64-bit 260190681Snwhitehorn * instruction and seeing what happens. The second gets copied in front 261190681Snwhitehorn * of all the other handlers to restore 32-bit bridge mode when traps 262190681Snwhitehorn * are taken. 263190681Snwhitehorn */ 264190681Snwhitehorn 265190681Snwhitehorn/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 266190681Snwhitehorn 267190681Snwhitehorn .globl CNAME(testppc64),CNAME(testppc64size) 268190681SnwhitehornCNAME(testppc64): 269190681Snwhitehorn mtsprg1 %r31 270190681Snwhitehorn mfsrr0 %r31 271190681Snwhitehorn addi %r31, %r31, 4 272190681Snwhitehorn mtsrr0 %r31 273190681Snwhitehorn 274190681Snwhitehorn li %r31, 0 275190681Snwhitehorn mtsprg2 %r31 276190681Snwhitehorn mfsprg1 %r31 277190681Snwhitehorn 278190681Snwhitehorn rfi 279190681SnwhitehornCNAME(testppc64size) = .-CNAME(testppc64) 280190681Snwhitehorn 281190681Snwhitehorn 282190681Snwhitehorn/* 64-bit bridge mode restore snippet. Gets copied in front of everything else 283190681Snwhitehorn * on 64-bit systems. */ 284190681Snwhitehorn 285190681Snwhitehorn .globl CNAME(restorebridge),CNAME(restorebridgesize) 286190681SnwhitehornCNAME(restorebridge): 287190681Snwhitehorn mtsprg1 %r31 288190681Snwhitehorn mfmsr %r31 289190681Snwhitehorn clrldi %r31,%r31,1 290190681Snwhitehorn mtmsrd %r31 291190681Snwhitehorn mfsprg1 %r31 292190681Snwhitehorn isync 293190681SnwhitehornCNAME(restorebridgesize) = .-CNAME(restorebridge) 294190681Snwhitehorn 295178628Smarcel#ifdef SMP 29695719Sbenno/* 297178628Smarcel * Processor reset exception handler. These are typically 298178628Smarcel * the first instructions the processor executes after a 299198400Snwhitehorn * software reset. We do this in two bits so that we are 300198400Snwhitehorn * not still hanging around in the trap handling region 301198400Snwhitehorn * once the MMU is turned on. 302132571Sgrehan */ 303178628Smarcel .globl CNAME(rstcode), CNAME(rstsize) 304178628SmarcelCNAME(rstcode): 305198400Snwhitehorn ba cpu_reset 306198400SnwhitehornCNAME(rstsize) = . - CNAME(rstcode) 307198400Snwhitehorn 308198400Snwhitehorncpu_reset: 309178628Smarcel bl 1f 310178628Smarcel 311183060Smarcel .space 124 312178628Smarcel 313178628Smarcel1: 314183060Smarcel mflr %r1 315183060Smarcel addi %r1,%r1,(124-16)@l 316178628Smarcel 317183060Smarcel lis %r3,1@l 318209975Snwhitehorn bla CNAME(cpudep_ap_early_bootstrap) 319227386Snwhitehorn lis %r3,1@l 320178628Smarcel bla CNAME(pmap_cpu_bootstrap) 321178628Smarcel bla CNAME(cpudep_ap_bootstrap) 322178628Smarcel mr %r1,%r3 323178628Smarcel bla CNAME(machdep_ap_bootstrap) 324178628Smarcel 325178628Smarcel /* Should not be reached */ 326178628Smarcel9: 327178628Smarcel b 9b 328132571Sgrehan#endif 329132571Sgrehan 330132571Sgrehan/* 33195719Sbenno * This code gets copied to all the trap vectors 332125441Sgrehan * (except ISI/DSI, ALI, and the interrupts) 33395719Sbenno */ 334178628Smarcel 33596773Sbenno .globl CNAME(trapcode),CNAME(trapsize) 33696773SbennoCNAME(trapcode): 337125441Sgrehan mtsprg1 %r1 /* save SP */ 338188860Snwhitehorn mflr %r1 /* Save the old LR in r1 */ 339188860Snwhitehorn mtsprg2 %r1 /* And then in SPRG2 */ 340188860Snwhitehorn li %r1, 0x20 /* How to get the vector from LR */ 341188860Snwhitehorn bla generictrap /* LR & SPRG3 is exception # */ 34296773SbennoCNAME(trapsize) = .-CNAME(trapcode) 34395719Sbenno 34495719Sbenno/* 345190681Snwhitehorn * 64-bit version of trapcode. Identical, except it calls generictrap64. 346190681Snwhitehorn */ 347190681Snwhitehorn .globl CNAME(trapcode64) 348190681SnwhitehornCNAME(trapcode64): 349190681Snwhitehorn mtsprg1 %r1 /* save SP */ 350190681Snwhitehorn mflr %r1 /* Save the old LR in r1 */ 351190681Snwhitehorn mtsprg2 %r1 /* And then in SPRG2 */ 352190681Snwhitehorn li %r1, 0x20 /* How to get the vector from LR */ 353190681Snwhitehorn bla generictrap64 /* LR & SPRG3 is exception # */ 354190681Snwhitehorn 355190681Snwhitehorn/* 35695719Sbenno * For ALI: has to save DSISR and DAR 35795719Sbenno */ 35896773Sbenno .globl CNAME(alitrap),CNAME(alisize) 35996773SbennoCNAME(alitrap): 360125441Sgrehan mtsprg1 %r1 /* save SP */ 361125441Sgrehan GET_CPUINFO(%r1) 362125441Sgrehan stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 363125441Sgrehan stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 364125441Sgrehan stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 365125441Sgrehan stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 366125441Sgrehan mfdar %r30 367125441Sgrehan mfdsisr %r31 368176742Sraj stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 369176742Sraj stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 370125441Sgrehan mfsprg1 %r1 /* restore SP, in case of branch */ 371125441Sgrehan mflr %r28 /* save LR */ 372125441Sgrehan mfcr %r29 /* save CR */ 373188860Snwhitehorn 374188951Snwhitehorn /* Put our exception vector in SPRG3 */ 375188860Snwhitehorn li %r31, EXC_ALI 376188860Snwhitehorn mtsprg3 %r31 377188860Snwhitehorn 378188860Snwhitehorn /* Test whether we already had PR set */ 379125441Sgrehan mfsrr1 %r31 380125441Sgrehan mtcr %r31 381188860Snwhitehorn bla s_trap 38296773SbennoCNAME(alisize) = .-CNAME(alitrap) 38395719Sbenno 38495719Sbenno/* 385215107Snwhitehorn * G2 specific: instuction TLB miss. 386215107Snwhitehorn */ 387215107Snwhitehorn .globl CNAME(imisstrap),CNAME(imisssize) 388215107SnwhitehornCNAME(imisstrap): 389215107Snwhitehorn mfspr %r2, SPR_HASH1 /* get first pointer */ 390215107Snwhitehorn addi %r1, 0, 8 /* load 8 for counter */ 391215107Snwhitehorn mfctr %r0 /* save counter */ 392215107Snwhitehorn mfspr %r3, SPR_ICMP /* get first compare value */ 393215107Snwhitehorn addi %r2, %r2, -8 /* pre dec the pointer */ 394215107Snwhitehornim0: 395215107Snwhitehorn mtctr %r1 /* load counter */ 396215107Snwhitehornim1: 397215107Snwhitehorn lwzu %r1, 8(%r2) /* get next pte */ 398215107Snwhitehorn cmp 0, %r1, %r3 /* see if found pte */ 399215107Snwhitehorn bdnzf 2, im1 /* dec count br if cmp ne and if 400215107Snwhitehorn * count not zero */ 401215107Snwhitehorn bne instr_sec_hash /* if not found set up second hash 402215107Snwhitehorn * or exit */ 403215107Snwhitehorn lwz %r1, +4(%r2) /* load tlb entry lower-word */ 404215107Snwhitehorn andi. %r3, %r1, 8 /* check G bit */ 405215107Snwhitehorn bne do_isi_prot /* if guarded, take an ISI */ 406215107Snwhitehorn mtctr %r0 /* restore counter */ 407215107Snwhitehorn mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ 408215107Snwhitehorn mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 409215107Snwhitehorn mtcrf 0x80, %r3 /* restore CR0 */ 410215107Snwhitehorn mtspr SPR_RPA, %r1 /* set the pte */ 411215107Snwhitehorn ori %r1, %r1, 0x100 /* set reference bit */ 412215107Snwhitehorn srwi %r1, %r1, 8 /* get byte 7 of pte */ 413215107Snwhitehorn tlbli %r0 /* load the itlb */ 414215107Snwhitehorn stb %r1, +6(%r2) /* update page table */ 415215107Snwhitehorn rfi /* return to executing program */ 416215107Snwhitehorn 417215107Snwhitehorninstr_sec_hash: 418215107Snwhitehorn andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 419215107Snwhitehorn bne do_isi /* if so, go to ISI interrupt */ 420215107Snwhitehorn mfspr %r2, SPR_HASH2 /* get the second pointer */ 421215107Snwhitehorn ori %r3, %r3, 0x0040 /* change the compare value */ 422215107Snwhitehorn addi %r1, %r0, 8 /* load 8 for counter */ 423215107Snwhitehorn addi %r2, %r2, -8 /* pre dec for update on load */ 424215107Snwhitehorn b im0 /* try second hash */ 425215107Snwhitehorn 426215107Snwhitehorn/* Create a faked ISI interrupt as the address was not found */ 427215107Snwhitehorndo_isi_prot: 428215107Snwhitehorn mfspr %r3, SPR_SRR1 /* get srr1 */ 429215107Snwhitehorn andi. %r2, %r3, 0xffff /* clean upper srr1 */ 430215107Snwhitehorn addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot 431215107Snwhitehorn * violation */ 432215107Snwhitehorn b isi1 433215107Snwhitehorndo_isi: 434215107Snwhitehorn mfspr %r3, SPR_SRR1 /* get srr1 */ 435215107Snwhitehorn andi. %r2, %r3, 0xffff /* clean srr1 */ 436215107Snwhitehorn addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte 437215107Snwhitehorn * not found */ 438215107Snwhitehornisi1: 439215107Snwhitehorn mtctr %r0 /* restore counter */ 440215107Snwhitehorn mtspr SPR_SRR1, %r2 /* set srr1 */ 441215107Snwhitehorn mfmsr %r0 /* get msr */ 442215107Snwhitehorn xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 443215107Snwhitehorn mtcrf 0x80, %r3 /* restore CR0 */ 444215107Snwhitehorn mtmsr %r0 /* flip back to the native gprs */ 445215107Snwhitehorn ba EXC_ISI /* go to instr. access interrupt */ 446215107Snwhitehorn 447215107SnwhitehornCNAME(imisssize) = .-CNAME(imisstrap) 448215107Snwhitehorn 449215107Snwhitehorn/* 450215107Snwhitehorn * G2 specific: data load TLB miss. 451215107Snwhitehorn */ 452215107Snwhitehorn .globl CNAME(dlmisstrap),CNAME(dlmisssize) 453215107SnwhitehornCNAME(dlmisstrap): 454215107Snwhitehorn mfspr %r2, SPR_HASH1 /* get first pointer */ 455215107Snwhitehorn addi %r1, 0, 8 /* load 8 for counter */ 456215107Snwhitehorn mfctr %r0 /* save counter */ 457215107Snwhitehorn mfspr %r3, SPR_DCMP /* get first compare value */ 458215107Snwhitehorn addi %r2, %r2, -8 /* pre dec the pointer */ 459215107Snwhitehorndm0: 460215107Snwhitehorn mtctr %r1 /* load counter */ 461215107Snwhitehorndm1: 462215107Snwhitehorn lwzu %r1, 8(%r2) /* get next pte */ 463215107Snwhitehorn cmp 0, 0, %r1, %r3 /* see if found pte */ 464215107Snwhitehorn bdnzf 2, dm1 /* dec count br if cmp ne and if 465215107Snwhitehorn * count not zero */ 466215107Snwhitehorn bne data_sec_hash /* if not found set up second hash 467215107Snwhitehorn * or exit */ 468215107Snwhitehorn lwz %r1, +4(%r2) /* load tlb entry lower-word */ 469215107Snwhitehorn mtctr %r0 /* restore counter */ 470215107Snwhitehorn mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 471215107Snwhitehorn mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 472215107Snwhitehorn mtcrf 0x80, %r3 /* restore CR0 */ 473215107Snwhitehorn mtspr SPR_RPA, %r1 /* set the pte */ 474215107Snwhitehorn ori %r1, %r1, 0x100 /* set reference bit */ 475215107Snwhitehorn srwi %r1, %r1, 8 /* get byte 7 of pte */ 476215107Snwhitehorn tlbld %r0 /* load the dtlb */ 477215107Snwhitehorn stb %r1, +6(%r2) /* update page table */ 478215107Snwhitehorn rfi /* return to executing program */ 479215107Snwhitehorn 480215107Snwhitehorndata_sec_hash: 481215107Snwhitehorn andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 482215107Snwhitehorn bne do_dsi /* if so, go to DSI interrupt */ 483215107Snwhitehorn mfspr %r2, SPR_HASH2 /* get the second pointer */ 484215107Snwhitehorn ori %r3, %r3, 0x0040 /* change the compare value */ 485215107Snwhitehorn addi %r1, 0, 8 /* load 8 for counter */ 486215107Snwhitehorn addi %r2, %r2, -8 /* pre dec for update on load */ 487215107Snwhitehorn b dm0 /* try second hash */ 488215107Snwhitehorn 489215107SnwhitehornCNAME(dlmisssize) = .-CNAME(dlmisstrap) 490215107Snwhitehorn 491215107Snwhitehorn/* 492215107Snwhitehorn * G2 specific: data store TLB miss. 493215107Snwhitehorn */ 494215107Snwhitehorn .globl CNAME(dsmisstrap),CNAME(dsmisssize) 495215107SnwhitehornCNAME(dsmisstrap): 496215107Snwhitehorn mfspr %r2, SPR_HASH1 /* get first pointer */ 497215107Snwhitehorn addi %r1, 0, 8 /* load 8 for counter */ 498215107Snwhitehorn mfctr %r0 /* save counter */ 499215107Snwhitehorn mfspr %r3, SPR_DCMP /* get first compare value */ 500215107Snwhitehorn addi %r2, %r2, -8 /* pre dec the pointer */ 501215107Snwhitehornds0: 502215107Snwhitehorn mtctr %r1 /* load counter */ 503215107Snwhitehornds1: 504215107Snwhitehorn lwzu %r1, 8(%r2) /* get next pte */ 505215107Snwhitehorn cmp 0, 0, %r1, %r3 /* see if found pte */ 506215107Snwhitehorn bdnzf 2, ds1 /* dec count br if cmp ne and if 507215107Snwhitehorn * count not zero */ 508215107Snwhitehorn bne data_store_sec_hash /* if not found set up second hash 509215107Snwhitehorn * or exit */ 510215107Snwhitehorn lwz %r1, +4(%r2) /* load tlb entry lower-word */ 511215107Snwhitehorn andi. %r3, %r1, 0x80 /* check the C-bit */ 512215107Snwhitehorn beq data_store_chk_prot /* if (C==0) 513215107Snwhitehorn * go check protection modes */ 514215107Snwhitehornds2: 515215107Snwhitehorn mtctr %r0 /* restore counter */ 516215107Snwhitehorn mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 517215107Snwhitehorn mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 518215107Snwhitehorn mtcrf 0x80, %r3 /* restore CR0 */ 519215107Snwhitehorn mtspr SPR_RPA, %r1 /* set the pte */ 520215107Snwhitehorn tlbld %r0 /* load the dtlb */ 521215107Snwhitehorn rfi /* return to executing program */ 522215107Snwhitehorn 523215107Snwhitehorndata_store_sec_hash: 524215107Snwhitehorn andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 525215107Snwhitehorn bne do_dsi /* if so, go to DSI interrupt */ 526215107Snwhitehorn mfspr %r2, SPR_HASH2 /* get the second pointer */ 527215107Snwhitehorn ori %r3, %r3, 0x0040 /* change the compare value */ 528215107Snwhitehorn addi %r1, 0, 8 /* load 8 for counter */ 529215107Snwhitehorn addi %r2, %r2, -8 /* pre dec for update on load */ 530215107Snwhitehorn b ds0 /* try second hash */ 531215107Snwhitehorn 532215107Snwhitehorn/* Check the protection before setting PTE(c-bit) */ 533215107Snwhitehorndata_store_chk_prot: 534215107Snwhitehorn rlwinm. %r3,%r1,30,0,1 /* test PP */ 535215107Snwhitehorn bge- chk0 /* if (PP == 00 or PP == 01) 536215107Snwhitehorn * goto chk0: */ 537215107Snwhitehorn andi. %r3, %r1, 1 /* test PP[0] */ 538215107Snwhitehorn beq+ chk2 /* return if PP[0] == 0 */ 539215107Snwhitehorn b do_dsi_prot /* else DSIp */ 540215107Snwhitehornchk0: 541215107Snwhitehorn mfspr %r3,SPR_SRR1 /* get old msr */ 542215107Snwhitehorn andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ 543215107Snwhitehorn beq chk2 /* if (KEY==0) goto chk2: */ 544215107Snwhitehorn b do_dsi_prot /* else do_dsi_prot */ 545215107Snwhitehornchk2: 546215107Snwhitehorn ori %r1, %r1, 0x180 /* set reference and change bit */ 547215107Snwhitehorn sth %r1, 6(%r2) /* update page table */ 548215107Snwhitehorn b ds2 /* and back we go */ 549215107Snwhitehorn 550215107Snwhitehorn/* Create a faked DSI interrupt as the address was not found */ 551215107Snwhitehorndo_dsi: 552215107Snwhitehorn mfspr %r3, SPR_SRR1 /* get srr1 */ 553215107Snwhitehorn rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 554215107Snwhitehorn * load/store, zero rest */ 555215107Snwhitehorn addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte 556215107Snwhitehorn * not found */ 557215107Snwhitehorn b dsi1 558215107Snwhitehorn 559215107Snwhitehorndo_dsi_prot: 560215107Snwhitehorn mfspr %r3, SPR_SRR1 /* get srr1 */ 561215107Snwhitehorn rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 562215107Snwhitehorn *load/store, zero rest */ 563215107Snwhitehorn addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot 564215107Snwhitehorn * violation */ 565215107Snwhitehorn 566215107Snwhitehorndsi1: 567215107Snwhitehorn mtctr %r0 /* restore counter */ 568215107Snwhitehorn andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ 569215107Snwhitehorn mtspr SPR_SRR1, %r2 /* set srr1 */ 570215107Snwhitehorn mtspr SPR_DSISR, %r1 /* load the dsisr */ 571215107Snwhitehorn mfspr %r1, SPR_DMISS /* get miss address */ 572215107Snwhitehorn rlwinm. %r2,%r2,0,31,31 /* test LE bit */ 573215107Snwhitehorn beq dsi2 /* if little endian then: */ 574215107Snwhitehorn xor %r1, %r1, 0x07 /* de-mung the data address */ 575215107Snwhitehorndsi2: 576215107Snwhitehorn mtspr SPR_DAR, %r1 /* put in dar */ 577215107Snwhitehorn mfmsr %r0 /* get msr */ 578215107Snwhitehorn xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 579215107Snwhitehorn mtcrf 0x80, %r3 /* restore CR0 */ 580215107Snwhitehorn mtmsr %r0 /* flip back to the native gprs */ 581215107Snwhitehorn ba EXC_DSI /* branch to DSI interrupt */ 582215107Snwhitehorn 583215107SnwhitehornCNAME(dsmisssize) = .-CNAME(dsmisstrap) 584215107Snwhitehorn 585215107Snwhitehorn/* 58695719Sbenno * Similar to the above for DSI 58795719Sbenno * Has to handle BAT spills 58895719Sbenno * and standard pagetable spills 58995719Sbenno */ 59096773Sbenno .globl CNAME(dsitrap),CNAME(dsisize) 59196773SbennoCNAME(dsitrap): 592125441Sgrehan mtsprg1 %r1 /* save SP */ 593125441Sgrehan GET_CPUINFO(%r1) 594125441Sgrehan stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 595125441Sgrehan stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 596125441Sgrehan stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 597125441Sgrehan stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 598125441Sgrehan mfsprg1 %r1 /* restore SP */ 599125441Sgrehan mfcr %r29 /* save CR */ 600125441Sgrehan mfxer %r30 /* save XER */ 601125441Sgrehan mtsprg2 %r30 /* in SPRG2 */ 602125441Sgrehan mfsrr1 %r31 /* test kernel mode */ 603125441Sgrehan mtcr %r31 604125441Sgrehan bt 17,1f /* branch if PSL_PR is set */ 605125441Sgrehan mfdar %r31 /* get fault address */ 606125441Sgrehan rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 60795719Sbenno 60895719Sbenno /* get batu */ 609125441Sgrehan addis %r31,%r31,CNAME(battable)@ha 610125441Sgrehan lwz %r30,CNAME(battable)@l(31) 611125441Sgrehan mtcr %r30 612125441Sgrehan bf 30,1f /* branch if supervisor valid is 61395719Sbenno false */ 61495719Sbenno /* get batl */ 615125441Sgrehan lwz %r31,CNAME(battable)+4@l(31) 61695719Sbenno/* We randomly use the highest two bat registers here */ 617125441Sgrehan mftb %r28 618125441Sgrehan andi. %r28,%r28,1 61995719Sbenno bne 2f 620125441Sgrehan mtdbatu 2,%r30 621125441Sgrehan mtdbatl 2,%r31 62295719Sbenno b 3f 62395719Sbenno2: 624125441Sgrehan mtdbatu 3,%r30 625125441Sgrehan mtdbatl 3,%r31 62695719Sbenno3: 627125441Sgrehan mfsprg2 %r30 /* restore XER */ 628125441Sgrehan mtxer %r30 629125441Sgrehan mtcr %r29 /* restore CR */ 630125441Sgrehan mtsprg1 %r1 631125441Sgrehan GET_CPUINFO(%r1) 632125441Sgrehan lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 633125441Sgrehan lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 634125441Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 635125441Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 636125441Sgrehan mfsprg1 %r1 63795719Sbenno rfi /* return to trapped code */ 63895719Sbenno1: 639125441Sgrehan mflr %r28 /* save LR (SP already saved) */ 640125441Sgrehan bla disitrap 64196773SbennoCNAME(dsisize) = .-CNAME(dsitrap) 64295719Sbenno 64395719Sbenno/* 64495719Sbenno * Preamble code for DSI/ISI traps 64595719Sbenno */ 64695719Sbennodisitrap: 647188951Snwhitehorn /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 648188860Snwhitehorn mflr %r1 649188860Snwhitehorn andi. %r1,%r1,0xff00 650188860Snwhitehorn mtsprg3 %r1 651188860Snwhitehorn 652125441Sgrehan GET_CPUINFO(%r1) 653125441Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 654125441Sgrehan stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 655125441Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 656125441Sgrehan stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 657125441Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 658125441Sgrehan stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 659125441Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 660125441Sgrehan stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 661125441Sgrehan mfdar %r30 662125441Sgrehan mfdsisr %r31 663176742Sraj stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 664176742Sraj stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 665125441Sgrehan 666132571Sgrehan#ifdef KDB 667132571Sgrehan /* Try and detect a kernel stack overflow */ 668132571Sgrehan mfsrr1 %r31 669132571Sgrehan mtcr %r31 670132571Sgrehan bt 17,realtrap /* branch is user mode */ 671132571Sgrehan mfsprg1 %r31 /* get old SP */ 672132571Sgrehan sub. %r30,%r31,%r30 /* SP - DAR */ 673132571Sgrehan bge 1f 674132571Sgrehan neg %r30,%r30 /* modulo value */ 675132571Sgrehan1: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 676132571Sgrehan bge %cr0,realtrap /* no, too far away. */ 677132571Sgrehan 678132571Sgrehan /* Now convert this DSI into a DDB trap. */ 679132571Sgrehan GET_CPUINFO(%r1) 680176742Sraj lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 681176742Sraj stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 682227386Snwhitehorn lwz %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 683227386Snwhitehorn stw %r31,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 684132571Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 685132571Sgrehan stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 686132571Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 687132571Sgrehan stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 688132571Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 689132571Sgrehan stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 690132571Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 691132571Sgrehan stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 692191039Snwhitehorn b dbtrap 693132571Sgrehan#endif 694132571Sgrehan 695125441Sgrehan /* XXX need stack probe here */ 69695719Sbennorealtrap: 69795719Sbenno/* Test whether we already had PR set */ 698125441Sgrehan mfsrr1 %r1 699125441Sgrehan mtcr %r1 700125441Sgrehan mfsprg1 %r1 /* restore SP (might have been 70195719Sbenno overwritten) */ 702188860Snwhitehorn bf 17,k_trap /* branch if PSL_PR is false */ 703188860Snwhitehorn GET_CPUINFO(%r1) 704188860Snwhitehorn lwz %r1,PC_CURPCB(%r1) 705188860Snwhitehorn RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 706188860Snwhitehorn ba s_trap 707188860Snwhitehorn 708188860Snwhitehorn/* 709188860Snwhitehorn * generictrap does some standard setup for trap handling to minimize 710188860Snwhitehorn * the code that need be installed in the actual vectors. It expects 711188860Snwhitehorn * the following conditions. 712188860Snwhitehorn * 713188860Snwhitehorn * R1 - Trap vector = LR & (0xff00 | R1) 714188860Snwhitehorn * SPRG1 - Original R1 contents 715188860Snwhitehorn * SPRG2 - Original LR 716188860Snwhitehorn */ 717188860Snwhitehorn 718190681Snwhitehorngenerictrap64: 719190681Snwhitehorn mtsprg3 %r31 720190681Snwhitehorn mfmsr %r31 721190681Snwhitehorn clrldi %r31,%r31,1 722190681Snwhitehorn mtmsrd %r31 723190681Snwhitehorn mfsprg3 %r31 724190681Snwhitehorn isync 725190681Snwhitehorn 726188860Snwhitehorngenerictrap: 727188860Snwhitehorn /* Save R1 for computing the exception vector */ 728188860Snwhitehorn mtsprg3 %r1 729188860Snwhitehorn 730188860Snwhitehorn /* Save interesting registers */ 731188860Snwhitehorn GET_CPUINFO(%r1) 732188860Snwhitehorn stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 733188860Snwhitehorn stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 734188860Snwhitehorn stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 735188860Snwhitehorn stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 736188860Snwhitehorn mfsprg1 %r1 /* restore SP, in case of branch */ 737188860Snwhitehorn mfsprg2 %r28 /* save LR */ 738188860Snwhitehorn mfcr %r29 /* save CR */ 739188860Snwhitehorn 740188860Snwhitehorn /* Compute the exception vector from the link register */ 741188860Snwhitehorn mfsprg3 %r31 742188860Snwhitehorn ori %r31,%r31,0xff00 743188860Snwhitehorn mflr %r30 744188860Snwhitehorn and %r30,%r30,%r31 745188860Snwhitehorn mtsprg3 %r30 746188860Snwhitehorn 747188860Snwhitehorn /* Test whether we already had PR set */ 748188860Snwhitehorn mfsrr1 %r31 749188860Snwhitehorn mtcr %r31 750188860Snwhitehorn 751125441Sgrehans_trap: 752125441Sgrehan bf 17,k_trap /* branch if PSL_PR is false */ 753125441Sgrehan GET_CPUINFO(%r1) 754125441Sgrehanu_trap: 755125441Sgrehan lwz %r1,PC_CURPCB(%r1) 756125441Sgrehan RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 75795719Sbenno 75895719Sbenno/* 75995719Sbenno * Now the common trap catching code. 76095719Sbenno */ 761125441Sgrehank_trap: 762125441Sgrehan FRAME_SETUP(PC_TEMPSAVE) 763214574Snwhitehorn /* Restore USER_SR */ 764214574Snwhitehorn GET_CPUINFO(%r30) 765214574Snwhitehorn lwz %r30,PC_CURPCB(%r30) 766214574Snwhitehorn lwz %r30,PCB_AIM_USR_VSID(%r30) 767214574Snwhitehorn mtsr USER_SR,%r30; sync; isync 76899032Sbenno/* Call C interrupt dispatcher: */ 76995719Sbennotrapagain: 770125441Sgrehan addi %r3,%r1,8 77199032Sbenno bl CNAME(powerpc_interrupt) 772132075Sgrehan .globl CNAME(trapexit) /* backtrace code sentinel */ 77396773SbennoCNAME(trapexit): 77499032Sbenno 77595719Sbenno/* Disable interrupts: */ 776125441Sgrehan mfmsr %r3 777125441Sgrehan andi. %r3,%r3,~PSL_EE@l 778125441Sgrehan mtmsr %r3 77995719Sbenno/* Test AST pending: */ 780125441Sgrehan lwz %r5,FRAME_SRR1+8(%r1) 781125441Sgrehan mtcr %r5 782125441Sgrehan bf 17,1f /* branch if PSL_PR is false */ 78399032Sbenno 784125441Sgrehan GET_CPUINFO(%r3) /* get per-CPU pointer */ 785223485Snwhitehorn lwz %r4, TD_FLAGS(%r2) /* get thread flags value 786223485Snwhitehorn * (r2 is curthread) */ 787125441Sgrehan lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 788125441Sgrehan ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 789125441Sgrehan and. %r4,%r4,%r5 79095719Sbenno beq 1f 791125441Sgrehan mfmsr %r3 /* re-enable interrupts */ 792125441Sgrehan ori %r3,%r3,PSL_EE@l 793125441Sgrehan mtmsr %r3 79499032Sbenno isync 795125441Sgrehan addi %r3,%r1,8 796103608Sgrehan bl CNAME(ast) 797153685Sgrehan .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 798153685SgrehanCNAME(asttrapexit): 79999032Sbenno b trapexit /* test ast ret value ? */ 80095719Sbenno1: 801125441Sgrehan FRAME_LEAVE(PC_TEMPSAVE) 802190681Snwhitehorn 803190681Snwhitehorn .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 804190681SnwhitehornCNAME(rfi_patch1): 80595719Sbenno rfi 80695719Sbenno 807190681Snwhitehorn .globl CNAME(rfid_patch) 808190681SnwhitehornCNAME(rfid_patch): 809190681Snwhitehorn rfid 810190681Snwhitehorn 811132075Sgrehan#if defined(KDB) 81295719Sbenno/* 813132075Sgrehan * Deliberate entry to dbtrap 81495719Sbenno */ 815178628Smarcel .globl CNAME(breakpoint) 816178628SmarcelCNAME(breakpoint): 817125441Sgrehan mtsprg1 %r1 818125441Sgrehan mfmsr %r3 819125441Sgrehan mtsrr1 %r3 820125441Sgrehan andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 821125441Sgrehan mtmsr %r3 /* disable interrupts */ 82295719Sbenno isync 823125441Sgrehan GET_CPUINFO(%r3) 824132075Sgrehan stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 825132075Sgrehan stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 826132075Sgrehan stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 827132075Sgrehan stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 828125441Sgrehan mflr %r28 829125441Sgrehan li %r29,EXC_BPT 830125441Sgrehan mtlr %r29 831125441Sgrehan mfcr %r29 832125441Sgrehan mtsrr0 %r28 83395719Sbenno 83495719Sbenno/* 835132075Sgrehan * Now the kdb trap catching code. 83695719Sbenno */ 837132075Sgrehandbtrap: 838188951Snwhitehorn /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 839188860Snwhitehorn mflr %r1 840188860Snwhitehorn andi. %r1,%r1,0xff00 841188860Snwhitehorn mtsprg3 %r1 842188860Snwhitehorn 843188860Snwhitehorn lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */ 844188860Snwhitehorn addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l 845188860Snwhitehorn 846132075Sgrehan FRAME_SETUP(PC_DBSAVE) 84795719Sbenno/* Call C trap code: */ 848125441Sgrehan addi %r3,%r1,8 849132075Sgrehan bl CNAME(db_trap_glue) 850125441Sgrehan or. %r3,%r3,%r3 851132075Sgrehan bne dbleave 852132075Sgrehan/* This wasn't for KDB, so switch to real trap: */ 853125441Sgrehan lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 854125441Sgrehan GET_CPUINFO(%r4) 855132075Sgrehan stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 856132075Sgrehan FRAME_LEAVE(PC_DBSAVE) 857125441Sgrehan mtsprg1 %r1 /* prepare for entrance to realtrap */ 858125441Sgrehan GET_CPUINFO(%r1) 859125441Sgrehan stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 860125441Sgrehan stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 861125441Sgrehan stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 862125441Sgrehan stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 863125441Sgrehan mflr %r28 864125441Sgrehan mfcr %r29 865132075Sgrehan lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 866190946Snwhitehorn mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 867125441Sgrehan mfsprg1 %r1 86895719Sbenno b realtrap 869132075Sgrehandbleave: 870132075Sgrehan FRAME_LEAVE(PC_DBSAVE) 871190681Snwhitehorn .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 872190681SnwhitehornCNAME(rfi_patch2): 87395719Sbenno rfi 87495719Sbenno 87595719Sbenno/* 876132075Sgrehan * In case of KDB we want a separate trap catcher for it 87795719Sbenno */ 878132075Sgrehan .globl CNAME(dblow),CNAME(dbsize) 879132075SgrehanCNAME(dblow): 880125441Sgrehan mtsprg1 %r1 /* save SP */ 881125441Sgrehan mtsprg2 %r29 /* save r29 */ 882125441Sgrehan mfcr %r29 /* save CR in r29 */ 883125441Sgrehan mfsrr1 %r1 884125441Sgrehan mtcr %r1 885125441Sgrehan bf 17,1f /* branch if privileged */ 886188860Snwhitehorn 887188860Snwhitehorn /* Unprivileged case */ 888188860Snwhitehorn mtcr %r29 /* put the condition register back */ 889188860Snwhitehorn mfsprg2 %r29 /* ... and r29 */ 890188860Snwhitehorn mflr %r1 /* save LR */ 891188860Snwhitehorn mtsprg2 %r1 /* And then in SPRG2 */ 892188860Snwhitehorn li %r1, 0 /* How to get the vector from LR */ 893188860Snwhitehorn 894188860Snwhitehorn bla generictrap /* and we look like a generic trap */ 895125441Sgrehan1: 896188860Snwhitehorn /* Privileged, so drop to KDB */ 897188860Snwhitehorn GET_CPUINFO(%r1) 898132075Sgrehan stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 899125441Sgrehan mfsprg2 %r28 /* r29 holds cr... */ 900132075Sgrehan stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 901132075Sgrehan stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 902132075Sgrehan stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 903125441Sgrehan mflr %r28 /* save LR */ 904132075Sgrehan bla dbtrap 905132075SgrehanCNAME(dbsize) = .-CNAME(dblow) 906132075Sgrehan#endif /* KDB */ 907