if_axe.c revision 252143
1/*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 252143 2013-06-24 05:18:31Z yongari $"); 35 36/* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51/* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70/* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/bus.h> 82#include <sys/condvar.h> 83#include <sys/endian.h> 84#include <sys/kernel.h> 85#include <sys/lock.h> 86#include <sys/malloc.h> 87#include <sys/mbuf.h> 88#include <sys/module.h> 89#include <sys/mutex.h> 90#include <sys/socket.h> 91#include <sys/sockio.h> 92#include <sys/sysctl.h> 93#include <sys/sx.h> 94 95#include <net/if.h> 96#include <net/ethernet.h> 97#include <net/if_types.h> 98#include <net/if_media.h> 99#include <net/if_vlan_var.h> 100 101#include <dev/mii/mii.h> 102#include <dev/mii/miivar.h> 103 104#include <dev/usb/usb.h> 105#include <dev/usb/usbdi.h> 106#include <dev/usb/usbdi_util.h> 107#include "usbdevs.h" 108 109#define USB_DEBUG_VAR axe_debug 110#include <dev/usb/usb_debug.h> 111#include <dev/usb/usb_process.h> 112 113#include <dev/usb/net/usb_ethernet.h> 114#include <dev/usb/net/if_axereg.h> 115 116/* 117 * AXE_178_MAX_FRAME_BURST 118 * max frame burst size for Ax88178 and Ax88772 119 * 0 2048 bytes 120 * 1 4096 bytes 121 * 2 8192 bytes 122 * 3 16384 bytes 123 * use the largest your system can handle without USB stalling. 124 * 125 * NB: 88772 parts appear to generate lots of input errors with 126 * a 2K rx buffer and 8K is only slightly faster than 4K on an 127 * EHCI port on a T42 so change at your own risk. 128 */ 129#define AXE_178_MAX_FRAME_BURST 1 130 131#define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 132 133#ifdef USB_DEBUG 134static int axe_debug = 0; 135 136static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 137SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0, 138 "Debug level"); 139#endif 140 141/* 142 * Various supported device vendors/products. 143 */ 144static const STRUCT_USB_HOST_ID axe_devs[] = { 145#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 146 AXE_DEV(ABOCOM, UF200, 0), 147 AXE_DEV(ACERCM, EP1427X2, 0), 148 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 149 AXE_DEV(ASIX, AX88172, 0), 150 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 151 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 152 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 153 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), 154 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), 155 AXE_DEV(ATEN, UC210T, 0), 156 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 157 AXE_DEV(BILLIONTON, USB2AR, 0), 158 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 159 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 160 AXE_DEV(DLINK, DUBE100, 0), 161 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 162 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), 163 AXE_DEV(GOODWAY, GWUSB2E, 0), 164 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 165 AXE_DEV(JVC, MP_PRX1, 0), 166 AXE_DEV(LINKSYS2, USB200M, 0), 167 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 168 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 169 AXE_DEV(MELCO, LUAU2KTX, 0), 170 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 171 AXE_DEV(NETGEAR, FA120, 0), 172 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 173 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 174 AXE_DEV(SITECOM, LN029, 0), 175 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 176 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 177#undef AXE_DEV 178}; 179 180static device_probe_t axe_probe; 181static device_attach_t axe_attach; 182static device_detach_t axe_detach; 183 184static usb_callback_t axe_bulk_read_callback; 185static usb_callback_t axe_bulk_write_callback; 186 187static miibus_readreg_t axe_miibus_readreg; 188static miibus_writereg_t axe_miibus_writereg; 189static miibus_statchg_t axe_miibus_statchg; 190 191static uether_fn_t axe_attach_post; 192static uether_fn_t axe_init; 193static uether_fn_t axe_stop; 194static uether_fn_t axe_start; 195static uether_fn_t axe_tick; 196static uether_fn_t axe_setmulti; 197static uether_fn_t axe_setpromisc; 198 199static int axe_attach_post_sub(struct usb_ether *); 200static int axe_ifmedia_upd(struct ifnet *); 201static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 202static int axe_cmd(struct axe_softc *, int, int, int, void *); 203static void axe_ax88178_init(struct axe_softc *); 204static void axe_ax88772_init(struct axe_softc *); 205static void axe_ax88772_phywake(struct axe_softc *); 206static void axe_ax88772a_init(struct axe_softc *); 207static void axe_ax88772b_init(struct axe_softc *); 208static int axe_get_phyno(struct axe_softc *, int); 209static int axe_ioctl(struct ifnet *, u_long, caddr_t); 210static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 211static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 212 unsigned int offset, unsigned int, struct axe_csum_hdr *); 213static void axe_csum_cfg(struct usb_ether *); 214 215static const struct usb_config axe_config[AXE_N_TRANSFER] = { 216 217 [AXE_BULK_DT_WR] = { 218 .type = UE_BULK, 219 .endpoint = UE_ADDR_ANY, 220 .direction = UE_DIR_OUT, 221 .frames = 16, 222 .bufsize = 16 * MCLBYTES, 223 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 224 .callback = axe_bulk_write_callback, 225 .timeout = 10000, /* 10 seconds */ 226 }, 227 228 [AXE_BULK_DT_RD] = { 229 .type = UE_BULK, 230 .endpoint = UE_ADDR_ANY, 231 .direction = UE_DIR_IN, 232 .bufsize = 16384, /* bytes */ 233 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 234 .callback = axe_bulk_read_callback, 235 .timeout = 0, /* no timeout */ 236 }, 237}; 238 239static const struct ax88772b_mfb ax88772b_mfb_table[] = { 240 { 0x8000, 0x8001, 2048 }, 241 { 0x8100, 0x8147, 4096}, 242 { 0x8200, 0x81EB, 6144}, 243 { 0x8300, 0x83D7, 8192}, 244 { 0x8400, 0x851E, 16384}, 245 { 0x8500, 0x8666, 20480}, 246 { 0x8600, 0x87AE, 24576}, 247 { 0x8700, 0x8A3D, 32768} 248}; 249 250static device_method_t axe_methods[] = { 251 /* Device interface */ 252 DEVMETHOD(device_probe, axe_probe), 253 DEVMETHOD(device_attach, axe_attach), 254 DEVMETHOD(device_detach, axe_detach), 255 256 /* MII interface */ 257 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 258 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 259 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 260 261 DEVMETHOD_END 262}; 263 264static driver_t axe_driver = { 265 .name = "axe", 266 .methods = axe_methods, 267 .size = sizeof(struct axe_softc), 268}; 269 270static devclass_t axe_devclass; 271 272DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 273DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 274MODULE_DEPEND(axe, uether, 1, 1, 1); 275MODULE_DEPEND(axe, usb, 1, 1, 1); 276MODULE_DEPEND(axe, ether, 1, 1, 1); 277MODULE_DEPEND(axe, miibus, 1, 1, 1); 278MODULE_VERSION(axe, 1); 279 280static const struct usb_ether_methods axe_ue_methods = { 281 .ue_attach_post = axe_attach_post, 282 .ue_attach_post_sub = axe_attach_post_sub, 283 .ue_start = axe_start, 284 .ue_init = axe_init, 285 .ue_stop = axe_stop, 286 .ue_tick = axe_tick, 287 .ue_setmulti = axe_setmulti, 288 .ue_setpromisc = axe_setpromisc, 289 .ue_mii_upd = axe_ifmedia_upd, 290 .ue_mii_sts = axe_ifmedia_sts, 291}; 292 293static int 294axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 295{ 296 struct usb_device_request req; 297 usb_error_t err; 298 299 AXE_LOCK_ASSERT(sc, MA_OWNED); 300 301 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 302 UT_WRITE_VENDOR_DEVICE : 303 UT_READ_VENDOR_DEVICE); 304 req.bRequest = AXE_CMD_CMD(cmd); 305 USETW(req.wValue, val); 306 USETW(req.wIndex, index); 307 USETW(req.wLength, AXE_CMD_LEN(cmd)); 308 309 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 310 311 return (err); 312} 313 314static int 315axe_miibus_readreg(device_t dev, int phy, int reg) 316{ 317 struct axe_softc *sc = device_get_softc(dev); 318 uint16_t val; 319 int locked; 320 321 locked = mtx_owned(&sc->sc_mtx); 322 if (!locked) 323 AXE_LOCK(sc); 324 325 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 326 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 327 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 328 329 val = le16toh(val); 330 if (AXE_IS_772(sc) && reg == MII_BMSR) { 331 /* 332 * BMSR of AX88772 indicates that it supports extended 333 * capability but the extended status register is 334 * revered for embedded ethernet PHY. So clear the 335 * extended capability bit of BMSR. 336 */ 337 val &= ~BMSR_EXTCAP; 338 } 339 340 if (!locked) 341 AXE_UNLOCK(sc); 342 return (val); 343} 344 345static int 346axe_miibus_writereg(device_t dev, int phy, int reg, int val) 347{ 348 struct axe_softc *sc = device_get_softc(dev); 349 int locked; 350 351 val = htole32(val); 352 locked = mtx_owned(&sc->sc_mtx); 353 if (!locked) 354 AXE_LOCK(sc); 355 356 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 357 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 358 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 359 360 if (!locked) 361 AXE_UNLOCK(sc); 362 return (0); 363} 364 365static void 366axe_miibus_statchg(device_t dev) 367{ 368 struct axe_softc *sc = device_get_softc(dev); 369 struct mii_data *mii = GET_MII(sc); 370 struct ifnet *ifp; 371 uint16_t val; 372 int err, locked; 373 374 locked = mtx_owned(&sc->sc_mtx); 375 if (!locked) 376 AXE_LOCK(sc); 377 378 ifp = uether_getifp(&sc->sc_ue); 379 if (mii == NULL || ifp == NULL || 380 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 381 goto done; 382 383 sc->sc_flags &= ~AXE_FLAG_LINK; 384 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 385 (IFM_ACTIVE | IFM_AVALID)) { 386 switch (IFM_SUBTYPE(mii->mii_media_active)) { 387 case IFM_10_T: 388 case IFM_100_TX: 389 sc->sc_flags |= AXE_FLAG_LINK; 390 break; 391 case IFM_1000_T: 392 if ((sc->sc_flags & AXE_FLAG_178) == 0) 393 break; 394 sc->sc_flags |= AXE_FLAG_LINK; 395 break; 396 default: 397 break; 398 } 399 } 400 401 /* Lost link, do nothing. */ 402 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 403 goto done; 404 405 val = 0; 406 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 407 val |= AXE_MEDIA_FULL_DUPLEX; 408 if (AXE_IS_178_FAMILY(sc)) { 409 if ((IFM_OPTIONS(mii->mii_media_active) & 410 IFM_ETH_TXPAUSE) != 0) 411 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 412 if ((IFM_OPTIONS(mii->mii_media_active) & 413 IFM_ETH_RXPAUSE) != 0) 414 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 415 } 416 } 417 if (AXE_IS_178_FAMILY(sc)) { 418 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 419 if ((sc->sc_flags & AXE_FLAG_178) != 0) 420 val |= AXE_178_MEDIA_ENCK; 421 switch (IFM_SUBTYPE(mii->mii_media_active)) { 422 case IFM_1000_T: 423 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 424 break; 425 case IFM_100_TX: 426 val |= AXE_178_MEDIA_100TX; 427 break; 428 case IFM_10_T: 429 /* doesn't need to be handled */ 430 break; 431 } 432 } 433 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 434 if (err) 435 device_printf(dev, "media change failed, error %d\n", err); 436done: 437 if (!locked) 438 AXE_UNLOCK(sc); 439} 440 441/* 442 * Set media options. 443 */ 444static int 445axe_ifmedia_upd(struct ifnet *ifp) 446{ 447 struct axe_softc *sc = ifp->if_softc; 448 struct mii_data *mii = GET_MII(sc); 449 struct mii_softc *miisc; 450 int error; 451 452 AXE_LOCK_ASSERT(sc, MA_OWNED); 453 454 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 455 PHY_RESET(miisc); 456 error = mii_mediachg(mii); 457 return (error); 458} 459 460/* 461 * Report current media status. 462 */ 463static void 464axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 465{ 466 struct axe_softc *sc = ifp->if_softc; 467 struct mii_data *mii = GET_MII(sc); 468 469 AXE_LOCK(sc); 470 mii_pollstat(mii); 471 ifmr->ifm_active = mii->mii_media_active; 472 ifmr->ifm_status = mii->mii_media_status; 473 AXE_UNLOCK(sc); 474} 475 476static void 477axe_setmulti(struct usb_ether *ue) 478{ 479 struct axe_softc *sc = uether_getsc(ue); 480 struct ifnet *ifp = uether_getifp(ue); 481 struct ifmultiaddr *ifma; 482 uint32_t h = 0; 483 uint16_t rxmode; 484 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 485 486 AXE_LOCK_ASSERT(sc, MA_OWNED); 487 488 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 489 rxmode = le16toh(rxmode); 490 491 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 492 rxmode |= AXE_RXCMD_ALLMULTI; 493 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 494 return; 495 } 496 rxmode &= ~AXE_RXCMD_ALLMULTI; 497 498 if_maddr_rlock(ifp); 499 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 500 { 501 if (ifma->ifma_addr->sa_family != AF_LINK) 502 continue; 503 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 504 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 505 hashtbl[h / 8] |= 1 << (h % 8); 506 } 507 if_maddr_runlock(ifp); 508 509 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 510 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 511} 512 513static int 514axe_get_phyno(struct axe_softc *sc, int sel) 515{ 516 int phyno; 517 518 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 519 case PHY_TYPE_100_HOME: 520 case PHY_TYPE_GIG: 521 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 522 break; 523 case PHY_TYPE_SPECIAL: 524 /* FALLTHROUGH */ 525 case PHY_TYPE_RSVD: 526 /* FALLTHROUGH */ 527 case PHY_TYPE_NON_SUP: 528 /* FALLTHROUGH */ 529 default: 530 phyno = -1; 531 break; 532 } 533 534 return (phyno); 535} 536 537#define AXE_GPIO_WRITE(x, y) do { \ 538 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 539 uether_pause(ue, (y)); \ 540} while (0) 541 542static void 543axe_ax88178_init(struct axe_softc *sc) 544{ 545 struct usb_ether *ue; 546 int gpio0, ledmode, phymode; 547 uint16_t eeprom, val; 548 549 ue = &sc->sc_ue; 550 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 551 /* XXX magic */ 552 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 553 eeprom = le16toh(eeprom); 554 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 555 556 /* if EEPROM is invalid we have to use to GPIO0 */ 557 if (eeprom == 0xffff) { 558 phymode = AXE_PHY_MODE_MARVELL; 559 gpio0 = 1; 560 ledmode = 0; 561 } else { 562 phymode = eeprom & 0x7f; 563 gpio0 = (eeprom & 0x80) ? 0 : 1; 564 ledmode = eeprom >> 8; 565 } 566 567 if (bootverbose) 568 device_printf(sc->sc_ue.ue_dev, 569 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 570 phymode); 571 /* Program GPIOs depending on PHY hardware. */ 572 switch (phymode) { 573 case AXE_PHY_MODE_MARVELL: 574 if (gpio0 == 1) { 575 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 576 hz / 32); 577 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 578 hz / 32); 579 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 580 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 581 hz / 32); 582 } else { 583 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 584 AXE_GPIO1_EN, hz / 3); 585 if (ledmode == 1) { 586 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 587 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 588 hz / 3); 589 } else { 590 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 591 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 592 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 593 AXE_GPIO2_EN, hz / 4); 594 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 595 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 596 } 597 } 598 break; 599 case AXE_PHY_MODE_CICADA: 600 case AXE_PHY_MODE_CICADA_V2: 601 case AXE_PHY_MODE_CICADA_V2_ASIX: 602 if (gpio0 == 1) 603 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 604 AXE_GPIO0_EN, hz / 32); 605 else 606 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 607 AXE_GPIO1_EN, hz / 32); 608 break; 609 case AXE_PHY_MODE_AGERE: 610 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 611 AXE_GPIO1_EN, hz / 32); 612 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 613 AXE_GPIO2_EN, hz / 32); 614 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 615 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 616 AXE_GPIO2_EN, hz / 32); 617 break; 618 case AXE_PHY_MODE_REALTEK_8211CL: 619 case AXE_PHY_MODE_REALTEK_8211BN: 620 case AXE_PHY_MODE_REALTEK_8251CL: 621 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 622 AXE_GPIO1 | AXE_GPIO1_EN; 623 AXE_GPIO_WRITE(val, hz / 32); 624 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 625 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 626 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 627 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 628 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 629 0x1F, 0x0005); 630 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 631 0x0C, 0x0000); 632 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 633 0x0001); 634 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 635 0x01, val | 0x0080); 636 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 637 0x1F, 0x0000); 638 } 639 break; 640 default: 641 /* Unknown PHY model or no need to program GPIOs. */ 642 break; 643 } 644 645 /* soft reset */ 646 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 647 uether_pause(ue, hz / 4); 648 649 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 650 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 651 uether_pause(ue, hz / 4); 652 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 653 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 654 uether_pause(ue, hz / 4); 655 656 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 657} 658 659static void 660axe_ax88772_init(struct axe_softc *sc) 661{ 662 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 663 uether_pause(&sc->sc_ue, hz / 16); 664 665 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 666 /* ask for the embedded PHY */ 667 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 668 uether_pause(&sc->sc_ue, hz / 64); 669 670 /* power down and reset state, pin reset state */ 671 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 672 AXE_SW_RESET_CLEAR, NULL); 673 uether_pause(&sc->sc_ue, hz / 16); 674 675 /* power down/reset state, pin operating state */ 676 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 677 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 678 uether_pause(&sc->sc_ue, hz / 4); 679 680 /* power up, reset */ 681 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 682 683 /* power up, operating */ 684 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 685 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 686 } else { 687 /* ask for external PHY */ 688 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 689 uether_pause(&sc->sc_ue, hz / 64); 690 691 /* power down internal PHY */ 692 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 693 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 694 } 695 696 uether_pause(&sc->sc_ue, hz / 4); 697 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 698} 699 700static void 701axe_ax88772_phywake(struct axe_softc *sc) 702{ 703 struct usb_ether *ue; 704 705 ue = &sc->sc_ue; 706 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 707 /* Manually select internal(embedded) PHY - MAC mode. */ 708 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 709 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 710 NULL); 711 uether_pause(&sc->sc_ue, hz / 32); 712 } else { 713 /* 714 * Manually select external PHY - MAC mode. 715 * Reverse MII/RMII is for AX88772A PHY mode. 716 */ 717 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 718 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 719 uether_pause(&sc->sc_ue, hz / 32); 720 } 721 /* Take PHY out of power down. */ 722 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 723 AXE_SW_RESET_IPRL, NULL); 724 uether_pause(&sc->sc_ue, hz / 4); 725 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 726 uether_pause(&sc->sc_ue, hz); 727 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 728 uether_pause(&sc->sc_ue, hz / 32); 729 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 730 uether_pause(&sc->sc_ue, hz / 32); 731} 732 733static void 734axe_ax88772a_init(struct axe_softc *sc) 735{ 736 struct usb_ether *ue; 737 738 ue = &sc->sc_ue; 739 /* Reload EEPROM. */ 740 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 741 axe_ax88772_phywake(sc); 742 /* Stop MAC. */ 743 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 744} 745 746static void 747axe_ax88772b_init(struct axe_softc *sc) 748{ 749 struct usb_ether *ue; 750 uint16_t eeprom; 751 uint8_t *eaddr; 752 int i; 753 754 ue = &sc->sc_ue; 755 /* Reload EEPROM. */ 756 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 757 /* 758 * Save PHY power saving configuration(high byte) and 759 * clear EEPROM checksum value(low byte). 760 */ 761 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 762 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 763 764 /* 765 * Auto-loaded default station address from internal ROM is 766 * 00:00:00:00:00:00 such that an explicit access to EEPROM 767 * is required to get real station address. 768 */ 769 eaddr = ue->ue_eaddr; 770 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 771 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 772 &eeprom); 773 eeprom = le16toh(eeprom); 774 *eaddr++ = (uint8_t)(eeprom & 0xFF); 775 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 776 } 777 /* Wakeup PHY. */ 778 axe_ax88772_phywake(sc); 779 /* Stop MAC. */ 780 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 781} 782 783#undef AXE_GPIO_WRITE 784 785static void 786axe_reset(struct axe_softc *sc) 787{ 788 struct usb_config_descriptor *cd; 789 usb_error_t err; 790 791 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 792 793 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 794 cd->bConfigurationValue); 795 if (err) 796 DPRINTF("reset failed (ignored)\n"); 797 798 /* Wait a little while for the chip to get its brains in order. */ 799 uether_pause(&sc->sc_ue, hz / 100); 800 801 /* Reinitialize controller to achieve full reset. */ 802 if (sc->sc_flags & AXE_FLAG_178) 803 axe_ax88178_init(sc); 804 else if (sc->sc_flags & AXE_FLAG_772) 805 axe_ax88772_init(sc); 806 else if (sc->sc_flags & AXE_FLAG_772A) 807 axe_ax88772a_init(sc); 808 else if (sc->sc_flags & AXE_FLAG_772B) 809 axe_ax88772b_init(sc); 810} 811 812static void 813axe_attach_post(struct usb_ether *ue) 814{ 815 struct axe_softc *sc = uether_getsc(ue); 816 817 /* 818 * Load PHY indexes first. Needed by axe_xxx_init(). 819 */ 820 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 821 if (bootverbose) 822 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 823 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 824 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 825 if (sc->sc_phyno == -1) 826 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 827 if (sc->sc_phyno == -1) { 828 device_printf(sc->sc_ue.ue_dev, 829 "no valid PHY address found, assuming PHY address 0\n"); 830 sc->sc_phyno = 0; 831 } 832 833 /* Initialize controller and get station address. */ 834 if (sc->sc_flags & AXE_FLAG_178) { 835 axe_ax88178_init(sc); 836 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 837 } else if (sc->sc_flags & AXE_FLAG_772) { 838 axe_ax88772_init(sc); 839 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 840 } else if (sc->sc_flags & AXE_FLAG_772A) { 841 axe_ax88772a_init(sc); 842 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 843 } else if (sc->sc_flags & AXE_FLAG_772B) { 844 axe_ax88772b_init(sc); 845 } else 846 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 847 848 /* 849 * Fetch IPG values. 850 */ 851 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 852 /* Set IPG values. */ 853 sc->sc_ipgs[0] = 0x15; 854 sc->sc_ipgs[1] = 0x16; 855 sc->sc_ipgs[2] = 0x1A; 856 } else 857 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 858} 859 860static int 861axe_attach_post_sub(struct usb_ether *ue) 862{ 863 struct axe_softc *sc; 864 struct ifnet *ifp; 865 u_int adv_pause; 866 int error; 867 868 sc = uether_getsc(ue); 869 ifp = ue->ue_ifp; 870 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 871 ifp->if_start = uether_start; 872 ifp->if_ioctl = axe_ioctl; 873 ifp->if_init = uether_init; 874 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 875 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 876 IFQ_SET_READY(&ifp->if_snd); 877 878 if (AXE_IS_178_FAMILY(sc)) 879 ifp->if_capabilities |= IFCAP_VLAN_MTU; 880 if (sc->sc_flags & AXE_FLAG_772B) { 881 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM; 882 ifp->if_hwassist = AXE_CSUM_FEATURES; 883 /* 884 * Checksum offloading of AX88772B also works with VLAN 885 * tagged frames but there is no way to take advantage 886 * of the feature because vlan(4) assumes 887 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 888 * support checksum offloading with VLAN. VLAN hardware 889 * tagging support of AX88772B is very limited so it's 890 * not possible to announce IFCAP_VLAN_HWTAGGING. 891 */ 892 } 893 ifp->if_capenable = ifp->if_capabilities; 894 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) 895 adv_pause = MIIF_DOPAUSE; 896 else 897 adv_pause = 0; 898 mtx_lock(&Giant); 899 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 900 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 901 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); 902 mtx_unlock(&Giant); 903 904 return (error); 905} 906 907/* 908 * Probe for a AX88172 chip. 909 */ 910static int 911axe_probe(device_t dev) 912{ 913 struct usb_attach_arg *uaa = device_get_ivars(dev); 914 915 if (uaa->usb_mode != USB_MODE_HOST) 916 return (ENXIO); 917 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 918 return (ENXIO); 919 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 920 return (ENXIO); 921 922 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 923} 924 925/* 926 * Attach the interface. Allocate softc structures, do ifmedia 927 * setup and ethernet/BPF attach. 928 */ 929static int 930axe_attach(device_t dev) 931{ 932 struct usb_attach_arg *uaa = device_get_ivars(dev); 933 struct axe_softc *sc = device_get_softc(dev); 934 struct usb_ether *ue = &sc->sc_ue; 935 uint8_t iface_index; 936 int error; 937 938 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 939 940 device_set_usb_desc(dev); 941 942 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 943 944 iface_index = AXE_IFACE_IDX; 945 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 946 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 947 if (error) { 948 device_printf(dev, "allocating USB transfers failed\n"); 949 goto detach; 950 } 951 952 ue->ue_sc = sc; 953 ue->ue_dev = dev; 954 ue->ue_udev = uaa->device; 955 ue->ue_mtx = &sc->sc_mtx; 956 ue->ue_methods = &axe_ue_methods; 957 958 error = uether_ifattach(ue); 959 if (error) { 960 device_printf(dev, "could not attach interface\n"); 961 goto detach; 962 } 963 return (0); /* success */ 964 965detach: 966 axe_detach(dev); 967 return (ENXIO); /* failure */ 968} 969 970static int 971axe_detach(device_t dev) 972{ 973 struct axe_softc *sc = device_get_softc(dev); 974 struct usb_ether *ue = &sc->sc_ue; 975 976 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 977 uether_ifdetach(ue); 978 mtx_destroy(&sc->sc_mtx); 979 980 return (0); 981} 982 983#if (AXE_BULK_BUF_SIZE >= 0x10000) 984#error "Please update axe_bulk_read_callback()!" 985#endif 986 987static void 988axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 989{ 990 struct axe_softc *sc = usbd_xfer_softc(xfer); 991 struct usb_ether *ue = &sc->sc_ue; 992 struct usb_page_cache *pc; 993 int actlen; 994 995 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 996 997 switch (USB_GET_STATE(xfer)) { 998 case USB_ST_TRANSFERRED: 999 pc = usbd_xfer_get_frame(xfer, 0); 1000 axe_rx_frame(ue, pc, actlen); 1001 1002 /* FALLTHROUGH */ 1003 case USB_ST_SETUP: 1004tr_setup: 1005 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1006 usbd_transfer_submit(xfer); 1007 uether_rxflush(ue); 1008 return; 1009 1010 default: /* Error */ 1011 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 1012 1013 if (error != USB_ERR_CANCELLED) { 1014 /* try to clear stall first */ 1015 usbd_xfer_set_stall(xfer); 1016 goto tr_setup; 1017 } 1018 return; 1019 1020 } 1021} 1022 1023static int 1024axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 1025{ 1026 struct axe_softc *sc; 1027 struct axe_sframe_hdr hdr; 1028 struct axe_csum_hdr csum_hdr; 1029 int error, len, pos; 1030 1031 sc = uether_getsc(ue); 1032 pos = 0; 1033 len = 0; 1034 error = 0; 1035 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 1036 while (pos < actlen) { 1037 if ((int)(pos + sizeof(hdr)) > actlen) { 1038 /* too little data */ 1039 error = EINVAL; 1040 break; 1041 } 1042 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 1043 1044 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 1045 /* we lost sync */ 1046 error = EINVAL; 1047 break; 1048 } 1049 pos += sizeof(hdr); 1050 len = le16toh(hdr.len); 1051 if (pos + len > actlen) { 1052 /* invalid length */ 1053 error = EINVAL; 1054 break; 1055 } 1056 axe_rxeof(ue, pc, pos, len, NULL); 1057 pos += len + (len % 2); 1058 } 1059 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 1060 while (pos < actlen) { 1061 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 1062 /* too little data */ 1063 error = EINVAL; 1064 break; 1065 } 1066 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 1067 1068 csum_hdr.len = le16toh(csum_hdr.len); 1069 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1070 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1071 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1072 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1073 sc->sc_lenmask) { 1074 /* we lost sync */ 1075 error = EINVAL; 1076 break; 1077 } 1078 /* 1079 * Get total transferred frame length including 1080 * checksum header. The length should be multiple 1081 * of 4. 1082 */ 1083 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 1084 len = (len + 3) & ~3; 1085 if (pos + len > actlen) { 1086 /* invalid length */ 1087 error = EINVAL; 1088 break; 1089 } 1090 axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 1091 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 1092 pos += len; 1093 } 1094 } else 1095 axe_rxeof(ue, pc, 0, actlen, NULL); 1096 1097 if (error != 0) 1098 ue->ue_ifp->if_ierrors++; 1099 return (error); 1100} 1101 1102static int 1103axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1104 unsigned int len, struct axe_csum_hdr *csum_hdr) 1105{ 1106 struct ifnet *ifp = ue->ue_ifp; 1107 struct mbuf *m; 1108 1109 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1110 ifp->if_ierrors++; 1111 return (EINVAL); 1112 } 1113 1114 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1115 if (m == NULL) { 1116 ifp->if_iqdrops++; 1117 return (ENOMEM); 1118 } 1119 m->m_len = m->m_pkthdr.len = MCLBYTES; 1120 m_adj(m, ETHER_ALIGN); 1121 1122 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1123 1124 ifp->if_ipackets++; 1125 m->m_pkthdr.rcvif = ifp; 1126 m->m_pkthdr.len = m->m_len = len; 1127 1128 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1129 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | 1130 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { 1131 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1132 CSUM_IP_VALID; 1133 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1134 AXE_CSUM_HDR_L4_TYPE_TCP || 1135 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1136 AXE_CSUM_HDR_L4_TYPE_UDP) { 1137 m->m_pkthdr.csum_flags |= 1138 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1139 m->m_pkthdr.csum_data = 0xffff; 1140 } 1141 } 1142 } 1143 1144 _IF_ENQUEUE(&ue->ue_rxq, m); 1145 return (0); 1146} 1147 1148#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 1149#error "Please update axe_bulk_write_callback()!" 1150#endif 1151 1152static void 1153axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1154{ 1155 struct axe_softc *sc = usbd_xfer_softc(xfer); 1156 struct axe_sframe_hdr hdr; 1157 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1158 struct usb_page_cache *pc; 1159 struct mbuf *m; 1160 int nframes, pos; 1161 1162 switch (USB_GET_STATE(xfer)) { 1163 case USB_ST_TRANSFERRED: 1164 DPRINTFN(11, "transfer complete\n"); 1165 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1166 /* FALLTHROUGH */ 1167 case USB_ST_SETUP: 1168tr_setup: 1169 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 1170 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 1171 /* 1172 * Don't send anything if there is no link or 1173 * controller is busy. 1174 */ 1175 return; 1176 } 1177 1178 for (nframes = 0; nframes < 16 && 1179 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 1180 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1181 if (m == NULL) 1182 break; 1183 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1184 nframes); 1185 pos = 0; 1186 pc = usbd_xfer_get_frame(xfer, nframes); 1187 if (AXE_IS_178_FAMILY(sc)) { 1188 hdr.len = htole16(m->m_pkthdr.len); 1189 hdr.ilen = ~hdr.len; 1190 /* 1191 * If upper stack computed checksum, driver 1192 * should tell controller not to insert 1193 * computed checksum for checksum offloading 1194 * enabled controller. 1195 */ 1196 if (ifp->if_capabilities & IFCAP_TXCSUM) { 1197 if ((m->m_pkthdr.csum_flags & 1198 AXE_CSUM_FEATURES) != 0) 1199 hdr.len |= htole16( 1200 AXE_TX_CSUM_PSEUDO_HDR); 1201 else 1202 hdr.len |= htole16( 1203 AXE_TX_CSUM_DIS); 1204 } 1205 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 1206 pos += sizeof(hdr); 1207 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1208 pos += m->m_pkthdr.len; 1209 if ((pos % 512) == 0) { 1210 hdr.len = 0; 1211 hdr.ilen = 0xffff; 1212 usbd_copy_in(pc, pos, &hdr, 1213 sizeof(hdr)); 1214 pos += sizeof(hdr); 1215 } 1216 } else { 1217 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1218 pos += m->m_pkthdr.len; 1219 } 1220 1221 /* 1222 * XXX 1223 * Update TX packet counter here. This is not 1224 * correct way but it seems that there is no way 1225 * to know how many packets are sent at the end 1226 * of transfer because controller combines 1227 * multiple writes into single one if there is 1228 * room in TX buffer of controller. 1229 */ 1230 ifp->if_opackets++; 1231 1232 /* 1233 * if there's a BPF listener, bounce a copy 1234 * of this frame to him: 1235 */ 1236 BPF_MTAP(ifp, m); 1237 1238 m_freem(m); 1239 1240 /* Set frame length. */ 1241 usbd_xfer_set_frame_len(xfer, nframes, pos); 1242 } 1243 if (nframes != 0) { 1244 usbd_xfer_set_frames(xfer, nframes); 1245 usbd_transfer_submit(xfer); 1246 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1247 } 1248 return; 1249 /* NOTREACHED */ 1250 default: /* Error */ 1251 DPRINTFN(11, "transfer error, %s\n", 1252 usbd_errstr(error)); 1253 1254 ifp->if_oerrors++; 1255 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1256 1257 if (error != USB_ERR_CANCELLED) { 1258 /* try to clear stall first */ 1259 usbd_xfer_set_stall(xfer); 1260 goto tr_setup; 1261 } 1262 return; 1263 1264 } 1265} 1266 1267static void 1268axe_tick(struct usb_ether *ue) 1269{ 1270 struct axe_softc *sc = uether_getsc(ue); 1271 struct mii_data *mii = GET_MII(sc); 1272 1273 AXE_LOCK_ASSERT(sc, MA_OWNED); 1274 1275 mii_tick(mii); 1276 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1277 axe_miibus_statchg(ue->ue_dev); 1278 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1279 axe_start(ue); 1280 } 1281} 1282 1283static void 1284axe_start(struct usb_ether *ue) 1285{ 1286 struct axe_softc *sc = uether_getsc(ue); 1287 1288 /* 1289 * start the USB transfers, if not already started: 1290 */ 1291 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1292 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1293} 1294 1295static void 1296axe_csum_cfg(struct usb_ether *ue) 1297{ 1298 struct axe_softc *sc; 1299 struct ifnet *ifp; 1300 uint16_t csum1, csum2; 1301 1302 sc = uether_getsc(ue); 1303 AXE_LOCK_ASSERT(sc, MA_OWNED); 1304 1305 if ((sc->sc_flags & AXE_FLAG_772B) != 0) { 1306 ifp = uether_getifp(ue); 1307 csum1 = 0; 1308 csum2 = 0; 1309 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1310 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | 1311 AXE_TXCSUM_UDP; 1312 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1313 csum1 = 0; 1314 csum2 = 0; 1315 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1316 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | 1317 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | 1318 AXE_RXCSUM_IGMP; 1319 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1320 } 1321} 1322 1323static void 1324axe_init(struct usb_ether *ue) 1325{ 1326 struct axe_softc *sc = uether_getsc(ue); 1327 struct ifnet *ifp = uether_getifp(ue); 1328 uint16_t rxmode; 1329 1330 AXE_LOCK_ASSERT(sc, MA_OWNED); 1331 1332 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1333 return; 1334 1335 /* Cancel pending I/O */ 1336 axe_stop(ue); 1337 1338 axe_reset(sc); 1339 1340 /* Set MAC address and transmitter IPG values. */ 1341 if (AXE_IS_178_FAMILY(sc)) { 1342 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1343 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1344 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1345 } else { 1346 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1347 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1348 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1349 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1350 } 1351 1352 if (AXE_IS_178_FAMILY(sc)) { 1353 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1354 if ((sc->sc_flags & AXE_FLAG_772B) != 0 && 1355 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1356 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1357 sc->sc_flags |= AXE_FLAG_CSUM_FRAME; 1358 } else { 1359 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1360 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1361 } 1362 } 1363 1364 /* Configure TX/RX checksum offloading. */ 1365 axe_csum_cfg(ue); 1366 1367 if (sc->sc_flags & AXE_FLAG_772B) { 1368 /* AX88772B uses different maximum frame burst configuration. */ 1369 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1370 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1371 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1372 } 1373 1374 /* Enable receiver, set RX mode. */ 1375 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1376 if (AXE_IS_178_FAMILY(sc)) { 1377 if (sc->sc_flags & AXE_FLAG_772B) { 1378 /* 1379 * Select RX header format type 1. Aligning IP 1380 * header on 4 byte boundary is not needed when 1381 * checksum offloading feature is not used 1382 * because we always copy the received frame in 1383 * RX handler. When RX checksum offloading is 1384 * active, aligning IP header is required to 1385 * reflect actual frame length including RX 1386 * header size. 1387 */ 1388 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1389 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1390 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1391 } else { 1392 /* 1393 * Default Rx buffer size is too small to get 1394 * maximum performance. 1395 */ 1396 rxmode |= AXE_178_RXCMD_MFB_16384; 1397 } 1398 } else { 1399 rxmode |= AXE_172_RXCMD_UNICAST; 1400 } 1401 1402 /* If we want promiscuous mode, set the allframes bit. */ 1403 if (ifp->if_flags & IFF_PROMISC) 1404 rxmode |= AXE_RXCMD_PROMISC; 1405 1406 if (ifp->if_flags & IFF_BROADCAST) 1407 rxmode |= AXE_RXCMD_BROADCAST; 1408 1409 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1410 1411 /* Load the multicast filter. */ 1412 axe_setmulti(ue); 1413 1414 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1415 1416 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1417 /* Switch to selected media. */ 1418 axe_ifmedia_upd(ifp); 1419} 1420 1421static void 1422axe_setpromisc(struct usb_ether *ue) 1423{ 1424 struct axe_softc *sc = uether_getsc(ue); 1425 struct ifnet *ifp = uether_getifp(ue); 1426 uint16_t rxmode; 1427 1428 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1429 1430 rxmode = le16toh(rxmode); 1431 1432 if (ifp->if_flags & IFF_PROMISC) { 1433 rxmode |= AXE_RXCMD_PROMISC; 1434 } else { 1435 rxmode &= ~AXE_RXCMD_PROMISC; 1436 } 1437 1438 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1439 1440 axe_setmulti(ue); 1441} 1442 1443static void 1444axe_stop(struct usb_ether *ue) 1445{ 1446 struct axe_softc *sc = uether_getsc(ue); 1447 struct ifnet *ifp = uether_getifp(ue); 1448 1449 AXE_LOCK_ASSERT(sc, MA_OWNED); 1450 1451 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1452 sc->sc_flags &= ~AXE_FLAG_LINK; 1453 1454 /* 1455 * stop all the transfers, if not already stopped: 1456 */ 1457 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1458 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1459} 1460 1461static int 1462axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1463{ 1464 struct usb_ether *ue = ifp->if_softc; 1465 struct axe_softc *sc; 1466 struct ifreq *ifr; 1467 int error, mask, reinit; 1468 1469 sc = uether_getsc(ue); 1470 ifr = (struct ifreq *)data; 1471 error = 0; 1472 reinit = 0; 1473 if (cmd == SIOCSIFCAP) { 1474 AXE_LOCK(sc); 1475 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1476 if ((mask & IFCAP_TXCSUM) != 0 && 1477 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1478 ifp->if_capenable ^= IFCAP_TXCSUM; 1479 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1480 ifp->if_hwassist |= AXE_CSUM_FEATURES; 1481 else 1482 ifp->if_hwassist &= ~AXE_CSUM_FEATURES; 1483 reinit++; 1484 } 1485 if ((mask & IFCAP_RXCSUM) != 0 && 1486 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1487 ifp->if_capenable ^= IFCAP_RXCSUM; 1488 reinit++; 1489 } 1490 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1491 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1492 else 1493 reinit = 0; 1494 AXE_UNLOCK(sc); 1495 if (reinit > 0) 1496 uether_init(ue); 1497 } else 1498 error = uether_ioctl(ifp, cmd, data); 1499 1500 return (error); 1501} 1502