140804Ssemenu/*- 240804Ssemenu * Copyright (c) 1997 Semen Ustimenko 340804Ssemenu * All rights reserved. 440804Ssemenu * 540804Ssemenu * Redistribution and use in source and binary forms, with or without 640804Ssemenu * modification, are permitted provided that the following conditions 740804Ssemenu * are met: 840804Ssemenu * 1. Redistributions of source code must retain the above copyright 940804Ssemenu * notice, this list of conditions and the following disclaimer. 1040804Ssemenu * 2. Redistributions in binary form must reproduce the above copyright 1140804Ssemenu * notice, this list of conditions and the following disclaimer in the 1240804Ssemenu * documentation and/or other materials provided with the distribution. 1340804Ssemenu * 1440804Ssemenu * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1540804Ssemenu * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1640804Ssemenu * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1740804Ssemenu * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1840804Ssemenu * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1940804Ssemenu * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2040804Ssemenu * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2140804Ssemenu * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2240804Ssemenu * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2340804Ssemenu * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2440804Ssemenu * SUCH DAMAGE. 25105666Ssemenu * 26105666Ssemenu * $FreeBSD$ 2740804Ssemenu */ 2840804Ssemenu 2940804Ssemenu/* 3040804Ssemenu * Configuration 3140804Ssemenu */ 32105666Ssemenu/*#define EPIC_DIAG 1*/ 3359164Ssemenu/*#define EPIC_USEIOSPACE 1*/ 34105666Ssemenu/*#define EPIC_EARLY_RX 1*/ 3559164Ssemenu 3640804Ssemenu#ifndef ETHER_MAX_LEN 3740804Ssemenu#define ETHER_MAX_LEN 1518 3840804Ssemenu#endif 3940804Ssemenu#ifndef ETHER_MIN_LEN 4040804Ssemenu#define ETHER_MIN_LEN 64 4140804Ssemenu#endif 4240804Ssemenu#ifndef ETHER_CRC_LEN 4340804Ssemenu#define ETHER_CRC_LEN 4 4440804Ssemenu#endif 4540804Ssemenu#define TX_RING_SIZE 16 /* Leave this a power of 2 */ 4640804Ssemenu#define RX_RING_SIZE 16 /* And this too, to do not */ 4740804Ssemenu /* confuse RX(TX)_RING_MASK */ 4840804Ssemenu#define TX_RING_MASK (TX_RING_SIZE - 1) 4940804Ssemenu#define RX_RING_MASK (RX_RING_SIZE - 1) 5040804Ssemenu#define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN) 51105966Ssam#define ETHER_ALIGN 2 5240804Ssemenu 5340804Ssemenu/* This is driver's structure to define EPIC descriptors */ 5440804Ssemenustruct epic_rx_buffer { 55113754Smux struct mbuf *mbuf; /* mbuf receiving packet */ 56113754Smux bus_dmamap_t map; /* DMA map */ 5740804Ssemenu}; 5840804Ssemenu 5940804Ssemenustruct epic_tx_buffer { 60113754Smux struct mbuf *mbuf; /* mbuf contained packet */ 61113754Smux bus_dmamap_t map; /* DMA map */ 6240804Ssemenu}; 6340804Ssemenu 6472134Ssemenu/* PHY, known by tx driver */ 6572134Ssemenu#define EPIC_UNKN_PHY 0x0000 6672134Ssemenu#define EPIC_QS6612_PHY 0x0001 6772134Ssemenu#define EPIC_AC101_PHY 0x0002 6872134Ssemenu#define EPIC_LXT970_PHY 0x0003 6972134Ssemenu#define EPIC_SERIAL 0x0004 7072134Ssemenu 7140804Ssemenu/* Driver status structure */ 7240804Ssemenutypedef struct { 73147256Sbrooks struct ifnet *ifp; 7459164Ssemenu struct resource *res; 7559164Ssemenu struct resource *irq; 7659164Ssemenu 7759164Ssemenu device_t miibus; 7861906Ssemenu device_t dev; 79179706Sjhb struct callout timer; 80179706Sjhb struct mtx lock; 81179706Sjhb int tx_timeout; 8259164Ssemenu 8340804Ssemenu void *sc_ih; 84113754Smux bus_dma_tag_t mtag; 85113754Smux bus_dma_tag_t rtag; 86113754Smux bus_dmamap_t rmap; 87113754Smux bus_dma_tag_t ttag; 88113754Smux bus_dmamap_t tmap; 89113754Smux bus_dma_tag_t ftag; 90113754Smux bus_dmamap_t fmap; 91113754Smux bus_dmamap_t sparemap; 9259164Ssemenu 9340804Ssemenu struct epic_rx_buffer rx_buffer[RX_RING_SIZE]; 9440804Ssemenu struct epic_tx_buffer tx_buffer[TX_RING_SIZE]; 9540804Ssemenu 9640804Ssemenu /* Each element of array MUST be aligned on dword */ 9740804Ssemenu /* and bounded on PAGE_SIZE */ 9840804Ssemenu struct epic_rx_desc *rx_desc; 9940804Ssemenu struct epic_tx_desc *tx_desc; 10040804Ssemenu struct epic_frag_list *tx_flist; 101113754Smux u_int32_t rx_addr; 102113754Smux u_int32_t tx_addr; 103113754Smux u_int32_t frag_addr; 10440804Ssemenu u_int32_t flags; 10540804Ssemenu u_int32_t tx_threshold; 10640804Ssemenu u_int32_t txcon; 10772134Ssemenu u_int32_t miicfg; 10840804Ssemenu u_int32_t cur_tx; 10940804Ssemenu u_int32_t cur_rx; 11040804Ssemenu u_int32_t dirty_tx; 11140804Ssemenu u_int32_t pending_txs; 11272134Ssemenu u_int16_t cardvend; 11372134Ssemenu u_int16_t cardid; 11472134Ssemenu struct mii_softc *physc; 11572134Ssemenu u_int32_t phyid; 11672134Ssemenu int serinst; 117105666Ssemenu void *pool; 11840804Ssemenu} epic_softc_t; 11940804Ssemenu 120179706Sjhb#define EPIC_LOCK(sc) mtx_lock(&(sc)->lock) 121179706Sjhb#define EPIC_UNLOCK(sc) mtx_unlock(&(sc)->lock) 122179706Sjhb#define EPIC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED) 123179706Sjhb 12459164Ssemenustruct epic_type { 12559164Ssemenu u_int16_t ven_id; 12659164Ssemenu u_int16_t dev_id; 12759164Ssemenu char *name; 12859164Ssemenu}; 12959164Ssemenu 130105666Ssemenu#define CSR_WRITE_4(sc, reg, val) \ 131179706Sjhb bus_write_4((sc)->res, (reg), (val)) 132105666Ssemenu#define CSR_WRITE_2(sc, reg, val) \ 133179706Sjhb bus_write_2((sc)->res, (reg), (val)) 134105666Ssemenu#define CSR_WRITE_1(sc, reg, val) \ 135179706Sjhb bus_write_1((sc)->res, (reg), (val)) 136105666Ssemenu#define CSR_READ_4(sc, reg) \ 137179706Sjhb bus_read_4((sc)->res, (reg)) 138105666Ssemenu#define CSR_READ_2(sc, reg) \ 139179706Sjhb bus_read_2((sc)->res, (reg)) 140105666Ssemenu#define CSR_READ_1(sc, reg) \ 141179706Sjhb bus_read_1((sc)->res, (reg)) 14240804Ssemenu 143105666Ssemenu#define PHY_READ_2(sc, phy, reg) \ 144105666Ssemenu epic_read_phy_reg((sc), (phy), (reg)) 145105666Ssemenu#define PHY_WRITE_2(sc, phy, reg, val) \ 146105666Ssemenu epic_write_phy_reg((sc), (phy), (reg), (val)) 147