1176774Sraj/*- 2209908Sraj * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski 3209908Sraj * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 4176774Sraj * All rights reserved. 5176774Sraj * 6176774Sraj * Redistribution and use in source and binary forms, with or without 7176774Sraj * modification, are permitted provided that the following conditions 8176774Sraj * are met: 9176774Sraj * 1. Redistributions of source code must retain the above copyright 10176774Sraj * notice, this list of conditions and the following disclaimer. 11176774Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176774Sraj * notice, this list of conditions and the following disclaimer in the 13176774Sraj * documentation and/or other materials provided with the distribution. 14176774Sraj * 15176774Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176774Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176774Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176774Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176774Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176774Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176774Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176774Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176774Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176774Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176774Sraj */ 26176774Sraj 27176774Sraj/* 28176774Sraj * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 29176774Sraj */ 30176774Sraj#include <sys/cdefs.h> 31176774Sraj__FBSDID("$FreeBSD$"); 32176774Sraj 33188711Sraj#ifdef HAVE_KERNEL_OPTION_HEADERS 34188711Sraj#include "opt_device_polling.h" 35188711Sraj#endif 36188711Sraj 37176774Sraj#include <sys/param.h> 38176774Sraj#include <sys/systm.h> 39182189Sraj#include <sys/bus.h> 40176774Sraj#include <sys/endian.h> 41176774Sraj#include <sys/mbuf.h> 42176774Sraj#include <sys/kernel.h> 43176774Sraj#include <sys/module.h> 44176774Sraj#include <sys/socket.h> 45182189Sraj#include <sys/sockio.h> 46176774Sraj#include <sys/sysctl.h> 47176774Sraj 48182189Sraj#include <net/bpf.h> 49182189Sraj#include <net/ethernet.h> 50176774Sraj#include <net/if.h> 51182189Sraj#include <net/if_arp.h> 52176774Sraj#include <net/if_dl.h> 53176774Sraj#include <net/if_media.h> 54182189Sraj#include <net/if_types.h> 55182189Sraj#include <net/if_vlan_var.h> 56176774Sraj 57188711Sraj#include <netinet/in_systm.h> 58188711Sraj#include <netinet/in.h> 59188711Sraj#include <netinet/ip.h> 60188711Sraj 61176774Sraj#include <machine/bus.h> 62176774Sraj 63176774Sraj#include <dev/mii/mii.h> 64176774Sraj#include <dev/mii/miivar.h> 65176774Sraj 66176774Sraj#include <dev/tsec/if_tsec.h> 67176774Sraj#include <dev/tsec/if_tsecreg.h> 68176774Sraj 69182189Srajstatic int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 70182189Sraj bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 71182189Sraj const char *dname); 72182189Srajstatic void tsec_dma_ctl(struct tsec_softc *sc, int state); 73188711Srajstatic int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head, 74188711Sraj int fcb_inserted); 75176774Srajstatic void tsec_free_dma(struct tsec_softc *sc); 76182189Srajstatic void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 77176774Srajstatic int tsec_ifmedia_upd(struct ifnet *ifp); 78176774Srajstatic void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 79176774Srajstatic int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 80176774Sraj struct mbuf **mbufp, uint32_t *paddr); 81176774Srajstatic void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 82176774Sraj int nseg, int error); 83182189Srajstatic void tsec_intrs_ctl(struct tsec_softc *sc, int state); 84182189Srajstatic void tsec_init(void *xsc); 85182189Srajstatic void tsec_init_locked(struct tsec_softc *sc); 86182189Srajstatic int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 87182189Srajstatic void tsec_reset_mac(struct tsec_softc *sc); 88182189Srajstatic void tsec_setfilter(struct tsec_softc *sc); 89182189Srajstatic void tsec_set_mac_address(struct tsec_softc *sc); 90182189Srajstatic void tsec_start(struct ifnet *ifp); 91182189Srajstatic void tsec_start_locked(struct ifnet *ifp); 92176774Srajstatic void tsec_stop(struct tsec_softc *sc); 93182189Srajstatic void tsec_tick(void *arg); 94182189Srajstatic void tsec_watchdog(struct tsec_softc *sc); 95188711Srajstatic void tsec_add_sysctls(struct tsec_softc *sc); 96188711Srajstatic int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 97188711Srajstatic int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 98188711Srajstatic void tsec_set_rxic(struct tsec_softc *sc); 99188711Srajstatic void tsec_set_txic(struct tsec_softc *sc); 100193096Sattiliostatic int tsec_receive_intr_locked(struct tsec_softc *sc, int count); 101188711Srajstatic void tsec_transmit_intr_locked(struct tsec_softc *sc); 102188711Srajstatic void tsec_error_intr_locked(struct tsec_softc *sc, int count); 103188711Srajstatic void tsec_offload_setup(struct tsec_softc *sc); 104188711Srajstatic void tsec_offload_process_frame(struct tsec_softc *sc, 105188711Sraj struct mbuf *m); 106188711Srajstatic void tsec_setup_multicast(struct tsec_softc *sc); 107188711Srajstatic int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 108176774Sraj 109182189Srajdevclass_t tsec_devclass; 110182189SrajDRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); 111182189SrajMODULE_DEPEND(tsec, ether, 1, 1, 1); 112182189SrajMODULE_DEPEND(tsec, miibus, 1, 1, 1); 113176774Sraj 114182189Srajint 115182189Srajtsec_attach(struct tsec_softc *sc) 116182189Sraj{ 117182189Sraj uint8_t hwaddr[ETHER_ADDR_LEN]; 118182189Sraj struct ifnet *ifp; 119182189Sraj bus_dmamap_t *map_ptr; 120182189Sraj bus_dmamap_t **map_pptr; 121182189Sraj int error = 0; 122182189Sraj int i; 123176774Sraj 124182189Sraj /* Reset all TSEC counters */ 125182189Sraj TSEC_TX_RX_COUNTERS_INIT(sc); 126176774Sraj 127182189Sraj /* Stop DMA engine if enabled by firmware */ 128182189Sraj tsec_dma_ctl(sc, 0); 129176774Sraj 130182189Sraj /* Reset MAC */ 131182189Sraj tsec_reset_mac(sc); 132176774Sraj 133182189Sraj /* Disable interrupts for now */ 134182189Sraj tsec_intrs_ctl(sc, 0); 135176774Sraj 136188711Sraj /* Configure defaults for interrupts coalescing */ 137188711Sraj sc->rx_ic_time = 768; 138188711Sraj sc->rx_ic_count = 16; 139188711Sraj sc->tx_ic_time = 768; 140188711Sraj sc->tx_ic_count = 16; 141188711Sraj tsec_set_rxic(sc); 142188711Sraj tsec_set_txic(sc); 143188711Sraj tsec_add_sysctls(sc); 144188711Sraj 145182189Sraj /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 146188711Sraj error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 147188711Sraj &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 148182189Sraj (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 149188711Sraj 150182189Sraj if (error) { 151182189Sraj tsec_detach(sc); 152182189Sraj return (ENXIO); 153182189Sraj } 154176774Sraj 155182189Sraj /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 156188711Sraj error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 157188711Sraj &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 158182189Sraj (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 159182189Sraj if (error) { 160182189Sraj tsec_detach(sc); 161182189Sraj return (ENXIO); 162182189Sraj } 163176774Sraj 164182189Sraj /* Allocate a busdma tag for TX mbufs. */ 165182189Sraj error = bus_dma_tag_create(NULL, /* parent */ 166188712Sraj TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 167188712Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 168188712Sraj BUS_SPACE_MAXADDR, /* highaddr */ 169188712Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 170188712Sraj MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 171188712Sraj TSEC_TX_NUM_DESC - 1, /* nsegments */ 172188712Sraj MCLBYTES, 0, /* maxsegsz, flags */ 173188712Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 174188712Sraj &sc->tsec_tx_mtag); /* dmat */ 175182189Sraj if (error) { 176188712Sraj device_printf(sc->dev, "failed to allocate busdma tag " 177188712Sraj "(tx mbufs)\n"); 178182189Sraj tsec_detach(sc); 179182189Sraj return (ENXIO); 180182189Sraj } 181182189Sraj 182182189Sraj /* Allocate a busdma tag for RX mbufs. */ 183182189Sraj error = bus_dma_tag_create(NULL, /* parent */ 184188712Sraj TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 185188712Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 186188712Sraj BUS_SPACE_MAXADDR, /* highaddr */ 187188712Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 188188712Sraj MCLBYTES, /* maxsize */ 189188712Sraj 1, /* nsegments */ 190188712Sraj MCLBYTES, 0, /* maxsegsz, flags */ 191188712Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 192188712Sraj &sc->tsec_rx_mtag); /* dmat */ 193182189Sraj if (error) { 194188712Sraj device_printf(sc->dev, "failed to allocate busdma tag " 195188712Sraj "(rx mbufs)\n"); 196182189Sraj tsec_detach(sc); 197182189Sraj return (ENXIO); 198182189Sraj } 199182189Sraj 200182189Sraj /* Create TX busdma maps */ 201182189Sraj map_ptr = sc->tx_map_data; 202182189Sraj map_pptr = sc->tx_map_unused_data; 203182189Sraj 204182189Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 205182189Sraj map_pptr[i] = &map_ptr[i]; 206182189Sraj error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]); 207182189Sraj if (error) { 208182189Sraj device_printf(sc->dev, "failed to init TX ring\n"); 209182189Sraj tsec_detach(sc); 210182189Sraj return (ENXIO); 211182189Sraj } 212182189Sraj } 213182189Sraj 214182189Sraj /* Create RX busdma maps and zero mbuf handlers */ 215182189Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 216188712Sraj error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 217188712Sraj &sc->rx_data[i].map); 218182189Sraj if (error) { 219182189Sraj device_printf(sc->dev, "failed to init RX ring\n"); 220182189Sraj tsec_detach(sc); 221182189Sraj return (ENXIO); 222182189Sraj } 223182189Sraj sc->rx_data[i].mbuf = NULL; 224182189Sraj } 225182189Sraj 226182189Sraj /* Create mbufs for RX buffers */ 227182189Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 228182189Sraj error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 229182189Sraj &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 230182189Sraj if (error) { 231188712Sraj device_printf(sc->dev, "can't load rx DMA map %d, " 232188712Sraj "error = %d\n", i, error); 233182189Sraj tsec_detach(sc); 234182189Sraj return (error); 235182189Sraj } 236182189Sraj } 237182189Sraj 238182189Sraj /* Create network interface for upper layers */ 239182189Sraj ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 240182189Sraj if (ifp == NULL) { 241182189Sraj device_printf(sc->dev, "if_alloc() failed\n"); 242182189Sraj tsec_detach(sc); 243182189Sraj return (ENOMEM); 244182189Sraj } 245182189Sraj 246182189Sraj ifp->if_softc = sc; 247182189Sraj if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 248188711Sraj ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 249182189Sraj ifp->if_init = tsec_init; 250182189Sraj ifp->if_start = tsec_start; 251182189Sraj ifp->if_ioctl = tsec_ioctl; 252182189Sraj 253182189Sraj IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 254182189Sraj ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 255182189Sraj IFQ_SET_READY(&ifp->if_snd); 256182189Sraj 257188711Sraj ifp->if_capabilities = IFCAP_VLAN_MTU; 258188711Sraj if (sc->is_etsec) 259188711Sraj ifp->if_capabilities |= IFCAP_HWCSUM; 260188711Sraj 261182189Sraj ifp->if_capenable = ifp->if_capabilities; 262182189Sraj 263188711Sraj#ifdef DEVICE_POLLING 264188711Sraj /* Advertise that polling is supported */ 265188711Sraj ifp->if_capabilities |= IFCAP_POLLING; 266188711Sraj#endif 267188711Sraj 268213893Smarius /* Attach PHY(s) */ 269213893Smarius error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd, 270213893Smarius tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 271213893Smarius 0); 272182189Sraj if (error) { 273213893Smarius device_printf(sc->dev, "attaching PHYs failed\n"); 274182189Sraj if_free(ifp); 275182189Sraj sc->tsec_ifp = NULL; 276182189Sraj tsec_detach(sc); 277182189Sraj return (error); 278182189Sraj } 279182189Sraj sc->tsec_mii = device_get_softc(sc->tsec_miibus); 280182189Sraj 281182189Sraj /* Set MAC address */ 282182189Sraj tsec_get_hwaddr(sc, hwaddr); 283182189Sraj ether_ifattach(ifp, hwaddr); 284182189Sraj 285182189Sraj return (0); 286182189Sraj} 287182189Sraj 288182189Srajint 289182189Srajtsec_detach(struct tsec_softc *sc) 290176774Sraj{ 291176774Sraj 292235144Sthompsa if (sc->tsec_ifp != NULL) { 293188711Sraj#ifdef DEVICE_POLLING 294235144Sthompsa if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 295235144Sthompsa ether_poll_deregister(sc->tsec_ifp); 296188711Sraj#endif 297188711Sraj 298235144Sthompsa /* Stop TSEC controller and free TX queue */ 299235144Sthompsa if (sc->sc_rres) 300235144Sthompsa tsec_shutdown(sc->dev); 301182189Sraj 302235144Sthompsa /* Detach network interface */ 303182189Sraj ether_ifdetach(sc->tsec_ifp); 304182189Sraj if_free(sc->tsec_ifp); 305182189Sraj sc->tsec_ifp = NULL; 306177110Sraj } 307177110Sraj 308182189Sraj /* Free DMA resources */ 309182189Sraj tsec_free_dma(sc); 310176774Sraj 311182189Sraj return (0); 312176774Sraj} 313176774Sraj 314194101Srajint 315182189Srajtsec_shutdown(device_t dev) 316182189Sraj{ 317182189Sraj struct tsec_softc *sc; 318182189Sraj 319182189Sraj sc = device_get_softc(dev); 320182189Sraj 321182189Sraj TSEC_GLOBAL_LOCK(sc); 322182189Sraj tsec_stop(sc); 323182189Sraj TSEC_GLOBAL_UNLOCK(sc); 324194101Sraj return (0); 325182189Sraj} 326182189Sraj 327182189Srajint 328182189Srajtsec_suspend(device_t dev) 329182189Sraj{ 330182189Sraj 331182189Sraj /* TODO not implemented! */ 332182189Sraj return (0); 333182189Sraj} 334182189Sraj 335182189Srajint 336182189Srajtsec_resume(device_t dev) 337182189Sraj{ 338182189Sraj 339182189Sraj /* TODO not implemented! */ 340182189Sraj return (0); 341182189Sraj} 342182189Sraj 343176774Srajstatic void 344176774Srajtsec_init(void *xsc) 345176774Sraj{ 346176774Sraj struct tsec_softc *sc = xsc; 347176774Sraj 348176774Sraj TSEC_GLOBAL_LOCK(sc); 349176774Sraj tsec_init_locked(sc); 350176774Sraj TSEC_GLOBAL_UNLOCK(sc); 351176774Sraj} 352176774Sraj 353176774Srajstatic void 354176774Srajtsec_init_locked(struct tsec_softc *sc) 355176774Sraj{ 356176774Sraj struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 357176774Sraj struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 358176774Sraj struct ifnet *ifp = sc->tsec_ifp; 359188712Sraj uint32_t timeout, val, i; 360176774Sraj 361235147Sthompsa if (ifp->if_drv_flags & IFF_DRV_RUNNING) 362235147Sthompsa return; 363235147Sthompsa 364176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 365176774Sraj tsec_stop(sc); 366176774Sraj 367176774Sraj /* 368176774Sraj * These steps are according to the MPC8555E PowerQUICCIII RM: 369176774Sraj * 14.7 Initialization/Application Information 370176774Sraj */ 371176774Sraj 372176774Sraj /* Step 1: soft reset MAC */ 373176774Sraj tsec_reset_mac(sc); 374176774Sraj 375176774Sraj /* Step 2: Initialize MACCFG2 */ 376176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG2, 377176774Sraj TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 378176774Sraj TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 379176774Sraj TSEC_MACCFG2_GMII | /* I/F Mode bit */ 380176774Sraj TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 381176774Sraj ); 382176774Sraj 383176774Sraj /* Step 3: Initialize ECNTRL 384176774Sraj * While the documentation states that R100M is ignored if RPM is 385176774Sraj * not set, it does seem to be needed to get the orange boxes to 386176774Sraj * work (which have a Marvell 88E1111 PHY). Go figure. 387176774Sraj */ 388176774Sraj 389176774Sraj /* 390176774Sraj * XXX kludge - use circumstancial evidence to program ECNTRL 391176774Sraj * correctly. Ideally we need some board information to guide 392176774Sraj * us here. 393176774Sraj */ 394176774Sraj i = TSEC_READ(sc, TSEC_REG_ID2); 395176774Sraj val = (i & 0xffff) 396176774Sraj ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 397176774Sraj : TSEC_ECNTRL_R100M; /* Orange + CDS */ 398176774Sraj TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 399176774Sraj 400176774Sraj /* Step 4: Initialize MAC station address */ 401176774Sraj tsec_set_mac_address(sc); 402176774Sraj 403176774Sraj /* 404176774Sraj * Step 5: Assign a Physical address to the TBI so as to not conflict 405176774Sraj * with the external PHY physical address 406176774Sraj */ 407176774Sraj TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 408176774Sraj 409176774Sraj /* Step 6: Reset the management interface */ 410232518Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 411176774Sraj 412176774Sraj /* Step 7: Setup the MII Mgmt clock speed */ 413232518Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 414176774Sraj 415176774Sraj /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 416176774Sraj timeout = TSEC_READ_RETRY; 417232518Sraj while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & 418176774Sraj TSEC_MIIMIND_BUSY)) 419176774Sraj DELAY(TSEC_READ_DELAY); 420176774Sraj if (timeout == 0) { 421176774Sraj if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 422176774Sraj return; 423176774Sraj } 424176774Sraj 425176774Sraj /* Step 9: Setup the MII Mgmt */ 426176774Sraj mii_mediachg(sc->tsec_mii); 427176774Sraj 428176774Sraj /* Step 10: Clear IEVENT register */ 429176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 430176774Sraj 431188711Sraj /* Step 11: Enable interrupts */ 432188711Sraj#ifdef DEVICE_POLLING 433188711Sraj /* 434188711Sraj * ...only if polling is not turned on. Disable interrupts explicitly 435188711Sraj * if polling is enabled. 436188711Sraj */ 437188711Sraj if (ifp->if_capenable & IFCAP_POLLING ) 438188711Sraj tsec_intrs_ctl(sc, 0); 439188711Sraj else 440188711Sraj#endif /* DEVICE_POLLING */ 441176774Sraj tsec_intrs_ctl(sc, 1); 442176774Sraj 443176774Sraj /* Step 12: Initialize IADDRn */ 444176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 445176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 446176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 447176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 448176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 449176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 450176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 451176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 452176774Sraj 453176774Sraj /* Step 13: Initialize GADDRn */ 454176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 455176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 456176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 457176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 458176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 459176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 460176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 461176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 462176774Sraj 463176774Sraj /* Step 14: Initialize RCTRL */ 464176774Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 465176774Sraj 466176774Sraj /* Step 15: Initialize DMACTRL */ 467176774Sraj tsec_dma_ctl(sc, 1); 468176774Sraj 469176774Sraj /* Step 16: Initialize FIFO_PAUSE_CTRL */ 470176774Sraj TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 471176774Sraj 472176774Sraj /* 473176774Sraj * Step 17: Initialize transmit/receive descriptor rings. 474176774Sraj * Initialize TBASE and RBASE. 475176774Sraj */ 476176774Sraj TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 477176774Sraj TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 478176774Sraj 479176774Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 480176774Sraj tx_desc[i].bufptr = 0; 481176774Sraj tx_desc[i].length = 0; 482188712Sraj tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 483188712Sraj TSEC_TXBD_W : 0); 484176774Sraj } 485182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 486182189Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 487176774Sraj 488176774Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 489176774Sraj rx_desc[i].bufptr = sc->rx_data[i].paddr; 490176774Sraj rx_desc[i].length = 0; 491176774Sraj rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 492182189Sraj ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 493176774Sraj } 494188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 495188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 496176774Sraj 497188711Sraj /* Step 18: Initialize the maximum receive buffer length */ 498188711Sraj TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 499176774Sraj 500188711Sraj /* Step 19: Configure ethernet frame sizes */ 501188711Sraj TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 502188711Sraj tsec_set_mtu(sc, ifp->if_mtu); 503188711Sraj 504188711Sraj /* Step 20: Enable Rx and RxBD sdata snooping */ 505176774Sraj TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 506176774Sraj TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 507176774Sraj 508188711Sraj /* Step 21: Reset collision counters in hardware */ 509176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 510176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 511176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 512176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 513176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 514176774Sraj 515188711Sraj /* Step 22: Mask all CAM interrupts */ 516176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 517176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 518176774Sraj 519188711Sraj /* Step 23: Enable Rx and Tx */ 520176774Sraj val = TSEC_READ(sc, TSEC_REG_MACCFG1); 521176774Sraj val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 522176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 523176774Sraj 524188711Sraj /* Step 24: Reset TSEC counters for Tx and Rx rings */ 525176774Sraj TSEC_TX_RX_COUNTERS_INIT(sc); 526176774Sraj 527188711Sraj /* Step 25: Setup TCP/IP Off-Load engine */ 528188711Sraj if (sc->is_etsec) 529188711Sraj tsec_offload_setup(sc); 530188711Sraj 531188711Sraj /* Step 26: Setup multicast filters */ 532188711Sraj tsec_setup_multicast(sc); 533188711Sraj 534188711Sraj /* Step 27: Activate network interface */ 535176774Sraj ifp->if_drv_flags |= IFF_DRV_RUNNING; 536176774Sraj ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 537176774Sraj sc->tsec_if_flags = ifp->if_flags; 538182187Sraj sc->tsec_watchdog = 0; 539177111Sraj 540177111Sraj /* Schedule watchdog timeout */ 541182187Sraj callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 542176774Sraj} 543176774Sraj 544176774Srajstatic void 545176774Srajtsec_set_mac_address(struct tsec_softc *sc) 546176774Sraj{ 547176774Sraj uint32_t macbuf[2] = { 0, 0 }; 548188712Sraj char *macbufp, *curmac; 549182189Sraj int i; 550176774Sraj 551176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 552176774Sraj 553176774Sraj KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 554188712Sraj ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, 555188712Sraj sizeof(macbuf))); 556176774Sraj 557176774Sraj macbufp = (char *)macbuf; 558176774Sraj curmac = (char *)IF_LLADDR(sc->tsec_ifp); 559176774Sraj 560176774Sraj /* Correct order of MAC address bytes */ 561176774Sraj for (i = 1; i <= ETHER_ADDR_LEN; i++) 562176774Sraj macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 563176774Sraj 564176774Sraj /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 565176774Sraj TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 566176774Sraj TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 567176774Sraj} 568176774Sraj 569176774Sraj/* 570176774Sraj * DMA control function, if argument state is: 571176774Sraj * 0 - DMA engine will be disabled 572176774Sraj * 1 - DMA engine will be enabled 573176774Sraj */ 574176774Srajstatic void 575176774Srajtsec_dma_ctl(struct tsec_softc *sc, int state) 576176774Sraj{ 577176774Sraj device_t dev; 578188712Sraj uint32_t dma_flags, timeout; 579176774Sraj 580176774Sraj dev = sc->dev; 581176774Sraj 582176774Sraj dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 583176774Sraj 584176774Sraj switch (state) { 585176774Sraj case 0: 586176774Sraj /* Temporarily clear stop graceful stop bits. */ 587176774Sraj tsec_dma_ctl(sc, 1000); 588176774Sraj 589176774Sraj /* Set it again */ 590176774Sraj dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 591176774Sraj break; 592176774Sraj case 1000: 593176774Sraj case 1: 594176774Sraj /* Set write with response (WWR), wait (WOP) and snoop bits */ 595176774Sraj dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 596176774Sraj DMACTRL_WWR | DMACTRL_WOP); 597176774Sraj 598176774Sraj /* Clear graceful stop bits */ 599176774Sraj dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 600176774Sraj break; 601176774Sraj default: 602176774Sraj device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 603176774Sraj state); 604176774Sraj } 605176774Sraj 606176774Sraj TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 607176774Sraj 608176774Sraj switch (state) { 609176774Sraj case 0: 610176774Sraj /* Wait for DMA stop */ 611176774Sraj timeout = TSEC_READ_RETRY; 612176774Sraj while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 613176774Sraj (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 614176774Sraj DELAY(TSEC_READ_DELAY); 615176774Sraj 616176774Sraj if (timeout == 0) 617176774Sraj device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 618176774Sraj break; 619176774Sraj case 1: 620176774Sraj /* Restart transmission function */ 621176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 622176774Sraj } 623176774Sraj} 624176774Sraj 625176774Sraj/* 626176774Sraj * Interrupts control function, if argument state is: 627176774Sraj * 0 - all TSEC interrupts will be masked 628176774Sraj * 1 - all TSEC interrupts will be unmasked 629176774Sraj */ 630176774Srajstatic void 631176774Srajtsec_intrs_ctl(struct tsec_softc *sc, int state) 632176774Sraj{ 633176774Sraj device_t dev; 634176774Sraj 635176774Sraj dev = sc->dev; 636176774Sraj 637176774Sraj switch (state) { 638176774Sraj case 0: 639176774Sraj TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 640176774Sraj break; 641176774Sraj case 1: 642188712Sraj TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 643188712Sraj TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 644188712Sraj TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 645188712Sraj TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 646176774Sraj break; 647176774Sraj default: 648176774Sraj device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 649176774Sraj state); 650176774Sraj } 651176774Sraj} 652176774Sraj 653176774Srajstatic void 654176774Srajtsec_reset_mac(struct tsec_softc *sc) 655176774Sraj{ 656176774Sraj uint32_t maccfg1_flags; 657176774Sraj 658176774Sraj /* Set soft reset bit */ 659176774Sraj maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 660176774Sraj maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 661176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 662176774Sraj 663176774Sraj /* Clear soft reset bit */ 664176774Sraj maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 665176774Sraj maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 666176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 667176774Sraj} 668176774Sraj 669176774Srajstatic void 670177111Srajtsec_watchdog(struct tsec_softc *sc) 671176774Sraj{ 672177111Sraj struct ifnet *ifp; 673176774Sraj 674177111Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 675176774Sraj 676182187Sraj if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 677177111Sraj return; 678177111Sraj 679177111Sraj ifp = sc->tsec_ifp; 680176774Sraj ifp->if_oerrors++; 681176774Sraj if_printf(ifp, "watchdog timeout\n"); 682176774Sraj 683176774Sraj tsec_stop(sc); 684176774Sraj tsec_init_locked(sc); 685176774Sraj} 686176774Sraj 687176774Srajstatic void 688176774Srajtsec_start(struct ifnet *ifp) 689176774Sraj{ 690176774Sraj struct tsec_softc *sc = ifp->if_softc; 691176774Sraj 692176774Sraj TSEC_TRANSMIT_LOCK(sc); 693176774Sraj tsec_start_locked(ifp); 694176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 695176774Sraj} 696176774Sraj 697176774Srajstatic void 698176774Srajtsec_start_locked(struct ifnet *ifp) 699176774Sraj{ 700176774Sraj struct tsec_softc *sc; 701188711Sraj struct mbuf *m0, *mtmp; 702188711Sraj struct tsec_tx_fcb *tx_fcb; 703176774Sraj unsigned int queued = 0; 704188711Sraj int csum_flags, fcb_inserted = 0; 705176774Sraj 706176774Sraj sc = ifp->if_softc; 707176774Sraj 708176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 709176774Sraj 710176774Sraj if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 711176774Sraj IFF_DRV_RUNNING) 712176774Sraj return; 713176774Sraj 714176774Sraj if (sc->tsec_link == 0) 715176774Sraj return; 716176774Sraj 717188712Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 718188712Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 719176774Sraj 720199580Sraj while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 721176774Sraj /* Get packet from the queue */ 722199580Sraj IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 723176774Sraj if (m0 == NULL) 724176774Sraj break; 725176774Sraj 726188711Sraj /* Insert TCP/IP Off-load frame control block */ 727188711Sraj csum_flags = m0->m_pkthdr.csum_flags; 728188711Sraj if (csum_flags) { 729188711Sraj 730243857Sglebius M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT); 731188711Sraj if (m0 == NULL) 732188711Sraj break; 733188711Sraj 734188711Sraj tx_fcb = mtod(m0, struct tsec_tx_fcb *); 735188711Sraj tx_fcb->flags = 0; 736188711Sraj tx_fcb->l3_offset = ETHER_HDR_LEN; 737188711Sraj tx_fcb->l4_offset = sizeof(struct ip); 738188711Sraj 739188711Sraj if (csum_flags & CSUM_IP) 740188711Sraj tx_fcb->flags |= TSEC_TX_FCB_IP4 | 741188711Sraj TSEC_TX_FCB_CSUM_IP; 742188711Sraj 743188711Sraj if (csum_flags & CSUM_TCP) 744188711Sraj tx_fcb->flags |= TSEC_TX_FCB_TCP | 745188711Sraj TSEC_TX_FCB_CSUM_TCP_UDP; 746188711Sraj 747188711Sraj if (csum_flags & CSUM_UDP) 748188711Sraj tx_fcb->flags |= TSEC_TX_FCB_UDP | 749188711Sraj TSEC_TX_FCB_CSUM_TCP_UDP; 750188711Sraj 751188711Sraj fcb_inserted = 1; 752188711Sraj } 753188711Sraj 754243857Sglebius mtmp = m_defrag(m0, M_NOWAIT); 755176774Sraj if (mtmp) 756176774Sraj m0 = mtmp; 757176774Sraj 758188711Sraj if (tsec_encap(sc, m0, fcb_inserted)) { 759199580Sraj IFQ_DRV_PREPEND(&ifp->if_snd, m0); 760176774Sraj ifp->if_drv_flags |= IFF_DRV_OACTIVE; 761176774Sraj break; 762176774Sraj } 763176774Sraj queued++; 764176774Sraj BPF_MTAP(ifp, m0); 765176774Sraj } 766188712Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 767188712Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 768176774Sraj 769176774Sraj if (queued) { 770176774Sraj /* Enable transmitter and watchdog timer */ 771176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 772182187Sraj sc->tsec_watchdog = 5; 773176774Sraj } 774176774Sraj} 775176774Sraj 776176774Srajstatic int 777188711Srajtsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted) 778176774Sraj{ 779176774Sraj struct tsec_desc *tx_desc = NULL; 780176774Sraj struct ifnet *ifp; 781176774Sraj bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; 782176774Sraj bus_dmamap_t *mapp; 783188711Sraj int csum_flag = 0, error, seg, nsegs; 784176774Sraj 785176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 786176774Sraj 787176774Sraj ifp = sc->tsec_ifp; 788176774Sraj 789176774Sraj if (TSEC_FREE_TX_DESC(sc) == 0) { 790176774Sraj /* No free descriptors */ 791176774Sraj return (-1); 792176774Sraj } 793176774Sraj 794176774Sraj /* Fetch unused map */ 795176774Sraj mapp = TSEC_ALLOC_TX_MAP(sc); 796176774Sraj 797176774Sraj /* Create mapping in DMA memory */ 798176774Sraj error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 799188712Sraj *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); 800176774Sraj if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { 801176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 802176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 803176774Sraj return ((error != 0) ? error : -1); 804176774Sraj } 805176774Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); 806176774Sraj 807176774Sraj if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) 808176774Sraj if_printf(ifp, "TX buffer has %d segments\n", nsegs); 809176774Sraj 810188711Sraj if (fcb_inserted) 811188711Sraj csum_flag = TSEC_TXBD_TOE; 812188711Sraj 813176774Sraj /* Everything is ok, now we can send buffers */ 814176774Sraj for (seg = 0; seg < nsegs; seg++) { 815176774Sraj tx_desc = TSEC_GET_CUR_TX_DESC(sc); 816176774Sraj 817176774Sraj tx_desc->length = segs[seg].ds_len; 818176774Sraj tx_desc->bufptr = segs[seg].ds_addr; 819176774Sraj 820188711Sraj /* 821188711Sraj * Set flags: 822188711Sraj * - wrap 823188711Sraj * - checksum 824188711Sraj * - ready to send 825188711Sraj * - transmit the CRC sequence after the last data byte 826188711Sraj * - interrupt after the last buffer 827188711Sraj */ 828176774Sraj tx_desc->flags = 829188711Sraj (tx_desc->flags & TSEC_TXBD_W) | 830188711Sraj ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC | 831188711Sraj ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0); 832176774Sraj } 833176774Sraj 834176774Sraj /* Save mbuf and DMA mapping for release at later stage */ 835176774Sraj TSEC_PUT_TX_MBUF(sc, m0); 836176774Sraj TSEC_PUT_TX_MAP(sc, mapp); 837176774Sraj 838176774Sraj return (0); 839176774Sraj} 840176774Sraj 841176774Srajstatic void 842176774Srajtsec_setfilter(struct tsec_softc *sc) 843176774Sraj{ 844176774Sraj struct ifnet *ifp; 845176774Sraj uint32_t flags; 846176774Sraj 847176774Sraj ifp = sc->tsec_ifp; 848176774Sraj flags = TSEC_READ(sc, TSEC_REG_RCTRL); 849176774Sraj 850176774Sraj /* Promiscuous mode */ 851176774Sraj if (ifp->if_flags & IFF_PROMISC) 852176774Sraj flags |= TSEC_RCTRL_PROM; 853176774Sraj else 854176774Sraj flags &= ~TSEC_RCTRL_PROM; 855176774Sraj 856176774Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 857176774Sraj} 858176774Sraj 859188711Sraj#ifdef DEVICE_POLLING 860188711Srajstatic poll_handler_t tsec_poll; 861188711Sraj 862193096Sattiliostatic int 863188711Srajtsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 864188711Sraj{ 865188711Sraj uint32_t ie; 866188711Sraj struct tsec_softc *sc = ifp->if_softc; 867193096Sattilio int rx_npkts; 868188711Sraj 869193096Sattilio rx_npkts = 0; 870193096Sattilio 871188711Sraj TSEC_GLOBAL_LOCK(sc); 872188711Sraj if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 873188711Sraj TSEC_GLOBAL_UNLOCK(sc); 874193096Sattilio return (rx_npkts); 875188711Sraj } 876188711Sraj 877188711Sraj if (cmd == POLL_AND_CHECK_STATUS) { 878188715Sraj tsec_error_intr_locked(sc, count); 879188711Sraj 880188711Sraj /* Clear all events reported */ 881188715Sraj ie = TSEC_READ(sc, TSEC_REG_IEVENT); 882188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 883188711Sraj } 884188711Sraj 885188711Sraj tsec_transmit_intr_locked(sc); 886188711Sraj 887188711Sraj TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 888188711Sraj 889193096Sattilio rx_npkts = tsec_receive_intr_locked(sc, count); 890188711Sraj 891188711Sraj TSEC_RECEIVE_UNLOCK(sc); 892193096Sattilio 893193096Sattilio return (rx_npkts); 894188711Sraj} 895188711Sraj#endif /* DEVICE_POLLING */ 896188711Sraj 897176774Srajstatic int 898176774Srajtsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 899176774Sraj{ 900176774Sraj struct tsec_softc *sc = ifp->if_softc; 901176774Sraj struct ifreq *ifr = (struct ifreq *)data; 902176774Sraj device_t dev; 903188711Sraj int mask, error = 0; 904176774Sraj 905176774Sraj dev = sc->dev; 906176774Sraj 907176774Sraj switch (command) { 908188711Sraj case SIOCSIFMTU: 909188711Sraj TSEC_GLOBAL_LOCK(sc); 910188711Sraj if (tsec_set_mtu(sc, ifr->ifr_mtu)) 911188711Sraj ifp->if_mtu = ifr->ifr_mtu; 912188711Sraj else 913188711Sraj error = EINVAL; 914188711Sraj TSEC_GLOBAL_UNLOCK(sc); 915188711Sraj break; 916176774Sraj case SIOCSIFFLAGS: 917176774Sraj TSEC_GLOBAL_LOCK(sc); 918176774Sraj if (ifp->if_flags & IFF_UP) { 919176774Sraj if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 920188711Sraj if ((sc->tsec_if_flags ^ ifp->if_flags) & 921188711Sraj IFF_PROMISC) 922176774Sraj tsec_setfilter(sc); 923188711Sraj 924188711Sraj if ((sc->tsec_if_flags ^ ifp->if_flags) & 925188711Sraj IFF_ALLMULTI) 926188711Sraj tsec_setup_multicast(sc); 927176774Sraj } else 928176774Sraj tsec_init_locked(sc); 929182189Sraj } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 930182189Sraj tsec_stop(sc); 931182189Sraj 932176774Sraj sc->tsec_if_flags = ifp->if_flags; 933176774Sraj TSEC_GLOBAL_UNLOCK(sc); 934176774Sraj break; 935188711Sraj case SIOCADDMULTI: 936188711Sraj case SIOCDELMULTI: 937188711Sraj if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 938188711Sraj TSEC_GLOBAL_LOCK(sc); 939188711Sraj tsec_setup_multicast(sc); 940188711Sraj TSEC_GLOBAL_UNLOCK(sc); 941188711Sraj } 942176774Sraj case SIOCGIFMEDIA: 943176774Sraj case SIOCSIFMEDIA: 944188711Sraj error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 945188711Sraj command); 946176774Sraj break; 947188711Sraj case SIOCSIFCAP: 948188711Sraj mask = ifp->if_capenable ^ ifr->ifr_reqcap; 949188711Sraj if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 950188711Sraj TSEC_GLOBAL_LOCK(sc); 951188711Sraj ifp->if_capenable &= ~IFCAP_HWCSUM; 952188711Sraj ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 953188711Sraj tsec_offload_setup(sc); 954188711Sraj TSEC_GLOBAL_UNLOCK(sc); 955188711Sraj } 956188711Sraj#ifdef DEVICE_POLLING 957188711Sraj if (mask & IFCAP_POLLING) { 958188711Sraj if (ifr->ifr_reqcap & IFCAP_POLLING) { 959188711Sraj error = ether_poll_register(tsec_poll, ifp); 960188711Sraj if (error) 961188711Sraj return (error); 962188711Sraj 963188711Sraj TSEC_GLOBAL_LOCK(sc); 964188711Sraj /* Disable interrupts */ 965188711Sraj tsec_intrs_ctl(sc, 0); 966188711Sraj ifp->if_capenable |= IFCAP_POLLING; 967188711Sraj TSEC_GLOBAL_UNLOCK(sc); 968188711Sraj } else { 969188711Sraj error = ether_poll_deregister(ifp); 970188711Sraj TSEC_GLOBAL_LOCK(sc); 971188711Sraj /* Enable interrupts */ 972188711Sraj tsec_intrs_ctl(sc, 1); 973188711Sraj ifp->if_capenable &= ~IFCAP_POLLING; 974188711Sraj TSEC_GLOBAL_UNLOCK(sc); 975188711Sraj } 976188711Sraj } 977188711Sraj#endif 978188719Sraj break; 979188711Sraj 980176774Sraj default: 981176774Sraj error = ether_ioctl(ifp, command, data); 982176774Sraj } 983176774Sraj 984176774Sraj /* Flush buffers if not empty */ 985176774Sraj if (ifp->if_flags & IFF_UP) 986176774Sraj tsec_start(ifp); 987176774Sraj return (error); 988176774Sraj} 989176774Sraj 990176774Srajstatic int 991176774Srajtsec_ifmedia_upd(struct ifnet *ifp) 992176774Sraj{ 993176774Sraj struct tsec_softc *sc = ifp->if_softc; 994176774Sraj struct mii_data *mii; 995176774Sraj 996176774Sraj TSEC_TRANSMIT_LOCK(sc); 997176774Sraj 998176774Sraj mii = sc->tsec_mii; 999176774Sraj mii_mediachg(mii); 1000176774Sraj 1001176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 1002176774Sraj return (0); 1003176774Sraj} 1004176774Sraj 1005176774Srajstatic void 1006176774Srajtsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1007176774Sraj{ 1008176774Sraj struct tsec_softc *sc = ifp->if_softc; 1009176774Sraj struct mii_data *mii; 1010176774Sraj 1011176774Sraj TSEC_TRANSMIT_LOCK(sc); 1012176774Sraj 1013176774Sraj mii = sc->tsec_mii; 1014176774Sraj mii_pollstat(mii); 1015176774Sraj 1016176774Sraj ifmr->ifm_active = mii->mii_media_active; 1017176774Sraj ifmr->ifm_status = mii->mii_media_status; 1018176774Sraj 1019176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 1020176774Sraj} 1021176774Sraj 1022176774Srajstatic int 1023176774Srajtsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1024182189Sraj uint32_t *paddr) 1025176774Sraj{ 1026176774Sraj struct mbuf *new_mbuf; 1027176774Sraj bus_dma_segment_t seg[1]; 1028188711Sraj int error, nsegs; 1029176774Sraj 1030176774Sraj KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1031176774Sraj 1032243857Sglebius new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1033176774Sraj if (new_mbuf == NULL) 1034176774Sraj return (ENOBUFS); 1035176774Sraj new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1036176774Sraj 1037176774Sraj if (*mbufp) { 1038176774Sraj bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1039176774Sraj bus_dmamap_unload(tag, map); 1040176774Sraj } 1041176774Sraj 1042176774Sraj error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1043188712Sraj BUS_DMA_NOWAIT); 1044176774Sraj KASSERT(nsegs == 1, ("Too many segments returned!")); 1045176774Sraj if (nsegs != 1 || error) 1046176774Sraj panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1047176774Sraj 1048176774Sraj#if 0 1049176774Sraj if (error) { 1050176774Sraj printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1051176774Sraj error); 1052176774Sraj m_freem(new_mbuf); 1053176774Sraj return (ENOBUFS); 1054176774Sraj } 1055176774Sraj#endif 1056176774Sraj 1057176774Sraj#if 0 1058176774Sraj KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1059176774Sraj ("Wrong alignment of RX buffer!")); 1060176774Sraj#endif 1061176774Sraj bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1062176774Sraj 1063176774Sraj (*mbufp) = new_mbuf; 1064176774Sraj (*paddr) = seg->ds_addr; 1065176774Sraj return (0); 1066176774Sraj} 1067176774Sraj 1068176774Srajstatic void 1069176774Srajtsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1070176774Sraj{ 1071176774Sraj u_int32_t *paddr; 1072176774Sraj 1073176774Sraj KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1074176774Sraj paddr = arg; 1075176774Sraj *paddr = segs->ds_addr; 1076176774Sraj} 1077176774Sraj 1078176774Srajstatic int 1079176774Srajtsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1080176774Sraj bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1081176774Sraj{ 1082176774Sraj int error; 1083176774Sraj 1084176774Sraj /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1085176774Sraj error = bus_dma_tag_create(NULL, /* parent */ 1086176774Sraj PAGE_SIZE, 0, /* alignment, boundary */ 1087176774Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1088176774Sraj BUS_SPACE_MAXADDR, /* highaddr */ 1089176774Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 1090176774Sraj dsize, 1, /* maxsize, nsegments */ 1091176774Sraj dsize, 0, /* maxsegsz, flags */ 1092176774Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 1093176774Sraj dtag); /* dmat */ 1094176774Sraj 1095176774Sraj if (error) { 1096188712Sraj device_printf(dev, "failed to allocate busdma %s tag\n", 1097188712Sraj dname); 1098176774Sraj (*vaddr) = NULL; 1099176774Sraj return (ENXIO); 1100176774Sraj } 1101176774Sraj 1102176774Sraj error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1103188712Sraj dmap); 1104176774Sraj if (error) { 1105176774Sraj device_printf(dev, "failed to allocate %s DMA safe memory\n", 1106188712Sraj dname); 1107176774Sraj bus_dma_tag_destroy(*dtag); 1108176774Sraj (*vaddr) = NULL; 1109176774Sraj return (ENXIO); 1110176774Sraj } 1111176774Sraj 1112188712Sraj error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1113188712Sraj tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1114176774Sraj if (error) { 1115188712Sraj device_printf(dev, "cannot get address of the %s " 1116188712Sraj "descriptors\n", dname); 1117176774Sraj bus_dmamem_free(*dtag, *vaddr, *dmap); 1118176774Sraj bus_dma_tag_destroy(*dtag); 1119176774Sraj (*vaddr) = NULL; 1120176774Sraj return (ENXIO); 1121176774Sraj } 1122176774Sraj 1123176774Sraj return (0); 1124176774Sraj} 1125176774Sraj 1126176774Srajstatic void 1127176774Srajtsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1128176774Sraj{ 1129176774Sraj 1130176774Sraj if (vaddr == NULL) 1131176774Sraj return; 1132176774Sraj 1133176774Sraj /* Unmap descriptors from DMA memory */ 1134188712Sraj bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1135188712Sraj BUS_DMASYNC_POSTWRITE); 1136176774Sraj bus_dmamap_unload(dtag, dmap); 1137176774Sraj 1138176774Sraj /* Free descriptors memory */ 1139176774Sraj bus_dmamem_free(dtag, vaddr, dmap); 1140176774Sraj 1141176774Sraj /* Destroy descriptors tag */ 1142176774Sraj bus_dma_tag_destroy(dtag); 1143176774Sraj} 1144176774Sraj 1145176774Srajstatic void 1146176774Srajtsec_free_dma(struct tsec_softc *sc) 1147176774Sraj{ 1148176774Sraj int i; 1149176774Sraj 1150176774Sraj /* Free TX maps */ 1151176774Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1152176774Sraj if (sc->tx_map_data[i] != NULL) 1153188712Sraj bus_dmamap_destroy(sc->tsec_tx_mtag, 1154188712Sraj sc->tx_map_data[i]); 1155188712Sraj /* Destroy tag for TX mbufs */ 1156176774Sraj bus_dma_tag_destroy(sc->tsec_tx_mtag); 1157176774Sraj 1158176774Sraj /* Free RX mbufs and maps */ 1159176774Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1160176774Sraj if (sc->rx_data[i].mbuf) { 1161176774Sraj /* Unload buffer from DMA */ 1162176774Sraj bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1163176774Sraj BUS_DMASYNC_POSTREAD); 1164188712Sraj bus_dmamap_unload(sc->tsec_rx_mtag, 1165188712Sraj sc->rx_data[i].map); 1166176774Sraj 1167176774Sraj /* Free buffer */ 1168176774Sraj m_freem(sc->rx_data[i].mbuf); 1169176774Sraj } 1170176774Sraj /* Destroy map for this buffer */ 1171176774Sraj if (sc->rx_data[i].map != NULL) 1172176774Sraj bus_dmamap_destroy(sc->tsec_rx_mtag, 1173176774Sraj sc->rx_data[i].map); 1174176774Sraj } 1175188712Sraj /* Destroy tag for RX mbufs */ 1176176774Sraj bus_dma_tag_destroy(sc->tsec_rx_mtag); 1177176774Sraj 1178176774Sraj /* Unload TX/RX descriptors */ 1179176774Sraj tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1180176774Sraj sc->tsec_tx_vaddr); 1181176774Sraj tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1182176774Sraj sc->tsec_rx_vaddr); 1183176774Sraj} 1184176774Sraj 1185176774Srajstatic void 1186176774Srajtsec_stop(struct tsec_softc *sc) 1187176774Sraj{ 1188176774Sraj struct ifnet *ifp; 1189176774Sraj struct mbuf *m0; 1190176774Sraj bus_dmamap_t *mapp; 1191176774Sraj uint32_t tmpval; 1192176774Sraj 1193176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1194176774Sraj 1195176774Sraj ifp = sc->tsec_ifp; 1196176774Sraj 1197188712Sraj /* Disable interface and watchdog timer */ 1198182187Sraj callout_stop(&sc->tsec_callout); 1199176774Sraj ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1200182187Sraj sc->tsec_watchdog = 0; 1201176774Sraj 1202176774Sraj /* Disable all interrupts and stop DMA */ 1203176774Sraj tsec_intrs_ctl(sc, 0); 1204176774Sraj tsec_dma_ctl(sc, 0); 1205176774Sraj 1206176774Sraj /* Remove pending data from TX queue */ 1207176774Sraj while (!TSEC_EMPTYQ_TX_MBUF(sc)) { 1208176774Sraj m0 = TSEC_GET_TX_MBUF(sc); 1209176774Sraj mapp = TSEC_GET_TX_MAP(sc); 1210176774Sraj 1211188711Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1212188711Sraj BUS_DMASYNC_POSTWRITE); 1213176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1214176774Sraj 1215176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 1216176774Sraj m_freem(m0); 1217176774Sraj } 1218176774Sraj 1219188711Sraj /* Disable RX and TX */ 1220176774Sraj tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1221176774Sraj tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1222176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1223176774Sraj DELAY(10); 1224176774Sraj} 1225176774Sraj 1226188711Srajstatic void 1227188711Srajtsec_tick(void *arg) 1228176774Sraj{ 1229176774Sraj struct tsec_softc *sc = arg; 1230188711Sraj struct ifnet *ifp; 1231188711Sraj int link; 1232188711Sraj 1233188711Sraj TSEC_GLOBAL_LOCK(sc); 1234188711Sraj 1235188711Sraj tsec_watchdog(sc); 1236188711Sraj 1237188711Sraj ifp = sc->tsec_ifp; 1238188711Sraj link = sc->tsec_link; 1239188711Sraj 1240188711Sraj mii_tick(sc->tsec_mii); 1241188711Sraj 1242188711Sraj if (link == 0 && sc->tsec_link == 1 && 1243188711Sraj (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1244188711Sraj tsec_start_locked(ifp); 1245188711Sraj 1246188711Sraj /* Schedule another timeout one second from now. */ 1247188711Sraj callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1248188711Sraj 1249188711Sraj TSEC_GLOBAL_UNLOCK(sc); 1250188711Sraj} 1251188711Sraj 1252188711Sraj/* 1253188711Sraj * This is the core RX routine. It replenishes mbufs in the descriptor and 1254188711Sraj * sends data which have been dma'ed into host memory to upper layer. 1255188711Sraj * 1256188711Sraj * Loops at most count times if count is > 0, or until done if count < 0. 1257188711Sraj */ 1258193096Sattiliostatic int 1259188711Srajtsec_receive_intr_locked(struct tsec_softc *sc, int count) 1260188711Sraj{ 1261176774Sraj struct tsec_desc *rx_desc; 1262176774Sraj struct ifnet *ifp; 1263176774Sraj struct rx_data_type *rx_data; 1264176774Sraj struct mbuf *m; 1265176774Sraj device_t dev; 1266176774Sraj uint32_t i; 1267193096Sattilio int c, rx_npkts; 1268176774Sraj uint16_t flags; 1269176774Sraj 1270188711Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); 1271188711Sraj 1272176774Sraj ifp = sc->tsec_ifp; 1273176774Sraj rx_data = sc->rx_data; 1274176774Sraj dev = sc->dev; 1275193096Sattilio rx_npkts = 0; 1276176774Sraj 1277188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1278188711Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1279176774Sraj 1280188711Sraj for (c = 0; ; c++) { 1281188711Sraj if (count >= 0 && count-- == 0) 1282188711Sraj break; 1283176774Sraj 1284176774Sraj rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1285176774Sraj flags = rx_desc->flags; 1286176774Sraj 1287176774Sraj /* Check if there is anything to receive */ 1288188711Sraj if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1289176774Sraj /* 1290176774Sraj * Avoid generating another interrupt 1291176774Sraj */ 1292176774Sraj if (flags & TSEC_RXBD_E) 1293176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, 1294176774Sraj TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1295176774Sraj /* 1296176774Sraj * We didn't consume current descriptor and have to 1297176774Sraj * return it to the queue 1298176774Sraj */ 1299176774Sraj TSEC_BACK_CUR_RX_DESC(sc); 1300176774Sraj break; 1301176774Sraj } 1302176774Sraj 1303176774Sraj if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1304176774Sraj TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1305182189Sraj 1306176774Sraj rx_desc->length = 0; 1307188711Sraj rx_desc->flags = (rx_desc->flags & 1308188711Sraj ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1309188711Sraj 1310188711Sraj if (sc->frame != NULL) { 1311188711Sraj m_free(sc->frame); 1312188711Sraj sc->frame = NULL; 1313188711Sraj } 1314188711Sraj 1315176774Sraj continue; 1316176774Sraj } 1317176774Sraj 1318176774Sraj /* Ok... process frame */ 1319176774Sraj i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1320176774Sraj m = rx_data[i].mbuf; 1321188711Sraj m->m_len = rx_desc->length; 1322176774Sraj 1323188711Sraj if (sc->frame != NULL) { 1324188711Sraj if ((flags & TSEC_RXBD_L) != 0) 1325188711Sraj m->m_len -= m_length(sc->frame, NULL); 1326188711Sraj 1327188711Sraj m->m_flags &= ~M_PKTHDR; 1328188711Sraj m_cat(sc->frame, m); 1329188711Sraj } else { 1330188711Sraj sc->frame = m; 1331188711Sraj } 1332188711Sraj 1333188711Sraj m = NULL; 1334188711Sraj 1335188711Sraj if ((flags & TSEC_RXBD_L) != 0) { 1336188711Sraj m = sc->frame; 1337188711Sraj sc->frame = NULL; 1338188711Sraj } 1339188711Sraj 1340176774Sraj if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1341176774Sraj &rx_data[i].mbuf, &rx_data[i].paddr)) { 1342176774Sraj ifp->if_ierrors++; 1343188713Sraj /* 1344188713Sraj * We ran out of mbufs; didn't consume current 1345188713Sraj * descriptor and have to return it to the queue. 1346188713Sraj */ 1347188713Sraj TSEC_BACK_CUR_RX_DESC(sc); 1348188713Sraj break; 1349176774Sraj } 1350188711Sraj 1351188711Sraj /* Attach new buffer to descriptor and clear flags */ 1352176774Sraj rx_desc->bufptr = rx_data[i].paddr; 1353176774Sraj rx_desc->length = 0; 1354176774Sraj rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1355176774Sraj TSEC_RXBD_E | TSEC_RXBD_I; 1356176774Sraj 1357188711Sraj if (m != NULL) { 1358188711Sraj m->m_pkthdr.rcvif = ifp; 1359176774Sraj 1360188711Sraj m_fixhdr(m); 1361188711Sraj m_adj(m, -ETHER_CRC_LEN); 1362176774Sraj 1363188711Sraj if (sc->is_etsec) 1364188711Sraj tsec_offload_process_frame(sc, m); 1365176774Sraj 1366188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1367188711Sraj (*ifp->if_input)(ifp, m); 1368188711Sraj TSEC_RECEIVE_LOCK(sc); 1369193096Sattilio rx_npkts++; 1370188711Sraj } 1371188711Sraj } 1372176774Sraj 1373188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1374188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1375188718Sraj 1376188718Sraj /* 1377188718Sraj * Make sure TSEC receiver is not halted. 1378188718Sraj * 1379188718Sraj * Various conditions can stop the TSEC receiver, but not all are 1380188718Sraj * signaled and handled by error interrupt, so make sure the receiver 1381188718Sraj * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1382188718Sraj * halted, and is harmless if already running. 1383188718Sraj */ 1384188718Sraj TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1385193096Sattilio return (rx_npkts); 1386176774Sraj} 1387176774Sraj 1388182189Srajvoid 1389188711Srajtsec_receive_intr(void *arg) 1390176774Sraj{ 1391176774Sraj struct tsec_softc *sc = arg; 1392188711Sraj 1393188711Sraj TSEC_RECEIVE_LOCK(sc); 1394188711Sraj 1395188711Sraj#ifdef DEVICE_POLLING 1396188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1397188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1398188711Sraj return; 1399188711Sraj } 1400188711Sraj#endif 1401188711Sraj 1402188711Sraj /* Confirm the interrupt was received by driver */ 1403188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1404188711Sraj tsec_receive_intr_locked(sc, -1); 1405188711Sraj 1406188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1407188711Sraj} 1408188711Sraj 1409188711Srajstatic void 1410188711Srajtsec_transmit_intr_locked(struct tsec_softc *sc) 1411188711Sraj{ 1412176774Sraj struct tsec_desc *tx_desc; 1413176774Sraj struct ifnet *ifp; 1414176774Sraj struct mbuf *m0; 1415176774Sraj bus_dmamap_t *mapp; 1416176774Sraj int send = 0; 1417176774Sraj 1418188711Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 1419188711Sraj 1420176774Sraj ifp = sc->tsec_ifp; 1421176774Sraj 1422176774Sraj /* Update collision statistics */ 1423176774Sraj ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); 1424176774Sraj 1425176774Sraj /* Reset collision counters in hardware */ 1426176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1427176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1428176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1429176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1430176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1431176774Sraj 1432182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1433182189Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1434176774Sraj 1435176774Sraj while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { 1436176774Sraj tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); 1437176774Sraj if (tx_desc->flags & TSEC_TXBD_R) { 1438176774Sraj TSEC_BACK_DIRTY_TX_DESC(sc); 1439176774Sraj break; 1440176774Sraj } 1441176774Sraj 1442176774Sraj if ((tx_desc->flags & TSEC_TXBD_L) == 0) 1443176774Sraj continue; 1444176774Sraj 1445176774Sraj /* 1446176774Sraj * This is the last buf in this packet, so unmap and free it. 1447176774Sraj */ 1448176774Sraj m0 = TSEC_GET_TX_MBUF(sc); 1449176774Sraj mapp = TSEC_GET_TX_MAP(sc); 1450176774Sraj 1451188712Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1452188712Sraj BUS_DMASYNC_POSTWRITE); 1453176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1454176774Sraj 1455176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 1456176774Sraj m_freem(m0); 1457176774Sraj 1458176774Sraj ifp->if_opackets++; 1459176774Sraj send = 1; 1460176774Sraj } 1461188711Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1462188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1463176774Sraj 1464176774Sraj if (send) { 1465176774Sraj /* Now send anything that was pending */ 1466176774Sraj ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1467176774Sraj tsec_start_locked(ifp); 1468176774Sraj 1469188711Sraj /* Stop wathdog if all sent */ 1470176774Sraj if (TSEC_EMPTYQ_TX_MBUF(sc)) 1471182187Sraj sc->tsec_watchdog = 0; 1472176774Sraj } 1473176774Sraj} 1474176774Sraj 1475182189Srajvoid 1476188711Srajtsec_transmit_intr(void *arg) 1477176774Sraj{ 1478176774Sraj struct tsec_softc *sc = arg; 1479188711Sraj 1480188711Sraj TSEC_TRANSMIT_LOCK(sc); 1481188711Sraj 1482188711Sraj#ifdef DEVICE_POLLING 1483188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1484188711Sraj TSEC_TRANSMIT_UNLOCK(sc); 1485188711Sraj return; 1486188711Sraj } 1487188711Sraj#endif 1488188711Sraj /* Confirm the interrupt was received by driver */ 1489188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1490188711Sraj tsec_transmit_intr_locked(sc); 1491188711Sraj 1492188711Sraj TSEC_TRANSMIT_UNLOCK(sc); 1493188711Sraj} 1494188711Sraj 1495188711Srajstatic void 1496188711Srajtsec_error_intr_locked(struct tsec_softc *sc, int count) 1497188711Sraj{ 1498176774Sraj struct ifnet *ifp; 1499176774Sraj uint32_t eflags; 1500176774Sraj 1501188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1502188711Sraj 1503176774Sraj ifp = sc->tsec_ifp; 1504176774Sraj 1505176774Sraj eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1506176774Sraj 1507176774Sraj /* Clear events bits in hardware */ 1508176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1509176774Sraj TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1510176774Sraj TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1511176774Sraj TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1512176774Sraj 1513176774Sraj /* Check transmitter errors */ 1514176774Sraj if (eflags & TSEC_IEVENT_TXE) { 1515176774Sraj ifp->if_oerrors++; 1516176774Sraj 1517176774Sraj if (eflags & TSEC_IEVENT_LC) 1518176774Sraj ifp->if_collisions++; 1519176774Sraj 1520176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1521176774Sraj } 1522176774Sraj 1523176774Sraj /* Check receiver errors */ 1524176774Sraj if (eflags & TSEC_IEVENT_BSY) { 1525176774Sraj ifp->if_ierrors++; 1526176774Sraj ifp->if_iqdrops++; 1527176774Sraj 1528176774Sraj /* Get data from RX buffers */ 1529188711Sraj tsec_receive_intr_locked(sc, count); 1530176774Sraj } 1531188711Sraj 1532188711Sraj if (ifp->if_flags & IFF_DEBUG) 1533188711Sraj if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1534188711Sraj eflags); 1535188711Sraj 1536188711Sraj if (eflags & TSEC_IEVENT_EBERR) { 1537188711Sraj if_printf(ifp, "System bus error occurred during" 1538188711Sraj "DMA transaction (flags: 0x%x)\n", eflags); 1539188711Sraj tsec_init_locked(sc); 1540188711Sraj } 1541188711Sraj 1542188711Sraj if (eflags & TSEC_IEVENT_BABT) 1543188711Sraj ifp->if_oerrors++; 1544188711Sraj 1545176774Sraj if (eflags & TSEC_IEVENT_BABR) 1546176774Sraj ifp->if_ierrors++; 1547176774Sraj} 1548176774Sraj 1549188711Srajvoid 1550188711Srajtsec_error_intr(void *arg) 1551176774Sraj{ 1552188711Sraj struct tsec_softc *sc = arg; 1553176774Sraj 1554177111Sraj TSEC_GLOBAL_LOCK(sc); 1555188711Sraj tsec_error_intr_locked(sc, -1); 1556177111Sraj TSEC_GLOBAL_UNLOCK(sc); 1557176774Sraj} 1558176774Sraj 1559182189Srajint 1560176774Srajtsec_miibus_readreg(device_t dev, int phy, int reg) 1561176774Sraj{ 1562176774Sraj struct tsec_softc *sc; 1563176774Sraj uint32_t timeout; 1564176774Sraj 1565232518Sraj sc = device_get_softc(dev); 1566176774Sraj 1567232518Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1568232518Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, 0); 1569232518Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1570176774Sraj 1571176774Sraj timeout = TSEC_READ_RETRY; 1572232518Sraj while (--timeout && TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & 1573176774Sraj (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) 1574176774Sraj DELAY(TSEC_READ_DELAY); 1575176774Sraj 1576176774Sraj if (timeout == 0) 1577176774Sraj device_printf(dev, "Timeout while reading from PHY!\n"); 1578176774Sraj 1579232518Sraj return (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMSTAT)); 1580176774Sraj} 1581176774Sraj 1582194101Srajint 1583176774Srajtsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1584176774Sraj{ 1585176774Sraj struct tsec_softc *sc; 1586176774Sraj uint32_t timeout; 1587176774Sraj 1588232518Sraj sc = device_get_softc(dev); 1589176774Sraj 1590232518Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1591232518Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCON, value); 1592176774Sraj 1593176774Sraj timeout = TSEC_READ_RETRY; 1594232518Sraj while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & 1595188712Sraj TSEC_MIIMIND_BUSY)) 1596176774Sraj DELAY(TSEC_READ_DELAY); 1597176774Sraj 1598176774Sraj if (timeout == 0) 1599176774Sraj device_printf(dev, "Timeout while writing to PHY!\n"); 1600194101Sraj 1601194101Sraj return (0); 1602176774Sraj} 1603176774Sraj 1604182189Srajvoid 1605176774Srajtsec_miibus_statchg(device_t dev) 1606176774Sraj{ 1607176774Sraj struct tsec_softc *sc; 1608176774Sraj struct mii_data *mii; 1609176774Sraj uint32_t ecntrl, id, tmp; 1610176774Sraj int link; 1611176774Sraj 1612176774Sraj sc = device_get_softc(dev); 1613176774Sraj mii = sc->tsec_mii; 1614176774Sraj link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1615176774Sraj 1616176774Sraj tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1617176774Sraj 1618176774Sraj if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1619176774Sraj tmp |= TSEC_MACCFG2_FULLDUPLEX; 1620176774Sraj else 1621176774Sraj tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1622176774Sraj 1623176774Sraj switch (IFM_SUBTYPE(mii->mii_media_active)) { 1624176774Sraj case IFM_1000_T: 1625176774Sraj case IFM_1000_SX: 1626176774Sraj tmp |= TSEC_MACCFG2_GMII; 1627176774Sraj sc->tsec_link = link; 1628176774Sraj break; 1629176774Sraj case IFM_100_TX: 1630176774Sraj case IFM_10_T: 1631176774Sraj tmp |= TSEC_MACCFG2_MII; 1632176774Sraj sc->tsec_link = link; 1633176774Sraj break; 1634176774Sraj case IFM_NONE: 1635176774Sraj if (link) 1636188712Sraj device_printf(dev, "No speed selected but link " 1637188712Sraj "active!\n"); 1638176774Sraj sc->tsec_link = 0; 1639176774Sraj return; 1640176774Sraj default: 1641176774Sraj sc->tsec_link = 0; 1642176774Sraj device_printf(dev, "Unknown speed (%d), link %s!\n", 1643176774Sraj IFM_SUBTYPE(mii->mii_media_active), 1644182189Sraj ((link) ? "up" : "down")); 1645176774Sraj return; 1646176774Sraj } 1647176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1648176774Sraj 1649176774Sraj /* XXX kludge - use circumstantial evidence for reduced mode. */ 1650176774Sraj id = TSEC_READ(sc, TSEC_REG_ID2); 1651176774Sraj if (id & 0xffff) { 1652176774Sraj ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1653176774Sraj ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1654176774Sraj TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1655176774Sraj } 1656176774Sraj} 1657188711Sraj 1658188711Srajstatic void 1659188711Srajtsec_add_sysctls(struct tsec_softc *sc) 1660188711Sraj{ 1661188711Sraj struct sysctl_ctx_list *ctx; 1662188711Sraj struct sysctl_oid_list *children; 1663188711Sraj struct sysctl_oid *tree; 1664188711Sraj 1665188711Sraj ctx = device_get_sysctl_ctx(sc->dev); 1666188711Sraj children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1667188711Sraj tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1668188711Sraj CTLFLAG_RD, 0, "TSEC Interrupts coalescing"); 1669188711Sraj children = SYSCTL_CHILDREN(tree); 1670188711Sraj 1671188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1672188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time, 1673188711Sraj "I", "IC RX time threshold (0-65535)"); 1674188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1675188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count, 1676188711Sraj "I", "IC RX frame count threshold (0-255)"); 1677188711Sraj 1678188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1679188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time, 1680188711Sraj "I", "IC TX time threshold (0-65535)"); 1681188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1682188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count, 1683188711Sraj "I", "IC TX frame count threshold (0-255)"); 1684188711Sraj} 1685188711Sraj 1686188711Sraj/* 1687188711Sraj * With Interrupt Coalescing (IC) active, a transmit/receive frame 1688188711Sraj * interrupt is raised either upon: 1689188711Sraj * 1690188711Sraj * - threshold-defined period of time elapsed, or 1691188711Sraj * - threshold-defined number of frames is received/transmitted, 1692188711Sraj * whichever occurs first. 1693188711Sraj * 1694188711Sraj * The following sysctls regulate IC behaviour (for TX/RX separately): 1695188711Sraj * 1696188711Sraj * dev.tsec.<unit>.int_coal.rx_time 1697188711Sraj * dev.tsec.<unit>.int_coal.rx_count 1698188711Sraj * dev.tsec.<unit>.int_coal.tx_time 1699188711Sraj * dev.tsec.<unit>.int_coal.tx_count 1700188711Sraj * 1701188711Sraj * Values: 1702188711Sraj * 1703188711Sraj * - 0 for either time or count disables IC on the given TX/RX path 1704188711Sraj * 1705188711Sraj * - count: 1-255 (expresses frame count number; note that value of 1 is 1706188711Sraj * effectively IC off) 1707188711Sraj * 1708188711Sraj * - time: 1-65535 (value corresponds to a real time period and is 1709188711Sraj * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1710188711Sraj * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1711188711Sraj * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1712188711Sraj * TSEC reference manual. 1713188711Sraj */ 1714188711Srajstatic int 1715188711Srajtsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1716188711Sraj{ 1717188711Sraj int error; 1718188711Sraj uint32_t time; 1719188711Sraj struct tsec_softc *sc = (struct tsec_softc *)arg1; 1720188711Sraj 1721188711Sraj time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1722188711Sraj 1723188711Sraj error = sysctl_handle_int(oidp, &time, 0, req); 1724188711Sraj if (error != 0) 1725188711Sraj return (error); 1726188711Sraj 1727188711Sraj if (time > 65535) 1728188711Sraj return (EINVAL); 1729188711Sraj 1730188711Sraj TSEC_IC_LOCK(sc); 1731188711Sraj if (arg2 == TSEC_IC_RX) { 1732188711Sraj sc->rx_ic_time = time; 1733188711Sraj tsec_set_rxic(sc); 1734188711Sraj } else { 1735188711Sraj sc->tx_ic_time = time; 1736188711Sraj tsec_set_txic(sc); 1737188711Sraj } 1738188711Sraj TSEC_IC_UNLOCK(sc); 1739188711Sraj 1740188711Sraj return (0); 1741188711Sraj} 1742188711Sraj 1743188711Srajstatic int 1744188711Srajtsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1745188711Sraj{ 1746188711Sraj int error; 1747188711Sraj uint32_t count; 1748188711Sraj struct tsec_softc *sc = (struct tsec_softc *)arg1; 1749188711Sraj 1750188711Sraj count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1751188711Sraj 1752188711Sraj error = sysctl_handle_int(oidp, &count, 0, req); 1753188711Sraj if (error != 0) 1754188711Sraj return (error); 1755188711Sraj 1756188711Sraj if (count > 255) 1757188711Sraj return (EINVAL); 1758188711Sraj 1759188711Sraj TSEC_IC_LOCK(sc); 1760188711Sraj if (arg2 == TSEC_IC_RX) { 1761188711Sraj sc->rx_ic_count = count; 1762188711Sraj tsec_set_rxic(sc); 1763188711Sraj } else { 1764188711Sraj sc->tx_ic_count = count; 1765188711Sraj tsec_set_txic(sc); 1766188711Sraj } 1767188711Sraj TSEC_IC_UNLOCK(sc); 1768188711Sraj 1769188711Sraj return (0); 1770188711Sraj} 1771188711Sraj 1772188711Srajstatic void 1773188711Srajtsec_set_rxic(struct tsec_softc *sc) 1774188711Sraj{ 1775188711Sraj uint32_t rxic_val; 1776188711Sraj 1777188711Sraj if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1778188711Sraj /* Disable RX IC */ 1779188711Sraj rxic_val = 0; 1780188711Sraj else { 1781188711Sraj rxic_val = 0x80000000; 1782188711Sraj rxic_val |= (sc->rx_ic_count << 21); 1783188711Sraj rxic_val |= sc->rx_ic_time; 1784188711Sraj } 1785188711Sraj 1786188711Sraj TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1787188711Sraj} 1788188711Sraj 1789188711Srajstatic void 1790188711Srajtsec_set_txic(struct tsec_softc *sc) 1791188711Sraj{ 1792188711Sraj uint32_t txic_val; 1793188711Sraj 1794188711Sraj if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1795188711Sraj /* Disable TX IC */ 1796188711Sraj txic_val = 0; 1797188711Sraj else { 1798188711Sraj txic_val = 0x80000000; 1799188711Sraj txic_val |= (sc->tx_ic_count << 21); 1800188711Sraj txic_val |= sc->tx_ic_time; 1801188711Sraj } 1802188711Sraj 1803188711Sraj TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1804188711Sraj} 1805188711Sraj 1806188711Srajstatic void 1807188711Srajtsec_offload_setup(struct tsec_softc *sc) 1808188711Sraj{ 1809188711Sraj struct ifnet *ifp = sc->tsec_ifp; 1810188711Sraj uint32_t reg; 1811188711Sraj 1812188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1813188711Sraj 1814188711Sraj reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1815188711Sraj reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1816188711Sraj 1817188711Sraj if (ifp->if_capenable & IFCAP_TXCSUM) 1818188711Sraj ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1819188711Sraj else 1820188711Sraj ifp->if_hwassist = 0; 1821188711Sraj 1822188711Sraj TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1823188711Sraj 1824188711Sraj reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1825188711Sraj reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1826188711Sraj reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1827188711Sraj 1828188711Sraj if (ifp->if_capenable & IFCAP_RXCSUM) 1829188711Sraj reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1830188711Sraj TSEC_RCTRL_PRSDEP_PARSE_L234; 1831188711Sraj 1832188711Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1833188711Sraj} 1834188711Sraj 1835188711Sraj 1836188711Srajstatic void 1837188711Srajtsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1838188711Sraj{ 1839188711Sraj struct tsec_rx_fcb rx_fcb; 1840188711Sraj int csum_flags = 0; 1841188711Sraj int protocol, flags; 1842188711Sraj 1843188711Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); 1844188711Sraj 1845188711Sraj m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1846188711Sraj flags = rx_fcb.flags; 1847188711Sraj protocol = rx_fcb.protocol; 1848188711Sraj 1849188711Sraj if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1850188711Sraj csum_flags |= CSUM_IP_CHECKED; 1851188711Sraj 1852188711Sraj if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1853188711Sraj csum_flags |= CSUM_IP_VALID; 1854188711Sraj } 1855188711Sraj 1856188711Sraj if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1857188711Sraj TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1858188711Sraj (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1859188711Sraj 1860188711Sraj csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1861188711Sraj m->m_pkthdr.csum_data = 0xFFFF; 1862188711Sraj } 1863188711Sraj 1864188711Sraj m->m_pkthdr.csum_flags = csum_flags; 1865188711Sraj 1866188711Sraj if (flags & TSEC_RX_FCB_VLAN) { 1867188711Sraj m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1868188711Sraj m->m_flags |= M_VLANTAG; 1869188711Sraj } 1870188711Sraj 1871188711Sraj m_adj(m, sizeof(struct tsec_rx_fcb)); 1872188711Sraj} 1873188711Sraj 1874188711Srajstatic void 1875188711Srajtsec_setup_multicast(struct tsec_softc *sc) 1876188711Sraj{ 1877188711Sraj uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1878188711Sraj struct ifnet *ifp = sc->tsec_ifp; 1879188711Sraj struct ifmultiaddr *ifma; 1880188711Sraj uint32_t h; 1881188711Sraj int i; 1882188711Sraj 1883188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1884188711Sraj 1885188711Sraj if (ifp->if_flags & IFF_ALLMULTI) { 1886188711Sraj for (i = 0; i < 8; i++) 1887188711Sraj TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1888188711Sraj 1889188711Sraj return; 1890188711Sraj } 1891188711Sraj 1892195049Srwatson if_maddr_rlock(ifp); 1893188711Sraj TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1894188711Sraj 1895188711Sraj if (ifma->ifma_addr->sa_family != AF_LINK) 1896188711Sraj continue; 1897188711Sraj 1898188711Sraj h = (ether_crc32_be(LLADDR((struct sockaddr_dl *) 1899188711Sraj ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF; 1900188711Sraj 1901188711Sraj hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1902188711Sraj } 1903195049Srwatson if_maddr_runlock(ifp); 1904188711Sraj 1905188711Sraj for (i = 0; i < 8; i++) 1906188711Sraj TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1907188711Sraj} 1908188711Sraj 1909188711Srajstatic int 1910188711Srajtsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1911188711Sraj{ 1912188711Sraj 1913188711Sraj mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1914188711Sraj 1915188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1916188711Sraj 1917188711Sraj if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1918188711Sraj TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1919188711Sraj return (mtu); 1920188711Sraj } 1921188711Sraj 1922188711Sraj return (0); 1923188711Sraj} 1924