1/* 2 * Copyright (c) 2005 by David E. O'Brien <obrien@FreeBSD.org>. 3 * Copyright (c) 2003 by Quinton Dolan <q@onthenet.com.au>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS `AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id: if_nvreg.h,v 1.6 2004/08/12 14:00:05 q Exp $ 28 * $FreeBSD$ 29 */ 30 31#ifndef _IF_NVEREG_H_ 32#define _IF_NVEREG_H_ 33 34#ifndef PCI_VENDOR_NVIDIA 35#define PCI_VENDOR_NVIDIA 0x10DE 36#endif 37 38#define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3 39#define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066 40#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6 41#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086 42#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C 43#define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6 44#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF 45#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056 46#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057 47#define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037 48#define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038 49#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268 50#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269 51#define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372 52#define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373 53#define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5 54#define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6 55#define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee 56#define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef 57#define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450 58#define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451 59#define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452 60#define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453 61 62#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 63#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 64#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 65#define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 66#define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 67#define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 68#define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 69 70#define NV_RID 0x10 71 72#define TX_RING_SIZE 64 73#define RX_RING_SIZE 64 74#define NV_MAX_FRAGS 32 // match adapter.h:ADAPTER_WRITE_DATA.sElement[] 75 76#define FCS_LEN 4 77 78#define NVE_DEBUG 0x0000 79#define NVE_DEBUG_INIT 0x0001 80#define NVE_DEBUG_RUNNING 0x0002 81#define NVE_DEBUG_DEINIT 0x0004 82#define NVE_DEBUG_IOCTL 0x0008 83#define NVE_DEBUG_INTERRUPT 0x0010 84#define NVE_DEBUG_API 0x0020 85#define NVE_DEBUG_LOCK 0x0040 86#define NVE_DEBUG_BROKEN 0x0080 87#define NVE_DEBUG_MII 0x0100 88#define NVE_DEBUG_ALL 0xFFFF 89 90#if NVE_DEBUG 91#define DEBUGOUT(level, fmt, args...) if (NVE_DEBUG & level) \ 92 printf(fmt, ## args) 93#else 94#define DEBUGOUT(level, fmt, args...) 95#endif 96 97typedef unsigned long ulong; 98 99struct nve_map_buffer { 100 struct mbuf *mbuf; /* mbuf receiving packet */ 101 bus_dmamap_t map; /* DMA map */ 102}; 103 104struct nve_dma_info { 105 bus_dma_tag_t tag; 106 struct nve_map_buffer buf; 107 u_int16_t buflength; 108 caddr_t vaddr; /* Virtual memory address */ 109 bus_addr_t paddr; /* DMA physical address */ 110}; 111 112struct nve_rx_desc { 113 struct nve_rx_desc *next; 114 struct nve_map_buffer buf; 115 u_int16_t buflength; 116 caddr_t vaddr; 117 bus_addr_t paddr; 118}; 119 120struct nve_tx_desc { 121 /* Don't add anything above this structure */ 122 TX_INFO_ADAP TxInfoAdap; 123 struct nve_tx_desc *next; 124 struct nve_map_buffer buf; 125 u_int16_t buflength; 126 u_int32_t numfrags; 127 bus_dma_segment_t frags[NV_MAX_FRAGS]; 128}; 129 130struct nve_softc { 131 struct ifnet *ifp; /* interface info */ 132 struct resource *res; 133 struct resource *irq; 134 135 ADAPTER_API *hwapi; 136 OS_API osapi; 137 138 device_t miibus; 139 device_t dev; 140 struct callout stat_callout; 141 int tx_timer; 142 143 void *sc_ih; 144 bus_space_tag_t sc_st; 145 bus_space_handle_t sc_sh; 146 bus_dma_tag_t mtag; 147 bus_dma_tag_t rtag; 148 bus_dmamap_t rmap; 149 bus_dma_tag_t ttag; 150 bus_dmamap_t tmap; 151 152 struct nve_rx_desc *rx_desc; 153 struct nve_tx_desc *tx_desc; 154 bus_addr_t rx_addr; 155 bus_addr_t tx_addr; 156 u_int16_t rx_ring_full; 157 u_int16_t tx_ring_full; 158 u_int32_t cur_rx; 159 u_int32_t cur_tx; 160 u_int32_t pending_rxs; 161 u_int32_t pending_txs; 162 163 struct mtx mtx; 164 165 /* Stuff for dealing with the NVIDIA OS API */ 166 struct callout ostimer; 167 PTIMER_FUNC ostimer_func; 168 void *ostimer_params; 169 int linkup; 170 ulong tx_errors; 171 NV_UINT32 hwmode; 172 NV_UINT32 max_frame_size; 173 NV_UINT32 phyaddr; 174 NV_UINT32 media; 175 CMNDATA_OS_ADAPTER adapterdata; 176 unsigned char original_mac_addr[6]; 177}; 178 179struct nve_type { 180 u_int16_t vid_id; 181 u_int16_t dev_id; 182 char *name; 183}; 184 185#define NVE_LOCK(_sc) mtx_lock(&(_sc)->mtx) 186#define NVE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 187#define NVE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 188 189extern int ADAPTER_ReadPhy (PVOID pContext, ULONG ulPhyAddr, ULONG ulReg, ULONG *pulVal); 190extern int ADAPTER_WritePhy (PVOID pContext, ULONG ulPhyAddr, ULONG ulReg, ULONG ulVal); 191extern int ADAPTER_Init (PVOID pContext, USHORT usForcedSpeed, UCHAR ucForceDpx, UCHAR ucForceMode, UINT *puiLinkState); 192 193#endif /* _IF_NVEREG_H_ */ 194