1155852Sgallatin/*******************************************************************************
2155852Sgallatin
3247160SgallatinCopyright (c) 2006-2013, Myricom Inc.
4155852SgallatinAll rights reserved.
5155852Sgallatin
6155852SgallatinRedistribution and use in source and binary forms, with or without
7155852Sgallatinmodification, are permitted provided that the following conditions are met:
8155852Sgallatin
9155852Sgallatin 1. Redistributions of source code must retain the above copyright notice,
10155852Sgallatin    this list of conditions and the following disclaimer.
11155852Sgallatin
12171405Sgallatin 2. Neither the name of the Myricom Inc, nor the names of its
13155852Sgallatin    contributors may be used to endorse or promote products derived from
14155852Sgallatin    this software without specific prior written permission.
15155852Sgallatin
16155852SgallatinTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17155852SgallatinAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18155852SgallatinIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19155852SgallatinARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20155852SgallatinLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21155852SgallatinCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22155852SgallatinSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23155852SgallatinINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24155852SgallatinCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25155852SgallatinARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26155852SgallatinPOSSIBILITY OF SUCH DAMAGE.
27155852Sgallatin
28155852Sgallatin$FreeBSD$
29155852Sgallatin
30155852Sgallatin***************************************************************************/
31155852Sgallatin
32159571Sgallatin#define MXGE_ETH_STOPPED 0
33159571Sgallatin#define MXGE_ETH_STOPPING 1
34159571Sgallatin#define MXGE_ETH_STARTING 2
35159571Sgallatin#define MXGE_ETH_RUNNING 3
36159571Sgallatin#define MXGE_ETH_OPEN_FAILED 4
37155852Sgallatin
38159571Sgallatin#define MXGE_FW_OFFSET 1024*1024
39159571Sgallatin#define MXGE_EEPROM_STRINGS_SIZE 256
40169871Sgallatin#define MXGE_MAX_SEND_DESC 128
41155852Sgallatin
42181964Sgallatin#if ((__FreeBSD_version > 800000 && __FreeBSD_version < 800005) \
43181964Sgallatin     || __FreeBSD_version < 700111)
44175579Sgallatin#define MXGE_VIRT_JUMBOS 1
45175579Sgallatin#else
46175579Sgallatin#define MXGE_VIRT_JUMBOS 0
47175579Sgallatin#endif
48175579Sgallatin
49193311Sgallatin#if (__FreeBSD_version > 800082)
50193311Sgallatin#define IFNET_BUF_RING 1
51193311Sgallatin#endif
52193311Sgallatin
53247011Sgallatin#if (__FreeBSD_version < 1000020)
54247011Sgallatin#undef IF_Kbps
55247011Sgallatin#undef IF_Mbps
56247011Sgallatin#undef IF_Gbps
57247011Sgallatin#define	IF_Kbps(x)	((uintmax_t)(x) * 1000)	/* kilobits/sec. */
58247011Sgallatin#define	IF_Mbps(x)	(IF_Kbps((x) * 1000))	/* megabits/sec. */
59247011Sgallatin#define	IF_Gbps(x)	(IF_Mbps((x) * 1000))	/* gigabits/sec. */
60247011Sgallatinstatic __inline void
61247011Sgallatinif_initbaudrate(struct ifnet *ifp, uintmax_t baud)
62247011Sgallatin{
63247011Sgallatin	ifp->if_baudrate = baud;
64247011Sgallatin}
65247011Sgallatin#endif
66176261Sgallatin#ifndef VLAN_CAPABILITIES
67176261Sgallatin#define VLAN_CAPABILITIES(ifp)
68176261Sgallatin#define mxge_vlans_active(sc) (sc)->ifp->if_nvlans
69176261Sgallatin#else
70176261Sgallatin#define mxge_vlans_active(sc) (sc)->ifp->if_vlantrunk
71176261Sgallatin#endif
72176261Sgallatin
73176261Sgallatin#ifndef VLAN_TAG_VALUE
74176261Sgallatin#define MXGE_NEW_VLAN_API
75176261Sgallatin#endif
76176261Sgallatin
77176261Sgallatin#ifndef IFCAP_LRO
78176261Sgallatin#define IFCAP_LRO 0
79176261Sgallatin#endif
80176261Sgallatin
81176261Sgallatin#ifndef IFCAP_TSO
82176261Sgallatin#define IFCAP_TSO 0
83176261Sgallatin#endif
84176261Sgallatin
85176261Sgallatin#ifndef IFCAP_TSO4
86176261Sgallatin#define IFCAP_TSO4 0
87176261Sgallatin#endif
88176261Sgallatin
89247011Sgallatin#ifndef IFCAP_TSO6
90247011Sgallatin#define IFCAP_TSO6 0
91247011Sgallatin#endif
92247011Sgallatin
93247011Sgallatin#ifndef IFCAP_TXCSUM_IPV6
94247011Sgallatin#define IFCAP_TXCSUM_IPV6 0
95247011Sgallatin#endif
96247011Sgallatin
97247011Sgallatin#ifndef IFCAP_RXCSUM_IPV6
98247011Sgallatin#define IFCAP_RXCSUM_IPV6 0
99247011Sgallatin#endif
100247011Sgallatin
101176261Sgallatin#ifndef CSUM_TSO
102176261Sgallatin#define CSUM_TSO 0
103176261Sgallatin#endif
104176261Sgallatin
105247011Sgallatin#ifndef CSUM_TCP_IPV6
106247011Sgallatin#define CSUM_TCP_IPV6 0
107247011Sgallatin#endif
108176261Sgallatin
109247011Sgallatin#ifndef CSUM_UDP_IPV6
110247011Sgallatin#define CSUM_UDP_IPV6 0
111247011Sgallatin#endif
112247011Sgallatin
113247011Sgallatin#ifndef CSUM_DELAY_DATA_IPV6
114247011Sgallatin#define CSUM_DELAY_DATA_IPV6 0
115247011Sgallatin#endif
116247011Sgallatin
117155852Sgallatintypedef struct {
118155852Sgallatin	void *addr;
119155852Sgallatin	bus_addr_t bus_addr;
120155852Sgallatin	bus_dma_tag_t dmat;
121155852Sgallatin	bus_dmamap_t map;
122159571Sgallatin} mxge_dma_t;
123155852Sgallatin
124155852Sgallatin
125159612Sgallatintypedef struct {
126159612Sgallatin	mcp_slot_t *entry;
127159612Sgallatin	mxge_dma_t dma;
128159612Sgallatin	int cnt;
129159612Sgallatin	int idx;
130169871Sgallatin	int mask;
131159612Sgallatin} mxge_rx_done_t;
132155852Sgallatin
133155852Sgallatintypedef struct
134155852Sgallatin{
135155852Sgallatin  uint32_t data0;
136155852Sgallatin  uint32_t data1;
137155852Sgallatin  uint32_t data2;
138159571Sgallatin} mxge_cmd_t;
139155852Sgallatin
140159612Sgallatinstruct mxge_rx_buffer_state {
141155852Sgallatin	struct mbuf *m;
142155852Sgallatin	bus_dmamap_t map;
143155852Sgallatin};
144155852Sgallatin
145159612Sgallatinstruct mxge_tx_buffer_state {
146159612Sgallatin	struct mbuf *m;
147159612Sgallatin	bus_dmamap_t map;
148159612Sgallatin	int flag;
149159612Sgallatin};
150159612Sgallatin
151155852Sgallatintypedef struct
152155852Sgallatin{
153155852Sgallatin	volatile mcp_kreq_ether_recv_t *lanai;	/* lanai ptr for recv ring */
154155852Sgallatin	mcp_kreq_ether_recv_t *shadow;	/* host shadow of recv ring */
155159612Sgallatin	struct mxge_rx_buffer_state *info;
156155852Sgallatin	bus_dma_tag_t dmat;
157155852Sgallatin	bus_dmamap_t extra_map;
158155852Sgallatin	int cnt;
159169840Sgallatin	int nbufs;
160169840Sgallatin	int cl_size;
161155852Sgallatin	int alloc_fail;
162155852Sgallatin	int mask;			/* number of rx slots -1 */
163193250Sgallatin	int mlen;
164175365Sgallatin} mxge_rx_ring_t;
165155852Sgallatin
166155852Sgallatintypedef struct
167155852Sgallatin{
168175365Sgallatin	struct mtx mtx;
169191567Sgallatin#ifdef IFNET_BUF_RING
170191562Sgallatin	struct buf_ring *br;
171191562Sgallatin#endif
172155852Sgallatin	volatile mcp_kreq_ether_send_t *lanai;	/* lanai ptr for sendq	*/
173191562Sgallatin	volatile uint32_t *send_go;		/* doorbell for sendq */
174191562Sgallatin	volatile uint32_t *send_stop;		/* doorbell for sendq */
175155852Sgallatin	mcp_kreq_ether_send_t *req_list;	/* host shadow of sendq */
176155852Sgallatin	char *req_bytes;
177162322Sgallatin	bus_dma_segment_t *seg_list;
178159612Sgallatin	struct mxge_tx_buffer_state *info;
179155852Sgallatin	bus_dma_tag_t dmat;
180155852Sgallatin	int req;			/* transmits submitted	*/
181155852Sgallatin	int mask;			/* number of transmit slots -1 */
182155852Sgallatin	int done;			/* transmits completed	*/
183159612Sgallatin	int pkt_done;			/* packets completed */
184169871Sgallatin	int max_desc;			/* max descriptors per xmit */
185191562Sgallatin	int queue_active;		/* fw currently polling this queue*/
186191562Sgallatin	int activate;
187191562Sgallatin	int deactivate;
188166345Sgallatin	int stall;			/* #times hw queue exhausted */
189166345Sgallatin	int wake;			/* #times irq re-enabled xmit */
190166373Sgallatin	int watchdog_req;		/* cache of req */
191166373Sgallatin	int watchdog_done;		/* cache of done */
192171917Sgallatin	int watchdog_rx_pause;		/* cache of pause rq recvd */
193175365Sgallatin	int defrag;
194175365Sgallatin	char mtx_name[16];
195175365Sgallatin} mxge_tx_ring_t;
196155852Sgallatin
197175365Sgallatinstruct mxge_softc;
198175365Sgallatintypedef struct mxge_softc mxge_softc_t;
199175365Sgallatin
200175365Sgallatinstruct mxge_slice_state {
201175365Sgallatin	mxge_softc_t *sc;
202175365Sgallatin	mxge_tx_ring_t tx;		/* transmit ring 	*/
203175365Sgallatin	mxge_rx_ring_t rx_small;
204175365Sgallatin	mxge_rx_ring_t rx_big;
205159612Sgallatin	mxge_rx_done_t rx_done;
206159612Sgallatin	mcp_irq_data_t *fw_stats;
207175365Sgallatin	volatile uint32_t *irq_claim;
208175365Sgallatin	u_long ipackets;
209191562Sgallatin	u_long opackets;
210194751Sgallatin	u_long obytes;
211194751Sgallatin	u_long omcasts;
212191562Sgallatin	u_long oerrors;
213191562Sgallatin	int if_drv_flags;
214247133Sgallatin	struct lro_ctrl lc;
215175365Sgallatin	mxge_dma_t fw_stats_dma;
216175365Sgallatin	struct sysctl_oid *sysctl_tree;
217175365Sgallatin	struct sysctl_ctx_list sysctl_ctx;
218175365Sgallatin	char scratch[256];
219175365Sgallatin};
220175365Sgallatin
221175365Sgallatinstruct mxge_softc {
222175365Sgallatin	struct ifnet* ifp;
223175365Sgallatin	struct mxge_slice_state *ss;
224175365Sgallatin	int tx_boundary;		/* boundary transmits cannot cross*/
225169840Sgallatin	int lro_cnt;
226175365Sgallatin	bus_dma_tag_t	parent_dmat;
227175365Sgallatin	volatile uint8_t *sram;
228155852Sgallatin	int sram_size;
229159612Sgallatin	volatile uint32_t *irq_deassert;
230155852Sgallatin	mcp_cmd_response_t *cmd;
231159571Sgallatin	mxge_dma_t cmd_dma;
232159571Sgallatin	mxge_dma_t zeropad_dma;
233155852Sgallatin	struct pci_dev *pdev;
234176281Sgallatin	int legacy_irq;
235155852Sgallatin	int link_state;
236155852Sgallatin	unsigned int rdma_tags_available;
237155852Sgallatin	int intr_coal_delay;
238159612Sgallatin	volatile uint32_t *intr_coal_delay_ptr;
239155852Sgallatin	int wc;
240166370Sgallatin	struct mtx cmd_mtx;
241166370Sgallatin	struct mtx driver_mtx;
242155852Sgallatin	int wake_queue;
243155852Sgallatin	int stop_queue;
244155852Sgallatin	int down_cnt;
245155852Sgallatin	int watchdog_resets;
246175365Sgallatin	int watchdog_countdown;
247155852Sgallatin	int pause;
248155852Sgallatin	struct resource *mem_res;
249155852Sgallatin	struct resource *irq_res;
250175365Sgallatin	struct resource **msix_irq_res;
251175365Sgallatin	struct resource *msix_table_res;
252175365Sgallatin	struct resource *msix_pba_res;
253155852Sgallatin	void *ih;
254175365Sgallatin	void **msix_ih;
255155852Sgallatin	char *fw_name;
256159571Sgallatin	char eeprom_strings[MXGE_EEPROM_STRINGS_SIZE];
257155852Sgallatin	char fw_version[128];
258166875Sgallatin	int fw_ver_major;
259166875Sgallatin	int fw_ver_minor;
260166875Sgallatin	int fw_ver_tiny;
261166875Sgallatin	int adopted_rx_filter_bug;
262155852Sgallatin	device_t dev;
263155852Sgallatin	struct ifmedia media;
264159612Sgallatin	int read_dma;
265159612Sgallatin	int write_dma;
266159612Sgallatin	int read_write_dma;
267162328Sgallatin	int fw_multicast_support;
268164513Sgallatin	int link_width;
269169840Sgallatin	int max_mtu;
270197391Sgallatin	int throttle;
271169871Sgallatin	int tx_defrag;
272171917Sgallatin	int media_flags;
273171917Sgallatin	int need_media_probe;
274175365Sgallatin	int num_slices;
275175365Sgallatin	int rx_ring_size;
276194909Sgallatin	int dying;
277206662Sgallatin	int connector;
278206662Sgallatin	int current_media;
279247011Sgallatin	int max_tso6_hlen;
280166370Sgallatin	mxge_dma_t dmabench_dma;
281166373Sgallatin	struct callout co_hdl;
282198250Sgallatin	struct taskqueue *tq;
283198250Sgallatin	struct task watchdog_task;
284175365Sgallatin	struct sysctl_oid *slice_sysctl_tree;
285175365Sgallatin	struct sysctl_ctx_list slice_sysctl_ctx;
286159612Sgallatin	char *mac_addr_string;
287169871Sgallatin	uint8_t	mac_addr[6];		/* eeprom mac address */
288197645Sgallatin	uint16_t pectl;			/* save PCIe CTL state */
289159612Sgallatin	char product_code_string[64];
290159612Sgallatin	char serial_number_string[64];
291166370Sgallatin	char cmd_mtx_name[16];
292166370Sgallatin	char driver_mtx_name[16];
293175365Sgallatin};
294155852Sgallatin
295159571Sgallatin#define MXGE_PCI_VENDOR_MYRICOM 	0x14c1
296159571Sgallatin#define MXGE_PCI_DEVICE_Z8E 	0x0008
297172162Sgallatin#define MXGE_PCI_DEVICE_Z8E_9 	0x0009
298188736Sgallatin#define MXGE_PCI_REV_Z8E	0
299188736Sgallatin#define MXGE_PCI_REV_Z8ES	1
300171917Sgallatin#define MXGE_XFP_COMPLIANCE_BYTE	131
301188736Sgallatin#define MXGE_SFP_COMPLIANCE_BYTE	  3
302197391Sgallatin#define MXGE_MIN_THROTTLE	416
303197391Sgallatin#define MXGE_MAX_THROTTLE	4096
304155852Sgallatin
305206662Sgallatin/* Types of connectors on NICs supported by this driver */
306206662Sgallatin#define MXGE_CX4 0
307206662Sgallatin#define MXGE_XFP 1
308206662Sgallatin#define MXGE_SFP 2
309206662Sgallatin#define MXGE_QRF 3
310206662Sgallatin
311159571Sgallatin#define MXGE_HIGHPART_TO_U32(X) \
312155852Sgallatin(sizeof (X) == 8) ? ((uint32_t)((uint64_t)(X) >> 32)) : (0)
313159571Sgallatin#define MXGE_LOWPART_TO_U32(X) ((uint32_t)(X))
314155852Sgallatin
315171917Sgallatinstruct mxge_media_type
316171917Sgallatin{
317171917Sgallatin	int flag;
318171917Sgallatin	uint8_t bitmask;
319171917Sgallatin	char *name;
320171917Sgallatin};
321155852Sgallatin
322247011Sgallatinstruct mxge_pkt_info {
323247011Sgallatin	int ip_off;
324247011Sgallatin	int ip_hlen;
325247011Sgallatin	struct ip *ip;
326247011Sgallatin	struct ip6_hdr *ip6;
327247011Sgallatin	struct tcphdr *tcp;
328247011Sgallatin};
329247011Sgallatin
330247011Sgallatin
331155852Sgallatin/* implement our own memory barriers, since bus_space_barrier
332155852Sgallatin   cannot handle write-combining regions */
333155852Sgallatin
334185162Skmacy#if __FreeBSD_version < 800053
335185162Skmacy
336155852Sgallatin#if defined (__GNUC__)
337155852Sgallatin  #if #cpu(i386) || defined __i386 || defined i386 || defined __i386__ || #cpu(x86_64) || defined __x86_64__
338185255Sgallatin    #define wmb()  __asm__ __volatile__ ("sfence;": : :"memory")
339155852Sgallatin  #elif #cpu(sparc64) || defined sparc64 || defined __sparcv9
340185255Sgallatin    #define wmb()  __asm__ __volatile__ ("membar #MemIssue": : :"memory")
341155852Sgallatin  #elif #cpu(sparc) || defined sparc || defined __sparc__
342185255Sgallatin    #define wmb()  __asm__ __volatile__ ("stbar;": : :"memory")
343155852Sgallatin  #else
344185255Sgallatin    #define wmb() 	/* XXX just to make this compile */
345155852Sgallatin  #endif
346155852Sgallatin#else
347155852Sgallatin  #error "unknown compiler"
348155852Sgallatin#endif
349155852Sgallatin
350185162Skmacy#endif
351185162Skmacy
352155852Sgallatinstatic inline void
353159571Sgallatinmxge_pio_copy(volatile void *to_v, void *from_v, size_t size)
354155852Sgallatin{
355155852Sgallatin  register volatile uintptr_t *to;
356155852Sgallatin  volatile uintptr_t *from;
357155852Sgallatin  size_t i;
358155852Sgallatin
359155852Sgallatin  to = (volatile uintptr_t *) to_v;
360155852Sgallatin  from = from_v;
361155852Sgallatin  for (i = (size / sizeof (uintptr_t)); i; i--) {
362155852Sgallatin	  *to = *from;
363155852Sgallatin	  to++;
364155852Sgallatin	  from++;
365155852Sgallatin  }
366155852Sgallatin
367155852Sgallatin}
368155852Sgallatin
369175365Sgallatinvoid mxge_lro_flush(struct mxge_slice_state *ss, struct lro_entry *lro);
370175365Sgallatinint mxge_lro_rx(struct mxge_slice_state *ss, struct mbuf *m_head,
371175365Sgallatin		uint32_t csum);
372169840Sgallatin
373155852Sgallatin
374169840Sgallatin
375155852Sgallatin/*
376155852Sgallatin  This file uses Myri10GE driver indentation.
377155852Sgallatin
378155852Sgallatin  Local Variables:
379155852Sgallatin  c-file-style:"linux"
380155852Sgallatin  tab-width:8
381155852Sgallatin  End:
382155852Sgallatin*/
383