172132Ssemenu/* OpenBSD: lxtphyreg.h,v 1.1 1998/11/11 19:34:47 jason Exp */ 272132Ssemenu/* NetBSD: lxtphyreg.h,v 1.1 1998/10/24 00:33:17 thorpej Exp */ 372132Ssemenu/* $FreeBSD$ */ 472132Ssemenu 572132Ssemenu/*- 672132Ssemenu * Copyright (c) 1998 The NetBSD Foundation, Inc. 772132Ssemenu * All rights reserved. 872132Ssemenu * 972132Ssemenu * This code is derived from software contributed to The NetBSD Foundation 1072132Ssemenu * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 1172132Ssemenu * NASA Ames Research Center. 1272132Ssemenu * 1372132Ssemenu * Redistribution and use in source and binary forms, with or without 1472132Ssemenu * modification, are permitted provided that the following conditions 1572132Ssemenu * are met: 1672132Ssemenu * 1. Redistributions of source code must retain the above copyright 1772132Ssemenu * notice, this list of conditions and the following disclaimer. 1872132Ssemenu * 2. Redistributions in binary form must reproduce the above copyright 1972132Ssemenu * notice, this list of conditions and the following disclaimer in the 2072132Ssemenu * documentation and/or other materials provided with the distribution. 2172132Ssemenu * 2272132Ssemenu * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2372132Ssemenu * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2472132Ssemenu * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2572132Ssemenu * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2672132Ssemenu * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2772132Ssemenu * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2872132Ssemenu * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2972132Ssemenu * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3072132Ssemenu * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3172132Ssemenu * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3272132Ssemenu * POSSIBILITY OF SUCH DAMAGE. 3372132Ssemenu */ 3472132Ssemenu 3572132Ssemenu#ifndef _DEV_MII_LXTPHYREG_H_ 3672132Ssemenu#define _DEV_MII_LXTPHYREG_H_ 3772132Ssemenu 3872132Ssemenu/* 3972132Ssemenu * LXT970 registers. 4072132Ssemenu */ 4172132Ssemenu 4272132Ssemenu#define MII_LXTPHY_MIRROR 0x10 /* Mirror register */ 4372132Ssemenu /* All bits user-defined */ 4472132Ssemenu 4572132Ssemenu#define MII_LXTPHY_IER 0x11 /* Interrupt Enable Register */ 4672132Ssemenu#define IER_MIIDRVLVL 0x0008 /* Rediced MII driver levels */ 4772132Ssemenu#define IER_LNK_CRITERIA 0x0004 /* Enhanced Link Loss Criteria */ 4872132Ssemenu#define IER_INTEN 0x0002 /* Interrupt Enable */ 4972132Ssemenu#define IER_TINT 0x0001 /* Force Interrupt */ 5072132Ssemenu 5172132Ssemenu#define MII_LXTPHY_ISR 0x12 /* Interrupt Status Register */ 5272132Ssemenu#define ISR_MINT 0x8000 /* MII Interrupt Pending */ 5372132Ssemenu#define ISR_XTALOK 0x4000 /* Clocks OK */ 5472132Ssemenu 5572132Ssemenu#define MII_LXTPHY_CONFIG 0x13 /* Configuration Register */ 5672132Ssemenu#define CONFIG_TXMIT_TEST 0x4000 /* 100base-T Transmit Test */ 5772132Ssemenu#define CONFIG_REPEATER 0x2000 /* Repeater Mode */ 5872132Ssemenu#define CONFIG_MDIO_INT 0x1000 /* Enable intr signalling on MDIO */ 5972132Ssemenu#define CONFIG_TPLOOP 0x0800 /* Disable 10base-T Loopback */ 6072132Ssemenu#define CONFIG_SQE 0x0400 /* Enable SQE */ 6172132Ssemenu#define CONFIG_DISJABBER 0x0200 /* Disable Jabber */ 6272132Ssemenu#define CONFIG_DISLINKTEST 0x0100 /* Disable Link Test */ 6372132Ssemenu#define CONFIG_LEDC1 0x0080 /* LEDC configuration */ 6472132Ssemenu#define CONFIG_LEDC0 0x0040 /* ... */ 6572132Ssemenu /* 0 0 LEDC indicates collision */ 6672132Ssemenu /* 0 1 LEDC is off */ 6772132Ssemenu /* 1 0 LEDC indicates activity */ 6872132Ssemenu /* 1 1 LEDC is on */ 6972132Ssemenu#define CONFIG_ADVTXCLK 0x0020 /* Advance TX clock */ 7072132Ssemenu#define CONFIG_5BSYMBOL 0x0010 /* 5-bit Symbol mode */ 7172132Ssemenu#define CONFIG_SCRAMBLER 0x0008 /* Bypass scrambler */ 7272132Ssemenu#define CONFIG_100BASEFX 0x0004 /* 100base-FX */ 7372132Ssemenu#define CONFIG_TXDISCON 0x0001 /* Disconnect TP transmitter */ 7472132Ssemenu 7572132Ssemenu#define MII_LXTPHY_CSR 0x14 /* Chip Status Register */ 7672132Ssemenu#define CSR_LINK 0x2000 /* Link is up */ 7772132Ssemenu#define CSR_DUPLEX 0x1000 /* Full-duplex */ 7872132Ssemenu#define CSR_SPEED 0x0800 /* 100Mbps */ 7972132Ssemenu#define CSR_ACOMP 0x0400 /* Autonegotiation complete */ 8072132Ssemenu#define CSR_PAGERCVD 0x0200 /* Link page received */ 8172132Ssemenu#define CSR_LOWVCC 0x0004 /* Low Voltage Fault */ 8272132Ssemenu 8372132Ssemenu#endif /* _DEV_MII_LXTPHYREG_H_ */ 84