1139749Simp/*- 259477Swpaul * Copyright (c) 2000 359477Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 459477Swpaul * 559477Swpaul * Redistribution and use in source and binary forms, with or without 659477Swpaul * modification, are permitted provided that the following conditions 759477Swpaul * are met: 859477Swpaul * 1. Redistributions of source code must retain the above copyright 959477Swpaul * notice, this list of conditions and the following disclaimer. 1059477Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1159477Swpaul * notice, this list of conditions and the following disclaimer in the 1259477Swpaul * documentation and/or other materials provided with the distribution. 1359477Swpaul * 3. All advertising materials mentioning features or use of this software 1459477Swpaul * must display the following acknowledgement: 1559477Swpaul * This product includes software developed by Bill Paul. 1659477Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1759477Swpaul * may be used to endorse or promote products derived from this software 1859477Swpaul * without specific prior written permission. 1959477Swpaul * 2059477Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2159477Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2259477Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2359477Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2459477Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2559477Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2659477Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2759477Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2859477Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2959477Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3059477Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3159477Swpaul * 3259477Swpaul * $FreeBSD$ 3359477Swpaul */ 3459477Swpaul 3559477Swpaul#ifndef _DEV_MII_BRGPHYREG_H_ 3659477Swpaul#define _DEV_MII_BRGPHYREG_H_ 3759477Swpaul 3859477Swpaul/* 3959477Swpaul * Broadcom BCM5400 registers 4059477Swpaul */ 4159477Swpaul 42212307Syongari#define BRGPHY_MII_BMCR 0x00 43212307Syongari#define BRGPHY_BMCR_RESET 0x8000 44212307Syongari#define BRGPHY_BMCR_LOOP 0x4000 45212307Syongari#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */ 46212307Syongari#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 47212307Syongari#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ 48212307Syongari#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ 49166676Sjkim#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ 50212307Syongari#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ 51212307Syongari#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 52212307Syongari#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ 5359477Swpaul 54212307Syongari#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ 55212307Syongari#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ 56212307Syongari#define BRGPHY_S10 0 /* 10mbps */ 5759477Swpaul 58166676Sjkim#define BRGPHY_MII_BMSR 0x01 59166676Sjkim#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 60166676Sjkim#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 61166676Sjkim#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 62220938Smarius#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occurred */ 63166676Sjkim#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 64166676Sjkim#define BRGPHY_BMSR_LINK 0x0004 /* Link status */ 65166676Sjkim#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 66166676Sjkim#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */ 6759477Swpaul 68166676Sjkim#define BRGPHY_MII_ANAR 0x04 69166676Sjkim#define BRGPHY_ANAR_NP 0x8000 /* Next page */ 70166676Sjkim#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */ 71166676Sjkim#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ 72166676Sjkim#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */ 73166680Sjkim#define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */ 7459477Swpaul 75166676Sjkim#define BRGPHY_MII_ANLPAR 0x05 76166676Sjkim#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */ 77166676Sjkim#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */ 78166676Sjkim#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ 79166676Sjkim#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */ 80166680Sjkim#define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */ 8159477Swpaul 82166680Sjkim#define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */ 8359477Swpaul 84166676Sjkim#define BRGPHY_MII_ANER 0x06 85166676Sjkim#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */ 86166676Sjkim#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */ 87166676Sjkim#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */ 88166676Sjkim#define BRGPHY_ANER_RX 0x0002 /* Next page received */ 89166676Sjkim#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ 9059477Swpaul 91166676Sjkim#define BRGPHY_MII_NEXTP 0x07 /* Next page */ 9259477Swpaul 93166676Sjkim#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */ 9459477Swpaul 95166676Sjkim#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */ 96166680Sjkim#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */ 97166676Sjkim#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */ 98166676Sjkim#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */ 99166676Sjkim#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ 100166676Sjkim#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ 101166676Sjkim#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ 10259477Swpaul 103166676Sjkim#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */ 104166676Sjkim#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */ 105166676Sjkim#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */ 106166676Sjkim#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */ 107166676Sjkim#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */ 108166676Sjkim#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ 109166676Sjkim#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ 110166676Sjkim#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */ 11159477Swpaul 112166676Sjkim#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */ 113166676Sjkim#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ 114166676Sjkim#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ 115166676Sjkim#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ 116166676Sjkim#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ 11759477Swpaul 118166676Sjkim#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ 119166676Sjkim#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ 120166676Sjkim#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ 121166680Sjkim#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */ 122166676Sjkim#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ 123166676Sjkim#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ 124166676Sjkim#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ 125166676Sjkim#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ 126166676Sjkim#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ 127166676Sjkim#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ 128166676Sjkim#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ 129166676Sjkim#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ 130166676Sjkim#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ 131166676Sjkim#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ 132166676Sjkim#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ 133166676Sjkim#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ 134166676Sjkim#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ 13559477Swpaul 136166676Sjkim#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ 137166676Sjkim#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ 138166676Sjkim#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ 139166676Sjkim#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ 140166676Sjkim#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ 141166676Sjkim#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ 142166676Sjkim#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ 143166676Sjkim#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ 144166676Sjkim#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ 145166676Sjkim#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ 146166676Sjkim#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ 147166676Sjkim#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ 148166676Sjkim#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ 149166676Sjkim#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ 150166676Sjkim#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ 15159477Swpaul 152166676Sjkim#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ 15359477Swpaul 154166680Sjkim#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */ 155166676Sjkim#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ 15659477Swpaul 157166676Sjkim#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ 158166676Sjkim#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ 159166676Sjkim#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ 16059477Swpaul 161166676Sjkim#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ 16283930Swpaul 163166676Sjkim#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ 164178667Sjhb#define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */ 16583930Swpaul 166166676Sjkim#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 167166676Sjkim#define BRGPHY_DSP_AGC_A 0x00 168166676Sjkim#define BRGPHY_DSP_AGC_B 0x01 169166676Sjkim#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 170166676Sjkim#define BRGPHY_DSP_SOFT_DECISION 0x03 171166676Sjkim#define BRGPHY_DSP_PHASE_REG 0x04 172166676Sjkim#define BRGPHY_DSP_SKEW 0x05 173166676Sjkim#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 174166676Sjkim#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 175166676Sjkim#define BRGPHY_DSP_LAST_ECHO 0x08 176166676Sjkim#define BRGPHY_DSP_FREQUENCY 0x09 177166676Sjkim#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A 178166676Sjkim#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B 17983930Swpaul 180166676Sjkim#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 181166676Sjkim#define BRGPHY_DSP_FILTER_FEXT3 0x0B00 182166676Sjkim#define BRGPHY_DSP_FILTER_FEXT2 0x0A00 183166676Sjkim#define BRGPHY_DSP_FILTER_FEXT1 0x0900 184166676Sjkim#define BRGPHY_DSP_FILTER_FEXT0 0x0800 185166676Sjkim#define BRGPHY_DSP_FILTER_NEXT3 0x0700 186166676Sjkim#define BRGPHY_DSP_FILTER_NEXT2 0x0600 187166676Sjkim#define BRGPHY_DSP_FILTER_NEXT1 0x0500 188166676Sjkim#define BRGPHY_DSP_FILTER_NEXT0 0x0400 189166676Sjkim#define BRGPHY_DSP_FILTER_ECHO 0x0300 190166676Sjkim#define BRGPHY_DSP_FILTER_DFE 0x0200 191166676Sjkim#define BRGPHY_DSP_FILTER_FFE 0x0100 19283930Swpaul 193166676Sjkim#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 19483930Swpaul 195166676Sjkim#define BRGPHY_DSP_SEL_CH_0 0x0000 196166676Sjkim#define BRGPHY_DSP_SEL_CH_1 0x2000 197166676Sjkim#define BRGPHY_DSP_SEL_CH_2 0x4000 198166676Sjkim#define BRGPHY_DSP_SEL_CH_3 0x6000 19983930Swpaul 200166676Sjkim#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ 201166676Sjkim#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ 202166676Sjkim#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ 203166676Sjkim#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ 204166676Sjkim#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ 205166676Sjkim#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ 206166676Sjkim#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ 20759477Swpaul 208166676Sjkim#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ 209166680Sjkim#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */ 210166680Sjkim#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */ 211166680Sjkim#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */ 212166680Sjkim#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */ 213170391Sdavidch#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */ 214166676Sjkim#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ 215166680Sjkim#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */ 216166680Sjkim#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */ 217166680Sjkim#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */ 218166680Sjkim#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */ 219166676Sjkim#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ 220166676Sjkim#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ 221166676Sjkim#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ 22259477Swpaul 223166676Sjkim#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ 224166676Sjkim#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ 225166676Sjkim#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ 226166676Sjkim#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ 227166676Sjkim#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ 228166676Sjkim#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ 229166676Sjkim#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ 23059477Swpaul 231166680Sjkim#define BRGPHY_MII_ISR 0x1A /* Interrupt status */ 232166676Sjkim#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ 233166676Sjkim#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ 234166680Sjkim#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */ 235166680Sjkim#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */ 236166676Sjkim#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ 237166676Sjkim#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ 238166676Sjkim#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ 239166676Sjkim#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 240166676Sjkim#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 241166676Sjkim#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ 242166676Sjkim#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ 243166676Sjkim#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ 244166676Sjkim#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ 245166676Sjkim#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ 246166680Sjkim#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */ 24759477Swpaul 248166680Sjkim#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */ 249166676Sjkim#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ 250166676Sjkim#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ 251166680Sjkim#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */ 252166680Sjkim#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */ 253166676Sjkim#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ 254166676Sjkim#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ 255166676Sjkim#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ 256166676Sjkim#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 257166676Sjkim#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 258166676Sjkim#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ 259166676Sjkim#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ 260166676Sjkim#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ 261166676Sjkim#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ 262166676Sjkim#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 263166680Sjkim#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ 26459477Swpaul 265212306Syongari/*******************************************************/ 266212306Syongari/* Begin: Shared SerDes PHY register definitions */ 267212306Syongari/*******************************************************/ 268212306Syongari 269212306Syongari/* SerDes autoneg is different from copper */ 270212307Syongari#define BRGPHY_SERDES_ANAR 0x04 271212307Syongari#define BRGPHY_SERDES_ANAR_FDX 0x0020 272212307Syongari#define BRGPHY_SERDES_ANAR_HDX 0x0040 273212307Syongari#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7) 274212307Syongari#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7) 275212307Syongari#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7) 276212307Syongari#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7) 277212306Syongari 278212307Syongari#define BRGPHY_SERDES_ANLPAR 0x05 279212307Syongari#define BRGPHY_SERDES_ANLPAR_FDX 0x0020 280212307Syongari#define BRGPHY_SERDES_ANLPAR_HDX 0x0040 281212307Syongari#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7) 282212307Syongari#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7) 283212307Syongari#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7) 284212307Syongari#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7) 285212306Syongari 286212306Syongari/*******************************************************/ 287212306Syongari/* End: Shared SerDes PHY register definitions */ 288212306Syongari/*******************************************************/ 289212306Syongari 290212306Syongari/*******************************************************/ 291212306Syongari/* Begin: PHY register values for the 5706 PHY */ 292212306Syongari/*******************************************************/ 293212306Syongari 294212306Syongari/* 295212306Syongari * Shadow register 0x1C, bit 15 is write enable, 296212306Syongari * bits 14-10 select function (0x00 to 0x1F). 297212306Syongari */ 298212307Syongari#define BRGPHY_MII_SHADOW_1C 0x1C 299212307Syongari#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 300212307Syongari#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 301212306Syongari 302170391Sdavidch/* Shadow 0x1C Mode Control Register (select value 0x1F) */ 303212307Syongari#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) 304170391Sdavidch/* When set, Regs 0-0x0F are 1000X, else 1000T */ 305212307Syongari#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 306170391Sdavidch 307212307Syongari#define BRGPHY_MII_TEST1 0x1E 308212307Syongari#define BRGPHY_TEST1_TRIM_EN 0x0010 309212307Syongari#define BRGPHY_TEST1_CRC_EN 0x8000 310166673Sjkim 311212307Syongari#define BRGPHY_MII_TEST2 0x1F 312212306Syongari 313212306Syongari/*******************************************************/ 314212306Syongari/* End: PHY register values for the 5706 PHY */ 315212306Syongari/*******************************************************/ 316212306Syongari 317212306Syongari/*******************************************************/ 318212306Syongari/* Begin: PHY register values for the 5708S SerDes PHY */ 319212306Syongari/*******************************************************/ 320212306Syongari 321212306Syongari/* Autoneg Next Page Transmit 1 Regiser */ 322212307Syongari#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B 323212307Syongari#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 324212306Syongari 325212306Syongari/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ 326212307Syongari#define BRGPHY_5708S_BLOCK_ADDR 0x1f 327212307Syongari#define BRGPHY_5708S_DIG_PG0 0x0000 328212307Syongari#define BRGPHY_5708S_DIG3_PG2 0x0002 329212307Syongari#define BRGPHY_5708S_TX_MISC_PG5 0x0005 330170391Sdavidch 331212306Syongari/* 5708S SerDes "Digital" Registers (page 0) */ 332212307Syongari#define BRGPHY_5708S_PG0_1000X_CTL1 0x10 333212307Syongari#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 334212307Syongari#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 335212306Syongari 336212307Syongari#define BRGPHY_5708S_PG0_1000X_STAT1 0x14 337212307Syongari#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 338212307Syongari#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 339212307Syongari#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 340212307Syongari#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) 341212307Syongari#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) 342212307Syongari#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) 343212307Syongari#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) 344212306Syongari 345212306Syongari 346212307Syongari#define BRGPHY_5708S_PG0_1000X_CTL2 0x11 347212307Syongari#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 348212306Syongari 349212306Syongari/* 5708S SerDes "Digital 3" Registers (page 2) */ 350212307Syongari#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 351212307Syongari#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 352212306Syongari 353212306Syongari/* 5708S SerDes "TX Misc" Registers (page 5) */ 354212307Syongari#define BRGPHY_5708S_PG5_2500STATUS1 0x10 355212307Syongari#define BRGPHY_5708S_PG5_TXACTL1 0x15 356212307Syongari#define BRGPHY_5708S_PG5_TXACTL3 0x17 357212306Syongari 358205299Sdavidch/*******************************************************/ 359212306Syongari/* End: PHY register values for the 5708S SerDes PHY */ 360212306Syongari/*******************************************************/ 361212306Syongari 362212306Syongari/*******************************************************/ 363205299Sdavidch/* Begin: PHY register values for the 5709S SerDes PHY */ 364205299Sdavidch/*******************************************************/ 365205299Sdavidch 366205299Sdavidch/* 5709S SerDes "General Purpose Status" Registers */ 367212307Syongari#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 368212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B 369212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 370212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 371212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 372212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 373212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 374212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 375212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 376212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 377212307Syongari#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 378205299Sdavidch 379205299Sdavidch/* 5709S SerDes "SerDes Digital" Registers */ 380212307Syongari#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 381212307Syongari#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 382212307Syongari#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 383212307Syongari#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 384205299Sdavidch 385205299Sdavidch/* 5709S SerDes "Over 1G" Registers */ 386212307Syongari#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 387212307Syongari#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 388205299Sdavidch 389205299Sdavidch/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ 390212307Syongari#define BRGPHY_BLOCK_ADDR_MRBE 0x8350 391212307Syongari#define BRGPHY_MRBE_MSG_PG5_NP 0x10 392212307Syongari#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 393212342Syongari#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002 394205299Sdavidch 395205299Sdavidch/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 396212307Syongari#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 397212307Syongari#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 398205299Sdavidch#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 399205299Sdavidch#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 400212307Syongari#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 401205299Sdavidch 402205299Sdavidch/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 403212307Syongari#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 404205299Sdavidch 405205299Sdavidch/* 5709S SerDes "Combo IEEE 0" Registers */ 406212307Syongari#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 407205299Sdavidch 408212307Syongari#define BRGPHY_ADDR_EXT 0x1E 409212307Syongari#define BRGPHY_BLOCK_ADDR 0x1F 410205299Sdavidch 411212307Syongari#define BRGPHY_ADDR_EXT_AN_MMD 0x3800 412205299Sdavidch 413205299Sdavidch/*******************************************************/ 414205299Sdavidch/* End: PHY register values for the 5709S SerDes PHY */ 415205299Sdavidch/*******************************************************/ 416205299Sdavidch 417166676Sjkim#define BRGPHY_INTRS \ 41859477Swpaul ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) 41959477Swpaul 42059477Swpaul#endif /* _DEV_BRGPHY_MIIREG_H_ */ 421