1145247Sdamien/* $FreeBSD$ */ 2145247Sdamien 3145247Sdamien/*- 4158089Smlaier * Copyright (c) 2004, 2005 5145247Sdamien * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6145247Sdamien * 7145247Sdamien * Redistribution and use in source and binary forms, with or without 8145247Sdamien * modification, are permitted provided that the following conditions 9145247Sdamien * are met: 10145247Sdamien * 1. Redistributions of source code must retain the above copyright 11145247Sdamien * notice unmodified, this list of conditions, and the following 12145247Sdamien * disclaimer. 13145247Sdamien * 2. Redistributions in binary form must reproduce the above copyright 14145247Sdamien * notice, this list of conditions and the following disclaimer in the 15145247Sdamien * documentation and/or other materials provided with the distribution. 16145247Sdamien * 17145247Sdamien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18145247Sdamien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19145247Sdamien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20145247Sdamien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21145247Sdamien * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22145247Sdamien * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23145247Sdamien * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24145247Sdamien * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25145247Sdamien * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26145247Sdamien * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27145247Sdamien * SUCH DAMAGE. 28145247Sdamien */ 29145247Sdamien 30145247Sdamien#define IWI_CMD_RING_COUNT 16 31145247Sdamien#define IWI_TX_RING_COUNT 64 32145247Sdamien#define IWI_RX_RING_COUNT 32 33145247Sdamien 34145247Sdamien#define IWI_TX_DESC_SIZE (sizeof (struct iwi_tx_desc)) 35145247Sdamien#define IWI_CMD_DESC_SIZE (sizeof (struct iwi_cmd_desc)) 36145247Sdamien 37145247Sdamien#define IWI_CSR_INTR 0x0008 38145247Sdamien#define IWI_CSR_INTR_MASK 0x000c 39145247Sdamien#define IWI_CSR_INDIRECT_ADDR 0x0010 40145247Sdamien#define IWI_CSR_INDIRECT_DATA 0x0014 41145247Sdamien#define IWI_CSR_AUTOINC_ADDR 0x0018 42145247Sdamien#define IWI_CSR_AUTOINC_DATA 0x001c 43145247Sdamien#define IWI_CSR_RST 0x0020 44145247Sdamien#define IWI_CSR_CTL 0x0024 45145247Sdamien#define IWI_CSR_IO 0x0030 46145247Sdamien#define IWI_CSR_CMD_BASE 0x0200 47145247Sdamien#define IWI_CSR_CMD_SIZE 0x0204 48145247Sdamien#define IWI_CSR_TX1_BASE 0x0208 49145247Sdamien#define IWI_CSR_TX1_SIZE 0x020c 50145247Sdamien#define IWI_CSR_TX2_BASE 0x0210 51145247Sdamien#define IWI_CSR_TX2_SIZE 0x0214 52145247Sdamien#define IWI_CSR_TX3_BASE 0x0218 53145247Sdamien#define IWI_CSR_TX3_SIZE 0x021c 54145247Sdamien#define IWI_CSR_TX4_BASE 0x0220 55145247Sdamien#define IWI_CSR_TX4_SIZE 0x0224 56145247Sdamien#define IWI_CSR_CMD_RIDX 0x0280 57145247Sdamien#define IWI_CSR_TX1_RIDX 0x0284 58145247Sdamien#define IWI_CSR_TX2_RIDX 0x0288 59145247Sdamien#define IWI_CSR_TX3_RIDX 0x028c 60145247Sdamien#define IWI_CSR_TX4_RIDX 0x0290 61145247Sdamien#define IWI_CSR_RX_RIDX 0x02a0 62145247Sdamien#define IWI_CSR_RX_BASE 0x0500 63145247Sdamien#define IWI_CSR_TABLE0_SIZE 0x0700 64145247Sdamien#define IWI_CSR_TABLE0_BASE 0x0704 65150245Sdamien#define IWI_CSR_NODE_BASE 0x0c0c 66145247Sdamien#define IWI_CSR_CMD_WIDX 0x0f80 67145247Sdamien#define IWI_CSR_TX1_WIDX 0x0f84 68145247Sdamien#define IWI_CSR_TX2_WIDX 0x0f88 69145247Sdamien#define IWI_CSR_TX3_WIDX 0x0f8c 70145247Sdamien#define IWI_CSR_TX4_WIDX 0x0f90 71145247Sdamien#define IWI_CSR_RX_WIDX 0x0fa0 72145247Sdamien#define IWI_CSR_READ_INT 0x0ff4 73145247Sdamien 74145247Sdamien/* aliases */ 75145247Sdamien#define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 76145247Sdamien 77145247Sdamien/* flags for IWI_CSR_INTR */ 78145247Sdamien#define IWI_INTR_RX_DONE 0x00000002 79145247Sdamien#define IWI_INTR_CMD_DONE 0x00000800 80145247Sdamien#define IWI_INTR_TX1_DONE 0x00001000 81145247Sdamien#define IWI_INTR_TX2_DONE 0x00002000 82145247Sdamien#define IWI_INTR_TX3_DONE 0x00004000 83145247Sdamien#define IWI_INTR_TX4_DONE 0x00008000 84145247Sdamien#define IWI_INTR_FW_INITED 0x01000000 85145247Sdamien#define IWI_INTR_RADIO_OFF 0x04000000 86145247Sdamien#define IWI_INTR_FATAL_ERROR 0x40000000 87145247Sdamien#define IWI_INTR_PARITY_ERROR 0x80000000 88145247Sdamien 89145247Sdamien#define IWI_INTR_MASK \ 90145247Sdamien (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | IWI_INTR_TX1_DONE | \ 91145247Sdamien IWI_INTR_TX2_DONE | IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE | \ 92145247Sdamien IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ 93145247Sdamien IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) 94145247Sdamien 95145247Sdamien/* flags for IWI_CSR_RST */ 96145247Sdamien#define IWI_RST_PRINCETON_RESET 0x00000001 97158089Smlaier#define IWI_RST_STANDBY 0x00000004 98158089Smlaier#define IWI_RST_LED_ACTIVITY 0x00000010 /* tx/rx traffic led */ 99158089Smlaier#define IWI_RST_LED_ASSOCIATED 0x00000020 /* station associated led */ 100158089Smlaier#define IWI_RST_LED_OFDM 0x00000040 /* ofdm/cck led */ 101145247Sdamien#define IWI_RST_SOFT_RESET 0x00000080 102145247Sdamien#define IWI_RST_MASTER_DISABLED 0x00000100 103145247Sdamien#define IWI_RST_STOP_MASTER 0x00000200 104158089Smlaier#define IWI_RST_GATE_ODMA 0x02000000 105158089Smlaier#define IWI_RST_GATE_IDMA 0x04000000 106158089Smlaier#define IWI_RST_GATE_ADMA 0x20000000 107145247Sdamien 108145247Sdamien/* flags for IWI_CSR_CTL */ 109145247Sdamien#define IWI_CTL_CLOCK_READY 0x00000001 110145247Sdamien#define IWI_CTL_ALLOW_STANDBY 0x00000002 111145247Sdamien#define IWI_CTL_INIT 0x00000004 112145247Sdamien 113145247Sdamien/* flags for IWI_CSR_IO */ 114145247Sdamien#define IWI_IO_RADIO_ENABLED 0x00010000 115145247Sdamien 116145247Sdamien/* flags for IWI_CSR_READ_INT */ 117145247Sdamien#define IWI_READ_INT_INIT_HOST 0x20000000 118145247Sdamien 119145247Sdamien/* constants for command blocks */ 120145247Sdamien#define IWI_CB_DEFAULT_CTL 0x8cea0000 121145247Sdamien#define IWI_CB_MAXDATALEN 8191 122145247Sdamien 123145247Sdamien/* supported rates */ 124145247Sdamien#define IWI_RATE_DS1 10 125145247Sdamien#define IWI_RATE_DS2 20 126145247Sdamien#define IWI_RATE_DS5 55 127145247Sdamien#define IWI_RATE_DS11 110 128145247Sdamien#define IWI_RATE_OFDM6 13 129145247Sdamien#define IWI_RATE_OFDM9 15 130145247Sdamien#define IWI_RATE_OFDM12 5 131145247Sdamien#define IWI_RATE_OFDM18 7 132145247Sdamien#define IWI_RATE_OFDM24 9 133145247Sdamien#define IWI_RATE_OFDM36 11 134145247Sdamien#define IWI_RATE_OFDM48 1 135145247Sdamien#define IWI_RATE_OFDM54 3 136145247Sdamien 137166846Sluigi/* 138166846Sluigi * Old version firmware images start with this header, 139166846Sluigi * fields are in little endian (le32) format. 140166846Sluigi */ 141158089Smlaierstruct iwi_firmware_ohdr { 142152611Sdamien uint32_t version; 143158089Smlaier uint32_t mode; 144158089Smlaier}; 145158089Smlaier#define IWI_FW_REQ_MAJOR 2 146158089Smlaier#define IWI_FW_REQ_MINOR 4 147158089Smlaier#define IWI_FW_GET_MAJOR(ver) ((ver) & 0xff) 148158089Smlaier#define IWI_FW_GET_MINOR(ver) (((ver) & 0xff00) >> 8) 149152611Sdamien 150158089Smlaier#define IWI_FW_MODE_UCODE 0 151158089Smlaier#define IWI_FW_MODE_BOOT 0 152158089Smlaier#define IWI_FW_MODE_BSS 0 153158089Smlaier#define IWI_FW_MODE_IBSS 1 154158089Smlaier#define IWI_FW_MODE_MONITOR 2 155158089Smlaier 156166846Sluigi/* 157166846Sluigi * New version firmware images contain boot, ucode and firmware 158166846Sluigi * all in one chunk. The header at the beginning gives the version 159166846Sluigi * and the size of each (sub)image, in le32 format. 160166846Sluigi */ 161158089Smlaierstruct iwi_firmware_hdr { 162158089Smlaier uint32_t version; /* version stamp */ 163158089Smlaier uint32_t bsize; /* size of boot image */ 164158089Smlaier uint32_t usize; /* size of ucode image */ 165158089Smlaier uint32_t fsize; /* size of firmware image */ 166158089Smlaier}; 167158089Smlaier 168145247Sdamienstruct iwi_hdr { 169145247Sdamien uint8_t type; 170145247Sdamien#define IWI_HDR_TYPE_DATA 0 171145247Sdamien#define IWI_HDR_TYPE_COMMAND 1 172145247Sdamien#define IWI_HDR_TYPE_NOTIF 3 173145247Sdamien#define IWI_HDR_TYPE_FRAME 9 174145247Sdamien 175145247Sdamien uint8_t seq; 176145247Sdamien uint8_t flags; 177145247Sdamien#define IWI_HDR_FLAG_IRQ 0x04 178145247Sdamien 179145247Sdamien uint8_t reserved; 180145247Sdamien} __packed; 181145247Sdamien 182145247Sdamienstruct iwi_notif { 183145247Sdamien uint32_t reserved[2]; 184145247Sdamien uint8_t type; 185158089Smlaier#define IWI_NOTIF_TYPE_SUCCESS 0 186158089Smlaier#define IWI_NOTIF_TYPE_UNSPECIFIED 1 /* unspecified failure */ 187145247Sdamien#define IWI_NOTIF_TYPE_ASSOCIATION 10 188145247Sdamien#define IWI_NOTIF_TYPE_AUTHENTICATION 11 189145247Sdamien#define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 190145247Sdamien#define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 191158089Smlaier#define IWI_NOTIF_TYPE_FRAG_LENGTH 14 192158089Smlaier#define IWI_NOTIF_TYPE_LINK_QUALITY 15 /* "link deterioration" */ 193158089Smlaier#define IWI_NOTIF_TYPE_BEACON 17 /* beacon state, e.g. miss */ 194158089Smlaier#define IWI_NOTIF_TYPE_TGI_TX_KEY 18 /* WPA transmit key */ 195145247Sdamien#define IWI_NOTIF_TYPE_CALIBRATION 20 196145247Sdamien#define IWI_NOTIF_TYPE_NOISE 25 197145247Sdamien 198145247Sdamien uint8_t flags; 199145247Sdamien uint16_t len; 200145247Sdamien} __packed; 201145247Sdamien 202145247Sdamien/* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 203145247Sdamienstruct iwi_notif_authentication { 204145247Sdamien uint8_t state; 205158089Smlaier#define IWI_AUTH_FAIL 0 206158089Smlaier#define IWI_AUTH_SENT_1 1 /* tx first frame */ 207158089Smlaier#define IWI_AUTH_RECV_2 2 /* rx second frame */ 208158089Smlaier#define IWI_AUTH_SEQ1_PASS 3 /* 1st exchange passed */ 209158089Smlaier#define IWI_AUTH_SEQ1_FAIL 4 /* 1st exchange failed */ 210158089Smlaier#define IWI_AUTH_SUCCESS 9 211145247Sdamien} __packed; 212145247Sdamien 213145247Sdamien/* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 214145247Sdamienstruct iwi_notif_association { 215145247Sdamien uint8_t state; 216170530Ssam#define IWI_ASSOC_INIT 0 217158089Smlaier#define IWI_ASSOC_SUCCESS 12 218158089Smlaier uint8_t pad[11]; 219145247Sdamien} __packed; 220145247Sdamien 221145247Sdamien/* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 222145247Sdamienstruct iwi_notif_scan_channel { 223145247Sdamien uint8_t nchan; 224145247Sdamien uint8_t reserved[47]; 225145247Sdamien} __packed; 226145247Sdamien 227145247Sdamien/* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 228145247Sdamienstruct iwi_notif_scan_complete { 229145247Sdamien uint8_t type; 230145247Sdamien uint8_t nchan; 231145247Sdamien uint8_t status; 232145247Sdamien uint8_t reserved; 233145247Sdamien} __packed; 234145247Sdamien 235158089Smlaier/* structure for notification IWI_NOTIF_TYPE_BEACON */ 236158089Smlaierstruct iwi_notif_beacon_state { 237158089Smlaier uint32_t state; 238158089Smlaier#define IWI_BEACON_MISS 1 239158089Smlaier uint32_t number; 240158089Smlaier} __packed; 241158089Smlaier 242145247Sdamien/* received frame header */ 243145247Sdamienstruct iwi_frame { 244145247Sdamien uint32_t reserved1[2]; 245145247Sdamien uint8_t chan; 246145247Sdamien uint8_t status; 247145247Sdamien uint8_t rate; 248145247Sdamien uint8_t rssi; 249145247Sdamien uint8_t agc; 250145247Sdamien uint8_t rssi_dbm; 251145247Sdamien uint16_t signal; 252145247Sdamien uint16_t noise; 253145247Sdamien uint8_t antenna; 254145247Sdamien uint8_t control; 255145247Sdamien uint8_t reserved2[2]; 256145247Sdamien uint16_t len; 257145247Sdamien} __packed; 258145247Sdamien 259145247Sdamien/* header for transmission */ 260145247Sdamienstruct iwi_tx_desc { 261145247Sdamien struct iwi_hdr hdr; 262145247Sdamien uint32_t reserved1; 263158089Smlaier uint8_t station; /* adhoc sta #, 0 for bss */ 264145247Sdamien uint8_t reserved2[3]; 265145247Sdamien uint8_t cmd; 266145247Sdamien#define IWI_DATA_CMD_TX 0x0b 267145247Sdamien 268145247Sdamien uint8_t seq; 269145247Sdamien uint16_t len; 270145247Sdamien uint8_t priority; 271145247Sdamien uint8_t flags; 272145247Sdamien#define IWI_DATA_FLAG_SHPREAMBLE 0x04 273145247Sdamien#define IWI_DATA_FLAG_NO_WEP 0x20 274145247Sdamien#define IWI_DATA_FLAG_NEED_ACK 0x80 275145247Sdamien 276145247Sdamien uint8_t xflags; 277149338Sdamien#define IWI_DATA_XFLAG_QOS 0x10 278149338Sdamien 279158089Smlaier uint8_t wep_txkey; 280145247Sdamien uint8_t wepkey[IEEE80211_KEYBUF_SIZE]; 281145247Sdamien uint8_t rate; 282145247Sdamien uint8_t antenna; 283145247Sdamien uint8_t reserved3[10]; 284145247Sdamien struct ieee80211_qosframe_addr4 wh; 285145247Sdamien uint32_t iv; 286145247Sdamien uint32_t eiv; 287158089Smlaier 288145247Sdamien uint32_t nseg; 289145247Sdamien#define IWI_MAX_NSEG 6 290145247Sdamien uint32_t seg_addr[IWI_MAX_NSEG]; 291145247Sdamien uint16_t seg_len[IWI_MAX_NSEG]; 292145247Sdamien} __packed; 293145247Sdamien 294145247Sdamien/* command */ 295145247Sdamienstruct iwi_cmd_desc { 296145247Sdamien struct iwi_hdr hdr; 297145247Sdamien uint8_t type; 298145247Sdamien#define IWI_CMD_ENABLE 2 299145247Sdamien#define IWI_CMD_SET_CONFIG 6 300145247Sdamien#define IWI_CMD_SET_ESSID 8 301145247Sdamien#define IWI_CMD_SET_MAC_ADDRESS 11 302145247Sdamien#define IWI_CMD_SET_RTS_THRESHOLD 15 303146500Sdamien#define IWI_CMD_SET_FRAG_THRESHOLD 16 304145247Sdamien#define IWI_CMD_SET_POWER_MODE 17 305145247Sdamien#define IWI_CMD_SET_WEP_KEY 18 306158089Smlaier#define IWI_CMD_SCAN 20 307145247Sdamien#define IWI_CMD_ASSOCIATE 21 308145247Sdamien#define IWI_CMD_SET_RATES 22 309146500Sdamien#define IWI_CMD_ABORT_SCAN 23 310149338Sdamien#define IWI_CMD_SET_WME_PARAMS 25 311158089Smlaier#define IWI_CMD_SCAN_EXT 26 312146500Sdamien#define IWI_CMD_SET_OPTIE 31 313145247Sdamien#define IWI_CMD_DISABLE 33 314145247Sdamien#define IWI_CMD_SET_IV 34 315145247Sdamien#define IWI_CMD_SET_TX_POWER 35 316145247Sdamien#define IWI_CMD_SET_SENSITIVITY 42 317149338Sdamien#define IWI_CMD_SET_WMEIE 84 318145247Sdamien 319145247Sdamien uint8_t len; 320145247Sdamien uint16_t reserved; 321145247Sdamien uint8_t data[120]; 322145247Sdamien} __packed; 323145247Sdamien 324150245Sdamien/* node information (IBSS) */ 325150341Sdamienstruct iwi_ibssnode { 326150245Sdamien uint8_t bssid[IEEE80211_ADDR_LEN]; 327150245Sdamien uint8_t reserved[2]; 328150245Sdamien} __packed; 329150245Sdamien 330145247Sdamien/* constants for 'mode' fields */ 331145247Sdamien#define IWI_MODE_11A 0 332145247Sdamien#define IWI_MODE_11B 1 333145247Sdamien#define IWI_MODE_11G 2 334145247Sdamien 335145247Sdamien/* possible values for command IWI_CMD_SET_POWER_MODE */ 336158089Smlaier#define IWI_POWER_MODE_CAM 0 /* no power save */ 337158089Smlaier#define IWI_POWER_MODE_PSP 3 338158089Smlaier#define IWI_POWER_MODE_MAX 5 /* max power save operation */ 339145247Sdamien 340145247Sdamien/* structure for command IWI_CMD_SET_RATES */ 341145247Sdamienstruct iwi_rateset { 342145247Sdamien uint8_t mode; 343145247Sdamien uint8_t nrates; 344145247Sdamien uint8_t type; 345151030Sdamien#define IWI_RATESET_TYPE_NEGOTIATED 0 346145247Sdamien#define IWI_RATESET_TYPE_SUPPORTED 1 347145247Sdamien 348145247Sdamien uint8_t reserved; 349163618Smlaier#define IWI_RATESET_SIZE 12 350163618Smlaier uint8_t rates[IWI_RATESET_SIZE]; 351145247Sdamien} __packed; 352145247Sdamien 353145247Sdamien/* structure for command IWI_CMD_SET_TX_POWER */ 354145247Sdamienstruct iwi_txpower { 355145247Sdamien uint8_t nchan; 356145247Sdamien uint8_t mode; 357145247Sdamien struct { 358145247Sdamien uint8_t chan; 359145247Sdamien uint8_t power; 360145247Sdamien#define IWI_TXPOWER_MAX 20 361145247Sdamien#define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 362145247Sdamien } __packed chan[37]; 363145247Sdamien} __packed; 364145247Sdamien 365145247Sdamien/* structure for command IWI_CMD_ASSOCIATE */ 366145247Sdamienstruct iwi_associate { 367158089Smlaier uint8_t chan; /* channel # */ 368158089Smlaier uint8_t auth; /* type and key */ 369145247Sdamien#define IWI_AUTH_OPEN 0 370145247Sdamien#define IWI_AUTH_SHARED 1 371145247Sdamien#define IWI_AUTH_NONE 3 372145247Sdamien 373158089Smlaier uint8_t type; /* request */ 374158089Smlaier#define IWI_HC_ASSOC 0 375158089Smlaier#define IWI_HC_REASSOC 1 376158089Smlaier#define IWI_HC_DISASSOC 2 377158089Smlaier#define IWI_HC_IBSS_START 3 378158089Smlaier#define IWI_HC_IBSS_RECONF 4 379158089Smlaier#define IWI_HC_DISASSOC_QUIET 5 380158089Smlaier uint8_t reserved; 381146500Sdamien uint16_t policy; 382149338Sdamien#define IWI_POLICY_WME 1 383149338Sdamien#define IWI_POLICY_WPA 2 384146500Sdamien 385158089Smlaier uint8_t plen; /* preamble length */ 386158089Smlaier uint8_t mode; /* 11a, 11b, or 11g */ 387145247Sdamien uint8_t bssid[IEEE80211_ADDR_LEN]; 388158089Smlaier uint8_t tstamp[8]; /* tsf for beacon sync */ 389145247Sdamien uint16_t capinfo; 390158089Smlaier uint16_t lintval; /* listen interval */ 391158089Smlaier uint16_t intval; /* beacon interval */ 392145247Sdamien uint8_t dst[IEEE80211_ADDR_LEN]; 393158089Smlaier uint16_t atim_window; 394158089Smlaier uint8_t smr; 395158089Smlaier uint8_t reserved1; 396158089Smlaier uint16_t reserved2; 397145247Sdamien} __packed; 398145247Sdamien 399158089Smlaier#define IWI_SCAN_CHANNELS 54 400158089Smlaier 401145247Sdamien/* structure for command IWI_CMD_SCAN */ 402145247Sdamienstruct iwi_scan { 403158089Smlaier uint8_t type; 404158089Smlaier uint16_t dwelltime; /* channel dwell time (ms) */ 405158089Smlaier uint8_t channels[IWI_SCAN_CHANNELS]; 406145247Sdamien#define IWI_CHAN_5GHZ (0 << 6) 407145247Sdamien#define IWI_CHAN_2GHZ (1 << 6) 408145247Sdamien 409158089Smlaier uint8_t reserved[3]; 410158089Smlaier} __packed; 411151030Sdamien 412158089Smlaier/* scan type codes */ 413158089Smlaier#define IWI_SCAN_TYPE_PASSIVE_STOP 0 /* passive, stop on first beacon */ 414158089Smlaier#define IWI_SCAN_TYPE_PASSIVE 1 /* passive, full dwell on channel */ 415158089Smlaier#define IWI_SCAN_TYPE_DIRECTED 2 /* active, directed probe req */ 416158089Smlaier#define IWI_SCAN_TYPE_BROADCAST 3 /* active, bcast probe req */ 417158089Smlaier#define IWI_SCAN_TYPE_BDIRECTED 4 /* active, directed+bcast probe */ 418158089Smlaier#define IWI_SCAN_TYPES 5 419158089Smlaier 420170530Ssam/* scan result codes */ 421170530Ssam#define IWI_SCAN_COMPLETED 1 /* scan compeleted sucessfully */ 422170530Ssam#define IWI_SCAN_ABORTED 2 /* scan was aborted by the driver */ 423170530Ssam 424158089Smlaier/* structure for command IWI_CMD_SCAN_EXT */ 425158089Smlaierstruct iwi_scan_ext { 426158089Smlaier uint32_t full_scan_index; 427158089Smlaier uint8_t channels[IWI_SCAN_CHANNELS]; 428158089Smlaier uint8_t scan_type[IWI_SCAN_CHANNELS / 2]; 429158089Smlaier uint8_t reserved; 430158089Smlaier uint16_t dwell_time[IWI_SCAN_TYPES]; 431145247Sdamien} __packed; 432145247Sdamien 433145247Sdamien/* structure for command IWI_CMD_SET_CONFIG */ 434145247Sdamienstruct iwi_configuration { 435145247Sdamien uint8_t bluetooth_coexistence; 436145247Sdamien uint8_t reserved1; 437158089Smlaier uint8_t answer_pbreq; /* answer bcast ssid probe req frames */ 438158089Smlaier uint8_t allow_invalid_frames; /* accept data frames w/ errors */ 439158089Smlaier uint8_t multicast_enabled; /* accept frames w/ any bssid */ 440146500Sdamien uint8_t drop_unicast_unencrypted; 441145247Sdamien uint8_t disable_unicast_decryption; 442146500Sdamien uint8_t drop_multicast_unencrypted; 443145247Sdamien uint8_t disable_multicast_decryption; 444158089Smlaier uint8_t antenna; /* antenna diversity */ 445158089Smlaier#define IWI_ANTENNA_AUTO 0 /* firmware selects best antenna */ 446158089Smlaier#define IWI_ANTENNA_A 1 /* use antenna A only */ 447158089Smlaier#define IWI_ANTENNA_B 3 /* use antenna B only */ 448158089Smlaier#define IWI_ANTENNA_SLOWDIV 2 /* slow diversity algorithm */ 449158089Smlaier uint8_t include_crc; /* include crc in rx'd frames */ 450158089Smlaier uint8_t use_protection; /* auto-detect 11g operation */ 451158089Smlaier uint8_t protection_ctsonly; /* use CTS-to-self protection */ 452145247Sdamien uint8_t enable_multicast_filtering; 453158089Smlaier uint8_t bluetooth_threshold; /* collision threshold */ 454158089Smlaier uint8_t silence_threshold; /* silence over/under threshold */ 455158089Smlaier uint8_t allow_beacon_and_probe_resp;/* accept frames w/ any bssid */ 456158089Smlaier uint8_t allow_mgt; /* accept frames w/ any bssid */ 457158089Smlaier uint8_t noise_reported; /* report noise stats to host */ 458145247Sdamien uint8_t reserved5; 459145247Sdamien} __packed; 460145247Sdamien 461145247Sdamien/* structure for command IWI_CMD_SET_WEP_KEY */ 462145247Sdamienstruct iwi_wep_key { 463145247Sdamien uint8_t cmd; 464145247Sdamien#define IWI_WEP_KEY_CMD_SETKEY 0x08 465145247Sdamien 466145247Sdamien uint8_t seq; 467145247Sdamien uint8_t idx; 468145247Sdamien uint8_t len; 469145247Sdamien uint8_t key[IEEE80211_KEYBUF_SIZE]; 470145247Sdamien} __packed; 471145247Sdamien 472149338Sdamien/* structure for command IWI_CMD_SET_WME_PARAMS */ 473149338Sdamienstruct iwi_wme_params { 474149346Sdamien uint16_t cwmin[WME_NUM_AC]; 475149346Sdamien uint16_t cwmax[WME_NUM_AC]; 476149338Sdamien uint8_t aifsn[WME_NUM_AC]; 477149338Sdamien uint8_t acm[WME_NUM_AC]; 478149346Sdamien uint16_t burst[WME_NUM_AC]; 479149338Sdamien} __packed; 480149338Sdamien 481158089Smlaier/* structure for command IWI_CMD_SET_SENSITIVTY */ 482158089Smlaierstruct iwi_sensitivity { 483158089Smlaier uint16_t rssi; /* beacon rssi in dBm */ 484158089Smlaier#define IWI_RSSI_TO_DBM 112 485158089Smlaier uint16_t reserved; 486158089Smlaier} __packed; 487158089Smlaier 488158089Smlaier#define IWI_MEM_EEPROM_EVENT 0x00300004 489145247Sdamien#define IWI_MEM_EEPROM_CTL 0x00300040 490145247Sdamien 491145247Sdamien#define IWI_EEPROM_MAC 0x21 492158089Smlaier#define IWI_EEPROM_NIC 0x25 /* nic type (lsb) */ 493158089Smlaier#define IWI_EEPROM_SKU 0x25 /* nic type (msb) */ 494145247Sdamien 495145247Sdamien#define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 496145247Sdamien 497145247Sdamien#define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 498145247Sdamien#define IWI_EEPROM_S (1 << 1) /* Chip Select */ 499145247Sdamien#define IWI_EEPROM_D (1 << 2) /* Serial data input */ 500145247Sdamien#define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 501145247Sdamien 502145247Sdamien#define IWI_EEPROM_SHIFT_D 2 503145247Sdamien#define IWI_EEPROM_SHIFT_Q 4 504145247Sdamien 505145247Sdamien/* 506145247Sdamien * control and status registers access macros 507145247Sdamien */ 508145247Sdamien#define CSR_READ_1(sc, reg) \ 509145247Sdamien bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 510145247Sdamien 511145247Sdamien#define CSR_READ_2(sc, reg) \ 512145247Sdamien bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 513145247Sdamien 514145247Sdamien#define CSR_READ_4(sc, reg) \ 515145247Sdamien bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 516145247Sdamien 517145247Sdamien#define CSR_READ_REGION_4(sc, offset, datap, count) \ 518145247Sdamien bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 519145247Sdamien (datap), (count)) 520145247Sdamien 521145247Sdamien#define CSR_WRITE_1(sc, reg, val) \ 522145247Sdamien bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 523145247Sdamien 524145247Sdamien#define CSR_WRITE_2(sc, reg, val) \ 525145247Sdamien bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 526145247Sdamien 527145247Sdamien#define CSR_WRITE_4(sc, reg, val) \ 528145247Sdamien bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 529145247Sdamien 530150245Sdamien#define CSR_WRITE_REGION_1(sc, offset, datap, count) \ 531150245Sdamien bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 532150245Sdamien (datap), (count)) 533150245Sdamien 534145247Sdamien/* 535145247Sdamien * indirect memory space access macros 536145247Sdamien */ 537145247Sdamien#define MEM_WRITE_1(sc, addr, val) do { \ 538145247Sdamien CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 539145247Sdamien CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 540145247Sdamien} while (/* CONSTCOND */0) 541145247Sdamien 542145247Sdamien#define MEM_WRITE_2(sc, addr, val) do { \ 543145247Sdamien CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 544145247Sdamien CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 545145247Sdamien} while (/* CONSTCOND */0) 546145247Sdamien 547145247Sdamien#define MEM_WRITE_4(sc, addr, val) do { \ 548145247Sdamien CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 549145247Sdamien CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 550145247Sdamien} while (/* CONSTCOND */0) 551145247Sdamien 552145247Sdamien#define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 553145247Sdamien CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 554145247Sdamien CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 555145247Sdamien} while (/* CONSTCOND */0) 556145247Sdamien 557145247Sdamien/* 558145247Sdamien * EEPROM access macro 559145247Sdamien */ 560145247Sdamien#define IWI_EEPROM_CTL(sc, val) do { \ 561145247Sdamien MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 562145247Sdamien DELAY(IWI_EEPROM_DELAY); \ 563145247Sdamien} while (/* CONSTCOND */0) 564