1139749Simp/*- 239234Sgibbs * Copyright (c) 1997 by Simon Shapiro 339234Sgibbs * All Rights Reserved 439234Sgibbs * 539234Sgibbs * Redistribution and use in source and binary forms, with or without 639234Sgibbs * modification, are permitted provided that the following conditions 739234Sgibbs * are met: 839234Sgibbs * 1. Redistributions of source code must retain the above copyright 939234Sgibbs * notice, this list of conditions, and the following disclaimer, 1039234Sgibbs * without modification, immediately at the beginning of the file. 1139234Sgibbs * 2. Redistributions in binary form must reproduce the above copyright 1239234Sgibbs * notice, this list of conditions and the following disclaimer in the 1339234Sgibbs * documentation and/or other materials provided with the distribution. 1439234Sgibbs * 3. The name of the author may not be used to endorse or promote products 1539234Sgibbs * derived from this software without specific prior written permission. 1639234Sgibbs * 1739234Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1839234Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1939234Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2039234Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2139234Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2239234Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2339234Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2439234Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2539234Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2639234Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2739234Sgibbs * SUCH DAMAGE. 2839234Sgibbs * 29201807Strasz * $FreeBSD$ 3039234Sgibbs */ 3139234Sgibbs 3239234Sgibbs/* 3339234Sgibbs * 3439234Sgibbs * dpt.h: Definitions and constants used by the SCSI side of the DPT 3539234Sgibbs * 3639234Sgibbs * credits: Mike Neuffer; DPT low level code and in other areas as well. 3739234Sgibbs * Mark Salyzyn; Many vital bits of info and diagnostics. 3839234Sgibbs * Justin Gibbs; FreeBSD API, debugging and style 3939234Sgibbs * Ron McDaniels; SCSI Software Interrupts 4039234Sgibbs * FreeBSD.ORG; Great O/S to work on and for. 4139234Sgibbs */ 4239234Sgibbs 4339234Sgibbs#ifndef _DPT_H 4439234Sgibbs#define _DPT_H 4539234Sgibbs 4639234Sgibbs#include <sys/ioccom.h> 4739234Sgibbs 4839234Sgibbs 4939234Sgibbs#undef DPT_USE_DLM_SWI 5039234Sgibbs 5139234Sgibbs#define DPT_RELEASE 1 5239234Sgibbs#define DPT_VERSION 4 5339234Sgibbs#define DPT_PATCH 5 5439234Sgibbs#define DPT_MONTH 8 5539234Sgibbs#define DPT_DAY 3 5639234Sgibbs#define DPT_YEAR 18 /* 1998 - 1980 */ 5739234Sgibbs 5839234Sgibbs#define DPT_CTL_RELEASE 1 5939234Sgibbs#define DPT_CTL_VERSION 0 6039234Sgibbs#define DPT_CTL_PATCH 6 6139234Sgibbs 6239234Sgibbs#ifndef PAGESIZ 6339234Sgibbs#define PAGESIZ 4096 6439234Sgibbs#endif 6539234Sgibbs 6639234Sgibbs#ifndef physaddr 6739234Sgibbstypedef void *physaddr; 6839234Sgibbs#endif 6939234Sgibbs 7039234Sgibbs#undef DPT_INQUIRE_DEVICES /* We have no buyers for this function */ 7139234Sgibbs#define DPT_SUPPORT_POLLING /* Use polled mode at boot (must be ON!) */ 7239234Sgibbs#define DPT_OPENNINGS 8 /* Commands-in-progress per device */ 7339234Sgibbs 7439234Sgibbs#define DPT_RETRIES 5 /* Times to retry failed commands */ 7539234Sgibbs#undef DPT_DISABLE_SG 7639234Sgibbs#define DPT_HAS_OPEN 7739234Sgibbs 7839234Sgibbs/* Arguments to dpt_run_queue() can be: */ 7939234Sgibbs 8039234Sgibbs#define DPT_MAX_TARGET_MODE_BUFFER_SIZE 8192 8139234Sgibbs#define DPT_FREE_LIST_INCREMENT 64 8239234Sgibbs#define DPT_CMD_LEN 12 8339234Sgibbs 8439234Sgibbs/* 8539234Sgibbs * How many segments do we want in a Scatter/Gather list? 8639234Sgibbs * Some HBA's can do 16, Some 8192. Since we pre-allocate 8739234Sgibbs * them in fixed increments, we need to put a practical limit on 8839234Sgibbs * these. A passed parameter (from kernel boot or lkm) would help 8939234Sgibbs */ 9039515Sgibbs#define DPT_MAX_SEGS 32 9139234Sgibbs 9239234Sgibbs/* Debug levels */ 9339234Sgibbs 9439234Sgibbs#undef DPT_DEBUG_PCI 9539234Sgibbs#undef DPT_DEBUG_INIT 9639234Sgibbs#undef DPT_DEBUG_SETUP 9739234Sgibbs#undef DPT_DEBUG_STATES 9839234Sgibbs#undef DPT_DEBUG_CONFIG 9939234Sgibbs#undef DPT_DEBUG_QUEUES 10039234Sgibbs#undef DPT_DEBUG_SCSI_CMD 10139234Sgibbs#undef DPT_DEBUG_SOFTINTR 10239234Sgibbs#undef DPT_DEBUG_HARDINTR 10339234Sgibbs#undef DPT_DEBUG_HEX_DUMPS 10439234Sgibbs#undef DPT_DEBUG_POLLING 10539234Sgibbs#undef DPT_DEBUG_INQUIRE 10639234Sgibbs#undef DPT_DEBUG_COMPLETION 10739234Sgibbs#undef DPT_DEBUG_COMPLETION_ERRORS 10839234Sgibbs#define DPT_DEBUG_MINPHYS 10939234Sgibbs#undef DPT_DEBUG_SG 11039234Sgibbs#undef DPT_DEBUG_SG_SHOW_DATA 11139234Sgibbs#undef DPT_DEBUG_SCSI_CMD_NAME 11239234Sgibbs#undef DPT_DEBUG_CONTROL 11339234Sgibbs#undef DPT_DEBUG_TIMEOUTS 11439234Sgibbs#undef DPT_DEBUG_SHUTDOWN 11539234Sgibbs#define DPT_DEBUG_USER_CMD 11639234Sgibbs 11739234Sgibbs/* 11839234Sgibbs * Misc. definitions 11939234Sgibbs */ 12039234Sgibbs#undef TRUE 12139234Sgibbs#undef FALSE 12239234Sgibbs#define TRUE 1 12339234Sgibbs#define FALSE 0 12439234Sgibbs 12539234Sgibbs#define MAX_CHANNELS 3 12639234Sgibbs#define MAX_TARGETS 16 12739234Sgibbs#define MAX_LUNS 8 12839234Sgibbs 12939234Sgibbs/* Map minor numbers to device identity */ 13039234Sgibbs#define TARGET_MASK 0x000f 13139234Sgibbs#define BUS_MASK 0x0030 13239234Sgibbs#define HBA_MASK 0x01c0 13339234Sgibbs#define LUN_MASK 0x0e00 13439234Sgibbs 13539234Sgibbs#define minor2target(minor) ( minor & TARGET_MASK ) 13639234Sgibbs#define minor2bus(minor) ( (minor & BUS_MASK) >> 4 ) 13739234Sgibbs#define minor2hba(minor) ( (minor & HBA_MASK) >> 6 ) 13839234Sgibbs#define minor2lun(minor) ( (minor & LUN_MASK) >> 9 ) 13939234Sgibbs 14039234Sgibbs/* 14139234Sgibbs * Valid values for cache_type 14239234Sgibbs */ 14339234Sgibbs#define DPT_NO_CACHE 0 14439234Sgibbs#define DPT_CACHE_WRITETHROUGH 1 145234540Sdim#define DPT_CACHE_WRITEBACK 2 14639234Sgibbs 14739234Sgibbs#define min(a,b) ((a<b)?(a):(b)) 14839234Sgibbs 14939234Sgibbs#define MAXISA 4 15039234Sgibbs#define MAXEISA 16 15139234Sgibbs#define MAXPCI 16 15239234Sgibbs#define MAXIRQ 16 15339234Sgibbs#define MAXTARGET 16 15439234Sgibbs 15539234Sgibbs#define IS_ISA 'I' 15639234Sgibbs#define IS_EISA 'E' 15739234Sgibbs#define IS_PCI 'P' 15839234Sgibbs 15939234Sgibbs#define BROKEN_INQUIRY 1 16039234Sgibbs 16139234Sgibbs#define BUSMASTER 0xff 16239234Sgibbs#define PIO 0xfe 16339234Sgibbs 16439234Sgibbs#define EATA_SIGNATURE 0x41544145 /* little ENDIAN "EATA" */ 16539234Sgibbs#define DPT_BLINK_INDICATOR 0x42445054 16639234Sgibbs 16739234Sgibbs#define DPT_ID1 0x12 16839234Sgibbs#define DPT_ID2 0x1 16939234Sgibbs#define ATT_ID1 0x06 17039234Sgibbs#define ATT_ID2 0x94 17139234Sgibbs#define ATT_ID3 0x0 17239234Sgibbs 17339234Sgibbs#define NEC_ID1 0x38 17439234Sgibbs#define NEC_ID2 0xa3 17539234Sgibbs#define NEC_ID3 0x82 17639234Sgibbs 17739234Sgibbs#define MAX_PCI_DEVICES 32 /* Maximum # Of Devices Per Bus */ 17839234Sgibbs#define MAX_METHOD_2 16 /* Max Devices For Method 2 */ 17939234Sgibbs#define MAX_PCI_BUS 16 /* Maximum # Of Busses Allowed */ 18039234Sgibbs 18139234Sgibbs#define DPT_MAX_RETRIES 2 18239234Sgibbs 18339234Sgibbs#define READ 0 18439234Sgibbs#define WRITE 1 18539234Sgibbs#define OTHER 2 18639234Sgibbs 18739234Sgibbs#define HD(cmd) ((hostdata *)&(cmd->host->hostdata)) 18839234Sgibbs#define CD(cmd) ((struct eata_ccb *)(cmd->host_scribble)) 18939234Sgibbs#define SD(host) ((hostdata *)&(host->hostdata)) 19039234Sgibbs 19139234Sgibbs/* 19239234Sgibbs * EATA Command & Register definitions 19339234Sgibbs */ 19439234Sgibbs 19539234Sgibbs#define PCI_REG_DPTconfig 0x40 19639234Sgibbs#define PCI_REG_PumpModeAddress 0x44 19739234Sgibbs#define PCI_REG_PumpModeData 0x48 19839234Sgibbs#define PCI_REG_ConfigParam1 0x50 19939234Sgibbs#define PCI_REG_ConfigParam2 0x54 20039234Sgibbs 20139234Sgibbs#define EATA_CMD_PIO_SETUPTEST 0xc6 20239234Sgibbs#define EATA_CMD_PIO_READ_CONFIG 0xf0 20339234Sgibbs#define EATA_CMD_PIO_SET_CONFIG 0xf1 20439234Sgibbs#define EATA_CMD_PIO_SEND_CP 0xf2 20539234Sgibbs#define EATA_CMD_PIO_RECEIVE_SP 0xf3 20639234Sgibbs#define EATA_CMD_PIO_TRUNC 0xf4 20739234Sgibbs 20839234Sgibbs#define EATA_CMD_RESET 0xf9 20939234Sgibbs#define EATA_COLD_BOOT 0x06 /* Last resort only! */ 21039234Sgibbs 21139234Sgibbs#define EATA_CMD_IMMEDIATE 0xfa 21239234Sgibbs 21339234Sgibbs#define EATA_CMD_DMA_READ_CONFIG 0xfd 21439234Sgibbs#define EATA_CMD_DMA_SET_CONFIG 0xfe 21539234Sgibbs#define EATA_CMD_DMA_SEND_CP 0xff 21639234Sgibbs 21739234Sgibbs#define ECS_EMULATE_SENSE 0xd4 21839234Sgibbs 21939234Sgibbs/* 22039234Sgibbs * Immediate Commands 22139234Sgibbs * Beware of this enumeration. Not all commands are in sequence! 22239234Sgibbs */ 22339234Sgibbs 22489056Smsmithenum dpt_immediate_cmd { 22539234Sgibbs EATA_GENERIC_ABORT, 22639234Sgibbs EATA_SPECIFIC_RESET, 22739234Sgibbs EATA_BUS_RESET, 22839234Sgibbs EATA_SPECIFIC_ABORT, 22939234Sgibbs EATA_QUIET_INTR, 23039234Sgibbs EATA_SMART_ROM_DL_EN, 23139234Sgibbs EATA_COLD_BOOT_HBA, /* Only as a last resort */ 23239234Sgibbs EATA_FORCE_IO, 23339234Sgibbs EATA_SCSI_BUS_OFFLINE, 23439234Sgibbs EATA_RESET_MASKED_BUS, 23539234Sgibbs EATA_POWER_OFF_WARN 23689056Smsmith}; 23739234Sgibbs 23839234Sgibbs#define HA_CTRLREG 0x206 /* control register for HBA */ 23939234Sgibbs#define HA_CTRL_DISINT 0x02 /* CTRLREG: disable interrupts */ 24039234Sgibbs#define HA_CTRL_RESCPU 0x04 /* CTRLREG: reset processo */ 24139234Sgibbs#define HA_CTRL_8HEADS 0x08 /* 24239234Sgibbs * CTRLREG: set for drives with 24339234Sgibbs * >=8 heads 24439234Sgibbs * (WD1003 rudimentary :-) 24539234Sgibbs */ 24639234Sgibbs 24739234Sgibbs#define HA_WCOMMAND 0x07 /* command register offset */ 24839234Sgibbs#define HA_WIFC 0x06 /* immediate command offset */ 24939234Sgibbs#define HA_WCODE 0x05 25039234Sgibbs#define HA_WCODE2 0x04 25139234Sgibbs#define HA_WDMAADDR 0x02 /* DMA address LSB offset */ 25239234Sgibbs#define HA_RERROR 0x01 /* Error Register, offset 1 from base */ 25339234Sgibbs#define HA_RAUXSTAT 0x08 /* aux status register offset */ 25439234Sgibbs#define HA_RSTATUS 0x07 /* status register offset */ 25539234Sgibbs#define HA_RDATA 0x00 /* data register (16bit) */ 25639234Sgibbs#define HA_WDATA 0x00 /* data register (16bit) */ 25739234Sgibbs 25839234Sgibbs#define HA_ABUSY 0x01 /* aux busy bit */ 25939234Sgibbs#define HA_AIRQ 0x02 /* aux IRQ pending bit */ 26039234Sgibbs#define HA_SERROR 0x01 /* pr. command ended in error */ 26139234Sgibbs#define HA_SMORE 0x02 /* more data soon to come */ 26239234Sgibbs#define HA_SCORR 0x04 /* datio_addra corrected */ 26339234Sgibbs#define HA_SDRQ 0x08 /* data request active */ 26439234Sgibbs#define HA_SSC 0x10 /* seek complete */ 26539234Sgibbs#define HA_SFAULT 0x20 /* write fault */ 26639234Sgibbs#define HA_SREADY 0x40 /* drive ready */ 26739234Sgibbs#define HA_SBUSY 0x80 /* drive busy */ 26839234Sgibbs#define HA_SDRDY (HA_SSC|HA_SREADY|HA_SDRQ) 26939234Sgibbs 27039234Sgibbs/* 27139234Sgibbs * Message definitions 27239234Sgibbs */ 27339234Sgibbs 27489056Smsmithenum dpt_message { 27539234Sgibbs HA_NO_ERROR, /* No Error */ 27639234Sgibbs HA_ERR_SEL_TO, /* Selection Timeout */ 27739234Sgibbs HA_ERR_CMD_TO, /* Command Timeout */ 27839234Sgibbs HA_SCSIBUS_RESET, 27939234Sgibbs HA_HBA_POWER_UP, /* Initial Controller Power-up */ 28039234Sgibbs HA_UNX_BUSPHASE, /* Unexpected Bus Phase */ 28139234Sgibbs HA_UNX_BUS_FREE, /* Unexpected Bus Free */ 28239234Sgibbs HA_BUS_PARITY, /* Bus Parity Error */ 28339234Sgibbs HA_SCSI_HUNG, /* SCSI Hung */ 28439234Sgibbs HA_UNX_MSGRJCT, /* Unexpected Message Rejected */ 28539234Sgibbs HA_RESET_STUCK, /* SCSI Bus Reset Stuck */ 28639234Sgibbs HA_RSENSE_FAIL, /* Auto Request-Sense Failed */ 28739234Sgibbs HA_PARITY_ERR, /* Controller Ram Parity Error */ 28839234Sgibbs HA_CP_ABORT_NA, /* Abort Message sent to non-active cmd */ 28939234Sgibbs HA_CP_ABORTED, /* Abort Message sent to active cmd */ 29039234Sgibbs HA_CP_RESET_NA, /* Reset Message sent to non-active cmd */ 29139234Sgibbs HA_CP_RESET, /* Reset Message sent to active cmd */ 29239234Sgibbs HA_ECC_ERR, /* Controller Ram ECC Error */ 29339234Sgibbs HA_PCI_PARITY, /* PCI Parity Error */ 29439234Sgibbs HA_PCI_MABORT, /* PCI Master Abort */ 29539234Sgibbs HA_PCI_TABORT, /* PCI Target Abort */ 29639234Sgibbs HA_PCI_STABORT /* PCI Signaled Target Abort */ 29789056Smsmith}; 29839234Sgibbs 29939234Sgibbs#define HA_STATUS_MASK 0x7F 30039234Sgibbs#define HA_IDENTIFY_MSG 0x80 30139234Sgibbs#define HA_DISCO_RECO 0x40 /* Disconnect/Reconnect */ 30239234Sgibbs 30339234Sgibbs#define DPT_RW_BUFF_HEART 0X00 30439234Sgibbs#define DPT_RW_BUFF_DLM 0x02 30539234Sgibbs#define DPT_RW_BUFF_ACCESS 0x03 30639234Sgibbs 30739234Sgibbs#define HA_INTR_OFF 1 30839234Sgibbs#define HA_INTR_ON 0 30939234Sgibbs 31039234Sgibbs/* This is really a one-time shot through some black magic */ 31139234Sgibbs#define DPT_EATA_REVA 0x1c 31239234Sgibbs#define DPT_EATA_REVB 0x1e 31339234Sgibbs#define DPT_EATA_REVC 0x22 31439234Sgibbs#define DPT_EATA_REVZ 0x24 31539234Sgibbs 31639234Sgibbs 31739234Sgibbs/* IOCTL List */ 31839234Sgibbs 31939234Sgibbs#define DPT_RW_CMD_LEN 32 32039234Sgibbs#define DPT_RW_CMD_DUMP_SOFTC "dump softc" 32139234Sgibbs#define DPT_RW_CMD_DUMP_SYSINFO "dump sysinfo" 32239234Sgibbs#define DPT_RW_CMD_DUMP_METRICS "dump metrics" 32339234Sgibbs#define DPT_RW_CMD_CLEAR_METRICS "clear metrics" 32439234Sgibbs#define DPT_RW_CMD_SHOW_LED "show LED" 32539234Sgibbs 32639234Sgibbs#define DPT_IOCTL_INTERNAL_METRICS _IOR('D', 1, dpt_perf_t) 32739234Sgibbs#define DPT_IOCTL_SOFTC _IOR('D', 2, dpt_user_softc_t) 32839234Sgibbs#define DPT_IOCTL_SEND _IOWR('D', 3, eata_pt_t) 32939234Sgibbs#define SDI_SEND 0x40044444 /* Observed from dptmgr */ 33039234Sgibbs 33139234Sgibbs/* 33239234Sgibbs * Other definitions 33339234Sgibbs */ 33439234Sgibbs 33539234Sgibbs#define DPT_HCP_LENGTH(page) (ntohs(*(int16_t *)(void *)(&page[2]))+4) 33639234Sgibbs#define DPT_HCP_FIRST(page) (&page[4]) 33739234Sgibbs#define DPT_HCP_NEXT(param) (¶m[3 + param[3] + 1]) 33839234Sgibbs#define DPT_HCP_CODE(param) (ntohs(*(int16_t *)(void *)param)) 33939234Sgibbs 34039234Sgibbs 34139234Sgibbs/* Possible return values from dpt_register_buffer() */ 34239234Sgibbs 34339234Sgibbs#define SCSI_TM_READ_BUFFER 0x3c 34439234Sgibbs#define SCSI_TM_WRITE_BUFFER 0x3b 34539234Sgibbs 34639234Sgibbs#define SCSI_TM_MODE_MASK 0x07 /* Strip off reserved and LUN */ 34739234Sgibbs#define SCSI_TM_LUN_MASK 0xe0 /* Strip off reserved and LUN */ 34839234Sgibbs 34939234Sgibbstypedef enum { 35039234Sgibbs SUCCESSFULLY_REGISTERED, 35139234Sgibbs DRIVER_DOWN, 35239234Sgibbs ALREADY_REGISTERED, 35339234Sgibbs REGISTERED_TO_ANOTHER, 35439234Sgibbs NOT_REGISTERED, 35539234Sgibbs INVALID_UNIT, 35639234Sgibbs INVALID_SENDER, 35739234Sgibbs INVALID_CALLBACK, 35839234Sgibbs NO_RESOURCES 35939234Sgibbs} dpt_rb_t; 36039234Sgibbs 36139234Sgibbstypedef enum { 36239234Sgibbs REGISTER_BUFFER, 36339234Sgibbs RELEASE_BUFFER 36439234Sgibbs} dpt_rb_op_t; 36539234Sgibbs 36639234Sgibbs/* 36739234Sgibbs * New way for completion routines to reliably copmplete processing. 36839234Sgibbs * Should take properly typed dpt_softc_t and dpt_ccb_t, 36939234Sgibbs * but interdependencies preclude that. 37039234Sgibbs */ 37139234Sgibbstypedef void (*ccb_callback)(void *dpt, int bus, void *ccb); 37239234Sgibbs 37339234Sgibbstypedef void (*buff_wr_done)(int unit, u_int8_t channel, u_int8_t target, 37439234Sgibbs u_int8_t lun, u_int16_t offset, u_int16_t length, 37539234Sgibbs int result); 37639234Sgibbs 37739234Sgibbstypedef void (*dpt_rec_buff)(int unit, u_int8_t channel, u_int8_t target, 37839234Sgibbs u_int8_t lun, void *buffer, u_int16_t offset, 37939234Sgibbs u_int16_t length); 38039234Sgibbs 38139234Sgibbs/* HBA's Status port (register) bitmap */ 38239234Sgibbstypedef struct reg_bit { /* reading this one will clear the interrupt */ 38339234Sgibbs u_int8_t error :1, /* previous command ended in an error */ 38439234Sgibbs more :1, /* More DATA coming soon Poll BSY & DRQ (PIO) */ 38539234Sgibbs corr :1, /* data read was successfully corrected with ECC */ 38639234Sgibbs drq :1, /* data request active */ 38739234Sgibbs sc :1, /* seek complete */ 38839234Sgibbs fault :1, /* write fault */ 38939234Sgibbs ready :1, /* drive ready */ 39039234Sgibbs busy :1; /* controller busy */ 39139234Sgibbs} dpt_status_reg_t; 39239234Sgibbs 39339234Sgibbs/* HBA's Auxiliary status port (register) bitmap */ 39439234Sgibbstypedef struct reg_abit { /* reading this won't clear the interrupt */ 39539234Sgibbs u_int8_t abusy :1, /* auxiliary busy */ 39639234Sgibbs irq :1, /* set when drive interrupt is asserted */ 39739234Sgibbs :6; 39839234Sgibbs} dpt_aux_status_t; 39939234Sgibbs 40039234Sgibbs/* The EATA Register Set as a structure */ 40139234Sgibbstypedef struct eata_register { 40239234Sgibbs u_int8_t data_reg[2]; /* R, couldn't figure this one out */ 40339234Sgibbs u_int8_t cp_addr[4]; /* W, CP address register */ 40439234Sgibbs union { 40539234Sgibbs u_int8_t command; /* 40639234Sgibbs * W, command code: 40739234Sgibbs * [read|set] conf, send CP 40839234Sgibbs */ 40939234Sgibbs struct reg_bit status; /* R, see register_bit1 */ 41039234Sgibbs u_int8_t statusbyte; 41139234Sgibbs } ovr; 41239234Sgibbs struct reg_abit aux_stat; /* R, see register_bit2 */ 41339234Sgibbs} eata_reg_t; 41439234Sgibbs 41539234Sgibbs/* 41639234Sgibbs * Holds the results of a READ_CONFIGURATION command 41739234Sgibbs * Beware of data items which are larger than 1 byte. 41839234Sgibbs * these come from the DPT in network order. 41939234Sgibbs * On an Intel ``CPU'' they will be upside down and backwards! 42039234Sgibbs * The dpt_get_conf function is normally responsible for flipping 42139234Sgibbs * Everything back. 42239234Sgibbs */ 42339234Sgibbstypedef struct get_conf { /* Read Configuration Array */ 42439234Sgibbs union { 42539234Sgibbs struct { 42639234Sgibbs u_int8_t foo_DevType; 42739234Sgibbs u_int8_t foo_PageCode; 42839234Sgibbs u_int8_t foo_Reserved0; 42939234Sgibbs u_int8_t foo_len; 43039234Sgibbs } foo; 43139234Sgibbs u_int32_t foo_length; /* Should return 0x22, 0x24, etc */ 43239234Sgibbs } bar; 43339234Sgibbs#define gcs_length bar.foo_length 43439234Sgibbs#define gcs_PageCode bar.foo.foo_DevType 43539234Sgibbs#define gcs_reserved0 bar.foo.foo_Reserved0 43639234Sgibbs#define gcs_len bar.foo.foo_len 43739234Sgibbs 43839234Sgibbs u_int32_t signature; /* Signature MUST be "EATA". ntohl()`ed */ 43939234Sgibbs 44039234Sgibbs u_int8_t version2 :4, 44139234Sgibbs version :4; /* EATA Version level */ 44239234Sgibbs 44339234Sgibbs u_int8_t OCS_enabled :1, /* Overlap Command Support enabled */ 44439234Sgibbs TAR_support :1, /* SCSI Target Mode supported */ 44539234Sgibbs TRNXFR :1, /* Truncate Transfer Cmd Used in PIO Mode */ 44639234Sgibbs MORE_support:1, /* MORE supported (PIO Mode Only) */ 44739234Sgibbs DMA_support :1, /* DMA supported */ 44839234Sgibbs DMA_valid :1, /* DRQ value in Byte 30 is valid */ 44939234Sgibbs ATA :1, /* ATA device connected (not supported) */ 45039234Sgibbs HAA_valid :1; /* Hostadapter Address is valid */ 45139234Sgibbs 45239234Sgibbs u_int16_t cppadlen; /* 45339234Sgibbs * Number of pad bytes send after CD data set 45439234Sgibbs * to zero for DMA commands. Ntohl()`ed 45539234Sgibbs */ 45639234Sgibbs u_int8_t scsi_idS; /* SCSI ID of controller 2-0 Byte 0 res. */ 45739234Sgibbs u_int8_t scsi_id2; /* If not, zero is returned */ 45839234Sgibbs u_int8_t scsi_id1; 45939234Sgibbs u_int8_t scsi_id0; 46039234Sgibbs u_int32_t cplen; /* CP length: number of valid cp bytes */ 46139234Sgibbs 46239234Sgibbs u_int32_t splen; /* Returned bytes for a received SP command */ 46339234Sgibbs u_int16_t queuesiz; /* max number of queueable CPs */ 46439234Sgibbs 46539234Sgibbs u_int16_t dummy; 46639234Sgibbs u_int16_t SGsiz; /* max number of SG table entrie */ 46739234Sgibbs 46839234Sgibbs u_int8_t IRQ :4,/* IRQ used this HBA */ 46939234Sgibbs IRQ_TR :1,/* IRQ Trigger: 0=edge, 1=level */ 47039234Sgibbs SECOND :1,/* This is a secondary controller */ 47139234Sgibbs DMA_channel:2;/* DRQ index, DRQ is 2comp of DRQX */ 47239234Sgibbs 47339234Sgibbs u_int8_t sync; /* 0-7 sync active bitmask (deprecated) */ 47439234Sgibbs u_int8_t DSBLE :1, /* ISA i/o addressing is disabled */ 47539234Sgibbs FORCADR :1, /* i/o address has been forced */ 47639234Sgibbs SG_64K :1, 47739234Sgibbs SG_UAE :1, 47839234Sgibbs :4; 47939234Sgibbs 48039234Sgibbs u_int8_t MAX_ID :5, /* Max number of SCSI target IDs */ 48139234Sgibbs MAX_CHAN :3; /* Number of SCSI busses on HBA */ 48239234Sgibbs 48339234Sgibbs u_int8_t MAX_LUN; /* Max number of LUNs */ 48439234Sgibbs u_int8_t :3, 48539234Sgibbs AUTOTRM :1, 48639234Sgibbs M1_inst :1, 48739234Sgibbs ID_qest :1, /* Raidnum ID is questionable */ 48839234Sgibbs is_PCI :1, /* HBA is PCI */ 48939234Sgibbs is_EISA :1; /* HBA is EISA */ 49039234Sgibbs 49139234Sgibbs u_int8_t RAIDNUM; /* unique HBA identifier */ 49239234Sgibbs u_int8_t unused[4]; /* When doing PIO, you GET 512 bytes */ 49339234Sgibbs 49439234Sgibbs /* >>------>> End of The DPT structure <<------<< */ 49539234Sgibbs 49639234Sgibbs u_int32_t length; /* True length, after ntohl conversion */ 49739234Sgibbs} dpt_conf_t; 49839234Sgibbs 49939234Sgibbs/* Scatter-Gather list entry */ 50039234Sgibbstypedef struct dpt_sg_segment { 50139234Sgibbs u_int32_t seg_addr; /* All fields in network byte order */ 50239234Sgibbs u_int32_t seg_len; 50339234Sgibbs} dpt_sg_t; 50439234Sgibbs 50539234Sgibbs 50639234Sgibbs/* Status Packet */ 50739234Sgibbstypedef struct eata_sp { 50839234Sgibbs u_int8_t hba_stat :7, /* HBA status */ 50939234Sgibbs EOC :1; /* True if command finished */ 51039234Sgibbs 51139234Sgibbs u_int8_t scsi_stat; /* Target SCSI status */ 51239234Sgibbs 51339234Sgibbs u_int8_t reserved[2]; 51439234Sgibbs 51539234Sgibbs u_int32_t residue_len; /* Number of bytes not transferred */ 51639234Sgibbs 51739234Sgibbs u_int32_t ccb_busaddr; 51839234Sgibbs 51939234Sgibbs u_int8_t sp_ID_Message; 52039234Sgibbs u_int8_t sp_Que_Message; 52139234Sgibbs u_int8_t sp_Tag_Message; 52239234Sgibbs u_int8_t msg[9]; 52339234Sgibbs} dpt_sp_t; 52439234Sgibbs 52539234Sgibbs/* 52639234Sgibbs * A strange collection of O/S-Hardware releated bits and pieces. 52739234Sgibbs * Used by the dpt_ioctl() entry point to return DPT_SYSINFO command. 52839234Sgibbs */ 52939234Sgibbstypedef struct dpt_drive_parameters { 53039234Sgibbs u_int16_t cylinders; /* Up to 1024 */ 53139234Sgibbs u_int8_t heads; /* Up to 255 */ 53239234Sgibbs u_int8_t sectors; /* Up to 63 */ 53339234Sgibbs} dpt_drive_t; 53439234Sgibbs 53539234Sgibbstypedef struct driveParam_S driveParam_T; 53639234Sgibbs 53739234Sgibbs#define SI_CMOS_Valid 0x0001 53839234Sgibbs#define SI_NumDrivesValid 0x0002 53939234Sgibbs#define SI_ProcessorValid 0x0004 54039234Sgibbs#define SI_MemorySizeValid 0x0008 54139234Sgibbs#define SI_DriveParamsValid 0x0010 54239234Sgibbs#define SI_SmartROMverValid 0x0020 54339234Sgibbs#define SI_OSversionValid 0x0040 54439234Sgibbs#define SI_OSspecificValid 0x0080 54539234Sgibbs#define SI_BusTypeValid 0x0100 54639234Sgibbs 54739234Sgibbs#define SI_ALL_VALID 0x0FFF 54839234Sgibbs#define SI_NO_SmartROM 0x8000 54939234Sgibbs 55039234Sgibbs#define SI_ISA_BUS 0x00 55139234Sgibbs#define SI_MCA_BUS 0x01 55239234Sgibbs#define SI_EISA_BUS 0x02 55339234Sgibbs#define SI_PCI_BUS 0x04 55439234Sgibbs 55539234Sgibbs#define HBA_BUS_ISA 0x00 55639234Sgibbs#define HBA_BUS_EISA 0x01 55739234Sgibbs#define HBA_BUS_PCI 0x02 55839234Sgibbs 55939234Sgibbstypedef struct dpt_sysinfo { 56039234Sgibbs u_int8_t drive0CMOS; /* CMOS Drive 0 Type */ 56139234Sgibbs u_int8_t drive1CMOS; /* CMOS Drive 1 Type */ 56239234Sgibbs u_int8_t numDrives; /* 0040:0075 contents */ 56339234Sgibbs u_int8_t processorFamily; /* Same as DPTSIG definition */ 56439234Sgibbs u_int8_t processorType; /* Same as DPTSIG definition */ 56539234Sgibbs u_int8_t smartROMMajorVersion; 56639234Sgibbs u_int8_t smartROMMinorVersion; /* SmartROM version */ 56739234Sgibbs u_int8_t smartROMRevision; 56839234Sgibbs u_int16_t flags; /* See bit definitions above */ 56939234Sgibbs u_int16_t conventionalMemSize; /* in KB */ 57039234Sgibbs u_int32_t extendedMemSize; /* in KB */ 57139234Sgibbs u_int32_t osType; /* Same as DPTSIG definition */ 57239234Sgibbs u_int8_t osMajorVersion; 57339234Sgibbs u_int8_t osMinorVersion; /* The OS version */ 57439234Sgibbs u_int8_t osRevision; 57539234Sgibbs u_int8_t osSubRevision; 57639234Sgibbs u_int8_t busType; /* See defininitions above */ 57739234Sgibbs u_int8_t pad[3]; /* For alignment */ 57839234Sgibbs dpt_drive_t drives[16]; /* SmartROM Logical Drives */ 57939234Sgibbs} dpt_sysinfo_t; 58039234Sgibbs 58139234Sgibbs/* SEND_COMMAND packet structure */ 58239234Sgibbstypedef struct eata_ccb { 58339234Sgibbs u_int8_t SCSI_Reset :1, /* Cause a SCSI Bus reset on the cmd */ 58439234Sgibbs HBA_Init :1, /* Cause Controller to reinitialize */ 58539234Sgibbs Auto_Req_Sen :1, /* Do Auto Request Sense on errors */ 58639234Sgibbs scatter :1, /* Data Ptr points to a SG Packet */ 58739234Sgibbs Quick :1, /* Set this one for NO Status PAcket */ 58839234Sgibbs Interpret :1, /* Interpret the SCSI cdb for own use */ 58939234Sgibbs DataOut :1, /* Data Out phase with command */ 59039234Sgibbs DataIn :1; /* Data In phase with command */ 59139234Sgibbs 59239234Sgibbs u_int8_t reqlen; /* Request Sense Length, if Auto_Req_Sen=1 */ 59339234Sgibbs u_int8_t unused[3]; 59439234Sgibbs u_int8_t FWNEST :1, /* send cmd to phys RAID component */ 59539234Sgibbs unused2 :7; 59639234Sgibbs 59739234Sgibbs u_int8_t Phsunit :1, /* physical unit on mirrored pair */ 59839234Sgibbs I_AT :1, /* inhibit address translation */ 59939234Sgibbs Disable_Cache :1, /* HBA inhibit caching */ 60039234Sgibbs :5; 60139234Sgibbs 60239234Sgibbs u_int8_t cp_id :5, /* SCSI Device ID of target */ 60339234Sgibbs cp_channel :3; /* SCSI Channel # of HBA */ 60439234Sgibbs 60539553Sgibbs u_int8_t cp_LUN :5, 60639234Sgibbs cp_luntar :1, /* CP is for target ROUTINE */ 60739234Sgibbs cp_dispri :1, /* Grant disconnect privilege */ 60839234Sgibbs cp_identify :1; /* Always TRUE */ 60939234Sgibbs 61039234Sgibbs u_int8_t cp_msg[3]; /* Message bytes 0-3 */ 61139234Sgibbs 61239234Sgibbs union { 61339234Sgibbs struct { 61439234Sgibbs u_int8_t x_scsi_cmd; /* Partial SCSI CDB def */ 61539234Sgibbs 61639234Sgibbs u_int8_t x_extent :1, 61739234Sgibbs x_bytchk :1, 61839234Sgibbs x_reladr :1, 61939234Sgibbs x_cmplst :1, 62039234Sgibbs x_fmtdata :1, 62139234Sgibbs x_lun :3; 62239234Sgibbs 62339234Sgibbs u_int8_t x_page; 62439234Sgibbs u_int8_t reserved4; 62539234Sgibbs u_int8_t x_len; 62639234Sgibbs u_int8_t x_link :1; 62739234Sgibbs u_int8_t x_flag :1; 62839234Sgibbs u_int8_t reserved5 :4; 62939234Sgibbs u_int8_t x_vendor :2; 63039234Sgibbs } x; 63139234Sgibbs u_int8_t z[12]; /* Command Descriptor Block (= 12) */ 63239234Sgibbs } cp_w; 63339234Sgibbs 63439234Sgibbs#define cp_cdb cp_w.z 63539234Sgibbs#define cp_scsi_cmd cp_w.x.x_scsi_cmd 63639234Sgibbs#define cp_extent cp_w.x.x_extent 63739234Sgibbs#define cp_lun cp_w.x.x_lun 63839234Sgibbs#define cp_page cp_w.x.x_page 63939234Sgibbs#define cp_len cp_w.x.x_len 64039234Sgibbs 64139234Sgibbs#define MULTIFUNCTION_CMD 0x0e /* SCSI Multi Function Cmd */ 64239234Sgibbs#define BUS_QUIET 0x04 /* Quite Scsi Bus Code */ 64339234Sgibbs#define BUS_UNQUIET 0x05 /* Un Quiet Scsi Bus Code */ 64439234Sgibbs 64539234Sgibbs u_int32_t cp_datalen; /* 64639234Sgibbs * Data Transfer Length. If scatter=1 len (IN 64739234Sgibbs * BYTES!) of the S/G array 64839234Sgibbs */ 64939234Sgibbs 65039234Sgibbs u_int32_t cp_busaddr; /* Unique identifier. Busaddr works well */ 65139234Sgibbs u_int32_t cp_dataDMA; /* 65239234Sgibbs * Data Address, if scatter=1 then it is the 65339234Sgibbs * address of scatter packet 65439234Sgibbs */ 65539234Sgibbs u_int32_t cp_statDMA; /* address for Status Packet */ 65639234Sgibbs u_int32_t cp_reqDMA; /* 65739234Sgibbs * Request Sense Address, used if CP command 65839234Sgibbs * ends with error 65939234Sgibbs */ 66039234Sgibbs u_int8_t CP_OpCode; 66139234Sgibbs 66239234Sgibbs} eata_ccb_t; 66339234Sgibbs 66439234Sgibbs/* 66539234Sgibbs * DPT Signature Structure. 66639234Sgibbs * Used by /dev/dpt to directly pass commands to the HBA 66739234Sgibbs * We have more information here than we care for... 66839234Sgibbs */ 66939234Sgibbs 67039234Sgibbs/* Current Signature Version - sigBYTE dsSigVersion; */ 67139234Sgibbs#define SIG_VERSION 1 67239234Sgibbs 67339234Sgibbs/* 67439234Sgibbs * Processor Family - sigBYTE dsProcessorFamily; DISTINCT VALUE 67539234Sgibbs * 67639234Sgibbs * What type of processor the file is meant to run on. 67739234Sgibbs * This will let us know whether to read sigWORDs as high/low or low/high. 67839234Sgibbs */ 67939234Sgibbs#define PROC_INTEL 0x00 /* Intel 80x86 */ 68039234Sgibbs#define PROC_MOTOROLA 0x01 /* Motorola 68K */ 68139234Sgibbs#define PROC_MIPS4000 0x02 /* MIPS RISC 4000 */ 68239234Sgibbs#define PROC_ALPHA 0x03 /* DEC Alpha */ 68339234Sgibbs 68439234Sgibbs/* 68539234Sgibbs * Specific Minimim Processor - sigBYTE dsProcessor; FLAG BITS 68639234Sgibbs * 68739234Sgibbs * Different bit definitions dependent on processor_family 68839234Sgibbs */ 68939234Sgibbs 69039234Sgibbs/* PROC_INTEL: */ 69139234Sgibbs#define PROC_8086 0x01 /* Intel 8086 */ 69239234Sgibbs#define PROC_286 0x02 /* Intel 80286 */ 69339234Sgibbs#define PROC_386 0x04 /* Intel 80386 */ 69439234Sgibbs#define PROC_486 0x08 /* Intel 80486 */ 69539234Sgibbs#define PROC_PENTIUM 0x10 /* Intel 586 aka P5 aka Pentium */ 69639234Sgibbs#define PROC_P6 0x20 /* Intel 686 aka P6 */ 69739234Sgibbs 69839234Sgibbs/* PROC_MOTOROLA: */ 69939234Sgibbs#define PROC_68000 0x01 /* Motorola 68000 */ 70039234Sgibbs#define PROC_68020 0x02 /* Motorola 68020 */ 70139234Sgibbs#define PROC_68030 0x04 /* Motorola 68030 */ 70239234Sgibbs#define PROC_68040 0x08 /* Motorola 68040 */ 70339234Sgibbs 70439234Sgibbs/* Filetype - sigBYTE dsFiletype; DISTINCT VALUES */ 70539234Sgibbs#define FT_EXECUTABLE 0 /* Executable Program */ 70639234Sgibbs#define FT_SCRIPT 1 /* Script/Batch File??? */ 70739234Sgibbs#define FT_HBADRVR 2 /* HBA Driver */ 70839234Sgibbs#define FT_OTHERDRVR 3 /* Other Driver */ 70939234Sgibbs#define FT_IFS 4 /* Installable Filesystem Driver */ 71039234Sgibbs#define FT_ENGINE 5 /* DPT Engine */ 71139234Sgibbs#define FT_COMPDRVR 6 /* Compressed Driver Disk */ 71239234Sgibbs#define FT_LANGUAGE 7 /* Foreign Language file */ 71339234Sgibbs#define FT_FIRMWARE 8 /* Downloadable or actual Firmware */ 71439234Sgibbs#define FT_COMMMODL 9 /* Communications Module */ 71539234Sgibbs#define FT_INT13 10 /* INT 13 style HBA Driver */ 71639234Sgibbs#define FT_HELPFILE 11 /* Help file */ 71739234Sgibbs#define FT_LOGGER 12 /* Event Logger */ 71839234Sgibbs#define FT_INSTALL 13 /* An Install Program */ 71939234Sgibbs#define FT_LIBRARY 14 /* Storage Manager Real-Mode Calls */ 72039234Sgibbs#define FT_RESOURCE 15 /* Storage Manager Resource File */ 72139234Sgibbs#define FT_MODEM_DB 16 /* Storage Manager Modem Database */ 72239234Sgibbs 72339234Sgibbs/* Filetype flags - sigBYTE dsFiletypeFlags; FLAG BITS */ 72439234Sgibbs#define FTF_DLL 0x01 /* Dynamic Link Library */ 72539234Sgibbs#define FTF_NLM 0x02 /* Netware Loadable Module */ 72639234Sgibbs#define FTF_OVERLAYS 0x04 /* Uses overlays */ 72739234Sgibbs#define FTF_DEBUG 0x08 /* Debug version */ 72839234Sgibbs#define FTF_TSR 0x10 /* TSR */ 72939234Sgibbs#define FTF_SYS 0x20 /* DOS Lodable driver */ 73039234Sgibbs#define FTF_PROTECTED 0x40 /* Runs in protected mode */ 73139234Sgibbs#define FTF_APP_SPEC 0x80 /* Application Specific */ 73239234Sgibbs 73339234Sgibbs/* OEM - sigBYTE dsOEM; DISTINCT VALUES */ 73439234Sgibbs#define OEM_DPT 0 /* DPT */ 73539234Sgibbs#define OEM_ATT 1 /* ATT */ 73639234Sgibbs#define OEM_NEC 2 /* NEC */ 73739234Sgibbs#define OEM_ALPHA 3 /* Alphatronix */ 73839234Sgibbs#define OEM_AST 4 /* AST */ 73939234Sgibbs#define OEM_OLIVETTI 5 /* Olivetti */ 74039234Sgibbs#define OEM_SNI 6 /* Siemens/Nixdorf */ 74139234Sgibbs 74239234Sgibbs/* Operating System - sigLONG dsOS; FLAG BITS */ 74339234Sgibbs#define OS_DOS 0x00000001 /* PC/MS-DOS */ 74439234Sgibbs#define OS_WINDOWS 0x00000002 /* Microsoft Windows 3.x */ 74539234Sgibbs#define OS_WINDOWS_NT 0x00000004 /* Microsoft Windows NT */ 74639234Sgibbs#define OS_OS2M 0x00000008 /* OS/2 1.2.x,MS 1.3.0,IBM 1.3.x */ 74739234Sgibbs#define OS_OS2L 0x00000010 /* Microsoft OS/2 1.301 - LADDR */ 74839234Sgibbs#define OS_OS22x 0x00000020 /* IBM OS/2 2.x */ 74939234Sgibbs#define OS_NW286 0x00000040 /* Novell NetWare 286 */ 75039234Sgibbs#define OS_NW386 0x00000080 /* Novell NetWare 386 */ 75139234Sgibbs#define OS_GEN_UNIX 0x00000100 /* Generic Unix */ 75239234Sgibbs#define OS_SCO_UNIX 0x00000200 /* SCO Unix */ 75339234Sgibbs#define OS_ATT_UNIX 0x00000400 /* ATT Unix */ 75439234Sgibbs#define OS_UNIXWARE 0x00000800 /* UnixWare Unix */ 75539234Sgibbs#define OS_INT_UNIX 0x00001000 /* Interactive Unix */ 75639234Sgibbs#define OS_SOLARIS 0x00002000 /* SunSoft Solaris */ 75739234Sgibbs#define OS_QN 0x00004000 /* QNX for Tom Moch */ 75839234Sgibbs#define OS_NEXTSTEP 0x00008000 /* NeXTSTEP */ 75939234Sgibbs#define OS_BANYAN 0x00010000 /* Banyan Vines */ 76039234Sgibbs#define OS_OLIVETTI_UNIX 0x00020000 /* Olivetti Unix */ 76139234Sgibbs#define OS_FREEBSD 0x00040000 /* FreeBSD 2.2 and later */ 76239234Sgibbs#define OS_OTHER 0x80000000 /* Other */ 76339234Sgibbs 76439234Sgibbs/* Capabilities - sigWORD dsCapabilities; FLAG BITS */ 76539234Sgibbs#define CAP_RAID0 0x0001 /* RAID-0 */ 76639234Sgibbs#define CAP_RAID1 0x0002 /* RAID-1 */ 76739234Sgibbs#define CAP_RAID3 0x0004 /* RAID-3 */ 76839234Sgibbs#define CAP_RAID5 0x0008 /* RAID-5 */ 76939234Sgibbs#define CAP_SPAN 0x0010 /* Spanning */ 77039234Sgibbs#define CAP_PASS 0x0020 /* Provides passthrough */ 77139234Sgibbs#define CAP_OVERLAP 0x0040 /* Passthrough supports overlapped commands */ 77239234Sgibbs#define CAP_ASPI 0x0080 /* Supports ASPI Command Requests */ 77339234Sgibbs#define CAP_ABOVE16MB 0x0100 /* ISA Driver supports greater than 16MB */ 77439234Sgibbs#define CAP_EXTEND 0x8000 /* Extended info appears after description */ 77539234Sgibbs 77639234Sgibbs/* Devices Supported - sigWORD dsDeviceSupp; FLAG BITS */ 77739234Sgibbs#define DEV_DASD 0x0001 /* DASD (hard drives) */ 77839234Sgibbs#define DEV_TAPE 0x0002 /* Tape drives */ 77939234Sgibbs#define DEV_PRINTER 0x0004 /* Printers */ 78039234Sgibbs#define DEV_PROC 0x0008 /* Processors */ 78139234Sgibbs#define DEV_WORM 0x0010 /* WORM drives */ 78239234Sgibbs#define DEV_CDROM 0x0020 /* CD-ROM drives */ 78339234Sgibbs#define DEV_SCANNER 0x0040 /* Scanners */ 78439234Sgibbs#define DEV_OPTICAL 0x0080 /* Optical Drives */ 78539234Sgibbs#define DEV_JUKEBOX 0x0100 /* Jukebox */ 78639234Sgibbs#define DEV_COMM 0x0200 /* Communications Devices */ 78739234Sgibbs#define DEV_OTHER 0x0400 /* Other Devices */ 78839234Sgibbs#define DEV_ALL 0xFFFF /* All SCSI Devices */ 78939234Sgibbs 79039234Sgibbs/* Adapters Families Supported - sigWORD dsAdapterSupp; FLAG BITS */ 79139234Sgibbs#define ADF_2001 0x0001 /* PM2001 */ 79239234Sgibbs#define ADF_2012A 0x0002 /* PM2012A */ 79339234Sgibbs#define ADF_PLUS_ISA 0x0004 /* PM2011,PM2021 */ 79439234Sgibbs#define ADF_PLUS_EISA 0x0008 /* PM2012B,PM2022 */ 79539234Sgibbs#define ADF_SC3_ISA 0x0010 /* PM2021 */ 79639234Sgibbs#define ADF_SC3_EISA 0x0020 /* PM2022,PM2122, etc */ 79739234Sgibbs#define ADF_SC3_PCI 0x0040 /* SmartCache III PCI */ 79839234Sgibbs#define ADF_SC4_ISA 0x0080 /* SmartCache IV ISA */ 79939234Sgibbs#define ADF_SC4_EISA 0x0100 /* SmartCache IV EISA */ 80039234Sgibbs#define ADF_SC4_PCI 0x0200 /* SmartCache IV PCI */ 80139234Sgibbs#define ADF_ALL_MASTER 0xFFFE /* All bus mastering */ 80239234Sgibbs#define ADF_ALL_CACHE 0xFFFC /* All caching */ 80339234Sgibbs#define ADF_ALL 0xFFFF /* ALL DPT adapters */ 80439234Sgibbs 80539234Sgibbs/* Application - sigWORD dsApplication; FLAG BITS */ 80639234Sgibbs#define APP_DPTMGR 0x0001 /* DPT Storage Manager */ 80739234Sgibbs#define APP_ENGINE 0x0002 /* DPT Engine */ 80839234Sgibbs#define APP_SYTOS 0x0004 /* Sytron Sytos Plus */ 80939234Sgibbs#define APP_CHEYENNE 0x0008 /* Cheyenne ARCServe + ARCSolo */ 81039234Sgibbs#define APP_MSCDEX 0x0010 /* Microsoft CD-ROM extensions */ 81139234Sgibbs#define APP_NOVABACK 0x0020 /* NovaStor Novaback */ 81239234Sgibbs#define APP_AIM 0x0040 /* Archive Information Manager */ 81339234Sgibbs 81439234Sgibbs/* Requirements - sigBYTE dsRequirements; FLAG BITS */ 81539234Sgibbs#define REQ_SMARTROM 0x01 /* Requires SmartROM to be present */ 81639234Sgibbs#define REQ_DPTDDL 0x02 /* Requires DPTDDL.SYS to be loaded */ 81739234Sgibbs#define REQ_HBA_DRIVER 0x04 /* Requires an HBA driver to be loaded */ 81839234Sgibbs#define REQ_ASPI_TRAN 0x08 /* Requires an ASPI Transport Modules */ 81939234Sgibbs#define REQ_ENGINE 0x10 /* Requires a DPT Engine to be loaded */ 82039234Sgibbs#define REQ_COMM_ENG 0x20 /* Requires a DPT Communications Engine */ 82139234Sgibbs 82239234Sgibbstypedef struct dpt_sig { 82339234Sgibbs char dsSignature[6]; /* ALWAYS "dPtSiG" */ 82439234Sgibbs u_int8_t SigVersion; /* signature version (currently 1) */ 82539234Sgibbs u_int8_t ProcessorFamily; /* what type of processor */ 82639234Sgibbs u_int8_t Processor; /* precise processor */ 82739234Sgibbs u_int8_t Filetype; /* type of file */ 82839234Sgibbs u_int8_t FiletypeFlags; /* flags to specify load type, etc. */ 82939234Sgibbs u_int8_t OEM; /* OEM file was created for */ 83039234Sgibbs u_int32_t OS; /* which Operating systems */ 83139234Sgibbs u_int16_t Capabilities; /* RAID levels, etc. */ 83239234Sgibbs u_int16_t DeviceSupp; /* Types of SCSI devices supported */ 83339234Sgibbs u_int16_t AdapterSupp; /* DPT adapter families supported */ 83439234Sgibbs u_int16_t Application; /* applications file is for */ 83539234Sgibbs u_int8_t Requirements; /* Other driver dependencies */ 83639234Sgibbs u_int8_t Version; /* 1 */ 83739234Sgibbs u_int8_t Revision; /* 'J' */ 83839234Sgibbs u_int8_t SubRevision; /* '9', ' ' if N/A */ 83939234Sgibbs u_int8_t Month; /* creation month */ 84039234Sgibbs u_int8_t Day; /* creation day */ 84139234Sgibbs u_int8_t Year; /* creation year since 1980 */ 84239234Sgibbs char *Description; /* description (NULL terminated) */ 84339234Sgibbs} dpt_sig_t; 84439234Sgibbs 84539234Sgibbs/* 32 bytes minimum - with no description. Put NULL at description[0] */ 84639234Sgibbs/* 81 bytes maximum - with 49 character description plus NULL. */ 84739234Sgibbs 84839234Sgibbs/* This line added at Roycroft's request */ 84939234Sgibbs/* Microsoft's NT compiler gets confused if you do a pack and don't */ 85039234Sgibbs/* restore it. */ 85139234Sgibbstypedef struct eata_pass_through { 85239234Sgibbs u_int8_t eataID[4]; 85339234Sgibbs u_int32_t command; 85439234Sgibbs 85539234Sgibbs#define EATAUSRCMD (('D'<<8)|65) /* EATA PassThrough Command */ 85639234Sgibbs#define DPT_SIGNATURE (('D'<<8)|67) /* Get Signature Structure */ 85739234Sgibbs#define DPT_NUMCTRLS (('D'<<8)|68) /* Get Number Of DPT Adapters */ 85839234Sgibbs#define DPT_CTRLINFO (('D'<<8)|69) /* Get Adapter Info Structure */ 85939234Sgibbs#define DPT_SYSINFO (('D'<<8)|72) /* Get System Info Structure */ 86039234Sgibbs#define DPT_BLINKLED (('D'<<8)|75) /* Get The BlinkLED Status */ 86139234Sgibbs 86239234Sgibbs u_int8_t *command_buffer; 86339234Sgibbs eata_ccb_t command_packet; 86439234Sgibbs u_int32_t timeout; 86539234Sgibbs u_int8_t host_status; 86639234Sgibbs u_int8_t target_status; 86739234Sgibbs u_int8_t retries; 86839234Sgibbs} eata_pt_t; 86939234Sgibbs 87039234Sgibbstypedef enum { 87139234Sgibbs DCCB_FREE = 0x00, 87239234Sgibbs DCCB_ACTIVE = 0x01, 87339234Sgibbs DCCB_RELEASE_SIMQ = 0x02 87439234Sgibbs} dccb_state; 87539234Sgibbs 87639234Sgibbstypedef struct dpt_ccb { 87739234Sgibbs eata_ccb_t eata_ccb; 87839234Sgibbs bus_dmamap_t dmamap; 879241593Sjhb struct callout timer; 88039234Sgibbs dpt_sg_t *sg_list; 88139234Sgibbs u_int32_t sg_busaddr; 88239234Sgibbs dccb_state state; 88339234Sgibbs union ccb *ccb; 88439234Sgibbs struct scsi_sense_data sense_data; 88539515Sgibbs u_int8_t tag; 88639234Sgibbs u_int8_t retries; 88739515Sgibbs u_int8_t status; /* status of this queueslot */ 88839515Sgibbs u_int8_t *cmd; /* address of cmd */ 88939234Sgibbs 89039234Sgibbs u_int32_t transaction_id; 89139234Sgibbs u_int32_t result; 89239234Sgibbs caddr_t data; 89360938Sjake SLIST_ENTRY(dpt_ccb) links; 89439234Sgibbs 89539234Sgibbs#ifdef DPT_MEASURE_PERFORMANCE 89639234Sgibbs u_int32_t submitted_time; 89739234Sgibbs struct timeval command_started; 89839234Sgibbs struct timeval command_ended; 89939234Sgibbs#endif 90039234Sgibbs} dpt_ccb_t; 90139234Sgibbs 90239234Sgibbs/* 90372093Sasmodai * This is provided for compatibility with UnixWare only. 90439234Sgibbs * Some of the fields may be bogus. 90539234Sgibbs * Others may have a totally different meaning. 90639234Sgibbs */ 90739234Sgibbstypedef struct dpt_scsi_ha { 90839234Sgibbs u_int32_t ha_state; /* Operational state */ 90939234Sgibbs u_int8_t ha_id[MAX_CHANNELS]; /* Host adapter SCSI ids */ 91039234Sgibbs int32_t ha_base; /* Base I/O address */ 91139234Sgibbs int ha_max_jobs; /* Max number of Active Jobs */ 91239234Sgibbs int ha_cache:2; /* Cache parameters */ 91339234Sgibbs int ha_cachesize:30; /* In meg, only if cache present*/ 91439234Sgibbs int ha_nbus; /* Number Of Busses on HBA */ 91539234Sgibbs int ha_ntargets; /* Number Of Targets Supported */ 91639234Sgibbs int ha_nluns; /* Number Of LUNs Supported */ 91739234Sgibbs int ha_tshift; /* Shift value for target */ 91839234Sgibbs int ha_bshift; /* Shift value for bus */ 91939234Sgibbs int ha_npend; /* # of jobs sent to HBA */ 92039234Sgibbs int ha_active_jobs; /* Number Of Active Jobs */ 92139234Sgibbs char ha_fw_version[4]; /* Firmware Revision Level */ 92239234Sgibbs void *ha_ccb; /* Controller command blocks */ 92339234Sgibbs void *ha_cblist; /* Command block free list */ 92439234Sgibbs void *ha_dev; /* Logical unit queues */ 92539234Sgibbs void *ha_StPkt_lock; /* Status Packet Lock */ 92639234Sgibbs void *ha_ccb_lock; /* CCB Lock */ 92739234Sgibbs void *ha_LuQWaiting; /* Lu Queue Waiting List */ 92839234Sgibbs void *ha_QWait_lock; /* Device Que Waiting Lock */ 92939234Sgibbs int ha_QWait_opri; /* Saved Priority Level */ 93039234Sgibbs#ifdef DPT_TARGET_MODE 93139234Sgibbs dpt_ccb_t *target_ccb[MAX_CHANNELS]; /* Command block waiting writebuf */ 93239234Sgibbs#endif 93339234Sgibbs} dpt_compat_ha_t; 93439234Sgibbs 93539234Sgibbs/* 93639234Sgibbs * Describe the Inquiry Data returned on Page 0 from the Adapter. The 93739234Sgibbs * Page C1 Inquiry Data is described in the DptConfig_t structure above. 93839234Sgibbs */ 93939234Sgibbstypedef struct { 94039234Sgibbs u_int8_t deviceType; 94139234Sgibbs u_int8_t rm_dtq; 94239234Sgibbs u_int8_t otherData[6]; 94339234Sgibbs u_int8_t vendor[8]; 94439234Sgibbs u_int8_t modelNum[16]; 94539234Sgibbs u_int8_t firmware[4]; 94639234Sgibbs u_int8_t protocol[4]; 94739234Sgibbs} dpt_inq_t; 94839234Sgibbs 94939234Sgibbs/* 95039234Sgibbs * sp_EOC is not `safe', so I will check sp_Messages[0] instead! 95139234Sgibbs */ 95239234Sgibbs#define DptStat_BUSY(x) ((x)->sp_ID_Message) 95339234Sgibbs#define DptStat_Reset_BUSY(x) \ 95439234Sgibbs ((x)->msg[0] = 0xA5, (x)->EOC = 0, \ 95539234Sgibbs (x)->ccb_busaddr = ~0) 95639234Sgibbs 95739234Sgibbs#ifdef DPT_MEASURE_PERFORMANCE 95839234Sgibbs#define BIG_ENOUGH 0x8fffffff 95939234Sgibbstypedef struct dpt_metrics { 96039234Sgibbs u_int32_t command_count[256]; /* We assume MAX 256 SCSI commands */ 96139234Sgibbs u_int32_t max_command_time[256]; 96239234Sgibbs u_int32_t min_command_time[256]; 96339234Sgibbs 96439234Sgibbs u_int32_t min_intr_time; 96539234Sgibbs u_int32_t max_intr_time; 96639234Sgibbs u_int32_t aborted_interrupts; 96739234Sgibbs u_int32_t spurious_interrupts; 96839234Sgibbs 96939234Sgibbs u_int32_t max_waiting_count; 97039234Sgibbs u_int32_t max_submit_count; 97139234Sgibbs u_int32_t max_complete_count; 97239234Sgibbs 97339234Sgibbs u_int32_t min_waiting_time; 97439234Sgibbs u_int32_t min_submit_time; 97539234Sgibbs u_int32_t min_complete_time; 97639234Sgibbs 97739234Sgibbs u_int32_t max_waiting_time; 97839234Sgibbs u_int32_t max_submit_time; 97939234Sgibbs u_int32_t max_complete_time; 98039234Sgibbs 98139234Sgibbs u_int32_t command_collisions; 98239234Sgibbs u_int32_t command_too_busy; 98339234Sgibbs u_int32_t max_eata_tries; 98439234Sgibbs u_int32_t min_eata_tries; 98539234Sgibbs 98639234Sgibbs u_int32_t read_by_size_count[10]; 98739234Sgibbs u_int32_t write_by_size_count[10]; 98839234Sgibbs u_int32_t read_by_size_min_time[10]; 98939234Sgibbs u_int32_t read_by_size_max_time[10]; 99039234Sgibbs u_int32_t write_by_size_min_time[10]; 99139234Sgibbs u_int32_t write_by_size_max_time[10]; 99239234Sgibbs 99339234Sgibbs#define SIZE_512 0 99439234Sgibbs#define SIZE_1K 1 99539234Sgibbs#define SIZE_2K 2 99639234Sgibbs#define SIZE_4K 3 99739234Sgibbs#define SIZE_8K 4 99839234Sgibbs#define SIZE_16K 5 99939234Sgibbs#define SIZE_32K 6 100039234Sgibbs#define SIZE_64K 7 100139234Sgibbs#define SIZE_BIGGER 8 100239234Sgibbs#define SIZE_OTHER 9 100339234Sgibbs 100439234Sgibbs struct timeval intr_started; 100539234Sgibbs 100639234Sgibbs u_int32_t warm_starts; 100739234Sgibbs u_int32_t cold_boots; 100839234Sgibbs} dpt_perf_t; 100939234Sgibbs#endif 101039234Sgibbs 101139234Sgibbsstruct sg_map_node { 101239234Sgibbs bus_dmamap_t sg_dmamap; 101339234Sgibbs bus_addr_t sg_physaddr; 101439234Sgibbs dpt_sg_t* sg_vaddr; 101560938Sjake SLIST_ENTRY(sg_map_node) links; 101639234Sgibbs}; 101739234Sgibbs 101839234Sgibbs/* Main state machine and interface structure */ 101939234Sgibbstypedef struct dpt_softc { 1020170872Sscottl device_t dev; 1021241593Sjhb struct mtx lock; 1022112780Smdodd 1023112780Smdodd struct resource * io_res; 1024112780Smdodd int io_rid; 1025112780Smdodd int io_type; 1026112780Smdodd int io_offset; 1027112780Smdodd 1028112780Smdodd struct resource * irq_res; 1029112780Smdodd int irq_rid; 1030112780Smdodd void * ih; 1031112780Smdodd 1032112780Smdodd struct resource * drq_res; 1033112780Smdodd int drq_rid; 1034112780Smdodd 103539234Sgibbs bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 103639234Sgibbs dpt_ccb_t *dpt_dccbs; /* Array of dpt ccbs */ 103739234Sgibbs bus_addr_t dpt_ccb_busbase; /* phys base address of array */ 103839234Sgibbs bus_addr_t dpt_ccb_busend; /* phys end address of array */ 103939234Sgibbs 104039234Sgibbs u_int32_t handle_interrupts :1, /* Are we ready for real work? */ 104139234Sgibbs target_mode_enabled :1, 104239234Sgibbs resource_shortage :1, 104339234Sgibbs cache_type :2, 104439234Sgibbs spare :28; 104539234Sgibbs 104639234Sgibbs int total_dccbs; 104739234Sgibbs int free_dccbs; 104839234Sgibbs int pending_ccbs; 104939234Sgibbs int completed_ccbs; 105039234Sgibbs 105160938Sjake SLIST_HEAD(, dpt_ccb) free_dccb_list; 105260938Sjake LIST_HEAD(, ccb_hdr) pending_ccb_list; 105339234Sgibbs 105439234Sgibbs bus_dma_tag_t parent_dmat; 105539234Sgibbs bus_dma_tag_t dccb_dmat; /* dmat for our ccb array */ 105639234Sgibbs bus_dmamap_t dccb_dmamap; 105739234Sgibbs bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 105860938Sjake SLIST_HEAD(, sg_map_node) sg_maps; 105939234Sgibbs 106039234Sgibbs struct cam_sim *sims[MAX_CHANNELS]; 106139234Sgibbs struct cam_path *paths[MAX_CHANNELS]; 106239234Sgibbs u_int32_t commands_processed; 106339234Sgibbs u_int32_t lost_interrupts; 106439234Sgibbs 106539234Sgibbs /* 106639234Sgibbs * These three parameters can be used to allow for wide scsi, and 106739234Sgibbs * for host adapters that support multiple busses. The first two 106839234Sgibbs * should be set to 1 more than the actual max id or lun (i.e. 8 for 106939234Sgibbs * normal systems). 107039234Sgibbs * 107139234Sgibbs * There is a FAT assumption here; We assume that these will never 107239234Sgibbs * exceed MAX_CHANNELS, MAX_TARGETS, MAX_LUNS 107339234Sgibbs */ 107439234Sgibbs u_int channels; /* # of avail scsi chan. */ 107539234Sgibbs u_int32_t max_id; 107639234Sgibbs u_int32_t max_lun; 107739234Sgibbs 107839234Sgibbs u_int8_t irq; 107939234Sgibbs u_int8_t dma_channel; 108039234Sgibbs 108160938Sjake TAILQ_ENTRY(dpt_softc) links; 108239234Sgibbs int init_level; 108339234Sgibbs 108439234Sgibbs /* 108539234Sgibbs * Every object on a unit can have a receiver, if it treats 108639234Sgibbs * us as a target. We do that so that separate and independant 108739234Sgibbs * clients can consume received buffers. 108839234Sgibbs */ 108939234Sgibbs 109039234Sgibbs#define DPT_RW_BUFFER_SIZE (8 * 1024) 109139234Sgibbs dpt_ccb_t *target_ccb[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 109239234Sgibbs u_int8_t *rw_buffer[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 109339234Sgibbs dpt_rec_buff buffer_receiver[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 109439234Sgibbs 109539234Sgibbs dpt_inq_t board_data; 109639234Sgibbs u_int8_t EATA_revision; 109739234Sgibbs u_int8_t bustype; /* bustype of HBA */ 109839234Sgibbs u_int32_t state; /* state of HBA */ 109939234Sgibbs 110039234Sgibbs#define DPT_HA_FREE 0x00000000 110139234Sgibbs#define DPT_HA_OK 0x00000000 110239234Sgibbs#define DPT_HA_NO_TIMEOUT 0x00000000 110339234Sgibbs#define DPT_HA_BUSY 0x00000001 110439234Sgibbs#define DPT_HA_TIMEOUT 0x00000002 110539234Sgibbs#define DPT_HA_RESET 0x00000004 110639234Sgibbs#define DPT_HA_LOCKED 0x00000008 110739234Sgibbs#define DPT_HA_ABORTED 0x00000010 110839234Sgibbs#define DPT_HA_CONTROL_ACTIVE 0x00000020 110939234Sgibbs#define DPT_HA_SHUTDOWN_ACTIVE 0x00000040 111039234Sgibbs#define DPT_HA_COMMAND_ACTIVE 0x00000080 111139234Sgibbs#define DPT_HA_QUIET 0x00000100 111239234Sgibbs 111339234Sgibbs u_int8_t primary; /* true if primary */ 111439234Sgibbs 111539234Sgibbs u_int8_t more_support :1, /* HBA supports MORE flag */ 111639234Sgibbs immediate_support :1, /* HBA supports IMMEDIATE */ 111739234Sgibbs broken_INQUIRY :1, /* EISA HBA w/broken INQUIRY */ 111839234Sgibbs spare2 :5; 111939234Sgibbs 112039234Sgibbs u_int8_t resetlevel[MAX_CHANNELS]; 112139234Sgibbs u_int32_t last_ccb; /* Last used ccb */ 112239234Sgibbs u_int32_t cplen; /* size of CP in words */ 112339234Sgibbs u_int16_t cppadlen; /* pad length of cp */ 112439234Sgibbs u_int16_t max_dccbs; 112539234Sgibbs u_int16_t sgsize; /* Entries in the SG list */ 112639234Sgibbs u_int8_t hostid[MAX_CHANNELS]; /* SCSI ID of HBA */ 112739234Sgibbs u_int32_t cache_size; 112839234Sgibbs 112939234Sgibbs volatile dpt_sp_t *sp; /* status packet */ 113039234Sgibbs /* Copied from the status packet during interrupt handler */ 113139234Sgibbs u_int8_t hba_stat; 113239234Sgibbs u_int8_t scsi_stat; /* Target SCSI status */ 113339234Sgibbs u_int32_t residue_len; /* Number of bytes not transferred */ 113439234Sgibbs bus_addr_t sp_physaddr; /* phys address of status packet */ 113539234Sgibbs 113639234Sgibbs /* 113739234Sgibbs * We put ALL conditional elements at the tail for the structure. 113839234Sgibbs * If we do not, then userland code will crash or trash based on which 113939234Sgibbs * kernel it is running with. 114039234Sgibbs * This isi most visible with usr/sbin/dpt_softc(8) 114139234Sgibbs */ 114239234Sgibbs 114339234Sgibbs#ifdef DPT_MEASURE_PERFORMANCE 114439234Sgibbs dpt_perf_t performance; 114539234Sgibbs#endif 114639234Sgibbs 114739234Sgibbs#ifdef DPT_RESET_HBA 114839234Sgibbs struct timeval last_contact; 114939234Sgibbs#endif 115039234Sgibbs} dpt_softc_t; 115139234Sgibbs 115239234Sgibbs/* 115339234Sgibbs * This structure is used to pass dpt_softc contents to userland via the 115439234Sgibbs * ioctl DPT_IOCTL_SOFTC. The reason for this maddness, is that FreeBSD 115539234Sgibbs * (all BSDs ?) chose to actually assign a nasty meaning to the IOCTL word, 115639234Sgibbs * encoding 13 bits of it as size. As dpt_softc_t is somewhere between 115739234Sgibbs * 8,594 and 8,600 (depends on options), we have to copy the data to 115839234Sgibbs * something less than 4KB long. This siliness also solves the problem of 115939234Sgibbs * varying definition of dpt_softc_t, As the variants are exluded from 116039234Sgibbs * dpt_user_softc. 116139234Sgibbs * 116239234Sgibbs * See dpt_softc_t above for enumerations, comments and such. 116339234Sgibbs */ 116439234Sgibbstypedef struct dpt_user_softc { 116539234Sgibbs int unit; 116639234Sgibbs u_int32_t handle_interrupts :1, /* Are we ready for real work? */ 116739234Sgibbs target_mode_enabled :1, 116839234Sgibbs spare :30; 116939234Sgibbs 117039234Sgibbs int total_ccbs_count; 117139234Sgibbs int free_ccbs_count; 117239234Sgibbs int waiting_ccbs_count; 117339234Sgibbs int submitted_ccbs_count; 117439234Sgibbs int completed_ccbs_count; 117539234Sgibbs 117639234Sgibbs u_int32_t queue_status; 117739234Sgibbs u_int32_t free_lock; 117839234Sgibbs u_int32_t waiting_lock; 117939234Sgibbs u_int32_t submitted_lock; 118039234Sgibbs u_int32_t completed_lock; 118139234Sgibbs 118239234Sgibbs u_int32_t commands_processed; 118339234Sgibbs u_int32_t lost_interrupts; 118439234Sgibbs 118539234Sgibbs u_int8_t channels; 118639234Sgibbs u_int32_t max_id; 118739234Sgibbs u_int32_t max_lun; 118839234Sgibbs 118939234Sgibbs u_int16_t io_base; 119039234Sgibbs u_int8_t *v_membase; 119139234Sgibbs u_int8_t *p_membase; 119239234Sgibbs 119339234Sgibbs u_int8_t irq; 119439234Sgibbs u_int8_t dma_channel; 119539234Sgibbs 119639234Sgibbs dpt_inq_t board_data; 119739234Sgibbs u_int8_t EATA_revision; 119839234Sgibbs u_int8_t bustype; 119939234Sgibbs u_int32_t state; 120039234Sgibbs 120139234Sgibbs u_int8_t primary; 120239234Sgibbs u_int8_t more_support :1, 120339234Sgibbs immediate_support :1, 120439234Sgibbs broken_INQUIRY :1, 120539234Sgibbs spare2 :5; 120639234Sgibbs 120739234Sgibbs u_int8_t resetlevel[MAX_CHANNELS]; 120839234Sgibbs u_int32_t last_ccb; 120939234Sgibbs u_int32_t cplen; 121039234Sgibbs u_int16_t cppadlen; 121139234Sgibbs u_int16_t queuesize; 121239234Sgibbs u_int16_t sgsize; 121339234Sgibbs u_int8_t hostid[MAX_CHANNELS]; 121439234Sgibbs u_int32_t cache_type :2, 121539234Sgibbs cache_size :30; 121639234Sgibbs} dpt_user_softc_t; 121739234Sgibbs 121839234Sgibbs/* 121939234Sgibbs * Externals: 122039234Sgibbs * These all come from dpt_scsi.c 122139234Sgibbs * 122239234Sgibbs */ 122355205Speter#ifdef _KERNEL 122439234Sgibbs/* This function gets the current hi-res time and returns it to the caller */ 122539234Sgibbsstatic __inline struct timeval 122639234Sgibbsdpt_time_now(void) 122739234Sgibbs{ 122839234Sgibbs struct timeval now; 122939234Sgibbs 123039234Sgibbs microtime(&now); 123139234Sgibbs return(now); 123239234Sgibbs} 123339234Sgibbs 123439234Sgibbs/* 123539234Sgibbs * Given a minor device number, get its SCSI Unit. 123639234Sgibbs */ 123739234Sgibbsstatic __inline int 123839234Sgibbsdpt_minor2unit(int minor) 123939234Sgibbs{ 124039234Sgibbs return(minor2hba(minor)); 124139234Sgibbs} 124239234Sgibbs 124339234Sgibbsdpt_softc_t *dpt_minor2softc(int minor_no); 124439234Sgibbs 124555205Speter#endif /* _KERNEL */ 124639234Sgibbs 124739234Sgibbs/* 124839234Sgibbs * This function substracts one timval structure from another, 124939234Sgibbs * Returning the result in usec. 125039234Sgibbs * It assumes that less than 4 billion usecs passed form start to end. 125139234Sgibbs * If times are sensless, ~0 is returned. 125239234Sgibbs */ 125339234Sgibbsstatic __inline u_int32_t 125439234Sgibbsdpt_time_delta(struct timeval start, 125539234Sgibbs struct timeval end) 125639234Sgibbs{ 125739234Sgibbs if (start.tv_sec > end.tv_sec) 125839234Sgibbs return(~0); 125939234Sgibbs 126039234Sgibbs if ( (start.tv_sec == end.tv_sec) && (start.tv_usec > end.tv_usec) ) 126139234Sgibbs return(~0); 126239234Sgibbs 126339234Sgibbs return ( (end.tv_sec - start.tv_sec) * 1000000 + 126439234Sgibbs (end.tv_usec - start.tv_usec) ); 126539234Sgibbs} 126639234Sgibbs 1267112780Smdoddextern devclass_t dpt_devclass; 126839234Sgibbs 126959078Smdodd#ifdef _KERNEL 1270112780Smdoddvoid dpt_alloc(device_t); 1271112780Smdoddint dpt_detach(device_t); 1272112780Smdoddint dpt_alloc_resources(device_t); 1273112780Smdoddvoid dpt_release_resources(device_t); 127459078Smdodd#endif 127539234Sgibbsvoid dpt_free(struct dpt_softc *dpt); 127639234Sgibbsint dpt_init(struct dpt_softc *dpt); 127739234Sgibbsint dpt_attach(dpt_softc_t * dpt); 127839234Sgibbsvoid dpt_intr(void *arg); 127939234Sgibbs 1280166091Smarius#ifdef DEV_EISA 128152042Smdodddpt_conf_t * dpt_pio_get_conf(u_int32_t); 1282166091Smarius#endif 128352042Smdodd 128439234Sgibbs#if 0 128539234Sgibbsextern void hex_dump(u_char * data, int length, 128639234Sgibbs char *name, int no); 128739234Sgibbsextern char *i2bin(unsigned int no, int length); 128839234Sgibbsextern char *scsi_cmd_name(u_int8_t cmd); 128939234Sgibbs 129039234Sgibbsextern dpt_conf_t *dpt_get_conf(dpt_softc_t *dpt, u_int8_t page, 129139234Sgibbs u_int8_t target, u_int8_t size, 129239234Sgibbs int extent); 129339234Sgibbs 129439234Sgibbsextern int dpt_setup(dpt_softc_t * dpt, dpt_conf_t * conf); 129539234Sgibbsextern int dpt_attach(dpt_softc_t * dpt); 129639234Sgibbsextern void dpt_shutdown(int howto, dpt_softc_t *dpt); 129739234Sgibbsextern void dpt_detect_cache(dpt_softc_t *dpt); 129839234Sgibbs 129939234Sgibbsextern int dpt_user_cmd(dpt_softc_t *dpt, eata_pt_t *user_cmd, 130039234Sgibbs caddr_t cmdarg, int minor_no); 130139234Sgibbs 130239234Sgibbsextern u_int8_t dpt_blinking_led(dpt_softc_t *dpt); 130339234Sgibbs 130439234Sgibbsextern dpt_rb_t dpt_register_buffer(int unit, u_int8_t channel, u_int8_t target, 130539234Sgibbs u_int8_t lun, u_int8_t mode, 130639234Sgibbs u_int16_t length, u_int16_t offset, 130739234Sgibbs dpt_rec_buff callback, dpt_rb_op_t op); 130839234Sgibbs 130939234Sgibbsextern int dpt_send_buffer(int unit, u_int8_t channel, u_int8_t target, 131039234Sgibbs u_int8_t lun, u_int8_t mode, u_int16_t length, 131139234Sgibbs u_int16_t offset, void *data, 131239234Sgibbs buff_wr_done callback); 131339234Sgibbs 131439234Sgibbs 131539234Sgibbs 131639234Sgibbsvoid dpt_reset_performance(dpt_softc_t *dpt); 131739234Sgibbs#endif 131839234Sgibbs 131939234Sgibbs#endif /* _DPT_H */ 1320