1160814Ssimon/*- 2296465Sdelphij * Copyright (c) 2011 Chelsio Communications, Inc. 3296465Sdelphij * All rights reserved. 4296465Sdelphij * 5160814Ssimon * Redistribution and use in source and binary forms, with or without 6160814Ssimon * modification, are permitted provided that the following conditions 7160814Ssimon * are met: 8160814Ssimon * 1. Redistributions of source code must retain the above copyright 9160814Ssimon * notice, this list of conditions and the following disclaimer. 10160814Ssimon * 2. Redistributions in binary form must reproduce the above copyright 11160814Ssimon * notice, this list of conditions and the following disclaimer in the 12160814Ssimon * documentation and/or other materials provided with the distribution. 13160814Ssimon * 14296465Sdelphij * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15160814Ssimon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16160814Ssimon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17160814Ssimon * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18160814Ssimon * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19160814Ssimon * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20160814Ssimon * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21160814Ssimon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22160814Ssimon * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23160814Ssimon * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24160814Ssimon * SUCH DAMAGE. 25160814Ssimon * 26160814Ssimon * $FreeBSD$ 27160814Ssimon * 28160814Ssimon */ 29160814Ssimon 30160814Ssimon#ifndef __T4_HW_H 31160814Ssimon#define __T4_HW_H 32160814Ssimon 33160814Ssimon#include "osdep.h" 34160814Ssimon 35160814Ssimonenum { 36160814Ssimon NCHAN = 4, /* # of HW channels */ 37160814Ssimon MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 38160814Ssimon EEPROMSIZE = 17408, /* Serial EEPROM physical size */ 39160814Ssimon EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ 40160814Ssimon EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 41160814Ssimon RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 42160814Ssimon TCB_SIZE = 128, /* TCB size */ 43160814Ssimon NMTUS = 16, /* size of MTU table */ 44160814Ssimon NCCTRL_WIN = 32, /* # of congestion control windows */ 45160814Ssimon NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 46160814Ssimon PM_NSTATS = 5, /* # of PM stats */ 47160814Ssimon MBOX_LEN = 64, /* mailbox size in bytes */ 48160814Ssimon NTRACE = 4, /* # of tracing filters */ 49160814Ssimon TRACE_LEN = 112, /* length of trace data and mask */ 50160814Ssimon FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ 51160814Ssimon NWOL_PAT = 8, /* # of WoL patterns */ 52160814Ssimon WOL_PAT_LEN = 128, /* length of WoL patterns */ 53160814Ssimon UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */ 54160814Ssimon UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ 55160814Ssimon UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ 56160814Ssimon UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ 57160814Ssimon}; 58160814Ssimon 59160814Ssimonenum { 60160814Ssimon CIM_NUM_IBQ = 6, /* # of CIM IBQs */ 61160814Ssimon CIM_NUM_OBQ = 6, /* # of CIM OBQs */ 62160814Ssimon CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ 63160814Ssimon CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ 64160814Ssimon CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ 65296465Sdelphij CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ 66296465Sdelphij CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ 67296465Sdelphij CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ 68160814Ssimon TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ 69296465Sdelphij ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ 70296465Sdelphij}; 71296465Sdelphij 72296465Sdelphijenum { 73296465Sdelphij SF_PAGE_SIZE = 256, /* serial flash page size */ 74296465Sdelphij SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 75160814Ssimon}; 76296465Sdelphij 77296465Sdelphij/* SGE context types */ 78296465Sdelphijenum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM }; 79296465Sdelphij 80296465Sdelphijenum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 81160814Ssimon 82296465Sdelphijenum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 83296465Sdelphij 84296465Sdelphijenum { 85296465Sdelphij SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 86296465Sdelphij SGE_CTXT_SIZE = 24, /* size of SGE context */ 87296465Sdelphij SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 88296465Sdelphij SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 89160814Ssimon SGE_MAX_IQ_SIZE = 65520, 90296465Sdelphij}; 91296465Sdelphij 92296465Sdelphijstruct sge_qstat { /* data written to SGE queue status entries */ 93296465Sdelphij volatile __be32 qid; 94296465Sdelphij volatile __be16 cidx; 95296465Sdelphij volatile __be16 pidx; 96160814Ssimon}; 97296465Sdelphij 98296465Sdelphij#define S_QSTAT_PIDX 0 99296465Sdelphij#define M_QSTAT_PIDX 0xffff 100296465Sdelphij#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX) 101296465Sdelphij 102296465Sdelphij#define S_QSTAT_CIDX 16 103160814Ssimon#define M_QSTAT_CIDX 0xffff 104296465Sdelphij#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX) 105296465Sdelphij 106296465Sdelphij/* 107296465Sdelphij * Structure for last 128 bits of response descriptors 108296465Sdelphij */ 109296465Sdelphijstruct rsp_ctrl { 110296465Sdelphij __be32 hdrbuflen_pidx; 111160814Ssimon __be32 pldbuflen_qid; 112296465Sdelphij union { 113296465Sdelphij u8 type_gen; 114296465Sdelphij __be64 last_flit; 115296465Sdelphij } u; 116296465Sdelphij}; 117296465Sdelphij 118160814Ssimon#define S_RSPD_NEWBUF 31 119296465Sdelphij#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF) 120296465Sdelphij#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U) 121296465Sdelphij 122296465Sdelphij#define S_RSPD_LEN 0 123296465Sdelphij#define M_RSPD_LEN 0x7fffffff 124296465Sdelphij#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) 125160814Ssimon#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) 126296465Sdelphij 127296465Sdelphij#define S_RSPD_QID S_RSPD_LEN 128296465Sdelphij#define M_RSPD_QID M_RSPD_LEN 129296465Sdelphij#define V_RSPD_QID(x) V_RSPD_LEN(x) 130296465Sdelphij#define G_RSPD_QID(x) G_RSPD_LEN(x) 131296465Sdelphij 132160814Ssimon#define S_RSPD_GEN 7 133296465Sdelphij#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN) 134296465Sdelphij#define F_RSPD_GEN V_RSPD_GEN(1U) 135296465Sdelphij 136296465Sdelphij#define S_RSPD_QOVFL 6 137296465Sdelphij#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL) 138296465Sdelphij#define F_RSPD_QOVFL V_RSPD_QOVFL(1U) 139160814Ssimon 140296465Sdelphij#define S_RSPD_TYPE 4 141296465Sdelphij#define M_RSPD_TYPE 0x3 142296465Sdelphij#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) 143296465Sdelphij#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE) 144296465Sdelphij 145296465Sdelphij/* Rx queue interrupt deferral fields: counter enable and timer index */ 146160814Ssimon#define S_QINTR_CNT_EN 0 147296465Sdelphij#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN) 148296465Sdelphij#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U) 149296465Sdelphij 150296465Sdelphij#define S_QINTR_TIMER_IDX 1 151296465Sdelphij#define M_QINTR_TIMER_IDX 0x7 152296465Sdelphij#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX) 153296465Sdelphij#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) 154160814Ssimon 155296465Sdelphij/* # of pages a pagepod can hold without needing another pagepod */ 156296465Sdelphij#define PPOD_PAGES 4U 157296465Sdelphij 158296465Sdelphijstruct pagepod { 159296465Sdelphij __be64 vld_tid_pgsz_tag_color; 160296465Sdelphij __be64 len_offset; 161296465Sdelphij __be64 rsvd; 162160814Ssimon __be64 addr[PPOD_PAGES + 1]; 163296465Sdelphij}; 164296465Sdelphij 165296465Sdelphij#define S_PPOD_COLOR 0 166296465Sdelphij#define M_PPOD_COLOR 0x3F 167296465Sdelphij#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR) 168296465Sdelphij 169160814Ssimon#define S_PPOD_TAG 6 170296465Sdelphij#define M_PPOD_TAG 0xFFFFFF 171296465Sdelphij#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG) 172296465Sdelphij#define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG) 173296465Sdelphij 174296465Sdelphij#define S_PPOD_PGSZ 30 175296465Sdelphij#define M_PPOD_PGSZ 0x3 176160814Ssimon#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ) 177296465Sdelphij#define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ) 178296465Sdelphij 179296465Sdelphij#define S_PPOD_TID 32 180296465Sdelphij#define M_PPOD_TID 0xFFFFFF 181296465Sdelphij#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID) 182296465Sdelphij 183160814Ssimon#define S_PPOD_VALID 56 184296465Sdelphij#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID) 185296465Sdelphij#define F_PPOD_VALID V_PPOD_VALID(1ULL) 186296465Sdelphij 187296465Sdelphij#define S_PPOD_LEN 32 188296465Sdelphij#define M_PPOD_LEN 0xFFFFFFFF 189296465Sdelphij#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN) 190160814Ssimon 191296465Sdelphij#define S_PPOD_OFST 0 192296465Sdelphij#define M_PPOD_OFST 0xFFFFFFFF 193296465Sdelphij#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST) 194296465Sdelphij 195296465Sdelphij/* 196296465Sdelphij * Flash layout. 197160814Ssimon */ 198296465Sdelphij#define FLASH_START(start) ((start) * SF_SEC_SIZE) 199296465Sdelphij#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 200296465Sdelphij 201296465Sdelphijenum { 202296465Sdelphij /* 203160814Ssimon * Various Expansion-ROM boot images, etc. 204160814Ssimon */ 205296465Sdelphij FLASH_EXP_ROM_START_SEC = 0, 206296465Sdelphij FLASH_EXP_ROM_NSECS = 6, 207296465Sdelphij FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 208160814Ssimon FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 209296465Sdelphij 210296465Sdelphij /* 211296465Sdelphij * iSCSI Boot Firmware Table (iBFT) and other driver-related 212296465Sdelphij * parameters ... 213296465Sdelphij */ 214160814Ssimon FLASH_IBFT_START_SEC = 6, 215160814Ssimon FLASH_IBFT_NSECS = 1, 216296465Sdelphij FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), 217296465Sdelphij FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), 218296465Sdelphij 219160814Ssimon /* 220160814Ssimon * Boot configuration data. 221296465Sdelphij */ 222296465Sdelphij FLASH_BOOTCFG_START_SEC = 7, 223296465Sdelphij FLASH_BOOTCFG_NSECS = 1, 224160814Ssimon FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), 225296465Sdelphij FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), 226296465Sdelphij 227296465Sdelphij /* 228296465Sdelphij * Location of firmware image in FLASH. 229296465Sdelphij */ 230160814Ssimon FLASH_FW_START_SEC = 8, 231296465Sdelphij FLASH_FW_NSECS = 16, 232296465Sdelphij FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 233296465Sdelphij FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 234296465Sdelphij 235296465Sdelphij /* 236160814Ssimon * Location of bootstrap firmware image in FLASH. 237296465Sdelphij */ 238296465Sdelphij FLASH_FWBOOTSTRAP_START_SEC = 27, 239296465Sdelphij FLASH_FWBOOTSTRAP_NSECS = 1, 240296465Sdelphij FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), 241296465Sdelphij FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), 242160814Ssimon 243296465Sdelphij /* 244296465Sdelphij * iSCSI persistent/crash information. 245296465Sdelphij */ 246296465Sdelphij FLASH_ISCSI_CRASH_START_SEC = 29, 247296465Sdelphij FLASH_ISCSI_CRASH_NSECS = 1, 248160814Ssimon FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), 249296465Sdelphij FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), 250296465Sdelphij 251296465Sdelphij /* 252296465Sdelphij * FCoE persistent/crash information. 253296465Sdelphij */ 254160814Ssimon FLASH_FCOE_CRASH_START_SEC = 30, 255160814Ssimon FLASH_FCOE_CRASH_NSECS = 1, 256296465Sdelphij FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), 257296465Sdelphij FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), 258296465Sdelphij 259160814Ssimon /* 260296465Sdelphij * Location of Firmware Configuration File in FLASH. 261296465Sdelphij */ 262296465Sdelphij FLASH_CFG_START_SEC = 31, 263296465Sdelphij FLASH_CFG_NSECS = 1, 264296465Sdelphij FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 265160814Ssimon FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 266160814Ssimon 267296465Sdelphij /* 268296465Sdelphij * Sectors 32-63 are reserved for FLASH failover. 269296465Sdelphij */ 270160814Ssimon}; 271296465Sdelphij 272296465Sdelphij#undef FLASH_START 273296465Sdelphij#undef FLASH_MAX_SIZE 274296465Sdelphij 275296465Sdelphij#endif /* __T4_HW_H */ 276160814Ssimon