1139749Simp/*- 2123120Simp * Defines for Cronyx-Sigma adapter driver. 3123120Simp * 4123120Simp * Copyright (C) 1994-2001 Cronyx Engineering. 5123120Simp * Author: Serge Vakulenko, <vak@cronyx.ru> 6123120Simp * 7123120Simp * Copyright (C) 1998-2003 Cronyx Engineering. 8123120Simp * Author: Roman Kurakin, <rik@cronyx.ru> 9123120Simp * 10123120Simp * This software is distributed with NO WARRANTIES, not even the implied 11123120Simp * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12123120Simp * 13123120Simp * Authors grant any other persons or organisations permission to use 14123120Simp * or modify this software as long as this message is kept with the software, 15123120Simp * all derivative works or modified versions. 16123120Simp * 17123120Simp * Cronyx Id: cxddk.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $ 18123120Simp * $FreeBSD$ 19123120Simp */ 20123120Simp 21123120Simp#ifndef port_t 22123120Simp# ifdef _M_ALPHA /* port address on Alpha under */ 23123120Simp# define port_t unsigned long /* Windows NT is 32 bit long */ 24123120Simp# else 25123120Simp# define port_t unsigned short /* all other architectures */ 26123120Simp# endif /* have 16-bit port addresses */ 27123120Simp#endif 28123120Simp 29123120Simp#define NBRD 3 /* the max number of installed boards */ 30123120Simp#define NPORT 32 /* the number of i/o ports per board */ 31123120Simp#define DMABUFSZ 1600 32123120Simp 33123120Simp/* 34123120Simp * Asynchronous channel mode ------------------------------------------------- 35123120Simp */ 36123120Simp 37123120Simp/* Parity */ 38123120Simp#define PAR_EVEN 0 /* even parity */ 39123120Simp#define PAR_ODD 1 /* odd parity */ 40123120Simp 41123120Simp/* Parity mode */ 42123120Simp#define PARM_NOPAR 0 /* no parity */ 43123120Simp#define PARM_FORCE 1 /* force parity (odd = force 1, even = 0) */ 44123120Simp#define PARM_NORMAL 2 /* normal parity */ 45123120Simp 46123120Simp/* Flow control transparency mode */ 47123120Simp#define FLOWCC_PASS 0 /* pass flow ctl chars as exceptions */ 48123120Simp#define FLOWCC_NOTPASS 1 /* don't pass flow ctl chars to the host */ 49123120Simp 50123120Simp/* Stop bit length */ 51123120Simp#define STOPB_1 2 /* 1 stop bit */ 52123120Simp#define STOPB_15 3 /* 1.5 stop bits */ 53123120Simp#define STOPB_2 4 /* 2 stop bits */ 54123120Simp 55123120Simp/* Action on break condition */ 56123120Simp#define BRK_INTR 0 /* generate an exception interrupt */ 57123120Simp#define BRK_NULL 1 /* translate to a NULL character */ 58123120Simp#define BRK_RESERVED 2 /* reserved */ 59123120Simp#define BRK_DISCARD 3 /* discard character */ 60123120Simp 61123120Simp/* Parity/framing error actions */ 62123120Simp#define PERR_INTR 0 /* generate an exception interrupt */ 63123120Simp#define PERR_NULL 1 /* translate to a NULL character */ 64123120Simp#define PERR_IGNORE 2 /* ignore error; char passed as good data */ 65123120Simp#define PERR_DISCARD 3 /* discard error character */ 66123120Simp#define PERR_FFNULL 5 /* translate to FF NULL char */ 67123120Simp 68123120Simptypedef struct { /* async channel option register 1 */ 69123120Simp unsigned charlen : 4; /* character length, 5..8 */ 70123120Simp unsigned ignpar : 1; /* ignore parity */ 71123120Simp unsigned parmode : 2; /* parity mode */ 72123120Simp unsigned parity : 1; /* parity */ 73123120Simp} cx_cor1_async_t; 74123120Simp 75123120Simptypedef struct { /* async channel option register 2 */ 76123120Simp unsigned dsrae : 1; /* DSR automatic enable */ 77123120Simp unsigned ctsae : 1; /* CTS automatic enable */ 78123120Simp unsigned rtsao : 1; /* RTS automatic output enable */ 79123120Simp unsigned rlm : 1; /* remote loopback mode enable */ 80123120Simp unsigned zero : 1; 81123120Simp unsigned etc : 1; /* embedded transmitter cmd enable */ 82123120Simp unsigned ixon : 1; /* in-band XON/XOFF enable */ 83123120Simp unsigned ixany : 1; /* XON on any character */ 84123120Simp} cx_cor2_async_t; 85123120Simp 86123120Simptypedef struct { /* async channel option register 3 */ 87123120Simp unsigned stopb : 3; /* stop bit length */ 88123120Simp unsigned zero : 1; 89123120Simp unsigned scde : 1; /* special char detection enable */ 90123120Simp unsigned flowct : 1; /* flow control transparency mode */ 91123120Simp unsigned rngde : 1; /* range detect enable */ 92123120Simp unsigned escde : 1; /* extended spec. char detect enable */ 93123120Simp} cx_cor3_async_t; 94123120Simp 95123120Simptypedef struct { /* async channel option register 6 */ 96123120Simp unsigned parerr : 3; /* parity/framing error actions */ 97123120Simp unsigned brk : 2; /* action on break condition */ 98123120Simp unsigned inlcr : 1; /* translate NL to CR on input */ 99123120Simp unsigned icrnl : 1; /* translate CR to NL on input */ 100123120Simp unsigned igncr : 1; /* discard CR on input */ 101123120Simp} cx_cor6_async_t; 102123120Simp 103123120Simptypedef struct { /* async channel option register 7 */ 104123120Simp unsigned ocrnl : 1; /* translate CR to NL on output */ 105123120Simp unsigned onlcr : 1; /* translate NL to CR on output */ 106123120Simp unsigned zero : 3; 107123120Simp unsigned fcerr : 1; /* process flow ctl err chars enable */ 108123120Simp unsigned lnext : 1; /* LNext option enable */ 109123120Simp unsigned istrip : 1; /* strip 8-bit on input */ 110123120Simp} cx_cor7_async_t; 111123120Simp 112123120Simptypedef struct { /* async channel options */ 113123120Simp cx_cor1_async_t cor1; /* channel option register 1 */ 114123120Simp cx_cor2_async_t cor2; /* channel option register 2 */ 115123120Simp cx_cor3_async_t cor3; /* option register 3 */ 116123120Simp cx_cor6_async_t cor6; /* channel option register 6 */ 117123120Simp cx_cor7_async_t cor7; /* channel option register 7 */ 118123120Simp unsigned char schr1; /* special character register 1 (XON) */ 119123120Simp unsigned char schr2; /* special character register 2 (XOFF) */ 120123120Simp unsigned char schr3; /* special character register 3 */ 121123120Simp unsigned char schr4; /* special character register 4 */ 122123120Simp unsigned char scrl; /* special character range low */ 123123120Simp unsigned char scrh; /* special character range high */ 124123120Simp unsigned char lnxt; /* LNext character */ 125123120Simp} cx_opt_async_t; 126123120Simp 127123120Simp/* 128123120Simp * HDLC channel mode --------------------------------------------------------- 129123120Simp */ 130123120Simp/* Address field length option */ 131123120Simp#define AFLO_1OCT 0 /* address field is 1 octet in length */ 132123120Simp#define AFLO_2OCT 1 /* address field is 2 octet in length */ 133123120Simp 134123120Simp/* Clear detect for X.21 data transfer phase */ 135123120Simp#define CLRDET_DISABLE 0 /* clear detect disabled */ 136123120Simp#define CLRDET_ENABLE 1 /* clear detect enabled */ 137123120Simp 138123120Simp/* Addressing mode */ 139123120Simp#define ADMODE_NOADDR 0 /* no address */ 140123120Simp#define ADMODE_4_1 1 /* 4 * 1 byte */ 141123120Simp#define ADMODE_2_2 2 /* 2 * 2 byte */ 142123120Simp 143123120Simp/* FCS append */ 144123120Simp#define FCS_NOTPASS 0 /* receive CRC is not passed to the host */ 145123120Simp#define FCS_PASS 1 /* receive CRC is passed to the host */ 146123120Simp 147123120Simp/* CRC modes */ 148123120Simp#define CRC_INVERT 0 /* CRC is transmitted inverted (CRC V.41) */ 149123120Simp#define CRC_DONT_INVERT 1 /* CRC is not transmitted inverted (CRC-16) */ 150123120Simp 151123120Simp/* Send sync pattern */ 152123120Simp#define SYNC_00 0 /* send 00h as pad char (NRZI encoding) */ 153123120Simp#define SYNC_AA 1 /* send AAh (Manchester/NRZ encoding) */ 154123120Simp 155123120Simp/* FCS preset */ 156123120Simp#define FCSP_ONES 0 /* FCS is preset to all ones (CRC V.41) */ 157123120Simp#define FCSP_ZEROS 1 /* FCS is preset to all zeros (CRC-16) */ 158123120Simp 159123120Simp/* idle mode */ 160123120Simp#define IDLE_FLAG 0 /* idle in flag */ 161123120Simp#define IDLE_MARK 1 /* idle in mark */ 162123120Simp 163123120Simp/* CRC polynomial select */ 164123120Simp#define POLY_V41 0 /* x^16+x^12+x^5+1 (HDLC, preset to 1) */ 165123120Simp#define POLY_16 1 /* x^16+x^15+x^2+1 (bisync, preset to 0) */ 166123120Simp 167123120Simptypedef struct { /* hdlc channel option register 1 */ 168123120Simp unsigned ifflags : 4; /* number of inter-frame flags sent */ 169123120Simp unsigned admode : 2; /* addressing mode */ 170123120Simp unsigned clrdet : 1; /* clear detect for X.21 data transfer phase */ 171123120Simp unsigned aflo : 1; /* address field length option */ 172123120Simp} cx_cor1_hdlc_t; 173123120Simp 174123120Simptypedef struct { /* hdlc channel option register 2 */ 175123120Simp unsigned dsrae : 1; /* DSR automatic enable */ 176123120Simp unsigned ctsae : 1; /* CTS automatic enable */ 177123120Simp unsigned rtsao : 1; /* RTS automatic output enable */ 178123120Simp unsigned zero1 : 1; 179123120Simp unsigned crcninv : 1; /* CRC invertion option */ 180123120Simp unsigned zero2 : 1; 181123120Simp unsigned fcsapd : 1; /* FCS append */ 182123120Simp unsigned zero3 : 1; 183123120Simp} cx_cor2_hdlc_t; 184123120Simp 185123120Simptypedef struct { /* hdlc channel option register 3 */ 186123120Simp unsigned padcnt : 3; /* pad character count */ 187123120Simp unsigned idle : 1; /* idle mode */ 188123120Simp unsigned nofcs : 1; /* FCS disable */ 189123120Simp unsigned fcspre : 1; /* FCS preset */ 190123120Simp unsigned syncpat : 1; /* send sync pattern */ 191123120Simp unsigned sndpad : 1; /* send pad characters before flag enable */ 192123120Simp} cx_cor3_hdlc_t; 193123120Simp 194123120Simptypedef struct { /* hdlc channel options */ 195123120Simp cx_cor1_hdlc_t cor1; /* hdlc channel option register 1 */ 196123120Simp cx_cor2_hdlc_t cor2; /* hdlc channel option register 2 */ 197123120Simp cx_cor3_hdlc_t cor3; /* hdlc channel option register 3 */ 198123120Simp unsigned char rfar1; /* receive frame address register 1 */ 199123120Simp unsigned char rfar2; /* receive frame address register 2 */ 200123120Simp unsigned char rfar3; /* receive frame address register 3 */ 201123120Simp unsigned char rfar4; /* receive frame address register 4 */ 202123120Simp unsigned char cpsr; /* CRC polynomial select */ 203123120Simp} cx_opt_hdlc_t; 204123120Simp 205123120Simp/* 206123120Simp * CD2400 channel state structure -------------------------------------------- 207123120Simp */ 208123120Simp 209123120Simp/* Signal encoding */ 210123120Simp#define ENCOD_NRZ 0 /* NRZ mode */ 211123120Simp#define ENCOD_NRZI 1 /* NRZI mode */ 212123120Simp#define ENCOD_MANCHESTER 2 /* Manchester mode */ 213123120Simp 214123120Simp/* Clock source */ 215123120Simp#define CLK_0 0 /* clock 0 */ 216123120Simp#define CLK_1 1 /* clock 1 */ 217123120Simp#define CLK_2 2 /* clock 2 */ 218123120Simp#define CLK_3 3 /* clock 3 */ 219123120Simp#define CLK_4 4 /* clock 4 */ 220123120Simp#define CLK_EXT 6 /* external clock */ 221123120Simp#define CLK_RCV 7 /* receive clock */ 222123120Simp 223123120Simp/* Board type */ 224123120Simp#define B_SIGMA_XXX 0 /* old Sigmas */ 225123120Simp#define B_SIGMA_2X 1 /* Sigma-22 */ 226123120Simp#define B_SIGMA_800 2 /* Sigma-800 */ 227123120Simp 228123120Simp/* Channel type */ 229123120Simp#define T_NONE 0 /* no channel */ 230123120Simp#define T_ASYNC 1 /* pure asynchronous RS-232 channel */ 231123120Simp#define T_SYNC_RS232 2 /* pure synchronous RS-232 channel */ 232123120Simp#define T_SYNC_V35 3 /* pure synchronous V.35 channel */ 233123120Simp#define T_SYNC_RS449 4 /* pure synchronous RS-449 channel */ 234123120Simp#define T_UNIV_RS232 5 /* sync/async RS-232 channel */ 235123120Simp#define T_UNIV_RS449 6 /* sync/async RS-232/RS-449 channel */ 236123120Simp#define T_UNIV_V35 7 /* sync/async RS-232/V.35 channel */ 237123120Simp#define T_UNIV 8 /* sync/async, unknown interface */ 238123120Simp 239123120Simp#define M_ASYNC 0 /* asynchronous mode */ 240123120Simp#define M_HDLC 1 /* bit-sync mode (HDLC) */ 241123120Simp 242123120Simptypedef struct { /* channel option register 4 */ 243123120Simp unsigned thr : 4; /* FIFO threshold */ 244123120Simp unsigned zero : 1; 245123120Simp unsigned cts_zd : 1; /* detect 1 to 0 transition on the CTS */ 246123120Simp unsigned cd_zd : 1; /* detect 1 to 0 transition on the CD */ 247123120Simp unsigned dsr_zd : 1; /* detect 1 to 0 transition on the DSR */ 248123120Simp} cx_cor4_t; 249123120Simp 250123120Simptypedef struct { /* channel option register 5 */ 251123120Simp unsigned rx_thr : 4; /* receive flow control FIFO threshold */ 252123120Simp unsigned zero : 1; 253123120Simp unsigned cts_od : 1; /* detect 0 to 1 transition on the CTS */ 254123120Simp unsigned cd_od : 1; /* detect 0 to 1 transition on the CD */ 255123120Simp unsigned dsr_od : 1; /* detect 0 to 1 transition on the DSR */ 256123120Simp} cx_cor5_t; 257123120Simp 258123120Simptypedef struct { /* receive clock option register */ 259123120Simp unsigned clk : 3; /* receive clock source */ 260123120Simp unsigned encod : 2; /* signal encoding NRZ/NRZI/Manchester */ 261123120Simp unsigned dpll : 1; /* DPLL enable */ 262123120Simp unsigned zero : 1; 263123120Simp unsigned tlval : 1; /* transmit line value */ 264123120Simp} cx_rcor_t; 265123120Simp 266123120Simptypedef struct { /* transmit clock option register */ 267123120Simp unsigned zero1 : 1; 268123120Simp unsigned llm : 1; /* local loopback mode */ 269123120Simp unsigned zero2 : 1; 270123120Simp unsigned ext1x : 1; /* external 1x clock mode */ 271123120Simp unsigned zero3 : 1; 272123120Simp unsigned clk : 3; /* transmit clock source */ 273123120Simp} cx_tcor_t; 274123120Simp 275123120Simptypedef struct { 276123120Simp cx_cor4_t cor4; /* channel option register 4 */ 277123120Simp cx_cor5_t cor5; /* channel option register 5 */ 278123120Simp cx_rcor_t rcor; /* receive clock option register */ 279123120Simp cx_tcor_t tcor; /* transmit clock option register */ 280123120Simp} cx_chan_opt_t; 281123120Simp 282123120Simptypedef enum { /* line break mode */ 283123120Simp BRK_IDLE, /* normal line mode */ 284123120Simp BRK_SEND, /* start sending break */ 285123120Simp BRK_STOP, /* stop sending break */ 286123120Simp} cx_break_t; 287123120Simp 288123120Simp#define BUS_NORMAL 0 /* normal bus timing */ 289123120Simp#define BUS_FAST 1 /* fast bus timing (Sigma-22 and -800) */ 290123120Simp#define BUS_FAST2 2 /* fast bus timing (Sigma-800) */ 291123120Simp#define BUS_FAST3 3 /* fast bus timing (Sigma-800) */ 292123120Simp 293123120Simptypedef struct { /* board options */ 294123120Simp unsigned char fast; /* bus master timing (Sigma-22 and -800) */ 295123120Simp} cx_board_opt_t; 296123120Simp 297123120Simp#define NCHIP 4 /* the number of controllers per board */ 298123120Simp#define NCHAN 16 /* the number of channels on the board */ 299123120Simp 300123120Simptypedef struct { 301123120Simp unsigned char tbuffer [2] [DMABUFSZ]; 302123120Simp unsigned char rbuffer [2] [DMABUFSZ]; 303123120Simp} cx_buf_t; 304123120Simp 305123120Simptypedef struct _cx_chan_t { 306123120Simp struct _cx_board_t *board; /* board pointer */ 307123120Simp unsigned char type; /* channel type */ 308123120Simp unsigned char num; /* channel number, 0..15 */ 309123120Simp port_t port; /* base port address */ 310123120Simp unsigned long oscfreq; /* oscillator frequency in Hz */ 311123120Simp unsigned long rxbaud; /* receiver speed */ 312123120Simp unsigned long txbaud; /* transmitter speed */ 313123120Simp unsigned char mode; /* channel mode */ 314123120Simp cx_chan_opt_t opt; /* common channel options */ 315123120Simp cx_opt_async_t aopt; /* async mode options */ 316123120Simp cx_opt_hdlc_t hopt; /* hdlc mode options */ 317123120Simp unsigned char *arbuf; /* receiver A dma buffer */ 318123120Simp unsigned char *brbuf; /* receiver B dma buffer */ 319123120Simp unsigned char *atbuf; /* transmitter A dma buffer */ 320123120Simp unsigned char *btbuf; /* transmitter B dma buffer */ 321123120Simp unsigned long arphys; /* receiver A phys address */ 322123120Simp unsigned long brphys; /* receiver B phys address */ 323123120Simp unsigned long atphys; /* transmitter A phys address */ 324123120Simp unsigned long btphys; /* transmitter B phys address */ 325123120Simp unsigned char dtr; /* DTR signal value */ 326123120Simp unsigned char rts; /* RTS signal value */ 327123120Simp 328123120Simp unsigned long rintr; /* receive interrupts */ 329123120Simp unsigned long tintr; /* transmit interrupts */ 330123120Simp unsigned long mintr; /* modem interrupts */ 331123120Simp unsigned long ibytes; /* input bytes */ 332123120Simp unsigned long ipkts; /* input packets */ 333123120Simp unsigned long ierrs; /* input errors */ 334123120Simp unsigned long obytes; /* output bytes */ 335123120Simp unsigned long opkts; /* output packets */ 336123120Simp unsigned long oerrs; /* output errors */ 337123120Simp 338123120Simp void *sys; 339123120Simp int debug; 340180132Srik int debug_shadow; 341123120Simp void *attach [2]; 342123120Simp char *received_data; 343123120Simp int received_len; 344123120Simp int overflow; 345123120Simp 346123120Simp void (*call_on_rx) (struct _cx_chan_t*, char*, int); 347123120Simp void (*call_on_tx) (struct _cx_chan_t*, void*, int); 348123120Simp void (*call_on_msig) (struct _cx_chan_t*); 349123120Simp void (*call_on_err) (struct _cx_chan_t*, int); 350123120Simp 351123120Simp} cx_chan_t; 352123120Simp 353123120Simptypedef struct _cx_board_t { 354123120Simp unsigned char type; /* board type */ 355123120Simp unsigned char num; /* board number, 0..2 */ 356123120Simp port_t port; /* base board port, 0..3f0 */ 357123120Simp unsigned char irq; /* irq {3 5 7 10 11 12 15} */ 358123120Simp unsigned char dma; /* DMA request {5 6 7} */ 359123120Simp char name[16]; /* board version name */ 360123120Simp unsigned char nuniv; /* number of universal channels */ 361123120Simp unsigned char nsync; /* number of sync. channels */ 362123120Simp unsigned char nasync; /* number of async. channels */ 363123120Simp unsigned char if0type; /* chan0 interface RS-232/RS-449/V.35 */ 364123120Simp unsigned char if8type; /* chan8 interface RS-232/RS-449/V.35 */ 365123120Simp unsigned short bcr0; /* BCR0 image */ 366123120Simp unsigned short bcr0b; /* BCR0b image */ 367123120Simp unsigned short bcr1; /* BCR1 image */ 368123120Simp unsigned short bcr1b; /* BCR1b image */ 369123120Simp cx_board_opt_t opt; /* board options */ 370123120Simp cx_chan_t chan[NCHAN]; /* channel structures */ 371123120Simp void *sys; 372123120Simp} cx_board_t; 373123120Simp 374123120Simpextern long cx_rxbaud, cx_txbaud; 375123120Simpextern int cx_univ_mode, cx_sync_mode, cx_iftype; 376123120Simp 377123120Simpextern cx_chan_opt_t chan_opt_dflt; /* default mode-independent options */ 378123120Simpextern cx_opt_async_t opt_async_dflt; /* default async options */ 379123120Simpextern cx_opt_hdlc_t opt_hdlc_dflt; /* default hdlc options */ 380123120Simpextern cx_board_opt_t board_opt_dflt; /* default board options */ 381123120Simp 382123120Simpstruct _cr_dat_tst; 383123120Simpint cx_probe_board (port_t port, int irq, int dma); 384123120Simpvoid cx_init (cx_board_t *b, int num, port_t port, int irq, int dma); 385123120Simpvoid cx_init_board (cx_board_t *b, int num, port_t port, int irq, int dma, 386123120Simp int chain, int rev, int osc, int mod, int rev2, int osc2, int mod2); 387123120Simpvoid cx_init_2x (cx_board_t *b, int num, port_t port, int irq, int dma, 388123120Simp int rev, int osc); 389123120Simpvoid cx_init_800 (cx_board_t *b, int num, port_t port, int irq, int dma, 390123120Simp int chain); 391123120Simpint cx_download (port_t port, const unsigned char *firmware, long bits, 392123120Simp const struct _cr_dat_tst *tst); 393123120Simpint cx_setup_board (cx_board_t *b, const unsigned char *firmware, 394123120Simp long bits, const struct _cr_dat_tst *tst); 395123120Simpvoid cx_setup_chan (cx_chan_t *c); 396123120Simpvoid cx_update_chan (cx_chan_t *c); 397123120Simpvoid cx_set_dtr (cx_chan_t *c, int on); 398123120Simpvoid cx_set_rts (cx_chan_t *c, int on); 399123120Simpvoid cx_led (cx_board_t *b, int on); 400123120Simpvoid cx_cmd (port_t base, int cmd); 401123120Simpvoid cx_disable_dma (cx_board_t *b); 402123120Simpvoid cx_reinit_board (cx_board_t *b); 403123120Simpint cx_get_dsr (cx_chan_t *c); 404123120Simpint cx_get_cts (cx_chan_t *c); 405123120Simpint cx_get_cd (cx_chan_t *c); 406123120Simpvoid cx_clock (long hz, long ba, int *clk, int *div); 407123120Simp 408123120Simp/* DDK errors */ 409123120Simp#define CX_FRAME 1 410123120Simp#define CX_CRC 2 411123120Simp#define CX_OVERRUN 3 412123120Simp#define CX_OVERFLOW 4 413123120Simp#define CX_UNDERRUN 5 414123120Simp#define CX_BREAK 6 415123120Simp 416123120Simp/* clock sources */ 417123120Simp#define CX_CLK_INT 0 418123120Simp#define CX_CLK_EXT 6 419123120Simp#define CX_CLK_RCV 7 420123120Simp#define CX_CLK_DPLL 8 421123120Simp#define CX_CLK_DPLL_EXT 14 422123120Simp 423123120Simp/* functions dealing with interrupt vector in DOS */ 424123120Simp#if defined (MSDOS) || defined (__MSDOS__) 425123120Simpint ddk_int_alloc (int irq, void (*func)(), void *arg); 426123120Simpint ddk_int_restore (int irq); 427123120Simp#endif 428123120Simp 429123120Simpint cx_probe_irq (cx_board_t *b, int irq); 430123120Simpvoid cx_int_handler (cx_board_t *b); 431123120Simp 432123120Simpint cx_find (port_t *board_ports); 433123120Simpint cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma); 434123120Simpvoid cx_close_board (cx_board_t *b); 435123120Simp 436123120Simpvoid cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys); 437123120Simp 438123120Simp/* 439123120Simp Set port type for old models of Sigma 440123120Simp */ 441123120Simpvoid cx_set_port (cx_chan_t *c, int iftype); 442123120Simp 443123120Simp/* 444123120Simp Get port type for old models of Sigma 445123120Simp -1 Fixed port type or auto detect 446123120Simp 0 RS232 447123120Simp 1 V35 448123120Simp 2 RS449 449123120Simp */ 450123120Simpint cx_get_port (cx_chan_t *c); 451123120Simp 452123120Simpvoid cx_enable_receive (cx_chan_t *c, int on); 453123120Simpvoid cx_enable_transmit (cx_chan_t *c, int on); 454123120Simpint cx_receive_enabled (cx_chan_t *c); 455123120Simpint cx_transmit_enabled (cx_chan_t *c); 456123120Simp 457123120Simpvoid cx_set_baud (cx_chan_t *, unsigned long baud); 458123120Simpint cx_set_mode (cx_chan_t *c, int mode); 459123120Simpvoid cx_set_loop (cx_chan_t *c, int on); 460123120Simpvoid cx_set_nrzi (cx_chan_t *c, int nrzi); 461123120Simpvoid cx_set_dpll (cx_chan_t *c, int on); 462123120Simp 463123120Simpunsigned long cx_get_baud (cx_chan_t *c); 464123120Simpint cx_get_loop (cx_chan_t *c); 465123120Simpint cx_get_nrzi (cx_chan_t *c); 466123120Simpint cx_get_dpll (cx_chan_t *c); 467123120Simp 468123120Simpint cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment); 469123120Simpint cx_buf_free (cx_chan_t *c); 470123120Simp 471123120Simpvoid cx_register_transmit (cx_chan_t *c, 472123120Simp void (*func) (cx_chan_t *c, void *attachment, int len)); 473123120Simpvoid cx_register_receive (cx_chan_t *c, 474123120Simp void (*func) (cx_chan_t *c, char *data, int len)); 475123120Simpvoid cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c)); 476123120Simpvoid cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data)); 477123120Simpvoid cx_intr_off (cx_board_t *b); 478123120Simpvoid cx_intr_on (cx_board_t *b); 479123120Simpint cx_checkintr (cx_board_t *b); 480123120Simp 481123120Simp/* Async functions */ 482123120Simpvoid cx_transmitter_ctl (cx_chan_t *c, int start); 483123120Simpvoid cx_flush_transmit (cx_chan_t *c); 484123120Simpvoid cx_xflow_ctl (cx_chan_t *c, int on); 485123120Simpvoid cx_send_break (cx_chan_t *c, int msec); 486123120Simpvoid cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity, 487123120Simp int stop2, int ignpar, int rtscts, 488123120Simp int ixon, int ixany, int symstart, int symstop); 489