1139749Simp/*- 239223Sgibbs * Generic register and struct definitions for the BusLogic 339223Sgibbs * MultiMaster SCSI host adapters. Product specific probe and 439223Sgibbs * attach routines can be found in: 552052Smdodd * sys/dev/buslogic/bt_isa.c BT-54X, BT-445 cards 652052Smdodd * sys/dev/buslogic/bt_mca.c BT-64X, SDC3211B, SDC3211F 752052Smdodd * sys/dev/buslogic/bt_eisa.c BT-74X, BT-75x cards, SDC3222F 852052Smdodd * sys/dev/buslogic/bt_pci.c BT-946, BT-948, BT-956, BT-958 cards 939223Sgibbs * 1044581Sgibbs * Copyright (c) 1998, 1999 Justin T. Gibbs. 1139223Sgibbs * All rights reserved. 1239223Sgibbs * 1339223Sgibbs * Redistribution and use in source and binary forms, with or without 1439223Sgibbs * modification, are permitted provided that the following conditions 1539223Sgibbs * are met: 1639223Sgibbs * 1. Redistributions of source code must retain the above copyright 1739223Sgibbs * notice, this list of conditions, and the following disclaimer, 1839223Sgibbs * without modification, immediately at the beginning of the file. 1939223Sgibbs * 2. The name of the author may not be used to endorse or promote products 2039223Sgibbs * derived from this software without specific prior written permission. 2139223Sgibbs * 2239223Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2339223Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2439223Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2539223Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2639223Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2739223Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2839223Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2939223Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3039223Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3139223Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3239223Sgibbs * SUCH DAMAGE. 3339223Sgibbs * 3450477Speter * $FreeBSD$ 3539223Sgibbs */ 3639223Sgibbs 3739223Sgibbs#ifndef _BTREG_H_ 3839223Sgibbs#define _BTREG_H_ 3939223Sgibbs 4039223Sgibbs#include <sys/queue.h> 4139223Sgibbs 4239223Sgibbs#define BT_MAXTRANSFER_SIZE 0xffffffff /* limited by 32bit counter */ 4339223Sgibbs#define BT_NSEG 32 /* The number of dma segments supported. 4439223Sgibbs * BT_NSEG can be maxed out at 8192 entries, 4539223Sgibbs * but the kernel will never need to transfer 4639223Sgibbs * such a large request. To reduce the 4739223Sgibbs * driver's memory consumption, we reduce the 4839223Sgibbs * max to 32. 16 would work if all transfers 4939223Sgibbs * are paged alined since the kernel will only 5039223Sgibbs * generate at most a 64k transfer, but to 5139223Sgibbs * handle non-page aligned transfers, you need 5239223Sgibbs * 17, so we round to the next power of two 5339223Sgibbs * to make allocating SG space easy and 5439223Sgibbs * efficient. 5539223Sgibbs */ 5639223Sgibbs 5739223Sgibbs#define ALL_TARGETS (~0) 5839223Sgibbs 5939223Sgibbs/* 6039223Sgibbs * Control Register pp. 1-8, 1-9 (Write Only) 6139223Sgibbs */ 6239223Sgibbs#define CONTROL_REG 0x00 6339223Sgibbs#define HARD_RESET 0x80 /* Hard Reset - return to POST state */ 6439223Sgibbs#define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */ 6539223Sgibbs#define RESET_INTR 0x20 /* Reset/Ack Interrupt */ 6639223Sgibbs#define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */ 6739223Sgibbs 6839223Sgibbs/* 6939223Sgibbs * Status Register pp. 1-9, 1-10 (Read Only) 7039223Sgibbs */ 7139223Sgibbs#define STATUS_REG 0x00 7239223Sgibbs#define DIAG_ACTIVE 0x80 /* Performing Internal Diags */ 7339223Sgibbs#define DIAG_FAIL 0x40 /* Internal Diags failed */ 7439223Sgibbs#define INIT_REQUIRED 0x20 /* MBOXes need initialization */ 7539223Sgibbs#define HA_READY 0x10 /* HA ready for new commands */ 7639223Sgibbs#define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */ 7739223Sgibbs#define DATAIN_REG_READY 0x04 /* Data-in Byte available */ 7839223Sgibbs#define STATUS_REG_RSVD 0x02 7939223Sgibbs#define CMD_INVALID 0x01 /* Invalid Command detected */ 8039223Sgibbs 8139223Sgibbs/* 8239223Sgibbs * Command/Parameter Register pp. 1-10, 1-11 (Write Only) 8339223Sgibbs */ 8439223Sgibbs#define COMMAND_REG 0x01 8539223Sgibbs 8639223Sgibbs/* 8739223Sgibbs * Data in Register p. 1-11 (Read Only) 8839223Sgibbs */ 8939223Sgibbs#define DATAIN_REG 0x01 9039223Sgibbs 9139223Sgibbs/* 9239223Sgibbs * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only) 9339223Sgibbs */ 9439223Sgibbs#define INTSTAT_REG 0x02 9539223Sgibbs#define INTR_PENDING 0x80 /* There is a pending INTR */ 9639223Sgibbs#define INTSTAT_REG_RSVD 0x70 9739223Sgibbs#define SCSI_BUS_RESET 0x08 /* Bus Reset detected */ 9839223Sgibbs#define CMD_COMPLETE 0x04 9939223Sgibbs#define OMB_READY 0x02 /* Outgoin Mailbox Ready */ 10039223Sgibbs#define IMB_LOADED 0x01 /* Incoming Mailbox loaded */ 10139223Sgibbs 10239223Sgibbs/* 10339223Sgibbs * Definitions for the "undocumented" geometry register 10439223Sgibbs */ 10539223Sgibbstypedef enum { 10639223Sgibbs GEOM_NODISK, 10739223Sgibbs GEOM_64x32, 10839223Sgibbs GEOM_128x32, 10939223Sgibbs GEOM_255x32 11039223Sgibbs} disk_geom_t; 11139223Sgibbs 11239223Sgibbs#define GEOMETRY_REG 0x03 11339223Sgibbs#define DISK0_GEOMETRY 0x03 11439223Sgibbs#define DISK1_GEOMETRY 0x0c 11582365Speter#define EXTENDED_TRANSLATION 0x80 11639223Sgibbs#define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY) 11739223Sgibbs#define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2) 11839223Sgibbs 11939223Sgibbs#define BT_NREGS (4) 12039223Sgibbs/* 12139223Sgibbs * Opcodes for Adapter commands. 12239223Sgibbs * pp 1-18 -> 1-20 12339223Sgibbs */ 12439223Sgibbstypedef enum { 12539223Sgibbs BOP_TEST_CMDC_INTR = 0x00, 12639223Sgibbs BOP_INITIALIZE_24BMBOX = 0x01, 12739223Sgibbs BOP_START_MBOX = 0x02, 12839223Sgibbs BOP_EXECUTE_BIOS_CMD = 0x03, 12939223Sgibbs BOP_INQUIRE_BOARD_ID = 0x04, 13039223Sgibbs BOP_ENABLE_OMBR_INT = 0x05, 13139223Sgibbs BOP_SET_SEL_TIMOUT = 0x06, 13239223Sgibbs BOP_SET_TIME_ON_BUS = 0x07, 13339223Sgibbs BOP_SET_TIME_OFF_BUS = 0x08, 13439223Sgibbs BOP_SET_BUS_TRANS_RATE = 0x09, 13539223Sgibbs BOP_INQUIRE_INST_LDEVS = 0x0A, 13639223Sgibbs BOP_INQUIRE_CONFIG = 0x0B, 13739223Sgibbs BOP_ENABLE_TARGET_MODE = 0x0C, 13839223Sgibbs BOP_INQUIRE_SETUP_INFO = 0x0D, 13939223Sgibbs BOP_WRITE_LRAM = 0x1A, 14039223Sgibbs BOP_READ_LRAM = 0x1B, 14139223Sgibbs BOP_WRITE_CHIP_FIFO = 0x1C, 14239223Sgibbs BOP_READ_CHIP_FIFO = 0x1C, 14339223Sgibbs BOP_ECHO_DATA_BYTE = 0x1F, 14439223Sgibbs BOP_ADAPTER_DIAGNOSTICS = 0x20, 14539223Sgibbs BOP_SET_ADAPTER_OPTIONS = 0x21, 14639223Sgibbs BOP_INQUIRE_INST_HDEVS = 0x23, 14739223Sgibbs BOP_INQUIRE_TARG_DEVS = 0x24, 14839223Sgibbs BOP_DISABLE_HAC_INTR = 0x25, 14939223Sgibbs BOP_INITIALIZE_32BMBOX = 0x81, 15039223Sgibbs BOP_EXECUTE_SCSI_CMD = 0x83, 15139223Sgibbs BOP_INQUIRE_FW_VER_3DIG = 0x84, 15239223Sgibbs BOP_INQUIRE_FW_VER_4DIG = 0x85, 15339223Sgibbs BOP_INQUIRE_PCI_INFO = 0x86, 15439223Sgibbs BOP_INQUIRE_MODEL = 0x8B, 15539223Sgibbs BOP_TARG_SYNC_INFO = 0x8C, 15639223Sgibbs BOP_INQUIRE_ESETUP_INFO = 0x8D, 15739223Sgibbs BOP_ENABLE_STRICT_RR = 0x8F, 15839223Sgibbs BOP_STORE_LRAM = 0x90, 15939223Sgibbs BOP_FETCH_LRAM = 0x91, 16039223Sgibbs BOP_SAVE_TO_EEPROM = 0x92, 16139223Sgibbs BOP_UPLOAD_AUTO_SCSI = 0x94, 16239223Sgibbs BOP_MODIFY_IO_ADDR = 0x95, 16339223Sgibbs BOP_SET_CCB_FORMAT = 0x96, 16439223Sgibbs BOP_FLASH_ROM_DOWNLOAD = 0x97, 16539223Sgibbs BOP_FLASH_WRITE_ENABLE = 0x98, 16639223Sgibbs BOP_WRITE_INQ_BUFFER = 0x9A, 16739223Sgibbs BOP_READ_INQ_BUFFER = 0x9B, 16839223Sgibbs BOP_FLASH_UP_DOWNLOAD = 0xA7, 16939223Sgibbs BOP_READ_SCAM_DATA = 0xA8, 17039223Sgibbs BOP_WRITE_SCAM_DATA = 0xA9 17139223Sgibbs} bt_op_t; 17239223Sgibbs 17339223Sgibbs/************** Definitions of Multi-byte commands and responses ************/ 17439223Sgibbs 17539223Sgibbstypedef struct { 17639223Sgibbs u_int8_t num_mboxes; 17739223Sgibbs u_int8_t base_addr[3]; 17839223Sgibbs} init_24b_mbox_params_t; 17939223Sgibbs 18039223Sgibbstypedef struct { 18139223Sgibbs u_int8_t board_type; 18239223Sgibbs#define BOARD_TYPE_NON_MCA 0x41 18339223Sgibbs#define BOARD_TYPE_MCA 0x42 18439223Sgibbs u_int8_t cust_features; 18539223Sgibbs#define FEATURES_STANDARD 0x41 18639223Sgibbs u_int8_t firmware_rev_major; 18739223Sgibbs u_int8_t firmware_rev_minor; 18839223Sgibbs} board_id_data_t; 18939223Sgibbs 19039223Sgibbstypedef struct { 19139223Sgibbs u_int8_t enable; 19239223Sgibbs} enable_ombr_intr_params_t; 19339223Sgibbs 19439223Sgibbstypedef struct { 19539223Sgibbs u_int8_t enable; 19639223Sgibbs u_int8_t reserved; 19739223Sgibbs u_int8_t timeout[2]; /* timeout in milliseconds */ 19839223Sgibbs} set_selto_parmas_t; 19939223Sgibbs 20039223Sgibbstypedef struct { 20139223Sgibbs u_int8_t time; /* time in milliseconds (2-15) */ 20239223Sgibbs} set_timeon_bus_params_t; 20339223Sgibbs 20439223Sgibbstypedef struct { 20539223Sgibbs u_int8_t time; /* time in milliseconds (2-15) */ 20639223Sgibbs} set_timeoff_bus_params_t; 20739223Sgibbs 20839223Sgibbstypedef struct { 20939223Sgibbs u_int8_t rate; 21039223Sgibbs} set_bus_trasfer_rate_params_t; 21139223Sgibbs 21239223Sgibbstypedef struct { 21339223Sgibbs u_int8_t targets[8]; 21439223Sgibbs} installed_ldevs_data_t; 21539223Sgibbs 21639223Sgibbstypedef struct { 21739223Sgibbs u_int8_t dma_chan; 21839223Sgibbs#define DMA_CHAN_5 0x20 21939223Sgibbs#define DMA_CHAN_6 0x40 22039223Sgibbs#define DMA_CHAN_7 0x80 22139223Sgibbs u_int8_t irq; 22239223Sgibbs#define IRQ_9 0x01 22339223Sgibbs#define IRQ_10 0x02 22439223Sgibbs#define IRQ_11 0x04 22539223Sgibbs#define IRQ_12 0x08 22639223Sgibbs#define IRQ_14 0x20 22739223Sgibbs#define IRQ_15 0x40 22839223Sgibbs u_int8_t scsi_id; 22939223Sgibbs} config_data_t; 23039223Sgibbs 23139223Sgibbstypedef struct { 23239223Sgibbs u_int8_t enable; 23339223Sgibbs} target_mode_params_t; 23439223Sgibbs 23539223Sgibbstypedef struct { 23639223Sgibbs u_int8_t offset : 4, 23739223Sgibbs period : 3, 23839223Sgibbs sync : 1; 23939223Sgibbs} targ_syncinfo_t; 24039223Sgibbs 24139223Sgibbstypedef enum { 24239223Sgibbs HAB_ISA = 'A', 24339223Sgibbs HAB_MCA = 'B', 24439223Sgibbs HAB_EISA = 'C', 24539223Sgibbs HAB_NUBUS = 'D', 24639223Sgibbs HAB_VESA = 'E', 24739223Sgibbs HAB_PCI = 'F' 24839223Sgibbs} ha_type_t; 24939223Sgibbs 25039223Sgibbstypedef struct { 25139223Sgibbs u_int8_t initiate_sync : 1, 25239223Sgibbs parity_enable : 1, 25339223Sgibbs : 6; 25439223Sgibbs 25539223Sgibbs u_int8_t bus_transfer_rate; 25639223Sgibbs u_int8_t time_on_bus; 25739223Sgibbs u_int8_t time_off_bus; 25839223Sgibbs u_int8_t num_mboxes; 25939223Sgibbs u_int8_t mbox_base_addr[3]; 26039223Sgibbs targ_syncinfo_t low_syncinfo[8]; /* For fast and ultra, use 8C */ 26139223Sgibbs u_int8_t low_discinfo; 26239223Sgibbs u_int8_t customer_sig; 26339223Sgibbs u_int8_t letter_d; 26439223Sgibbs u_int8_t ha_type; 26539223Sgibbs u_int8_t low_wide_allowed; 26639223Sgibbs u_int8_t low_wide_active; 26739223Sgibbs targ_syncinfo_t high_syncinfo[8]; 26839223Sgibbs u_int8_t high_discinfo; 26939223Sgibbs u_int8_t high_wide_allowed; 27039223Sgibbs u_int8_t high_wide_active; 27139223Sgibbs} setup_data_t; 27239223Sgibbs 27339223Sgibbstypedef struct { 27439223Sgibbs u_int8_t phys_addr[3]; 27539223Sgibbs} write_adapter_lram_params_t; 27639223Sgibbs 27739223Sgibbstypedef struct { 27839223Sgibbs u_int8_t phys_addr[3]; 27939223Sgibbs} read_adapter_lram_params_t; 28039223Sgibbs 28139223Sgibbstypedef struct { 28239223Sgibbs u_int8_t phys_addr[3]; 28339223Sgibbs} write_chip_fifo_params_t; 28439223Sgibbs 28539223Sgibbstypedef struct { 28639223Sgibbs u_int8_t phys_addr[3]; 28739223Sgibbs} read_chip_fifo_params_t; 28839223Sgibbs 28939223Sgibbstypedef struct { 29039223Sgibbs u_int8_t length; /* Excludes this member */ 29139223Sgibbs u_int8_t low_disc_disable; 29239223Sgibbs u_int8_t low_busy_retry_disable; 29339223Sgibbs u_int8_t high_disc_disable; 29439223Sgibbs u_int8_t high_busy_retry_disable; 29539223Sgibbs} set_adapter_options_params_t; 29639223Sgibbs 29739223Sgibbstypedef struct { 29839223Sgibbs u_int8_t targets[8]; 29939223Sgibbs} installed_hdevs_data_t; 30039223Sgibbs 30139223Sgibbstypedef struct { 30239223Sgibbs u_int8_t low_devs; 30339223Sgibbs u_int8_t high_devs; 30439223Sgibbs} target_devs_data_t; 30539223Sgibbs 30639223Sgibbstypedef struct { 30739223Sgibbs u_int8_t enable; 30839223Sgibbs} enable_hac_interrupt_params_t; 30939223Sgibbs 31039223Sgibbstypedef struct { 31139223Sgibbs u_int8_t num_boxes; 31239223Sgibbs u_int8_t base_addr[4]; 31339223Sgibbs} init_32b_mbox_params_t; 31439223Sgibbs 31539223Sgibbstypedef u_int8_t fw_ver_3dig_data_t; 31639223Sgibbs 31739223Sgibbstypedef u_int8_t fw_ver_4dig_data_t; 31839223Sgibbs 31939223Sgibbstypedef struct { 32039223Sgibbs u_int8_t offset; 32139223Sgibbs u_int8_t response_len; 32239223Sgibbs} fetch_lram_params_t; 32339223Sgibbs 32439223Sgibbs#define AUTO_SCSI_BYTE_OFFSET 64 32539223Sgibbstypedef struct { 32639223Sgibbs u_int8_t factory_sig[2]; 32739223Sgibbs u_int8_t auto_scsi_data_size; /* 2 -> 64 bytes */ 32839223Sgibbs u_int8_t model_num[6]; 32939223Sgibbs u_int8_t adapter_ioport; 33039223Sgibbs u_int8_t floppy_enabled :1, 33139223Sgibbs floppy_secondary :1, 33239223Sgibbs level_trigger :1, 33339223Sgibbs :2, 33439223Sgibbs system_ram_area :3; 33539223Sgibbs u_int8_t dma_channel :7, 33639223Sgibbs dma_autoconf :1; 33739223Sgibbs u_int8_t irq_channel :7, 33839223Sgibbs irq_autoconf :1; 33939223Sgibbs u_int8_t dma_trans_rate; 34039223Sgibbs u_int8_t scsi_id; 34139223Sgibbs u_int8_t low_termination :1, 34239223Sgibbs scsi_parity :1, 34339223Sgibbs high_termination :1, 34439223Sgibbs req_ack_filter :1, 34539223Sgibbs fast_sync :1, 34639223Sgibbs bus_reset :1, 34739223Sgibbs :1, 34839223Sgibbs active_negation :1; 34939223Sgibbs u_int8_t bus_on_delay; 35039223Sgibbs u_int8_t bus_off_delay; 35139223Sgibbs u_int8_t bios_enabled :1, 35239223Sgibbs int19h_redirect :1, 35339223Sgibbs extended_trans :1, 35439223Sgibbs removable_drives :1, 35539223Sgibbs :1, 35639223Sgibbs morethan2disks :1, 35739223Sgibbs interrupt_mode :1, 35839223Sgibbs floptical_support:1; 35939223Sgibbs u_int8_t low_device_enabled; 36039223Sgibbs u_int8_t high_device_enabled; 36139223Sgibbs u_int8_t low_wide_permitted; 36239223Sgibbs u_int8_t high_wide_permitted; 36339223Sgibbs u_int8_t low_fast_permitted; 36439223Sgibbs u_int8_t high_fast_permitted; 36539223Sgibbs u_int8_t low_sync_permitted; 36639223Sgibbs u_int8_t high_sync_permitted; 36739223Sgibbs u_int8_t low_disc_permitted; 36839223Sgibbs u_int8_t high_disc_permitted; 36939223Sgibbs u_int8_t low_send_start_unit; 37039223Sgibbs u_int8_t high_send_start_unit; 37139223Sgibbs u_int8_t low_ignore_in_bios_scan; 37239223Sgibbs u_int8_t high_ignore_in_bios_scan; 37339223Sgibbs u_int8_t pci_int_pin :2, 37439223Sgibbs host_ioport :2, 37539223Sgibbs round_robin :1, 37639223Sgibbs vesa_bus_over_33 :1, 37739223Sgibbs vesa_burst_write :1, 37839223Sgibbs vesa_burst_read :1; 37939223Sgibbs u_int8_t low_ultra_permitted; 38039223Sgibbs u_int8_t high_ultra_permitted; 38139223Sgibbs u_int8_t reserved[5]; 38239223Sgibbs u_int8_t auto_scsi_max_lun; 38339223Sgibbs u_int8_t :1, 38439223Sgibbs scam_dominant :1, 38539223Sgibbs scam_enabled :1, 38639223Sgibbs scam_level2 :1, 38739223Sgibbs :4; 38839223Sgibbs u_int8_t int13_extensions :1, 38939223Sgibbs :1, 39039223Sgibbs cdrom_boot :1, 39139223Sgibbs :2, 39239223Sgibbs multi_boot :1, 39339223Sgibbs :2; 39439223Sgibbs u_int8_t boot_target_id :4, 39539223Sgibbs boot_channel :4; 39639223Sgibbs u_int8_t force_dev_scan :1, 39739223Sgibbs :7; 39839223Sgibbs u_int8_t low_tagged_lun_independance; 39939223Sgibbs u_int8_t high_tagged_lun_independance; 40039223Sgibbs u_int8_t low_renegotiate_after_cc; 40139223Sgibbs u_int8_t high_renegotiate_after_cc; 40239223Sgibbs u_int8_t reserverd2[10]; 40339223Sgibbs u_int8_t manufacturing_diagnotic[2]; 40439223Sgibbs u_int8_t checksum[2]; 40539223Sgibbs} auto_scsi_data_t; 40639223Sgibbs 40739223Sgibbsstruct bt_isa_port { 40839223Sgibbs u_int16_t addr; 40939223Sgibbs u_int8_t probed; 41041048Sgibbs u_int8_t bio; 41139223Sgibbs}; 41239223Sgibbs 41339223Sgibbsextern struct bt_isa_port bt_isa_ports[]; 41439223Sgibbs 41539223Sgibbs#define BT_NUM_ISAPORTS 6 41639223Sgibbs 41739223Sgibbstypedef enum { 41839223Sgibbs BIO_330 = 0, 41939223Sgibbs BIO_334 = 1, 42039223Sgibbs BIO_230 = 2, 42139223Sgibbs BIO_234 = 3, 42239223Sgibbs BIO_130 = 4, 42339223Sgibbs BIO_134 = 5, 42439223Sgibbs BIO_DISABLED = 6, 42539223Sgibbs BIO_DISABLED2 = 7 42639223Sgibbs} isa_compat_io_t; 42739223Sgibbs 42839223Sgibbstypedef struct { 42939223Sgibbs u_int8_t io_port; 43039223Sgibbs u_int8_t irq_num; 43139223Sgibbs u_int8_t low_byte_term :1, 43239223Sgibbs high_byte_term :1, 43339223Sgibbs :2, 43439223Sgibbs jp1_status :1, 43539223Sgibbs jp2_status :1, 43639223Sgibbs jp3_status :1, 43739223Sgibbs :1; 43839223Sgibbs u_int8_t reserved; 43939223Sgibbs} pci_info_data_t; 44039223Sgibbs 44139223Sgibbstypedef struct { 44239223Sgibbs u_int8_t ascii_model[5]; /* Fifth byte is always 0 */ 44339223Sgibbs} ha_model_data_t; 44439223Sgibbs 44539223Sgibbstypedef struct { 44639223Sgibbs u_int8_t sync_rate[16]; /* Sync in 10ns units */ 44739223Sgibbs} target_sync_info_data_t; 44839223Sgibbs 44939223Sgibbstypedef struct { 45039223Sgibbs u_int8_t bus_type; 45139223Sgibbs u_int8_t bios_addr; 45239223Sgibbs u_int16_t max_sg; 45339223Sgibbs u_int8_t num_mboxes; 45439223Sgibbs u_int8_t mbox_base[4]; 45539223Sgibbs u_int8_t :2, 45639223Sgibbs sync_neg10MB :1, 45739223Sgibbs floppy_disable :1, 45839223Sgibbs floppy_secondary_port :1, 45939223Sgibbs burst_mode_enabled :1, 46039223Sgibbs level_trigger_ints :1, 46139223Sgibbs :1; 46239223Sgibbs u_int8_t fw_ver_bytes_2_to_4[3]; 46339223Sgibbs u_int8_t wide_bus :1, 46439223Sgibbs diff_bus :1, 46539223Sgibbs scam_capable :1, 46639223Sgibbs ultra_scsi :1, 46739223Sgibbs auto_term :1, 46839223Sgibbs :3; 46939223Sgibbs} esetup_info_data_t; 47039223Sgibbs 47139223Sgibbstypedef struct { 47239223Sgibbs u_int32_t len; 47339223Sgibbs u_int32_t addr; 47439223Sgibbs} bt_sg_t; 47539223Sgibbs 47639223Sgibbs/********************** Mail Box definitions *******************************/ 47739223Sgibbs 47839223Sgibbstypedef enum { 47939223Sgibbs BMBO_FREE = 0x0, /* MBO intry is free */ 48039223Sgibbs BMBO_START = 0x1, /* MBO activate entry */ 48139223Sgibbs BMBO_ABORT = 0x2 /* MBO abort entry */ 48239223Sgibbs} bt_mbo_action_code_t; 48339223Sgibbs 48439223Sgibbstypedef struct bt_mbox_out { 48539223Sgibbs u_int32_t ccb_addr; 48639223Sgibbs u_int8_t reserved[3]; 48739223Sgibbs u_int8_t action_code; 48839223Sgibbs} bt_mbox_out_t; 48939223Sgibbs 49039223Sgibbstypedef enum { 49139223Sgibbs BMBI_FREE = 0x0, /* MBI entry is free */ 49239223Sgibbs BMBI_OK = 0x1, /* completed without error */ 49339223Sgibbs BMBI_ABORT = 0x2, /* aborted ccb */ 49439223Sgibbs BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */ 49539223Sgibbs BMBI_ERROR = 0x4 /* Completed with error */ 49639223Sgibbs} bt_mbi_comp_code_t; 49739223Sgibbs 49839223Sgibbstypedef struct bt_mbox_in { 49939223Sgibbs u_int32_t ccb_addr; 50039223Sgibbs u_int8_t btstat; 50139223Sgibbs u_int8_t sdstat; 50239223Sgibbs u_int8_t reserved; 50339223Sgibbs u_int8_t comp_code; 50439223Sgibbs} bt_mbox_in_t; 50539223Sgibbs 50644581Sgibbs/***************** Compiled Probe Information *******************************/ 50744581Sgibbsstruct bt_probe_info { 50844581Sgibbs int drq; 50944581Sgibbs int irq; 51044581Sgibbs}; 51144581Sgibbs 51239223Sgibbs/****************** Hardware CCB definition *********************************/ 51339223Sgibbstypedef enum { 51439223Sgibbs INITIATOR_CCB = 0x00, 51539223Sgibbs INITIATOR_SG_CCB = 0x02, 51639223Sgibbs INITIATOR_CCB_WRESID = 0x03, 51739223Sgibbs INITIATOR_SG_CCB_WRESID = 0x04, 51839223Sgibbs INITIATOR_BUS_DEV_RESET = 0x81 51939223Sgibbs} bt_ccb_opcode_t; 52039223Sgibbs 52139223Sgibbstypedef enum { 52239223Sgibbs BTSTAT_NOERROR = 0x00, 52339223Sgibbs BTSTAT_LINKED_CMD_COMPLETE = 0x0A, 52439223Sgibbs BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B, 52539223Sgibbs BTSTAT_DATAUNDERUN_ERROR = 0x0C, 52639223Sgibbs BTSTAT_SELTIMEOUT = 0x11, 52739223Sgibbs BTSTAT_DATARUN_ERROR = 0x12, 52839223Sgibbs BTSTAT_UNEXPECTED_BUSFREE = 0x13, 52939223Sgibbs BTSTAT_INVALID_PHASE = 0x14, 53039223Sgibbs BTSTAT_INVALID_ACTION_CODE = 0x15, 53139223Sgibbs BTSTAT_INVALID_OPCODE = 0x16, 53239223Sgibbs BTSTAT_LINKED_CCB_LUN_MISMATCH = 0x17, 53339223Sgibbs BTSTAT_INVALID_CCB_OR_SG_PARAM = 0x1A, 53439223Sgibbs BTSTAT_AUTOSENSE_FAILED = 0x1B, 53539223Sgibbs BTSTAT_TAGGED_MSG_REJECTED = 0x1C, 53639223Sgibbs BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D, 53739223Sgibbs BTSTAT_HARDWARE_FAILURE = 0x20, 53839223Sgibbs BTSTAT_TARGET_IGNORED_ATN = 0x21, 53939223Sgibbs BTSTAT_HA_SCSI_BUS_RESET = 0x22, 54039223Sgibbs BTSTAT_OTHER_SCSI_BUS_RESET = 0x23, 54139223Sgibbs BTSTAT_INVALID_RECONNECT = 0x24, 54239223Sgibbs BTSTAT_HA_BDR = 0x25, 54339223Sgibbs BTSTAT_ABORT_QUEUE_GENERATED = 0x26, 54439223Sgibbs BTSTAT_HA_SOFTWARE_ERROR = 0x27, 54539223Sgibbs BTSTAT_HA_WATCHDOG_ERROR = 0x28, 54639223Sgibbs BTSTAT_SCSI_PERROR_DETECTED = 0x30 54739223Sgibbs} btstat_t; 54839223Sgibbs 54939223Sgibbsstruct bt_hccb { 55039223Sgibbs u_int8_t opcode; 55139223Sgibbs u_int8_t :3, 55239223Sgibbs datain :1, 55339223Sgibbs dataout :1, 55439223Sgibbs wide_tag_enable :1, /* Wide Lun CCB format */ 55539223Sgibbs wide_tag_type :2; /* Wide Lun CCB format */ 55639223Sgibbs u_int8_t cmd_len; 55739223Sgibbs u_int8_t sense_len; 55841048Sgibbs int32_t data_len; /* residuals can be negative */ 55939223Sgibbs u_int32_t data_addr; 56039223Sgibbs u_int8_t reserved[2]; 56139223Sgibbs u_int8_t btstat; 56239223Sgibbs u_int8_t sdstat; 56339223Sgibbs u_int8_t target_id; 56439223Sgibbs u_int8_t target_lun :5, 56539223Sgibbs tag_enable :1, 56639223Sgibbs tag_type :2; 56739223Sgibbs u_int8_t scsi_cdb[12]; 56839223Sgibbs u_int8_t reserved2[6]; 56939223Sgibbs u_int32_t sense_addr; 57039223Sgibbs}; 57139223Sgibbs 57239223Sgibbstypedef enum { 57339223Sgibbs BCCB_FREE = 0x0, 57439223Sgibbs BCCB_ACTIVE = 0x1, 57539223Sgibbs BCCB_DEVICE_RESET = 0x2, 57639223Sgibbs BCCB_RELEASE_SIMQ = 0x4 57739223Sgibbs} bccb_flags_t; 57839223Sgibbs 57939223Sgibbsstruct bt_ccb { 58039223Sgibbs struct bt_hccb hccb; 58160938Sjake SLIST_ENTRY(bt_ccb) links; 58239223Sgibbs u_int32_t flags; 58339223Sgibbs union ccb *ccb; 58439223Sgibbs bus_dmamap_t dmamap; 585241592Sjhb struct callout timer; 58639223Sgibbs bt_sg_t *sg_list; 58739223Sgibbs u_int32_t sg_list_phys; 58839223Sgibbs}; 58939223Sgibbs 59039223Sgibbsstruct sg_map_node { 59139223Sgibbs bus_dmamap_t sg_dmamap; 59239223Sgibbs bus_addr_t sg_physaddr; 59339223Sgibbs bt_sg_t* sg_vaddr; 59460938Sjake SLIST_ENTRY(sg_map_node) links; 59539223Sgibbs}; 59639223Sgibbs 59739223Sgibbsstruct bt_softc { 59845791Speter struct device *dev; 59945791Speter struct resource *port; 60045791Speter struct resource *irq; 60145791Speter struct resource *drq; 60245791Speter void *ih; 603241592Sjhb struct mtx lock; 60439223Sgibbs struct cam_sim *sim; 60539223Sgibbs struct cam_path *path; 60639223Sgibbs bt_mbox_out_t *cur_outbox; 60739223Sgibbs bt_mbox_in_t *cur_inbox; 60839223Sgibbs bt_mbox_out_t *last_outbox; 60939223Sgibbs bt_mbox_in_t *last_inbox; 61039223Sgibbs struct bt_ccb *bt_ccb_array; 61160938Sjake SLIST_HEAD(,bt_ccb) free_bt_ccbs; 61260938Sjake LIST_HEAD(,ccb_hdr) pending_ccbs; 61341048Sgibbs u_int active_ccbs; 61439223Sgibbs u_int32_t bt_ccb_physbase; 61539223Sgibbs bt_mbox_in_t *in_boxes; 61639223Sgibbs bt_mbox_out_t *out_boxes; 61739223Sgibbs struct scsi_sense_data *sense_buffers; 61839223Sgibbs u_int32_t sense_buffers_physbase; 61939223Sgibbs struct bt_ccb *recovery_bccb; 62039223Sgibbs u_int num_boxes; 62139223Sgibbs bus_dma_tag_t parent_dmat; /* 62239223Sgibbs * All dmat's derive from 62339223Sgibbs * the dmat defined by our 62439223Sgibbs * bus. 62539223Sgibbs */ 62639223Sgibbs bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 62739223Sgibbs bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */ 62839223Sgibbs bus_dmamap_t mailbox_dmamap; 62939223Sgibbs bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */ 63039223Sgibbs bus_dmamap_t ccb_dmamap; 63145966Sgibbs bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 63245966Sgibbs bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 63339223Sgibbs bus_dmamap_t sense_dmamap; 63460938Sjake SLIST_HEAD(, sg_map_node) sg_maps; 63539223Sgibbs bus_addr_t mailbox_physbase; 63668661Sgibbs bus_addr_t mailbox_addrlimit; 63739223Sgibbs u_int num_ccbs; /* Number of CCBs malloc'd */ 63839223Sgibbs u_int max_ccbs; /* Maximum allocatable CCBs */ 63939223Sgibbs u_int max_sg; 64039223Sgibbs u_int scsi_id; 64144581Sgibbs u_int32_t extended_trans :1, 64244581Sgibbs wide_bus :1, 64344581Sgibbs diff_bus :1, 64444581Sgibbs ultra_scsi :1, 64544581Sgibbs extended_lun :1, 64644581Sgibbs strict_rr :1, 64744581Sgibbs tag_capable :1, 64844581Sgibbs wide_lun_ccb :1, 64944581Sgibbs resource_shortage :1, 65044581Sgibbs level_trigger_ints:1, 65144581Sgibbs :22; 65239223Sgibbs u_int16_t tags_permitted; 65339223Sgibbs u_int16_t disc_permitted; 65439223Sgibbs u_int16_t sync_permitted; 65539223Sgibbs u_int16_t fast_permitted; 65639223Sgibbs u_int16_t ultra_permitted; 65739223Sgibbs u_int16_t wide_permitted; 65839223Sgibbs u_int8_t init_level; 65939223Sgibbs volatile u_int8_t command_cmp; 66039223Sgibbs volatile u_int8_t latched_status; 66139223Sgibbs u_int32_t bios_addr; 66239223Sgibbs char firmware_ver[6]; 66339223Sgibbs char model[5]; 66439223Sgibbs}; 66539223Sgibbs 66639223Sgibbs#define BT_TEMP_UNIT 0xFF /* Unit for probes */ 66745791Spetervoid bt_init_softc(device_t dev, 66845791Speter struct resource *port, 66945791Speter struct resource *irq, 67045791Speter struct resource *drq); 67145791Spetervoid bt_free_softc(device_t dev); 67245791Speterint bt_port_probe(device_t dev, 67344581Sgibbs struct bt_probe_info *info); 67445791Speterint bt_probe(device_t dev); 67545791Speterint bt_fetch_adapter_info(device_t dev); 67645791Speterint bt_init(device_t dev); 67745791Speterint bt_attach(device_t dev); 67839223Sgibbsvoid bt_intr(void *arg); 67939223Sgibbsint bt_check_probed_iop(u_int ioport); 68039223Sgibbsvoid bt_mark_probed_bio(isa_compat_io_t port); 68139223Sgibbsvoid bt_mark_probed_iop(u_int ioport); 68241048Sgibbsvoid bt_find_probe_range(int ioport, 68341048Sgibbs int *port_index, 68441048Sgibbs int *max_port_index); 68539223Sgibbs 68641048Sgibbsint bt_iop_from_bio(isa_compat_io_t bio_index); 68741048Sgibbs 68845444Sgibbs#define DEFAULT_CMD_TIMEOUT 100000 /* 10 sec */ 68939223Sgibbsint bt_cmd(struct bt_softc *bt, bt_op_t opcode, 69039223Sgibbs u_int8_t *params, u_int param_len, 69139223Sgibbs u_int8_t *reply_data, u_int reply_len, 69239223Sgibbs u_int cmd_timeout); 69339223Sgibbs 69445791Speter#define bt_name(bt) device_get_nameunit(bt->dev) 69545791Speter 696241592Sjhb#define bt_inb(bt, reg) \ 697241592Sjhb bus_read_1((bt)->port, reg) 69839223Sgibbs 699241592Sjhb#define bt_outb(bt, reg, value) \ 700241592Sjhb bus_write_1((bt)->port, reg, value) 70139223Sgibbs 70239223Sgibbs#endif /* _BT_H_ */ 703