ar9280_attach.c revision 234510
1/* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 234510 2012-04-20 22:07:21Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27#include "ar9002/ar9280.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar9002/ar9280v1.ini" 32#include "ar9002/ar9280v2.ini" 33#include "ar9002/ar9280_olc.h" 34 35static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37 .calNumSamples = MIN_CAL_SAMPLES, 38 .calCountMax = PER_MAX_LOG_COUNT, 39 .calCollect = ar5416IQCalCollect, 40 .calPostProc = ar5416IQCalibration 41}; 42static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44 .calNumSamples = MIN_CAL_SAMPLES, 45 .calCountMax = PER_MAX_LOG_COUNT, 46 .calCollect = ar5416AdcGainCalCollect, 47 .calPostProc = ar5416AdcGainCalibration 48}; 49static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50 .calName = "ADC DC", .calType = ADC_DC_CAL, 51 .calNumSamples = MIN_CAL_SAMPLES, 52 .calCountMax = PER_MAX_LOG_COUNT, 53 .calCollect = ar5416AdcDcCalCollect, 54 .calPostProc = ar5416AdcDcCalibration 55}; 56static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58 .calNumSamples = MIN_CAL_SAMPLES, 59 .calCountMax = INIT_LOG_COUNT, 60 .calCollect = ar5416AdcDcCalCollect, 61 .calPostProc = ar5416AdcDcCalibration 62}; 63 64static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 65static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 66static void ar9280WriteIni(struct ath_hal *ah, 67 const struct ieee80211_channel *chan); 68 69static void 70ar9280AniSetup(struct ath_hal *ah) 71{ 72 /* 73 * These are the parameters from the AR5416 ANI code; 74 * they likely need quite a bit of adjustment for the 75 * AR9280. 76 */ 77 static const struct ar5212AniParams aniparams = { 78 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 79 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 80 .coarseHigh = { -14, -14, -14, -14, -12 }, 81 .coarseLow = { -64, -64, -64, -64, -70 }, 82 .firpwr = { -78, -78, -78, -78, -80 }, 83 .maxSpurImmunityLevel = 2, 84 .cycPwrThr1 = { 2, 4, 6 }, 85 .maxFirstepLevel = 2, /* levels 0..2 */ 86 .firstep = { 0, 4, 8 }, 87 .ofdmTrigHigh = 500, 88 .ofdmTrigLow = 200, 89 .cckTrigHigh = 200, 90 .cckTrigLow = 100, 91 .rssiThrHigh = 40, 92 .rssiThrLow = 7, 93 .period = 100, 94 }; 95 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 96 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 97 98 /* NB: ANI is not enabled yet */ 99 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 100} 101 102void 103ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 104{ 105 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 106 107 if (AR_SREV_MERLIN_20(ah) && 108 chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 109 /* 110 * PLL WAR for Merlin 2.0/2.1 111 * When doing fast clock, set PLL to 0x142c 112 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 113 */ 114 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 115 } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 116 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 117 if (chan != AH_NULL) { 118 if (IEEE80211_IS_CHAN_HALF(chan)) 119 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 120 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 121 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 122 if (IEEE80211_IS_CHAN_5GHZ(chan)) 123 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 124 else 125 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 126 } else 127 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 128 } 129 130 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 131 OS_DELAY(RTC_PLL_SETTLE_DELAY); 132 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 133} 134 135/* XXX shouldn't be here! */ 136#define EEP_MINOR(_ah) \ 137 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 138 139/* 140 * Attach for an AR9280 part. 141 */ 142static struct ath_hal * 143ar9280Attach(uint16_t devid, HAL_SOFTC sc, 144 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 145 HAL_STATUS *status) 146{ 147 struct ath_hal_9280 *ahp9280; 148 struct ath_hal_5212 *ahp; 149 struct ath_hal *ah; 150 uint32_t val; 151 HAL_STATUS ecode; 152 HAL_BOOL rfStatus; 153 int8_t pwr_table_offset; 154 uint8_t pwr; 155 156 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 157 __func__, sc, (void*) st, (void*) sh); 158 159 /* NB: memory is returned zero'd */ 160 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 161 if (ahp9280 == AH_NULL) { 162 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 163 "%s: cannot allocate memory for state block\n", __func__); 164 *status = HAL_ENOMEM; 165 return AH_NULL; 166 } 167 ahp = AH5212(ahp9280); 168 ah = &ahp->ah_priv.h; 169 170 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 171 172 /* 173 * Use the "local" EEPROM data given to us by the higher layers. 174 * This is a private copy out of system flash. The Linux ath9k 175 * commit for the initial AR9130 support mentions MMIO flash 176 * access is "unreliable." -adrian 177 */ 178 if (eepromdata != AH_NULL) { 179 AH_PRIVATE((ah))->ah_eepromRead = ath_hal_EepromDataRead; 180 AH_PRIVATE((ah))->ah_eepromWrite = NULL; 181 ah->ah_eepromdata = eepromdata; 182 } 183 184 /* XXX override with 9280 specific state */ 185 /* override 5416 methods for our needs */ 186 AH5416(ah)->ah_initPLL = ar9280InitPLL; 187 188 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 189 ah->ah_configPCIE = ar9280ConfigPCIE; 190 191 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 192 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 193 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 194 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 195 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 196 197 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 198 AH5416(ah)->ah_writeIni = ar9280WriteIni; 199 AH5416(ah)->ah_olcInit = ar9280olcInit; 200 AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 201 AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 202 203 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 204 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 205 206 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 207 /* reset chip */ 208 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 209 __func__); 210 ecode = HAL_EIO; 211 goto bad; 212 } 213 214 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 215 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 216 __func__); 217 ecode = HAL_EIO; 218 goto bad; 219 } 220 /* Read Revisions from Chips before taking out of reset */ 221 val = OS_REG_READ(ah, AR_SREV); 222 HALDEBUG(ah, HAL_DEBUG_ATTACH, 223 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 224 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 225 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 226 /* NB: include chip type to differentiate from pre-Sowl versions */ 227 AH_PRIVATE(ah)->ah_macVersion = 228 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 229 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 230 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 231 232 /* setup common ini data; rf backends handle remainder */ 233 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 234 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 235 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 236 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 237 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 238 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 239 ar9280Modes_fast_clock_v2, 3); 240 } else { 241 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 242 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 243 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 244 ar9280PciePhy_v1, 2); 245 } 246 ar5416AttachPCIE(ah); 247 248 ecode = ath_hal_v14EepromAttach(ah); 249 if (ecode != HAL_OK) 250 goto bad; 251 252 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 253 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 254 ecode = HAL_EIO; 255 goto bad; 256 } 257 258 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 259 260 if (!ar5212ChipTest(ah)) { 261 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 262 __func__); 263 ecode = HAL_ESELFTEST; 264 goto bad; 265 } 266 267 /* 268 * Set correct Baseband to analog shift 269 * setting to access analog chips. 270 */ 271 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 272 273 /* Read Radio Chip Rev Extract */ 274 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 275 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 276 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 277 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 278 break; 279 default: 280 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 281 AH_PRIVATE(ah)->ah_analog5GhzRev = 282 AR_RAD5133_SREV_MAJOR; 283 break; 284 } 285#ifdef AH_DEBUG 286 HALDEBUG(ah, HAL_DEBUG_ANY, 287 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 288 "this driver\n", __func__, 289 AH_PRIVATE(ah)->ah_analog5GhzRev); 290 ecode = HAL_ENOTSUPP; 291 goto bad; 292#endif 293 } 294 rfStatus = ar9280RfAttach(ah, &ecode); 295 if (!rfStatus) { 296 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 297 __func__, ecode); 298 goto bad; 299 } 300 301 /* Enable fixup for AR_AN_TOP2 if necessary */ 302 /* 303 * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 304 * by the EEPROM version. 305 * 306 * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 307 * the abstracted EEPROM access layer. 308 */ 309 ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 310 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 311 printf("[ath] enabling AN_TOP2_FIXUP\n"); 312 AH5416(ah)->ah_need_an_top2_fixup = 1; 313 } 314 315 /* 316 * Check whether the power table offset isn't the default. 317 * This can occur with eeprom minor V21 or greater on Merlin. 318 */ 319 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 320 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 321 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 322 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 323 324 /* XXX check for >= minor ver 17 */ 325 if (AR_SREV_MERLIN_20(ah)) { 326 /* setup rxgain table */ 327 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 328 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 329 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 330 ar9280Modes_backoff_13db_rxgain_v2, 6); 331 break; 332 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 333 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 334 ar9280Modes_backoff_23db_rxgain_v2, 6); 335 break; 336 case AR5416_EEP_RXGAIN_ORIG: 337 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 338 ar9280Modes_original_rxgain_v2, 6); 339 break; 340 default: 341 HALASSERT(AH_FALSE); 342 goto bad; /* XXX ? try to continue */ 343 } 344 } 345 346 /* XXX check for >= minor ver 19 */ 347 if (AR_SREV_MERLIN_20(ah)) { 348 /* setp txgain table */ 349 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 350 case AR5416_EEP_TXGAIN_HIGH_POWER: 351 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 352 ar9280Modes_high_power_tx_gain_v2, 6); 353 break; 354 case AR5416_EEP_TXGAIN_ORIG: 355 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 356 ar9280Modes_original_tx_gain_v2, 6); 357 break; 358 default: 359 HALASSERT(AH_FALSE); 360 goto bad; /* XXX ? try to continue */ 361 } 362 } 363 364 /* 365 * Got everything we need now to setup the capabilities. 366 */ 367 if (!ar9280FillCapabilityInfo(ah)) { 368 ecode = HAL_EEREAD; 369 goto bad; 370 } 371 372 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 373 if (ecode != HAL_OK) { 374 HALDEBUG(ah, HAL_DEBUG_ANY, 375 "%s: error getting mac address from EEPROM\n", __func__); 376 goto bad; 377 } 378 /* XXX How about the serial number ? */ 379 /* Read Reg Domain */ 380 AH_PRIVATE(ah)->ah_currentRD = 381 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 382 AH_PRIVATE(ah)->ah_currentRDext = 383 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 384 385 /* 386 * ah_miscMode is populated by ar5416FillCapabilityInfo() 387 * starting from griffin. Set here to make sure that 388 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 389 * placed into hardware. 390 */ 391 if (ahp->ah_miscMode != 0) 392 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 393 394 ar9280AniSetup(ah); /* Anti Noise Immunity */ 395 396 /* Setup noise floor min/max/nominal values */ 397 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 398 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 399 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 400 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 401 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 402 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 403 404 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 405 406 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 407 408 return ah; 409bad: 410 if (ah != AH_NULL) 411 ah->ah_detach(ah); 412 if (status) 413 *status = ecode; 414 return AH_NULL; 415} 416 417static void 418ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 419{ 420 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 421 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 422 OS_DELAY(1000); 423 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 424 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 425 } 426} 427 428static void 429ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 430{ 431 u_int modesIndex, freqIndex; 432 int regWrites = 0; 433 int i; 434 const HAL_INI_ARRAY *ia; 435 436 /* Setup the indices for the next set of register array writes */ 437 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 438 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 439 freqIndex = 2; 440 if (IEEE80211_IS_CHAN_HT40(chan)) 441 modesIndex = 3; 442 else if (IEEE80211_IS_CHAN_108G(chan)) 443 modesIndex = 5; 444 else 445 modesIndex = 4; 446 } else { 447 freqIndex = 1; 448 if (IEEE80211_IS_CHAN_HT40(chan) || 449 IEEE80211_IS_CHAN_TURBO(chan)) 450 modesIndex = 2; 451 else 452 modesIndex = 1; 453 } 454 455 /* Set correct Baseband to analog shift setting to access analog chips. */ 456 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 457 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 458 459 /* 460 * This is unwound because at the moment, there's a requirement 461 * for Merlin (and later, perhaps) to have a specific bit fixed 462 * in the AR_AN_TOP2 register before writing it. 463 */ 464 ia = &AH5212(ah)->ah_ini_modes; 465#if 0 466 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 467 modesIndex, regWrites); 468#endif 469 HALASSERT(modesIndex < ia->cols); 470 for (i = 0; i < ia->rows; i++) { 471 uint32_t reg = HAL_INI_VAL(ia, i, 0); 472 uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 473 474 if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 475 val &= ~AR_AN_TOP2_PWDCLKIND; 476 477 OS_REG_WRITE(ah, reg, val); 478 479 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 480 if (reg >= 0x7800 && reg < 0x7900) 481 OS_DELAY(100); 482 483 DMA_YIELD(regWrites); 484 } 485 486 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 487 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 488 modesIndex, regWrites); 489 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 490 modesIndex, regWrites); 491 } 492 /* XXX Merlin 100us delay for shift registers */ 493 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 494 1, regWrites); 495 496 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 497 /* 5GHz channels w/ Fast Clock use different modal values */ 498 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 499 modesIndex, regWrites); 500 } 501} 502 503#define AR_BASE_FREQ_2GHZ 2300 504#define AR_BASE_FREQ_5GHZ 4900 505#define AR_SPUR_FEEQ_BOUND_HT40 19 506#define AR_SPUR_FEEQ_BOUND_HT20 10 507 508void 509ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 510{ 511 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 512 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 513 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 514 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 515 static int inc[4] = { 0, 100, 0, 0 }; 516 517 int bb_spur = AR_NO_SPUR; 518 int freq; 519 int bin, cur_bin; 520 int bb_spur_off, spur_subchannel_sd; 521 int spur_freq_sd; 522 int spur_delta_phase; 523 int denominator; 524 int upper, lower, cur_vit_mask; 525 int tmp, newVal; 526 int i; 527 CHAN_CENTERS centers; 528 529 int8_t mask_m[123]; 530 int8_t mask_p[123]; 531 int8_t mask_amt; 532 int tmp_mask; 533 int cur_bb_spur; 534 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 535 536 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 537 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 538 539 ar5416GetChannelCenters(ah, chan, ¢ers); 540 freq = centers.synth_center; 541 542 /* 543 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 544 * otherwise spur is out-of-band and can be ignored. 545 */ 546 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 547 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 548 /* Get actual spur freq in MHz from EEPROM read value */ 549 if (is2GHz) { 550 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 551 } else { 552 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 553 } 554 555 if (AR_NO_SPUR == cur_bb_spur) 556 break; 557 cur_bb_spur = cur_bb_spur - freq; 558 559 if (IEEE80211_IS_CHAN_HT40(chan)) { 560 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 561 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 562 bb_spur = cur_bb_spur; 563 break; 564 } 565 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 566 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 567 bb_spur = cur_bb_spur; 568 break; 569 } 570 } 571 572 if (AR_NO_SPUR == bb_spur) { 573#if 1 574 /* 575 * MRC CCK can interfere with beacon detection and cause deaf/mute. 576 * Disable MRC CCK for now. 577 */ 578 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 579#else 580 /* Enable MRC CCK if no spur is found in this channel. */ 581 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 582#endif 583 return; 584 } else { 585 /* 586 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 587 * is found in this channel. 588 */ 589 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 590 } 591 592 bin = bb_spur * 320; 593 594 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 595 596 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 597 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 598 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 599 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 600 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 601 602 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 603 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 604 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 605 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 606 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 607 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 608 609 /* Pick control or extn channel to cancel the spur */ 610 if (IEEE80211_IS_CHAN_HT40(chan)) { 611 if (bb_spur < 0) { 612 spur_subchannel_sd = 1; 613 bb_spur_off = bb_spur + 10; 614 } else { 615 spur_subchannel_sd = 0; 616 bb_spur_off = bb_spur - 10; 617 } 618 } else { 619 spur_subchannel_sd = 0; 620 bb_spur_off = bb_spur; 621 } 622 623 /* 624 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 625 * /80 for dyn2040. 626 */ 627 if (IEEE80211_IS_CHAN_HT40(chan)) 628 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 629 else 630 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 631 632 /* 633 * in 11A mode the denominator of spur_freq_sd should be 40 and 634 * it should be 44 in 11G 635 */ 636 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 637 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 638 639 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 640 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 641 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 642 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 643 644 /* Choose to cancel between control and extension channels */ 645 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 646 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 647 648 /* 649 * ============================================ 650 * Set Pilot and Channel Masks 651 * 652 * pilot mask 1 [31:0] = +6..-26, no 0 bin 653 * pilot mask 2 [19:0] = +26..+7 654 * 655 * channel mask 1 [31:0] = +6..-26, no 0 bin 656 * channel mask 2 [19:0] = +26..+7 657 */ 658 cur_bin = -6000; 659 upper = bin + 100; 660 lower = bin - 100; 661 662 for (i = 0; i < 4; i++) { 663 int pilot_mask = 0; 664 int chan_mask = 0; 665 int bp = 0; 666 for (bp = 0; bp < 30; bp++) { 667 if ((cur_bin > lower) && (cur_bin < upper)) { 668 pilot_mask = pilot_mask | 0x1 << bp; 669 chan_mask = chan_mask | 0x1 << bp; 670 } 671 cur_bin += 100; 672 } 673 cur_bin += inc[i]; 674 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 675 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 676 } 677 678 /* ================================================= 679 * viterbi mask 1 based on channel magnitude 680 * four levels 0-3 681 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 682 * [1 2 2 1] for -9.6 or [1 2 1] for +16 683 * - enable_mask_ppm, all bins move with freq 684 * 685 * - mask_select, 8 bits for rates (reg 67,0x990c) 686 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 687 * choose which mask to use mask or mask2 688 */ 689 690 /* 691 * viterbi mask 2 2nd set for per data rate puncturing 692 * four levels 0-3 693 * - mask_select, 8 bits for rates (reg 67) 694 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 695 * [1 2 2 1] for -9.6 or [1 2 1] for +16 696 */ 697 cur_vit_mask = 6100; 698 upper = bin + 120; 699 lower = bin - 120; 700 701 for (i = 0; i < 123; i++) { 702 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 703 if ((abs(cur_vit_mask - bin)) < 75) { 704 mask_amt = 1; 705 } else { 706 mask_amt = 0; 707 } 708 if (cur_vit_mask < 0) { 709 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 710 } else { 711 mask_p[cur_vit_mask / 100] = mask_amt; 712 } 713 } 714 cur_vit_mask -= 100; 715 } 716 717 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 718 | (mask_m[48] << 26) | (mask_m[49] << 24) 719 | (mask_m[50] << 22) | (mask_m[51] << 20) 720 | (mask_m[52] << 18) | (mask_m[53] << 16) 721 | (mask_m[54] << 14) | (mask_m[55] << 12) 722 | (mask_m[56] << 10) | (mask_m[57] << 8) 723 | (mask_m[58] << 6) | (mask_m[59] << 4) 724 | (mask_m[60] << 2) | (mask_m[61] << 0); 725 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 726 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 727 728 tmp_mask = (mask_m[31] << 28) 729 | (mask_m[32] << 26) | (mask_m[33] << 24) 730 | (mask_m[34] << 22) | (mask_m[35] << 20) 731 | (mask_m[36] << 18) | (mask_m[37] << 16) 732 | (mask_m[48] << 14) | (mask_m[39] << 12) 733 | (mask_m[40] << 10) | (mask_m[41] << 8) 734 | (mask_m[42] << 6) | (mask_m[43] << 4) 735 | (mask_m[44] << 2) | (mask_m[45] << 0); 736 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 737 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 738 739 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 740 | (mask_m[18] << 26) | (mask_m[18] << 24) 741 | (mask_m[20] << 22) | (mask_m[20] << 20) 742 | (mask_m[22] << 18) | (mask_m[22] << 16) 743 | (mask_m[24] << 14) | (mask_m[24] << 12) 744 | (mask_m[25] << 10) | (mask_m[26] << 8) 745 | (mask_m[27] << 6) | (mask_m[28] << 4) 746 | (mask_m[29] << 2) | (mask_m[30] << 0); 747 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 748 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 749 750 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 751 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 752 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 753 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 754 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 755 | (mask_m[10] << 10) | (mask_m[11] << 8) 756 | (mask_m[12] << 6) | (mask_m[13] << 4) 757 | (mask_m[14] << 2) | (mask_m[15] << 0); 758 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 759 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 760 761 tmp_mask = (mask_p[15] << 28) 762 | (mask_p[14] << 26) | (mask_p[13] << 24) 763 | (mask_p[12] << 22) | (mask_p[11] << 20) 764 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 765 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 766 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 767 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 768 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 769 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 770 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 771 772 tmp_mask = (mask_p[30] << 28) 773 | (mask_p[29] << 26) | (mask_p[28] << 24) 774 | (mask_p[27] << 22) | (mask_p[26] << 20) 775 | (mask_p[25] << 18) | (mask_p[24] << 16) 776 | (mask_p[23] << 14) | (mask_p[22] << 12) 777 | (mask_p[21] << 10) | (mask_p[20] << 8) 778 | (mask_p[19] << 6) | (mask_p[18] << 4) 779 | (mask_p[17] << 2) | (mask_p[16] << 0); 780 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 781 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 782 783 tmp_mask = (mask_p[45] << 28) 784 | (mask_p[44] << 26) | (mask_p[43] << 24) 785 | (mask_p[42] << 22) | (mask_p[41] << 20) 786 | (mask_p[40] << 18) | (mask_p[39] << 16) 787 | (mask_p[38] << 14) | (mask_p[37] << 12) 788 | (mask_p[36] << 10) | (mask_p[35] << 8) 789 | (mask_p[34] << 6) | (mask_p[33] << 4) 790 | (mask_p[32] << 2) | (mask_p[31] << 0); 791 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 792 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 793 794 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 795 | (mask_p[59] << 26) | (mask_p[58] << 24) 796 | (mask_p[57] << 22) | (mask_p[56] << 20) 797 | (mask_p[55] << 18) | (mask_p[54] << 16) 798 | (mask_p[53] << 14) | (mask_p[52] << 12) 799 | (mask_p[51] << 10) | (mask_p[50] << 8) 800 | (mask_p[49] << 6) | (mask_p[48] << 4) 801 | (mask_p[47] << 2) | (mask_p[46] << 0); 802 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 803 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 804} 805 806/* 807 * Fill all software cached or static hardware state information. 808 * Return failure if capabilities are to come from EEPROM and 809 * cannot be read. 810 */ 811static HAL_BOOL 812ar9280FillCapabilityInfo(struct ath_hal *ah) 813{ 814 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 815 816 if (!ar5416FillCapabilityInfo(ah)) 817 return AH_FALSE; 818 pCap->halNumGpioPins = 10; 819 pCap->halWowSupport = AH_TRUE; 820 pCap->halWowMatchPatternExact = AH_TRUE; 821#if 0 822 pCap->halWowMatchPatternDword = AH_TRUE; 823#endif 824 pCap->halCSTSupport = AH_TRUE; 825 pCap->halRifsRxSupport = AH_TRUE; 826 pCap->halRifsTxSupport = AH_TRUE; 827 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 828 pCap->halExtChanDfsSupport = AH_TRUE; 829 pCap->halUseCombinedRadarRssi = AH_TRUE; 830#if 0 831 /* XXX bluetooth */ 832 pCap->halBtCoexSupport = AH_TRUE; 833#endif 834 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 835 pCap->hal4kbSplitTransSupport = AH_FALSE; 836 /* Disable this so Block-ACK works correctly */ 837 pCap->halHasRxSelfLinkedTail = AH_FALSE; 838 pCap->halMbssidAggrSupport = AH_TRUE; 839 pCap->hal4AddrAggrSupport = AH_TRUE; 840 841 if (AR_SREV_MERLIN_20(ah)) { 842 pCap->halPSPollBroken = AH_FALSE; 843 /* 844 * This just enables the support; it doesn't 845 * state 5ghz fast clock will always be used. 846 */ 847 pCap->halSupportsFastClock5GHz = AH_TRUE; 848 } 849 pCap->halRxStbcSupport = 1; 850 pCap->halTxStbcSupport = 1; 851 pCap->halEnhancedDfsSupport = AH_TRUE; 852 853 return AH_TRUE; 854} 855 856/* 857 * This has been disabled - having the HAL flip chainmasks on/off 858 * when attempting to implement 11n disrupts things. For now, just 859 * leave this flipped off and worry about implementing TX diversity 860 * for legacy and MCS0-7 when 11n is fully functioning. 861 */ 862HAL_BOOL 863ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 864{ 865#define ANTENNA0_CHAINMASK 0x1 866#define ANTENNA1_CHAINMASK 0x2 867#if 0 868 struct ath_hal_5416 *ahp = AH5416(ah); 869 870 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 871 switch (settings) { 872 case HAL_ANT_FIXED_A: 873 /* Enable first antenna only */ 874 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 875 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 876 break; 877 case HAL_ANT_FIXED_B: 878 /* Enable second antenna only, after checking capability */ 879 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 880 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 881 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 882 break; 883 case HAL_ANT_VARIABLE: 884 /* Restore original chainmask settings */ 885 /* XXX */ 886 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 887 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 888 break; 889 } 890 891 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 892 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 893 894#endif 895 return AH_TRUE; 896#undef ANTENNA0_CHAINMASK 897#undef ANTENNA1_CHAINMASK 898} 899 900static const char* 901ar9280Probe(uint16_t vendorid, uint16_t devid) 902{ 903 if (vendorid == ATHEROS_VENDOR_ID) { 904 if (devid == AR9280_DEVID_PCI) 905 return "Atheros 9220"; 906 if (devid == AR9280_DEVID_PCIE) 907 return "Atheros 9280"; 908 } 909 return AH_NULL; 910} 911AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 912