ar9280_attach.c revision 225883
1130803Smarcel/* 2130803Smarcel * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3130803Smarcel * Copyright (c) 2008 Atheros Communications, Inc. 4130803Smarcel * 5130803Smarcel * Permission to use, copy, modify, and/or distribute this software for any 6130803Smarcel * purpose with or without fee is hereby granted, provided that the above 7130803Smarcel * copyright notice and this permission notice appear in all copies. 8130803Smarcel * 9130803Smarcel * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10130803Smarcel * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11130803Smarcel * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12130803Smarcel * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13130803Smarcel * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14130803Smarcel * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15130803Smarcel * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16130803Smarcel * 17130803Smarcel * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 225883 2011-09-30 05:17:57Z adrian $ 18130803Smarcel */ 19130803Smarcel#include "opt_ah.h" 20130803Smarcel 21130803Smarcel#include "ah.h" 22130803Smarcel#include "ah_internal.h" 23130803Smarcel#include "ah_devid.h" 24130803Smarcel 25130803Smarcel#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26130803Smarcel 27130803Smarcel#include "ar9002/ar9280.h" 28130803Smarcel#include "ar5416/ar5416reg.h" 29130803Smarcel#include "ar5416/ar5416phy.h" 30130803Smarcel 31130803Smarcel#include "ar9002/ar9280v1.ini" 32130803Smarcel#include "ar9002/ar9280v2.ini" 33130803Smarcel#include "ar9002/ar9280_olc.h" 34130803Smarcel 35130803Smarcelstatic const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36130803Smarcel .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37130803Smarcel .calNumSamples = MIN_CAL_SAMPLES, 38130803Smarcel .calCountMax = PER_MAX_LOG_COUNT, 39130803Smarcel .calCollect = ar5416IQCalCollect, 40130803Smarcel .calPostProc = ar5416IQCalibration 41130803Smarcel}; 42130803Smarcelstatic const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43130803Smarcel .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44130803Smarcel .calNumSamples = MIN_CAL_SAMPLES, 45130803Smarcel .calCountMax = PER_MAX_LOG_COUNT, 46130803Smarcel .calCollect = ar5416AdcGainCalCollect, 47130803Smarcel .calPostProc = ar5416AdcGainCalibration 48130803Smarcel}; 49130803Smarcelstatic const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50130803Smarcel .calName = "ADC DC", .calType = ADC_DC_CAL, 51130803Smarcel .calNumSamples = MIN_CAL_SAMPLES, 52130803Smarcel .calCountMax = PER_MAX_LOG_COUNT, 53130803Smarcel .calCollect = ar5416AdcDcCalCollect, 54130803Smarcel .calPostProc = ar5416AdcDcCalibration 55130803Smarcel}; 56130803Smarcelstatic const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57130803Smarcel .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58130803Smarcel .calNumSamples = MIN_CAL_SAMPLES, 59130803Smarcel .calCountMax = INIT_LOG_COUNT, 60130803Smarcel .calCollect = ar5416AdcDcCalCollect, 61130803Smarcel .calPostProc = ar5416AdcDcCalibration 62130803Smarcel}; 63130803Smarcel 64130803Smarcelstatic void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 65130803Smarcelstatic HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 66130803Smarcelstatic void ar9280WriteIni(struct ath_hal *ah, 67130803Smarcel const struct ieee80211_channel *chan); 68130803Smarcel 69130803Smarcelstatic void 70130803Smarcelar9280AniSetup(struct ath_hal *ah) 71130803Smarcel{ 72130803Smarcel /* 73130803Smarcel * These are the parameters from the AR5416 ANI code; 74130803Smarcel * they likely need quite a bit of adjustment for the 75130803Smarcel * AR9280. 76130803Smarcel */ 77130803Smarcel static const struct ar5212AniParams aniparams = { 78130803Smarcel .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 79130803Smarcel .totalSizeDesired = { -55, -55, -55, -55, -62 }, 80130803Smarcel .coarseHigh = { -14, -14, -14, -14, -12 }, 81130803Smarcel .coarseLow = { -64, -64, -64, -64, -70 }, 82130803Smarcel .firpwr = { -78, -78, -78, -78, -80 }, 83130803Smarcel .maxSpurImmunityLevel = 2, 84130803Smarcel .cycPwrThr1 = { 2, 4, 6 }, 85130803Smarcel .maxFirstepLevel = 2, /* levels 0..2 */ 86130803Smarcel .firstep = { 0, 4, 8 }, 87130803Smarcel .ofdmTrigHigh = 500, 88130803Smarcel .ofdmTrigLow = 200, 89130803Smarcel .cckTrigHigh = 200, 90130803Smarcel .cckTrigLow = 100, 91130803Smarcel .rssiThrHigh = 40, 92130803Smarcel .rssiThrLow = 7, 93130803Smarcel .period = 100, 94130803Smarcel }; 95130803Smarcel /* NB: disable ANI noise immmunity for reliable RIFS rx */ 96130803Smarcel AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 97130803Smarcel 98130803Smarcel /* NB: ANI is not enabled yet */ 99130803Smarcel ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 100130803Smarcel} 101130803Smarcel 102130803Smarcelvoid 103130803Smarcelar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 104130803Smarcel{ 105130803Smarcel uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 106130803Smarcel 107130803Smarcel if (AR_SREV_MERLIN_20(ah) && 108130803Smarcel chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 109130803Smarcel /* 110130803Smarcel * PLL WAR for Merlin 2.0/2.1 111130803Smarcel * When doing fast clock, set PLL to 0x142c 112130803Smarcel * Else, set PLL to 0x2850 to prevent reset-to-reset variation 113130803Smarcel */ 114130803Smarcel pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 115130803Smarcel } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 116130803Smarcel pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 117130803Smarcel if (chan != AH_NULL) { 118130803Smarcel if (IEEE80211_IS_CHAN_HALF(chan)) 119130803Smarcel pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 120130803Smarcel else if (IEEE80211_IS_CHAN_QUARTER(chan)) 121130803Smarcel pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 122130803Smarcel if (IEEE80211_IS_CHAN_5GHZ(chan)) 123130803Smarcel pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 124130803Smarcel else 125130803Smarcel pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 126130803Smarcel } else 127130803Smarcel pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 128130803Smarcel } 129130803Smarcel 130130803Smarcel OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 131130803Smarcel OS_DELAY(RTC_PLL_SETTLE_DELAY); 132130803Smarcel OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 133130803Smarcel} 134130803Smarcel 135130803Smarcel/* XXX shouldn't be here! */ 136130803Smarcel#define EEP_MINOR(_ah) \ 137130803Smarcel (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 138130803Smarcel 139130803Smarcel/* 140130803Smarcel * Attach for an AR9280 part. 141130803Smarcel */ 142130803Smarcelstatic struct ath_hal * 143130803Smarcelar9280Attach(uint16_t devid, HAL_SOFTC sc, 144130803Smarcel HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 145130803Smarcel HAL_STATUS *status) 146130803Smarcel{ 147130803Smarcel struct ath_hal_9280 *ahp9280; 148130803Smarcel struct ath_hal_5212 *ahp; 149130803Smarcel struct ath_hal *ah; 150130803Smarcel uint32_t val; 151130803Smarcel HAL_STATUS ecode; 152130803Smarcel HAL_BOOL rfStatus; 153130803Smarcel int8_t pwr_table_offset; 154130803Smarcel uint8_t pwr; 155130803Smarcel 156130803Smarcel HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 157130803Smarcel __func__, sc, (void*) st, (void*) sh); 158130803Smarcel 159130803Smarcel /* NB: memory is returned zero'd */ 160130803Smarcel ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 161130803Smarcel if (ahp9280 == AH_NULL) { 162130803Smarcel HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 163130803Smarcel "%s: cannot allocate memory for state block\n", __func__); 164130803Smarcel *status = HAL_ENOMEM; 165130803Smarcel return AH_NULL; 166130803Smarcel } 167130803Smarcel ahp = AH5212(ahp9280); 168130803Smarcel ah = &ahp->ah_priv.h; 169130803Smarcel 170130803Smarcel ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 171130803Smarcel 172130803Smarcel /* XXX override with 9280 specific state */ 173130803Smarcel /* override 5416 methods for our needs */ 174130803Smarcel AH5416(ah)->ah_initPLL = ar9280InitPLL; 175130803Smarcel 176130803Smarcel ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 177130803Smarcel ah->ah_configPCIE = ar9280ConfigPCIE; 178130803Smarcel 179130803Smarcel AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 180130803Smarcel AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 181130803Smarcel AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 182130803Smarcel AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 183130803Smarcel AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 184130803Smarcel 185130803Smarcel AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 186130803Smarcel AH5416(ah)->ah_writeIni = ar9280WriteIni; 187130803Smarcel AH5416(ah)->ah_olcInit = ar9280olcInit; 188130803Smarcel AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 189130803Smarcel AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 190130803Smarcel 191130803Smarcel AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 192130803Smarcel AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 193130803Smarcel 194130803Smarcel if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 195130803Smarcel /* reset chip */ 196130803Smarcel HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 197130803Smarcel __func__); 198130803Smarcel ecode = HAL_EIO; 199130803Smarcel goto bad; 200130803Smarcel } 201130803Smarcel 202130803Smarcel if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 203130803Smarcel HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 204130803Smarcel __func__); 205130803Smarcel ecode = HAL_EIO; 206130803Smarcel goto bad; 207130803Smarcel } 208130803Smarcel /* Read Revisions from Chips before taking out of reset */ 209130803Smarcel val = OS_REG_READ(ah, AR_SREV); 210130803Smarcel HALDEBUG(ah, HAL_DEBUG_ATTACH, 211130803Smarcel "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 212130803Smarcel __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 213130803Smarcel MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 214130803Smarcel /* NB: include chip type to differentiate from pre-Sowl versions */ 215130803Smarcel AH_PRIVATE(ah)->ah_macVersion = 216130803Smarcel (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 217130803Smarcel AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 218130803Smarcel AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 219130803Smarcel 220130803Smarcel /* setup common ini data; rf backends handle remainder */ 221130803Smarcel if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 222130803Smarcel HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 223130803Smarcel HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 224130803Smarcel HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 225130803Smarcel ar9280PciePhy_clkreq_always_on_L1_v2, 2); 226130803Smarcel HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 227130803Smarcel ar9280Modes_fast_clock_v2, 3); 228130803Smarcel } else { 229130803Smarcel HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 230130803Smarcel HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 231130803Smarcel HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 232130803Smarcel ar9280PciePhy_v1, 2); 233130803Smarcel } 234130803Smarcel ar5416AttachPCIE(ah); 235130803Smarcel 236130803Smarcel ecode = ath_hal_v14EepromAttach(ah); 237130803Smarcel if (ecode != HAL_OK) 238130803Smarcel goto bad; 239130803Smarcel 240130803Smarcel if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 241130803Smarcel HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 242130803Smarcel ecode = HAL_EIO; 243130803Smarcel goto bad; 244130803Smarcel } 245130803Smarcel 246130803Smarcel AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 247130803Smarcel 248130803Smarcel if (!ar5212ChipTest(ah)) { 249130803Smarcel HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 250130803Smarcel __func__); 251130803Smarcel ecode = HAL_ESELFTEST; 252130803Smarcel goto bad; 253130803Smarcel } 254130803Smarcel 255130803Smarcel /* 256130803Smarcel * Set correct Baseband to analog shift 257130803Smarcel * setting to access analog chips. 258130803Smarcel */ 259130803Smarcel OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 260130803Smarcel 261130803Smarcel /* Read Radio Chip Rev Extract */ 262130803Smarcel AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 263130803Smarcel switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 264130803Smarcel case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 265130803Smarcel case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 266130803Smarcel break; 267130803Smarcel default: 268130803Smarcel if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 269130803Smarcel AH_PRIVATE(ah)->ah_analog5GhzRev = 270130803Smarcel AR_RAD5133_SREV_MAJOR; 271130803Smarcel break; 272130803Smarcel } 273130803Smarcel#ifdef AH_DEBUG 274130803Smarcel HALDEBUG(ah, HAL_DEBUG_ANY, 275130803Smarcel "%s: 5G Radio Chip Rev 0x%02X is not supported by " 276130803Smarcel "this driver\n", __func__, 277130803Smarcel AH_PRIVATE(ah)->ah_analog5GhzRev); 278130803Smarcel ecode = HAL_ENOTSUPP; 279130803Smarcel goto bad; 280130803Smarcel#endif 281130803Smarcel } 282130803Smarcel rfStatus = ar9280RfAttach(ah, &ecode); 283130803Smarcel if (!rfStatus) { 284130803Smarcel HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 285130803Smarcel __func__, ecode); 286130803Smarcel goto bad; 287130803Smarcel } 288130803Smarcel 289130803Smarcel /* Enable fixup for AR_AN_TOP2 if necessary */ 290130803Smarcel /* 291130803Smarcel * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 292130803Smarcel * by the EEPROM version. 293130803Smarcel * 294130803Smarcel * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 295130803Smarcel * the abstracted EEPROM access layer. 296130803Smarcel */ 297130803Smarcel ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 298130803Smarcel if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 299130803Smarcel printf("[ath] enabling AN_TOP2_FIXUP\n"); 300130803Smarcel AH5416(ah)->ah_need_an_top2_fixup = 1; 301130803Smarcel } 302130803Smarcel 303130803Smarcel /* 304130803Smarcel * Check whether the power table offset isn't the default. 305130803Smarcel * This can occur with eeprom minor V21 or greater on Merlin. 306130803Smarcel */ 307130803Smarcel (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 308130803Smarcel if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 309130803Smarcel ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 310130803Smarcel AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 311130803Smarcel 312130803Smarcel /* XXX check for >= minor ver 17 */ 313130803Smarcel if (AR_SREV_MERLIN_20(ah)) { 314130803Smarcel /* setup rxgain table */ 315130803Smarcel switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 316130803Smarcel case AR5416_EEP_RXGAIN_13dB_BACKOFF: 317130803Smarcel HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 318130803Smarcel ar9280Modes_backoff_13db_rxgain_v2, 6); 319130803Smarcel break; 320130803Smarcel case AR5416_EEP_RXGAIN_23dB_BACKOFF: 321130803Smarcel HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 322130803Smarcel ar9280Modes_backoff_23db_rxgain_v2, 6); 323130803Smarcel break; 324130803Smarcel case AR5416_EEP_RXGAIN_ORIG: 325130803Smarcel HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 326130803Smarcel ar9280Modes_original_rxgain_v2, 6); 327130803Smarcel break; 328130803Smarcel default: 329130803Smarcel HALASSERT(AH_FALSE); 330130803Smarcel goto bad; /* XXX ? try to continue */ 331130803Smarcel } 332130803Smarcel } 333130803Smarcel 334130803Smarcel /* XXX check for >= minor ver 19 */ 335130803Smarcel if (AR_SREV_MERLIN_20(ah)) { 336130803Smarcel /* setp txgain table */ 337130803Smarcel switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 338130803Smarcel case AR5416_EEP_TXGAIN_HIGH_POWER: 339130803Smarcel HAL_INI_INIT(&ahp9280->ah_ini_txgain, 340130803Smarcel ar9280Modes_high_power_tx_gain_v2, 6); 341130803Smarcel break; 342130803Smarcel case AR5416_EEP_TXGAIN_ORIG: 343130803Smarcel HAL_INI_INIT(&ahp9280->ah_ini_txgain, 344130803Smarcel ar9280Modes_original_tx_gain_v2, 6); 345130803Smarcel break; 346130803Smarcel default: 347130803Smarcel HALASSERT(AH_FALSE); 348130803Smarcel goto bad; /* XXX ? try to continue */ 349130803Smarcel } 350130803Smarcel } 351130803Smarcel 352130803Smarcel /* 353130803Smarcel * Got everything we need now to setup the capabilities. 354130803Smarcel */ 355130803Smarcel if (!ar9280FillCapabilityInfo(ah)) { 356130803Smarcel ecode = HAL_EEREAD; 357130803Smarcel goto bad; 358130803Smarcel } 359130803Smarcel 360130803Smarcel ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 361130803Smarcel if (ecode != HAL_OK) { 362130803Smarcel HALDEBUG(ah, HAL_DEBUG_ANY, 363130803Smarcel "%s: error getting mac address from EEPROM\n", __func__); 364130803Smarcel goto bad; 365130803Smarcel } 366130803Smarcel /* XXX How about the serial number ? */ 367130803Smarcel /* Read Reg Domain */ 368130803Smarcel AH_PRIVATE(ah)->ah_currentRD = 369130803Smarcel ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 370130803Smarcel AH_PRIVATE(ah)->ah_currentRDext = 371130803Smarcel ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 372130803Smarcel 373130803Smarcel /* 374130803Smarcel * ah_miscMode is populated by ar5416FillCapabilityInfo() 375130803Smarcel * starting from griffin. Set here to make sure that 376130803Smarcel * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 377130803Smarcel * placed into hardware. 378130803Smarcel */ 379130803Smarcel if (ahp->ah_miscMode != 0) 380130803Smarcel OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 381130803Smarcel 382130803Smarcel ar9280AniSetup(ah); /* Anti Noise Immunity */ 383130803Smarcel 384130803Smarcel /* Setup noise floor min/max/nominal values */ 385130803Smarcel AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 386130803Smarcel AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 387130803Smarcel AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 388130803Smarcel AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 389130803Smarcel AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 390130803Smarcel AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 391130803Smarcel 392130803Smarcel ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 393130803Smarcel 394130803Smarcel HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 395130803Smarcel 396130803Smarcel return ah; 397130803Smarcelbad: 398130803Smarcel if (ah != AH_NULL) 399130803Smarcel ah->ah_detach(ah); 400130803Smarcel if (status) 401130803Smarcel *status = ecode; 402130803Smarcel return AH_NULL; 403130803Smarcel} 404130803Smarcel 405130803Smarcelstatic void 406130803Smarcelar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 407130803Smarcel{ 408130803Smarcel if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 409130803Smarcel ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 410130803Smarcel OS_DELAY(1000); 411130803Smarcel OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 412130803Smarcel OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 413130803Smarcel } 414130803Smarcel} 415130803Smarcel 416130803Smarcelstatic void 417130803Smarcelar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 418130803Smarcel{ 419130803Smarcel u_int modesIndex, freqIndex; 420130803Smarcel int regWrites = 0; 421130803Smarcel int i; 422130803Smarcel const HAL_INI_ARRAY *ia; 423130803Smarcel 424130803Smarcel /* Setup the indices for the next set of register array writes */ 425130803Smarcel /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 426130803Smarcel if (IEEE80211_IS_CHAN_2GHZ(chan)) { 427130803Smarcel freqIndex = 2; 428130803Smarcel if (IEEE80211_IS_CHAN_HT40(chan)) 429130803Smarcel modesIndex = 3; 430130803Smarcel else if (IEEE80211_IS_CHAN_108G(chan)) 431130803Smarcel modesIndex = 5; 432130803Smarcel else 433130803Smarcel modesIndex = 4; 434130803Smarcel } else { 435130803Smarcel freqIndex = 1; 436130803Smarcel if (IEEE80211_IS_CHAN_HT40(chan) || 437130803Smarcel IEEE80211_IS_CHAN_TURBO(chan)) 438130803Smarcel modesIndex = 2; 439130803Smarcel else 440130803Smarcel modesIndex = 1; 441130803Smarcel } 442130803Smarcel 443130803Smarcel /* Set correct Baseband to analog shift setting to access analog chips. */ 444130803Smarcel OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 445130803Smarcel OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 446130803Smarcel 447130803Smarcel /* 448130803Smarcel * This is unwound because at the moment, there's a requirement 449130803Smarcel * for Merlin (and later, perhaps) to have a specific bit fixed 450130803Smarcel * in the AR_AN_TOP2 register before writing it. 451130803Smarcel */ 452130803Smarcel ia = &AH5212(ah)->ah_ini_modes; 453130803Smarcel#if 0 454130803Smarcel regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 455130803Smarcel modesIndex, regWrites); 456130803Smarcel#endif 457130803Smarcel HALASSERT(modesIndex < ia->cols); 458130803Smarcel for (i = 0; i < ia->rows; i++) { 459130803Smarcel uint32_t reg = HAL_INI_VAL(ia, i, 0); 460130803Smarcel uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 461130803Smarcel 462130803Smarcel if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 463130803Smarcel val &= ~AR_AN_TOP2_PWDCLKIND; 464130803Smarcel 465130803Smarcel OS_REG_WRITE(ah, reg, val); 466130803Smarcel 467130803Smarcel /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 468130803Smarcel if (reg >= 0x7800 && reg < 0x7900) 469130803Smarcel OS_DELAY(100); 470130803Smarcel 471130803Smarcel DMA_YIELD(regWrites); 472130803Smarcel } 473130803Smarcel 474130803Smarcel if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 475130803Smarcel regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 476130803Smarcel modesIndex, regWrites); 477130803Smarcel regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 478130803Smarcel modesIndex, regWrites); 479130803Smarcel } 480130803Smarcel /* XXX Merlin 100us delay for shift registers */ 481130803Smarcel regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 482130803Smarcel 1, regWrites); 483130803Smarcel 484130803Smarcel if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 485130803Smarcel /* 5GHz channels w/ Fast Clock use different modal values */ 486130803Smarcel regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 487130803Smarcel modesIndex, regWrites); 488130803Smarcel } 489130803Smarcel} 490130803Smarcel 491130803Smarcel#define AR_BASE_FREQ_2GHZ 2300 492130803Smarcel#define AR_BASE_FREQ_5GHZ 4900 493130803Smarcel#define AR_SPUR_FEEQ_BOUND_HT40 19 494130803Smarcel#define AR_SPUR_FEEQ_BOUND_HT20 10 495130803Smarcel 496130803Smarcelvoid 497130803Smarcelar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 498130803Smarcel{ 499130803Smarcel static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 500130803Smarcel AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 501130803Smarcel static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 502130803Smarcel AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 503130803Smarcel static int inc[4] = { 0, 100, 0, 0 }; 504130803Smarcel 505130803Smarcel int bb_spur = AR_NO_SPUR; 506130803Smarcel int freq; 507130803Smarcel int bin, cur_bin; 508130803Smarcel int bb_spur_off, spur_subchannel_sd; 509130803Smarcel int spur_freq_sd; 510130803Smarcel int spur_delta_phase; 511130803Smarcel int denominator; 512130803Smarcel int upper, lower, cur_vit_mask; 513130803Smarcel int tmp, newVal; 514130803Smarcel int i; 515130803Smarcel CHAN_CENTERS centers; 516130803Smarcel 517130803Smarcel int8_t mask_m[123]; 518130803Smarcel int8_t mask_p[123]; 519130803Smarcel int8_t mask_amt; 520130803Smarcel int tmp_mask; 521130803Smarcel int cur_bb_spur; 522130803Smarcel HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 523130803Smarcel 524130803Smarcel OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 525130803Smarcel OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 526130803Smarcel 527130803Smarcel ar5416GetChannelCenters(ah, chan, ¢ers); 528130803Smarcel freq = centers.synth_center; 529130803Smarcel 530130803Smarcel /* 531130803Smarcel * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 532130803Smarcel * otherwise spur is out-of-band and can be ignored. 533130803Smarcel */ 534130803Smarcel for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 535130803Smarcel cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 536130803Smarcel /* Get actual spur freq in MHz from EEPROM read value */ 537130803Smarcel if (is2GHz) { 538130803Smarcel cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 539130803Smarcel } else { 540130803Smarcel cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 541130803Smarcel } 542130803Smarcel 543130803Smarcel if (AR_NO_SPUR == cur_bb_spur) 544130803Smarcel break; 545130803Smarcel cur_bb_spur = cur_bb_spur - freq; 546130803Smarcel 547130803Smarcel if (IEEE80211_IS_CHAN_HT40(chan)) { 548130803Smarcel if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 549130803Smarcel (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 550130803Smarcel bb_spur = cur_bb_spur; 551130803Smarcel break; 552130803Smarcel } 553130803Smarcel } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 554130803Smarcel (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 555130803Smarcel bb_spur = cur_bb_spur; 556130803Smarcel break; 557130803Smarcel } 558130803Smarcel } 559130803Smarcel 560130803Smarcel if (AR_NO_SPUR == bb_spur) { 561130803Smarcel#if 1 562130803Smarcel /* 563130803Smarcel * MRC CCK can interfere with beacon detection and cause deaf/mute. 564130803Smarcel * Disable MRC CCK for now. 565130803Smarcel */ 566130803Smarcel OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 567130803Smarcel#else 568130803Smarcel /* Enable MRC CCK if no spur is found in this channel. */ 569130803Smarcel OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 570130803Smarcel#endif 571130803Smarcel return; 572130803Smarcel } else { 573130803Smarcel /* 574130803Smarcel * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 575130803Smarcel * is found in this channel. 576130803Smarcel */ 577130803Smarcel OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 578130803Smarcel } 579130803Smarcel 580130803Smarcel bin = bb_spur * 320; 581130803Smarcel 582130803Smarcel tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 583130803Smarcel 584130803Smarcel newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 585130803Smarcel AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 586130803Smarcel AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 587130803Smarcel AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 588130803Smarcel OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 589130803Smarcel 590130803Smarcel newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 591130803Smarcel AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 592130803Smarcel AR_PHY_SPUR_REG_MASK_RATE_SELECT | 593130803Smarcel AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 594130803Smarcel SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 595130803Smarcel OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 596130803Smarcel 597130803Smarcel /* Pick control or extn channel to cancel the spur */ 598130803Smarcel if (IEEE80211_IS_CHAN_HT40(chan)) { 599130803Smarcel if (bb_spur < 0) { 600130803Smarcel spur_subchannel_sd = 1; 601130803Smarcel bb_spur_off = bb_spur + 10; 602130803Smarcel } else { 603130803Smarcel spur_subchannel_sd = 0; 604130803Smarcel bb_spur_off = bb_spur - 10; 605130803Smarcel } 606130803Smarcel } else { 607130803Smarcel spur_subchannel_sd = 0; 608130803Smarcel bb_spur_off = bb_spur; 609130803Smarcel } 610130803Smarcel 611130803Smarcel /* 612130803Smarcel * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 613130803Smarcel * /80 for dyn2040. 614130803Smarcel */ 615130803Smarcel if (IEEE80211_IS_CHAN_HT40(chan)) 616130803Smarcel spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 617130803Smarcel else 618130803Smarcel spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 619130803Smarcel 620130803Smarcel /* 621130803Smarcel * in 11A mode the denominator of spur_freq_sd should be 40 and 622130803Smarcel * it should be 44 in 11G 623130803Smarcel */ 624130803Smarcel denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 625130803Smarcel spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 626130803Smarcel 627130803Smarcel newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 628130803Smarcel SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 629130803Smarcel SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 630130803Smarcel OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 631130803Smarcel 632130803Smarcel /* Choose to cancel between control and extension channels */ 633130803Smarcel newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 634130803Smarcel OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 635130803Smarcel 636130803Smarcel /* 637130803Smarcel * ============================================ 638130803Smarcel * Set Pilot and Channel Masks 639130803Smarcel * 640130803Smarcel * pilot mask 1 [31:0] = +6..-26, no 0 bin 641130803Smarcel * pilot mask 2 [19:0] = +26..+7 642130803Smarcel * 643130803Smarcel * channel mask 1 [31:0] = +6..-26, no 0 bin 644130803Smarcel * channel mask 2 [19:0] = +26..+7 645130803Smarcel */ 646130803Smarcel cur_bin = -6000; 647130803Smarcel upper = bin + 100; 648130803Smarcel lower = bin - 100; 649130803Smarcel 650130803Smarcel for (i = 0; i < 4; i++) { 651130803Smarcel int pilot_mask = 0; 652130803Smarcel int chan_mask = 0; 653130803Smarcel int bp = 0; 654130803Smarcel for (bp = 0; bp < 30; bp++) { 655 if ((cur_bin > lower) && (cur_bin < upper)) { 656 pilot_mask = pilot_mask | 0x1 << bp; 657 chan_mask = chan_mask | 0x1 << bp; 658 } 659 cur_bin += 100; 660 } 661 cur_bin += inc[i]; 662 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 663 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 664 } 665 666 /* ================================================= 667 * viterbi mask 1 based on channel magnitude 668 * four levels 0-3 669 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 670 * [1 2 2 1] for -9.6 or [1 2 1] for +16 671 * - enable_mask_ppm, all bins move with freq 672 * 673 * - mask_select, 8 bits for rates (reg 67,0x990c) 674 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 675 * choose which mask to use mask or mask2 676 */ 677 678 /* 679 * viterbi mask 2 2nd set for per data rate puncturing 680 * four levels 0-3 681 * - mask_select, 8 bits for rates (reg 67) 682 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 683 * [1 2 2 1] for -9.6 or [1 2 1] for +16 684 */ 685 cur_vit_mask = 6100; 686 upper = bin + 120; 687 lower = bin - 120; 688 689 for (i = 0; i < 123; i++) { 690 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 691 if ((abs(cur_vit_mask - bin)) < 75) { 692 mask_amt = 1; 693 } else { 694 mask_amt = 0; 695 } 696 if (cur_vit_mask < 0) { 697 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 698 } else { 699 mask_p[cur_vit_mask / 100] = mask_amt; 700 } 701 } 702 cur_vit_mask -= 100; 703 } 704 705 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 706 | (mask_m[48] << 26) | (mask_m[49] << 24) 707 | (mask_m[50] << 22) | (mask_m[51] << 20) 708 | (mask_m[52] << 18) | (mask_m[53] << 16) 709 | (mask_m[54] << 14) | (mask_m[55] << 12) 710 | (mask_m[56] << 10) | (mask_m[57] << 8) 711 | (mask_m[58] << 6) | (mask_m[59] << 4) 712 | (mask_m[60] << 2) | (mask_m[61] << 0); 713 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 714 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 715 716 tmp_mask = (mask_m[31] << 28) 717 | (mask_m[32] << 26) | (mask_m[33] << 24) 718 | (mask_m[34] << 22) | (mask_m[35] << 20) 719 | (mask_m[36] << 18) | (mask_m[37] << 16) 720 | (mask_m[48] << 14) | (mask_m[39] << 12) 721 | (mask_m[40] << 10) | (mask_m[41] << 8) 722 | (mask_m[42] << 6) | (mask_m[43] << 4) 723 | (mask_m[44] << 2) | (mask_m[45] << 0); 724 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 725 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 726 727 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 728 | (mask_m[18] << 26) | (mask_m[18] << 24) 729 | (mask_m[20] << 22) | (mask_m[20] << 20) 730 | (mask_m[22] << 18) | (mask_m[22] << 16) 731 | (mask_m[24] << 14) | (mask_m[24] << 12) 732 | (mask_m[25] << 10) | (mask_m[26] << 8) 733 | (mask_m[27] << 6) | (mask_m[28] << 4) 734 | (mask_m[29] << 2) | (mask_m[30] << 0); 735 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 736 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 737 738 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 739 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 740 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 741 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 742 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 743 | (mask_m[10] << 10) | (mask_m[11] << 8) 744 | (mask_m[12] << 6) | (mask_m[13] << 4) 745 | (mask_m[14] << 2) | (mask_m[15] << 0); 746 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 747 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 748 749 tmp_mask = (mask_p[15] << 28) 750 | (mask_p[14] << 26) | (mask_p[13] << 24) 751 | (mask_p[12] << 22) | (mask_p[11] << 20) 752 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 753 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 754 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 755 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 756 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 757 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 758 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 759 760 tmp_mask = (mask_p[30] << 28) 761 | (mask_p[29] << 26) | (mask_p[28] << 24) 762 | (mask_p[27] << 22) | (mask_p[26] << 20) 763 | (mask_p[25] << 18) | (mask_p[24] << 16) 764 | (mask_p[23] << 14) | (mask_p[22] << 12) 765 | (mask_p[21] << 10) | (mask_p[20] << 8) 766 | (mask_p[19] << 6) | (mask_p[18] << 4) 767 | (mask_p[17] << 2) | (mask_p[16] << 0); 768 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 769 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 770 771 tmp_mask = (mask_p[45] << 28) 772 | (mask_p[44] << 26) | (mask_p[43] << 24) 773 | (mask_p[42] << 22) | (mask_p[41] << 20) 774 | (mask_p[40] << 18) | (mask_p[39] << 16) 775 | (mask_p[38] << 14) | (mask_p[37] << 12) 776 | (mask_p[36] << 10) | (mask_p[35] << 8) 777 | (mask_p[34] << 6) | (mask_p[33] << 4) 778 | (mask_p[32] << 2) | (mask_p[31] << 0); 779 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 780 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 781 782 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 783 | (mask_p[59] << 26) | (mask_p[58] << 24) 784 | (mask_p[57] << 22) | (mask_p[56] << 20) 785 | (mask_p[55] << 18) | (mask_p[54] << 16) 786 | (mask_p[53] << 14) | (mask_p[52] << 12) 787 | (mask_p[51] << 10) | (mask_p[50] << 8) 788 | (mask_p[49] << 6) | (mask_p[48] << 4) 789 | (mask_p[47] << 2) | (mask_p[46] << 0); 790 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 791 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 792} 793 794/* 795 * Fill all software cached or static hardware state information. 796 * Return failure if capabilities are to come from EEPROM and 797 * cannot be read. 798 */ 799static HAL_BOOL 800ar9280FillCapabilityInfo(struct ath_hal *ah) 801{ 802 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 803 804 if (!ar5416FillCapabilityInfo(ah)) 805 return AH_FALSE; 806 pCap->halNumGpioPins = 10; 807 pCap->halWowSupport = AH_TRUE; 808 pCap->halWowMatchPatternExact = AH_TRUE; 809#if 0 810 pCap->halWowMatchPatternDword = AH_TRUE; 811#endif 812 /* AR9280 is a 2x2 stream device */ 813 pCap->halTxStreams = 2; 814 pCap->halRxStreams = 2; 815 816 pCap->halCSTSupport = AH_TRUE; 817 pCap->halRifsRxSupport = AH_TRUE; 818 pCap->halRifsTxSupport = AH_TRUE; 819 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 820 pCap->halExtChanDfsSupport = AH_TRUE; 821 pCap->halUseCombinedRadarRssi = AH_TRUE; 822#if 0 823 /* XXX bluetooth */ 824 pCap->halBtCoexSupport = AH_TRUE; 825#endif 826 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 827 pCap->hal4kbSplitTransSupport = AH_FALSE; 828 /* Disable this so Block-ACK works correctly */ 829 pCap->halHasRxSelfLinkedTail = AH_FALSE; 830 pCap->halMbssidAggrSupport = AH_TRUE; 831 pCap->hal4AddrAggrSupport = AH_TRUE; 832 833 if (AR_SREV_MERLIN_20(ah)) { 834 pCap->halPSPollBroken = AH_FALSE; 835 /* 836 * This just enables the support; it doesn't 837 * state 5ghz fast clock will always be used. 838 */ 839 pCap->halSupportsFastClock5GHz = AH_TRUE; 840 } 841 pCap->halRxStbcSupport = 1; 842 pCap->halTxStbcSupport = 1; 843 pCap->halEnhancedDfsSupport = AH_TRUE; 844 845 return AH_TRUE; 846} 847 848/* 849 * This has been disabled - having the HAL flip chainmasks on/off 850 * when attempting to implement 11n disrupts things. For now, just 851 * leave this flipped off and worry about implementing TX diversity 852 * for legacy and MCS0-7 when 11n is fully functioning. 853 */ 854HAL_BOOL 855ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 856{ 857#define ANTENNA0_CHAINMASK 0x1 858#define ANTENNA1_CHAINMASK 0x2 859#if 0 860 struct ath_hal_5416 *ahp = AH5416(ah); 861 862 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 863 switch (settings) { 864 case HAL_ANT_FIXED_A: 865 /* Enable first antenna only */ 866 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 867 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 868 break; 869 case HAL_ANT_FIXED_B: 870 /* Enable second antenna only, after checking capability */ 871 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 872 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 873 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 874 break; 875 case HAL_ANT_VARIABLE: 876 /* Restore original chainmask settings */ 877 /* XXX */ 878 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 879 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 880 break; 881 } 882 883 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 884 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 885 886#endif 887 return AH_TRUE; 888#undef ANTENNA0_CHAINMASK 889#undef ANTENNA1_CHAINMASK 890} 891 892static const char* 893ar9280Probe(uint16_t vendorid, uint16_t devid) 894{ 895 if (vendorid == ATHEROS_VENDOR_ID && 896 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 897 return "Atheros 9280"; 898 return AH_NULL; 899} 900AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 901