ar9280_attach.c revision 224515
1189747Ssam/* 2189747Ssam * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3189747Ssam * Copyright (c) 2008 Atheros Communications, Inc. 4189747Ssam * 5189747Ssam * Permission to use, copy, modify, and/or distribute this software for any 6189747Ssam * purpose with or without fee is hereby granted, provided that the above 7189747Ssam * copyright notice and this permission notice appear in all copies. 8189747Ssam * 9189747Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10189747Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11189747Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12189747Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13189747Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14189747Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15189747Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16189747Ssam * 17189747Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 224515 2011-07-30 13:31:27Z adrian $ 18189747Ssam */ 19189747Ssam#include "opt_ah.h" 20189747Ssam 21189747Ssam#include "ah.h" 22189747Ssam#include "ah_internal.h" 23189747Ssam#include "ah_devid.h" 24189747Ssam 25189747Ssam#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26189747Ssam 27217631Sadrian#include "ar9002/ar9280.h" 28189747Ssam#include "ar5416/ar5416reg.h" 29189747Ssam#include "ar5416/ar5416phy.h" 30189747Ssam 31217631Sadrian#include "ar9002/ar9280v1.ini" 32217631Sadrian#include "ar9002/ar9280v2.ini" 33219393Sadrian#include "ar9002/ar9280_olc.h" 34189747Ssam 35189747Ssamstatic const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36189747Ssam .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 38189747Ssam .calCountMax = PER_MAX_LOG_COUNT, 39189747Ssam .calCollect = ar5416IQCalCollect, 40189747Ssam .calPostProc = ar5416IQCalibration 41189747Ssam}; 42189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43189747Ssam .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 45224515Sadrian .calCountMax = PER_MAX_LOG_COUNT, 46189747Ssam .calCollect = ar5416AdcGainCalCollect, 47189747Ssam .calPostProc = ar5416AdcGainCalibration 48189747Ssam}; 49189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50189747Ssam .calName = "ADC DC", .calType = ADC_DC_CAL, 51189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 52224515Sadrian .calCountMax = PER_MAX_LOG_COUNT, 53189747Ssam .calCollect = ar5416AdcDcCalCollect, 54189747Ssam .calPostProc = ar5416AdcDcCalibration 55189747Ssam}; 56189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57189747Ssam .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 59189747Ssam .calCountMax = INIT_LOG_COUNT, 60189747Ssam .calCollect = ar5416AdcDcCalCollect, 61189747Ssam .calPostProc = ar5416AdcDcCalibration 62189747Ssam}; 63189747Ssam 64189747Ssamstatic void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 65189747Ssamstatic HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 66189747Ssamstatic void ar9280WriteIni(struct ath_hal *ah, 67189747Ssam const struct ieee80211_channel *chan); 68189747Ssam 69189747Ssamstatic void 70189747Ssamar9280AniSetup(struct ath_hal *ah) 71189747Ssam{ 72218764Sadrian /* 73218764Sadrian * These are the parameters from the AR5416 ANI code; 74218764Sadrian * they likely need quite a bit of adjustment for the 75218764Sadrian * AR9280. 76218764Sadrian */ 77218764Sadrian static const struct ar5212AniParams aniparams = { 78218764Sadrian .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 79218764Sadrian .totalSizeDesired = { -55, -55, -55, -55, -62 }, 80218764Sadrian .coarseHigh = { -14, -14, -14, -14, -12 }, 81218764Sadrian .coarseLow = { -64, -64, -64, -64, -70 }, 82218764Sadrian .firpwr = { -78, -78, -78, -78, -80 }, 83218764Sadrian .maxSpurImmunityLevel = 2, 84218764Sadrian .cycPwrThr1 = { 2, 4, 6 }, 85218764Sadrian .maxFirstepLevel = 2, /* levels 0..2 */ 86218764Sadrian .firstep = { 0, 4, 8 }, 87218764Sadrian .ofdmTrigHigh = 500, 88218764Sadrian .ofdmTrigLow = 200, 89218764Sadrian .cckTrigHigh = 200, 90218764Sadrian .cckTrigLow = 100, 91218764Sadrian .rssiThrHigh = 40, 92218764Sadrian .rssiThrLow = 7, 93218764Sadrian .period = 100, 94218764Sadrian }; 95218764Sadrian /* NB: disable ANI noise immmunity for reliable RIFS rx */ 96222276Sadrian AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 97218764Sadrian 98218764Sadrian /* NB: ANI is not enabled yet */ 99219979Sadrian ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 100189747Ssam} 101189747Ssam 102224243Sadrianvoid 103224243Sadrianar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 104224243Sadrian{ 105224243Sadrian uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 106224243Sadrian 107224243Sadrian if (AR_SREV_MERLIN_20(ah) && 108224243Sadrian chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 109224243Sadrian /* 110224243Sadrian * PLL WAR for Merlin 2.0/2.1 111224243Sadrian * When doing fast clock, set PLL to 0x142c 112224243Sadrian * Else, set PLL to 0x2850 to prevent reset-to-reset variation 113224243Sadrian */ 114224243Sadrian pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 115224243Sadrian } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 116224243Sadrian pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 117224243Sadrian if (chan != AH_NULL) { 118224243Sadrian if (IEEE80211_IS_CHAN_HALF(chan)) 119224243Sadrian pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 120224243Sadrian else if (IEEE80211_IS_CHAN_QUARTER(chan)) 121224243Sadrian pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 122224243Sadrian if (IEEE80211_IS_CHAN_5GHZ(chan)) 123224243Sadrian pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 124224243Sadrian else 125224243Sadrian pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 126224243Sadrian } else 127224243Sadrian pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 128224243Sadrian } 129224243Sadrian 130224243Sadrian OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 131224243Sadrian OS_DELAY(RTC_PLL_SETTLE_DELAY); 132224243Sadrian OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 133224243Sadrian} 134224243Sadrian 135221875Sadrian/* XXX shouldn't be here! */ 136221875Sadrian#define EEP_MINOR(_ah) \ 137221875Sadrian (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 138221875Sadrian 139189747Ssam/* 140189747Ssam * Attach for an AR9280 part. 141189747Ssam */ 142189747Ssamstatic struct ath_hal * 143189747Ssamar9280Attach(uint16_t devid, HAL_SOFTC sc, 144217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 145217624Sadrian HAL_STATUS *status) 146189747Ssam{ 147189747Ssam struct ath_hal_9280 *ahp9280; 148189747Ssam struct ath_hal_5212 *ahp; 149189747Ssam struct ath_hal *ah; 150189747Ssam uint32_t val; 151189747Ssam HAL_STATUS ecode; 152189747Ssam HAL_BOOL rfStatus; 153219393Sadrian int8_t pwr_table_offset; 154219441Sadrian uint8_t pwr; 155189747Ssam 156223466Sadrian HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 157189747Ssam __func__, sc, (void*) st, (void*) sh); 158189747Ssam 159189747Ssam /* NB: memory is returned zero'd */ 160189747Ssam ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 161189747Ssam if (ahp9280 == AH_NULL) { 162223466Sadrian HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY, 163189747Ssam "%s: cannot allocate memory for state block\n", __func__); 164189747Ssam *status = HAL_ENOMEM; 165189747Ssam return AH_NULL; 166189747Ssam } 167189747Ssam ahp = AH5212(ahp9280); 168189747Ssam ah = &ahp->ah_priv.h; 169189747Ssam 170189747Ssam ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 171189747Ssam 172189747Ssam /* XXX override with 9280 specific state */ 173189747Ssam /* override 5416 methods for our needs */ 174224243Sadrian AH5416(ah)->ah_initPLL = ar9280InitPLL; 175224243Sadrian 176189747Ssam ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 177189747Ssam ah->ah_configPCIE = ar9280ConfigPCIE; 178189747Ssam 179189747Ssam AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 180189747Ssam AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 181189747Ssam AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 182189747Ssam AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 183189747Ssam AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 184189747Ssam 185189747Ssam AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 186189747Ssam AH5416(ah)->ah_writeIni = ar9280WriteIni; 187219393Sadrian AH5416(ah)->ah_olcInit = ar9280olcInit; 188219393Sadrian AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 189219393Sadrian AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 190219393Sadrian 191189747Ssam AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 192189747Ssam AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 193189747Ssam 194189747Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 195189747Ssam /* reset chip */ 196189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 197189747Ssam __func__); 198189747Ssam ecode = HAL_EIO; 199189747Ssam goto bad; 200189747Ssam } 201189747Ssam 202189747Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 203189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 204189747Ssam __func__); 205189747Ssam ecode = HAL_EIO; 206189747Ssam goto bad; 207189747Ssam } 208189747Ssam /* Read Revisions from Chips before taking out of reset */ 209189747Ssam val = OS_REG_READ(ah, AR_SREV); 210189747Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 211189747Ssam "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 212189747Ssam __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 213189747Ssam MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 214189747Ssam /* NB: include chip type to differentiate from pre-Sowl versions */ 215189747Ssam AH_PRIVATE(ah)->ah_macVersion = 216189747Ssam (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 217189747Ssam AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 218189747Ssam AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 219189747Ssam 220189747Ssam /* setup common ini data; rf backends handle remainder */ 221203882Srpaulo if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 222189747Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 223189747Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 224189747Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 225189747Ssam ar9280PciePhy_clkreq_always_on_L1_v2, 2); 226189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 227189747Ssam ar9280Modes_fast_clock_v2, 3); 228189747Ssam } else { 229189747Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 230189747Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 231189747Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 232189747Ssam ar9280PciePhy_v1, 2); 233189747Ssam } 234189747Ssam ar5416AttachPCIE(ah); 235189747Ssam 236203882Srpaulo ecode = ath_hal_v14EepromAttach(ah); 237189747Ssam if (ecode != HAL_OK) 238189747Ssam goto bad; 239189747Ssam 240189747Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 241189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 242189747Ssam ecode = HAL_EIO; 243189747Ssam goto bad; 244189747Ssam } 245189747Ssam 246189747Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 247189747Ssam 248189747Ssam if (!ar5212ChipTest(ah)) { 249189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 250189747Ssam __func__); 251189747Ssam ecode = HAL_ESELFTEST; 252189747Ssam goto bad; 253189747Ssam } 254189747Ssam 255189747Ssam /* 256189747Ssam * Set correct Baseband to analog shift 257189747Ssam * setting to access analog chips. 258189747Ssam */ 259189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 260189747Ssam 261189747Ssam /* Read Radio Chip Rev Extract */ 262189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 263189747Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 264189747Ssam case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 265189747Ssam case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 266189747Ssam break; 267189747Ssam default: 268189747Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 269189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 270189747Ssam AR_RAD5133_SREV_MAJOR; 271189747Ssam break; 272189747Ssam } 273189747Ssam#ifdef AH_DEBUG 274189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 275189747Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 276189747Ssam "this driver\n", __func__, 277189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 278189747Ssam ecode = HAL_ENOTSUPP; 279189747Ssam goto bad; 280189747Ssam#endif 281189747Ssam } 282189747Ssam rfStatus = ar9280RfAttach(ah, &ecode); 283189747Ssam if (!rfStatus) { 284189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 285189747Ssam __func__, ecode); 286189747Ssam goto bad; 287189747Ssam } 288189747Ssam 289219441Sadrian /* Enable fixup for AR_AN_TOP2 if necessary */ 290219441Sadrian /* 291219441Sadrian * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 292219441Sadrian * by the EEPROM version. 293219441Sadrian * 294219441Sadrian * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 295219441Sadrian * the abstracted EEPROM access layer. 296219441Sadrian */ 297219441Sadrian ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 298219441Sadrian if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 299219441Sadrian printf("[ath] enabling AN_TOP2_FIXUP\n"); 300219441Sadrian AH5416(ah)->ah_need_an_top2_fixup = 1; 301219441Sadrian } 302219441Sadrian 303219393Sadrian /* 304219393Sadrian * Check whether the power table offset isn't the default. 305219393Sadrian * This can occur with eeprom minor V21 or greater on Merlin. 306219393Sadrian */ 307219393Sadrian (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 308219445Sadrian if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 309219445Sadrian ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 310219393Sadrian AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 311219393Sadrian 312221875Sadrian /* XXX check for >= minor ver 17 */ 313221875Sadrian if (AR_SREV_MERLIN_20(ah)) { 314189747Ssam /* setup rxgain table */ 315189747Ssam switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 316189747Ssam case AR5416_EEP_RXGAIN_13dB_BACKOFF: 317189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 318189747Ssam ar9280Modes_backoff_13db_rxgain_v2, 6); 319189747Ssam break; 320189747Ssam case AR5416_EEP_RXGAIN_23dB_BACKOFF: 321189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 322189747Ssam ar9280Modes_backoff_23db_rxgain_v2, 6); 323189747Ssam break; 324189747Ssam case AR5416_EEP_RXGAIN_ORIG: 325189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 326189747Ssam ar9280Modes_original_rxgain_v2, 6); 327189747Ssam break; 328189747Ssam default: 329189747Ssam HALASSERT(AH_FALSE); 330189747Ssam goto bad; /* XXX ? try to continue */ 331189747Ssam } 332189747Ssam } 333221875Sadrian 334221875Sadrian /* XXX check for >= minor ver 19 */ 335221875Sadrian if (AR_SREV_MERLIN_20(ah)) { 336189747Ssam /* setp txgain table */ 337189747Ssam switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 338189747Ssam case AR5416_EEP_TXGAIN_HIGH_POWER: 339189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_txgain, 340189747Ssam ar9280Modes_high_power_tx_gain_v2, 6); 341189747Ssam break; 342189747Ssam case AR5416_EEP_TXGAIN_ORIG: 343189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_txgain, 344189747Ssam ar9280Modes_original_tx_gain_v2, 6); 345189747Ssam break; 346189747Ssam default: 347189747Ssam HALASSERT(AH_FALSE); 348189747Ssam goto bad; /* XXX ? try to continue */ 349189747Ssam } 350189747Ssam } 351189747Ssam 352189747Ssam /* 353189747Ssam * Got everything we need now to setup the capabilities. 354189747Ssam */ 355189747Ssam if (!ar9280FillCapabilityInfo(ah)) { 356189747Ssam ecode = HAL_EEREAD; 357189747Ssam goto bad; 358189747Ssam } 359189747Ssam 360189747Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 361189747Ssam if (ecode != HAL_OK) { 362189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 363189747Ssam "%s: error getting mac address from EEPROM\n", __func__); 364189747Ssam goto bad; 365189747Ssam } 366189747Ssam /* XXX How about the serial number ? */ 367189747Ssam /* Read Reg Domain */ 368189747Ssam AH_PRIVATE(ah)->ah_currentRD = 369189747Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 370221596Sadrian AH_PRIVATE(ah)->ah_currentRDext = 371221596Sadrian ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 372189747Ssam 373189747Ssam /* 374189747Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 375189747Ssam * starting from griffin. Set here to make sure that 376189747Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 377189747Ssam * placed into hardware. 378189747Ssam */ 379189747Ssam if (ahp->ah_miscMode != 0) 380219852Sadrian OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 381189747Ssam 382189747Ssam ar9280AniSetup(ah); /* Anti Noise Immunity */ 383218068Sadrian 384218068Sadrian /* Setup noise floor min/max/nominal values */ 385218068Sadrian AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 386218068Sadrian AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 387218068Sadrian AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 388218068Sadrian AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 389218068Sadrian AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 390218068Sadrian AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 391218068Sadrian 392203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 393189747Ssam 394189747Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 395189747Ssam 396189747Ssam return ah; 397189747Ssambad: 398189747Ssam if (ah != AH_NULL) 399189747Ssam ah->ah_detach(ah); 400189747Ssam if (status) 401189747Ssam *status = ecode; 402189747Ssam return AH_NULL; 403189747Ssam} 404189747Ssam 405189747Ssamstatic void 406189747Ssamar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 407189747Ssam{ 408189747Ssam if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 409189747Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 410189747Ssam OS_DELAY(1000); 411189747Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 412203882Srpaulo OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 413189747Ssam } 414189747Ssam} 415189747Ssam 416189747Ssamstatic void 417189747Ssamar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 418189747Ssam{ 419189747Ssam u_int modesIndex, freqIndex; 420189747Ssam int regWrites = 0; 421219441Sadrian int i; 422219441Sadrian const HAL_INI_ARRAY *ia; 423189747Ssam 424189747Ssam /* Setup the indices for the next set of register array writes */ 425189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 426189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 427189747Ssam freqIndex = 2; 428189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 429189747Ssam modesIndex = 3; 430189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 431189747Ssam modesIndex = 5; 432189747Ssam else 433189747Ssam modesIndex = 4; 434189747Ssam } else { 435189747Ssam freqIndex = 1; 436189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 437189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 438189747Ssam modesIndex = 2; 439189747Ssam else 440189747Ssam modesIndex = 1; 441189747Ssam } 442189747Ssam 443189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 444189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 445189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 446189747Ssam 447219441Sadrian /* 448219441Sadrian * This is unwound because at the moment, there's a requirement 449219441Sadrian * for Merlin (and later, perhaps) to have a specific bit fixed 450219441Sadrian * in the AR_AN_TOP2 register before writing it. 451219441Sadrian */ 452219441Sadrian ia = &AH5212(ah)->ah_ini_modes; 453219441Sadrian#if 0 454189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 455189747Ssam modesIndex, regWrites); 456219441Sadrian#endif 457219441Sadrian HALASSERT(modesIndex < ia->cols); 458219441Sadrian for (i = 0; i < ia->rows; i++) { 459219441Sadrian uint32_t reg = HAL_INI_VAL(ia, i, 0); 460219441Sadrian uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 461219441Sadrian 462219441Sadrian if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 463219441Sadrian val &= ~AR_AN_TOP2_PWDCLKIND; 464219441Sadrian 465219441Sadrian OS_REG_WRITE(ah, reg, val); 466219441Sadrian 467219441Sadrian /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 468222157Sadrian if (reg >= 0x7800 && reg < 0x7900) 469219441Sadrian OS_DELAY(100); 470219441Sadrian 471219441Sadrian DMA_YIELD(regWrites); 472219441Sadrian } 473219441Sadrian 474189747Ssam if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 475189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 476189747Ssam modesIndex, regWrites); 477189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 478189747Ssam modesIndex, regWrites); 479189747Ssam } 480189747Ssam /* XXX Merlin 100us delay for shift registers */ 481189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 482189747Ssam 1, regWrites); 483189747Ssam 484189747Ssam if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 485189747Ssam /* 5GHz channels w/ Fast Clock use different modal values */ 486189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 487189747Ssam modesIndex, regWrites); 488189747Ssam } 489189747Ssam} 490189747Ssam 491189747Ssam#define AR_BASE_FREQ_2GHZ 2300 492189747Ssam#define AR_BASE_FREQ_5GHZ 4900 493189747Ssam#define AR_SPUR_FEEQ_BOUND_HT40 19 494189747Ssam#define AR_SPUR_FEEQ_BOUND_HT20 10 495189747Ssam 496203930Srpaulovoid 497189747Ssamar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 498189747Ssam{ 499189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 500189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 501189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 502189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 503189747Ssam static int inc[4] = { 0, 100, 0, 0 }; 504189747Ssam 505189747Ssam int bb_spur = AR_NO_SPUR; 506189747Ssam int freq; 507189747Ssam int bin, cur_bin; 508189747Ssam int bb_spur_off, spur_subchannel_sd; 509189747Ssam int spur_freq_sd; 510189747Ssam int spur_delta_phase; 511189747Ssam int denominator; 512189747Ssam int upper, lower, cur_vit_mask; 513189747Ssam int tmp, newVal; 514189747Ssam int i; 515189747Ssam CHAN_CENTERS centers; 516189747Ssam 517189747Ssam int8_t mask_m[123]; 518189747Ssam int8_t mask_p[123]; 519189747Ssam int8_t mask_amt; 520189747Ssam int tmp_mask; 521189747Ssam int cur_bb_spur; 522189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 523189747Ssam 524189747Ssam OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 525189747Ssam OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 526189747Ssam 527189747Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 528189747Ssam freq = centers.synth_center; 529189747Ssam 530189747Ssam /* 531189747Ssam * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 532189747Ssam * otherwise spur is out-of-band and can be ignored. 533189747Ssam */ 534189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 535189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 536189747Ssam /* Get actual spur freq in MHz from EEPROM read value */ 537189747Ssam if (is2GHz) { 538189747Ssam cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 539189747Ssam } else { 540189747Ssam cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 541189747Ssam } 542189747Ssam 543189747Ssam if (AR_NO_SPUR == cur_bb_spur) 544189747Ssam break; 545189747Ssam cur_bb_spur = cur_bb_spur - freq; 546189747Ssam 547189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 548189747Ssam if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 549189747Ssam (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 550189747Ssam bb_spur = cur_bb_spur; 551189747Ssam break; 552189747Ssam } 553189747Ssam } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 554189747Ssam (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 555189747Ssam bb_spur = cur_bb_spur; 556189747Ssam break; 557189747Ssam } 558189747Ssam } 559189747Ssam 560189747Ssam if (AR_NO_SPUR == bb_spur) { 561189747Ssam#if 1 562189747Ssam /* 563189747Ssam * MRC CCK can interfere with beacon detection and cause deaf/mute. 564189747Ssam * Disable MRC CCK for now. 565189747Ssam */ 566189747Ssam OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 567189747Ssam#else 568189747Ssam /* Enable MRC CCK if no spur is found in this channel. */ 569189747Ssam OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 570189747Ssam#endif 571189747Ssam return; 572189747Ssam } else { 573189747Ssam /* 574189747Ssam * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 575189747Ssam * is found in this channel. 576189747Ssam */ 577189747Ssam OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 578189747Ssam } 579189747Ssam 580189747Ssam bin = bb_spur * 320; 581189747Ssam 582189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 583189747Ssam 584189747Ssam newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 585189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 586189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 587189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 588189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 589189747Ssam 590189747Ssam newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 591189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 592189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 593189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 594189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 595189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 596189747Ssam 597189747Ssam /* Pick control or extn channel to cancel the spur */ 598189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 599189747Ssam if (bb_spur < 0) { 600189747Ssam spur_subchannel_sd = 1; 601189747Ssam bb_spur_off = bb_spur + 10; 602189747Ssam } else { 603189747Ssam spur_subchannel_sd = 0; 604189747Ssam bb_spur_off = bb_spur - 10; 605189747Ssam } 606189747Ssam } else { 607189747Ssam spur_subchannel_sd = 0; 608189747Ssam bb_spur_off = bb_spur; 609189747Ssam } 610189747Ssam 611189747Ssam /* 612189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 613189747Ssam * /80 for dyn2040. 614189747Ssam */ 615189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 616189747Ssam spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 617189747Ssam else 618189747Ssam spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 619189747Ssam 620189747Ssam /* 621189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 622189747Ssam * it should be 44 in 11G 623189747Ssam */ 624189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 625189747Ssam spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 626189747Ssam 627189747Ssam newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 628189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 629189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 630189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 631189747Ssam 632189747Ssam /* Choose to cancel between control and extension channels */ 633189747Ssam newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 634189747Ssam OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 635189747Ssam 636189747Ssam /* 637189747Ssam * ============================================ 638189747Ssam * Set Pilot and Channel Masks 639189747Ssam * 640189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 641189747Ssam * pilot mask 2 [19:0] = +26..+7 642189747Ssam * 643189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 644189747Ssam * channel mask 2 [19:0] = +26..+7 645189747Ssam */ 646189747Ssam cur_bin = -6000; 647189747Ssam upper = bin + 100; 648189747Ssam lower = bin - 100; 649189747Ssam 650189747Ssam for (i = 0; i < 4; i++) { 651189747Ssam int pilot_mask = 0; 652189747Ssam int chan_mask = 0; 653189747Ssam int bp = 0; 654189747Ssam for (bp = 0; bp < 30; bp++) { 655189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 656189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 657189747Ssam chan_mask = chan_mask | 0x1 << bp; 658189747Ssam } 659189747Ssam cur_bin += 100; 660189747Ssam } 661189747Ssam cur_bin += inc[i]; 662189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 663189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 664189747Ssam } 665189747Ssam 666189747Ssam /* ================================================= 667189747Ssam * viterbi mask 1 based on channel magnitude 668189747Ssam * four levels 0-3 669189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 670189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 671189747Ssam * - enable_mask_ppm, all bins move with freq 672189747Ssam * 673189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 674189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 675189747Ssam * choose which mask to use mask or mask2 676189747Ssam */ 677189747Ssam 678189747Ssam /* 679189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 680189747Ssam * four levels 0-3 681189747Ssam * - mask_select, 8 bits for rates (reg 67) 682189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 683189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 684189747Ssam */ 685189747Ssam cur_vit_mask = 6100; 686189747Ssam upper = bin + 120; 687189747Ssam lower = bin - 120; 688189747Ssam 689189747Ssam for (i = 0; i < 123; i++) { 690189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 691189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 692189747Ssam mask_amt = 1; 693189747Ssam } else { 694189747Ssam mask_amt = 0; 695189747Ssam } 696189747Ssam if (cur_vit_mask < 0) { 697189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 698189747Ssam } else { 699189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 700189747Ssam } 701189747Ssam } 702189747Ssam cur_vit_mask -= 100; 703189747Ssam } 704189747Ssam 705189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 706189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 707189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 708189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 709189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 710189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 711189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 712189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 713189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 714189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 715189747Ssam 716189747Ssam tmp_mask = (mask_m[31] << 28) 717189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 718189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 719189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 720189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 721189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 722189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 723189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 724189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 725189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 726189747Ssam 727189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 728189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 729189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 730189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 731189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 732189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 733189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 734189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 735189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 736189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 737189747Ssam 738189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 739189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 740189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 741189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 742189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 743189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 744189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 745189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 746189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 747189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 748189747Ssam 749189747Ssam tmp_mask = (mask_p[15] << 28) 750189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 751189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 752189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 753189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 754189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 755189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 756189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 757189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 758189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 759189747Ssam 760189747Ssam tmp_mask = (mask_p[30] << 28) 761189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 762189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 763189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 764189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 765189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 766189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 767189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 768189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 769189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 770189747Ssam 771189747Ssam tmp_mask = (mask_p[45] << 28) 772189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 773189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 774189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 775189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 776189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 777189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 778189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 779189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 780189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 781189747Ssam 782189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 783189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 784189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 785189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 786189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 787189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 788189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 789189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 790189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 791189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 792189747Ssam} 793189747Ssam 794189747Ssam/* 795189747Ssam * Fill all software cached or static hardware state information. 796189747Ssam * Return failure if capabilities are to come from EEPROM and 797189747Ssam * cannot be read. 798189747Ssam */ 799189747Ssamstatic HAL_BOOL 800189747Ssamar9280FillCapabilityInfo(struct ath_hal *ah) 801189747Ssam{ 802189747Ssam HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 803189747Ssam 804189747Ssam if (!ar5416FillCapabilityInfo(ah)) 805189747Ssam return AH_FALSE; 806203882Srpaulo pCap->halNumGpioPins = 10; 807189747Ssam pCap->halWowSupport = AH_TRUE; 808189747Ssam pCap->halWowMatchPatternExact = AH_TRUE; 809189747Ssam#if 0 810189747Ssam pCap->halWowMatchPatternDword = AH_TRUE; 811189747Ssam#endif 812218150Sadrian /* AR9280 is a 2x2 stream device */ 813218150Sadrian pCap->halTxStreams = 2; 814218150Sadrian pCap->halRxStreams = 2; 815218150Sadrian 816189747Ssam pCap->halCSTSupport = AH_TRUE; 817189747Ssam pCap->halRifsRxSupport = AH_TRUE; 818189747Ssam pCap->halRifsTxSupport = AH_TRUE; 819189747Ssam pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 820189747Ssam pCap->halExtChanDfsSupport = AH_TRUE; 821222584Sadrian pCap->halUseCombinedRadarRssi = AH_TRUE; 822189747Ssam#if 0 823189747Ssam /* XXX bluetooth */ 824189747Ssam pCap->halBtCoexSupport = AH_TRUE; 825189747Ssam#endif 826189747Ssam pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 827189747Ssam pCap->hal4kbSplitTransSupport = AH_FALSE; 828220325Sadrian /* Disable this so Block-ACK works correctly */ 829220325Sadrian pCap->halHasRxSelfLinkedTail = AH_FALSE; 830221603Sadrian pCap->halMbssidAggrSupport = AH_TRUE; 831221603Sadrian pCap->hal4AddrAggrSupport = AH_TRUE; 832221603Sadrian 833221667Sadrian if (AR_SREV_MERLIN_20(ah)) { 834221603Sadrian pCap->halPSPollBroken = AH_FALSE; 835221667Sadrian /* 836221667Sadrian * This just enables the support; it doesn't 837221667Sadrian * state 5ghz fast clock will always be used. 838221667Sadrian */ 839221667Sadrian pCap->halSupportsFastClock5GHz = AH_TRUE; 840221667Sadrian } 841189747Ssam pCap->halRxStbcSupport = 1; 842189747Ssam pCap->halTxStbcSupport = 1; 843222584Sadrian pCap->halEnhancedDfsSupport = AH_TRUE; 844189747Ssam 845189747Ssam return AH_TRUE; 846189747Ssam} 847189747Ssam 848218708Sadrian/* 849218708Sadrian * This has been disabled - having the HAL flip chainmasks on/off 850218708Sadrian * when attempting to implement 11n disrupts things. For now, just 851218708Sadrian * leave this flipped off and worry about implementing TX diversity 852218708Sadrian * for legacy and MCS0-7 when 11n is fully functioning. 853218708Sadrian */ 854189747SsamHAL_BOOL 855189747Ssamar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 856189747Ssam{ 857189747Ssam#define ANTENNA0_CHAINMASK 0x1 858189747Ssam#define ANTENNA1_CHAINMASK 0x2 859218708Sadrian#if 0 860189747Ssam struct ath_hal_5416 *ahp = AH5416(ah); 861189747Ssam 862189747Ssam /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 863189747Ssam switch (settings) { 864189747Ssam case HAL_ANT_FIXED_A: 865189747Ssam /* Enable first antenna only */ 866189747Ssam ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 867189747Ssam ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 868189747Ssam break; 869189747Ssam case HAL_ANT_FIXED_B: 870189747Ssam /* Enable second antenna only, after checking capability */ 871189747Ssam if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 872189747Ssam ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 873189747Ssam ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 874189747Ssam break; 875189747Ssam case HAL_ANT_VARIABLE: 876189747Ssam /* Restore original chainmask settings */ 877189747Ssam /* XXX */ 878217641Sadrian ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 879217641Sadrian ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 880189747Ssam break; 881189747Ssam } 882217684Sadrian 883217684Sadrian HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 884217684Sadrian __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 885217684Sadrian 886218708Sadrian#endif 887189747Ssam return AH_TRUE; 888189747Ssam#undef ANTENNA0_CHAINMASK 889189747Ssam#undef ANTENNA1_CHAINMASK 890189747Ssam} 891189747Ssam 892189747Ssamstatic const char* 893189747Ssamar9280Probe(uint16_t vendorid, uint16_t devid) 894189747Ssam{ 895203882Srpaulo if (vendorid == ATHEROS_VENDOR_ID && 896203882Srpaulo (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 897203882Srpaulo return "Atheros 9280"; 898189747Ssam return AH_NULL; 899189747Ssam} 900189747SsamAH_CHIP(AR9280, ar9280Probe, ar9280Attach); 901