ar9280_attach.c revision 218708
1/* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 218708 2011-02-15 13:29:52Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27#include "ar9002/ar9280.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar9002/ar9280v1.ini" 32#include "ar9002/ar9280v2.ini" 33 34static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 35 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 36 .calNumSamples = MIN_CAL_SAMPLES, 37 .calCountMax = PER_MAX_LOG_COUNT, 38 .calCollect = ar5416IQCalCollect, 39 .calPostProc = ar5416IQCalibration 40}; 41static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 42 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 43 .calNumSamples = MIN_CAL_SAMPLES, 44 .calCountMax = PER_MIN_LOG_COUNT, 45 .calCollect = ar5416AdcGainCalCollect, 46 .calPostProc = ar5416AdcGainCalibration 47}; 48static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 49 .calName = "ADC DC", .calType = ADC_DC_CAL, 50 .calNumSamples = MIN_CAL_SAMPLES, 51 .calCountMax = PER_MIN_LOG_COUNT, 52 .calCollect = ar5416AdcDcCalCollect, 53 .calPostProc = ar5416AdcDcCalibration 54}; 55static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 56 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 57 .calNumSamples = MIN_CAL_SAMPLES, 58 .calCountMax = INIT_LOG_COUNT, 59 .calCollect = ar5416AdcDcCalCollect, 60 .calPostProc = ar5416AdcDcCalibration 61}; 62 63static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 64static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 65static void ar9280WriteIni(struct ath_hal *ah, 66 const struct ieee80211_channel *chan); 67 68static void 69ar9280AniSetup(struct ath_hal *ah) 70{ 71 /* NB: disable ANI for reliable RIFS rx */ 72 ar5416AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE); 73} 74 75/* 76 * Attach for an AR9280 part. 77 */ 78static struct ath_hal * 79ar9280Attach(uint16_t devid, HAL_SOFTC sc, 80 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 81 HAL_STATUS *status) 82{ 83 struct ath_hal_9280 *ahp9280; 84 struct ath_hal_5212 *ahp; 85 struct ath_hal *ah; 86 uint32_t val; 87 HAL_STATUS ecode; 88 HAL_BOOL rfStatus; 89 90 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 91 __func__, sc, (void*) st, (void*) sh); 92 93 /* NB: memory is returned zero'd */ 94 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 95 if (ahp9280 == AH_NULL) { 96 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 97 "%s: cannot allocate memory for state block\n", __func__); 98 *status = HAL_ENOMEM; 99 return AH_NULL; 100 } 101 ahp = AH5212(ahp9280); 102 ah = &ahp->ah_priv.h; 103 104 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 105 106 /* XXX override with 9280 specific state */ 107 /* override 5416 methods for our needs */ 108 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 109 ah->ah_configPCIE = ar9280ConfigPCIE; 110 111 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 112 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 113 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 114 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 115 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 116 117 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 118 AH5416(ah)->ah_writeIni = ar9280WriteIni; 119 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 120 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 121 122 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 123 /* reset chip */ 124 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 125 __func__); 126 ecode = HAL_EIO; 127 goto bad; 128 } 129 130 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 131 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 132 __func__); 133 ecode = HAL_EIO; 134 goto bad; 135 } 136 /* Read Revisions from Chips before taking out of reset */ 137 val = OS_REG_READ(ah, AR_SREV); 138 HALDEBUG(ah, HAL_DEBUG_ATTACH, 139 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 140 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 141 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 142 /* NB: include chip type to differentiate from pre-Sowl versions */ 143 AH_PRIVATE(ah)->ah_macVersion = 144 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 145 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 146 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 147 148 /* setup common ini data; rf backends handle remainder */ 149 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 150 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 151 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 152 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 153 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 154 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 155 ar9280Modes_fast_clock_v2, 3); 156 } else { 157 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 158 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 159 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 160 ar9280PciePhy_v1, 2); 161 } 162 ar5416AttachPCIE(ah); 163 164 ecode = ath_hal_v14EepromAttach(ah); 165 if (ecode != HAL_OK) 166 goto bad; 167 168 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 169 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 170 ecode = HAL_EIO; 171 goto bad; 172 } 173 174 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 175 176 if (!ar5212ChipTest(ah)) { 177 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 178 __func__); 179 ecode = HAL_ESELFTEST; 180 goto bad; 181 } 182 183 /* 184 * Set correct Baseband to analog shift 185 * setting to access analog chips. 186 */ 187 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 188 189 /* Read Radio Chip Rev Extract */ 190 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 191 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 192 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 193 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 194 break; 195 default: 196 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 197 AH_PRIVATE(ah)->ah_analog5GhzRev = 198 AR_RAD5133_SREV_MAJOR; 199 break; 200 } 201#ifdef AH_DEBUG 202 HALDEBUG(ah, HAL_DEBUG_ANY, 203 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 204 "this driver\n", __func__, 205 AH_PRIVATE(ah)->ah_analog5GhzRev); 206 ecode = HAL_ENOTSUPP; 207 goto bad; 208#endif 209 } 210 rfStatus = ar9280RfAttach(ah, &ecode); 211 if (!rfStatus) { 212 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 213 __func__, ecode); 214 goto bad; 215 } 216 217 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 218 /* setup rxgain table */ 219 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 220 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 221 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 222 ar9280Modes_backoff_13db_rxgain_v2, 6); 223 break; 224 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 225 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 226 ar9280Modes_backoff_23db_rxgain_v2, 6); 227 break; 228 case AR5416_EEP_RXGAIN_ORIG: 229 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 230 ar9280Modes_original_rxgain_v2, 6); 231 break; 232 default: 233 HALASSERT(AH_FALSE); 234 goto bad; /* XXX ? try to continue */ 235 } 236 } 237 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 238 /* setp txgain table */ 239 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 240 case AR5416_EEP_TXGAIN_HIGH_POWER: 241 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 242 ar9280Modes_high_power_tx_gain_v2, 6); 243 break; 244 case AR5416_EEP_TXGAIN_ORIG: 245 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 246 ar9280Modes_original_tx_gain_v2, 6); 247 break; 248 default: 249 HALASSERT(AH_FALSE); 250 goto bad; /* XXX ? try to continue */ 251 } 252 } 253 254 /* 255 * Got everything we need now to setup the capabilities. 256 */ 257 if (!ar9280FillCapabilityInfo(ah)) { 258 ecode = HAL_EEREAD; 259 goto bad; 260 } 261 262 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 263 if (ecode != HAL_OK) { 264 HALDEBUG(ah, HAL_DEBUG_ANY, 265 "%s: error getting mac address from EEPROM\n", __func__); 266 goto bad; 267 } 268 /* XXX How about the serial number ? */ 269 /* Read Reg Domain */ 270 AH_PRIVATE(ah)->ah_currentRD = 271 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 272 273 /* 274 * ah_miscMode is populated by ar5416FillCapabilityInfo() 275 * starting from griffin. Set here to make sure that 276 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 277 * placed into hardware. 278 */ 279 if (ahp->ah_miscMode != 0) 280 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 281 282 ar9280AniSetup(ah); /* Anti Noise Immunity */ 283 284 /* Setup noise floor min/max/nominal values */ 285 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 286 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 287 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 288 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 289 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 290 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 291 292 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 293 294 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 295 296 return ah; 297bad: 298 if (ah != AH_NULL) 299 ah->ah_detach(ah); 300 if (status) 301 *status = ecode; 302 return AH_NULL; 303} 304 305static void 306ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 307{ 308 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 309 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 310 OS_DELAY(1000); 311 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 312 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 313 } 314} 315 316static void 317ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 318{ 319 u_int modesIndex, freqIndex; 320 int regWrites = 0; 321 322 /* Setup the indices for the next set of register array writes */ 323 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 324 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 325 freqIndex = 2; 326 if (IEEE80211_IS_CHAN_HT40(chan)) 327 modesIndex = 3; 328 else if (IEEE80211_IS_CHAN_108G(chan)) 329 modesIndex = 5; 330 else 331 modesIndex = 4; 332 } else { 333 freqIndex = 1; 334 if (IEEE80211_IS_CHAN_HT40(chan) || 335 IEEE80211_IS_CHAN_TURBO(chan)) 336 modesIndex = 2; 337 else 338 modesIndex = 1; 339 } 340 341 /* Set correct Baseband to analog shift setting to access analog chips. */ 342 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 343 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 344 345 /* XXX Merlin ini fixups */ 346 /* XXX Merlin 100us delay for shift registers */ 347 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 348 modesIndex, regWrites); 349 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 350 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 351 modesIndex, regWrites); 352 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 353 modesIndex, regWrites); 354 } 355 /* XXX Merlin 100us delay for shift registers */ 356 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 357 1, regWrites); 358 359 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 360 /* 5GHz channels w/ Fast Clock use different modal values */ 361 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 362 modesIndex, regWrites); 363 } 364} 365 366#define AR_BASE_FREQ_2GHZ 2300 367#define AR_BASE_FREQ_5GHZ 4900 368#define AR_SPUR_FEEQ_BOUND_HT40 19 369#define AR_SPUR_FEEQ_BOUND_HT20 10 370 371void 372ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 373{ 374 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 375 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 376 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 377 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 378 static int inc[4] = { 0, 100, 0, 0 }; 379 380 int bb_spur = AR_NO_SPUR; 381 int freq; 382 int bin, cur_bin; 383 int bb_spur_off, spur_subchannel_sd; 384 int spur_freq_sd; 385 int spur_delta_phase; 386 int denominator; 387 int upper, lower, cur_vit_mask; 388 int tmp, newVal; 389 int i; 390 CHAN_CENTERS centers; 391 392 int8_t mask_m[123]; 393 int8_t mask_p[123]; 394 int8_t mask_amt; 395 int tmp_mask; 396 int cur_bb_spur; 397 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 398 399 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 400 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 401 402 ar5416GetChannelCenters(ah, chan, ¢ers); 403 freq = centers.synth_center; 404 405 /* 406 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 407 * otherwise spur is out-of-band and can be ignored. 408 */ 409 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 410 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 411 /* Get actual spur freq in MHz from EEPROM read value */ 412 if (is2GHz) { 413 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 414 } else { 415 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 416 } 417 418 if (AR_NO_SPUR == cur_bb_spur) 419 break; 420 cur_bb_spur = cur_bb_spur - freq; 421 422 if (IEEE80211_IS_CHAN_HT40(chan)) { 423 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 424 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 425 bb_spur = cur_bb_spur; 426 break; 427 } 428 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 429 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 430 bb_spur = cur_bb_spur; 431 break; 432 } 433 } 434 435 if (AR_NO_SPUR == bb_spur) { 436#if 1 437 /* 438 * MRC CCK can interfere with beacon detection and cause deaf/mute. 439 * Disable MRC CCK for now. 440 */ 441 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 442#else 443 /* Enable MRC CCK if no spur is found in this channel. */ 444 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 445#endif 446 return; 447 } else { 448 /* 449 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 450 * is found in this channel. 451 */ 452 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 453 } 454 455 bin = bb_spur * 320; 456 457 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 458 459 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 460 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 461 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 462 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 463 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 464 465 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 466 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 467 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 468 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 469 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 470 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 471 472 /* Pick control or extn channel to cancel the spur */ 473 if (IEEE80211_IS_CHAN_HT40(chan)) { 474 if (bb_spur < 0) { 475 spur_subchannel_sd = 1; 476 bb_spur_off = bb_spur + 10; 477 } else { 478 spur_subchannel_sd = 0; 479 bb_spur_off = bb_spur - 10; 480 } 481 } else { 482 spur_subchannel_sd = 0; 483 bb_spur_off = bb_spur; 484 } 485 486 /* 487 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 488 * /80 for dyn2040. 489 */ 490 if (IEEE80211_IS_CHAN_HT40(chan)) 491 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 492 else 493 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 494 495 /* 496 * in 11A mode the denominator of spur_freq_sd should be 40 and 497 * it should be 44 in 11G 498 */ 499 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 500 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 501 502 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 503 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 504 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 505 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 506 507 /* Choose to cancel between control and extension channels */ 508 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 509 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 510 511 /* 512 * ============================================ 513 * Set Pilot and Channel Masks 514 * 515 * pilot mask 1 [31:0] = +6..-26, no 0 bin 516 * pilot mask 2 [19:0] = +26..+7 517 * 518 * channel mask 1 [31:0] = +6..-26, no 0 bin 519 * channel mask 2 [19:0] = +26..+7 520 */ 521 cur_bin = -6000; 522 upper = bin + 100; 523 lower = bin - 100; 524 525 for (i = 0; i < 4; i++) { 526 int pilot_mask = 0; 527 int chan_mask = 0; 528 int bp = 0; 529 for (bp = 0; bp < 30; bp++) { 530 if ((cur_bin > lower) && (cur_bin < upper)) { 531 pilot_mask = pilot_mask | 0x1 << bp; 532 chan_mask = chan_mask | 0x1 << bp; 533 } 534 cur_bin += 100; 535 } 536 cur_bin += inc[i]; 537 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 538 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 539 } 540 541 /* ================================================= 542 * viterbi mask 1 based on channel magnitude 543 * four levels 0-3 544 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 545 * [1 2 2 1] for -9.6 or [1 2 1] for +16 546 * - enable_mask_ppm, all bins move with freq 547 * 548 * - mask_select, 8 bits for rates (reg 67,0x990c) 549 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 550 * choose which mask to use mask or mask2 551 */ 552 553 /* 554 * viterbi mask 2 2nd set for per data rate puncturing 555 * four levels 0-3 556 * - mask_select, 8 bits for rates (reg 67) 557 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 558 * [1 2 2 1] for -9.6 or [1 2 1] for +16 559 */ 560 cur_vit_mask = 6100; 561 upper = bin + 120; 562 lower = bin - 120; 563 564 for (i = 0; i < 123; i++) { 565 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 566 if ((abs(cur_vit_mask - bin)) < 75) { 567 mask_amt = 1; 568 } else { 569 mask_amt = 0; 570 } 571 if (cur_vit_mask < 0) { 572 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 573 } else { 574 mask_p[cur_vit_mask / 100] = mask_amt; 575 } 576 } 577 cur_vit_mask -= 100; 578 } 579 580 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 581 | (mask_m[48] << 26) | (mask_m[49] << 24) 582 | (mask_m[50] << 22) | (mask_m[51] << 20) 583 | (mask_m[52] << 18) | (mask_m[53] << 16) 584 | (mask_m[54] << 14) | (mask_m[55] << 12) 585 | (mask_m[56] << 10) | (mask_m[57] << 8) 586 | (mask_m[58] << 6) | (mask_m[59] << 4) 587 | (mask_m[60] << 2) | (mask_m[61] << 0); 588 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 589 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 590 591 tmp_mask = (mask_m[31] << 28) 592 | (mask_m[32] << 26) | (mask_m[33] << 24) 593 | (mask_m[34] << 22) | (mask_m[35] << 20) 594 | (mask_m[36] << 18) | (mask_m[37] << 16) 595 | (mask_m[48] << 14) | (mask_m[39] << 12) 596 | (mask_m[40] << 10) | (mask_m[41] << 8) 597 | (mask_m[42] << 6) | (mask_m[43] << 4) 598 | (mask_m[44] << 2) | (mask_m[45] << 0); 599 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 600 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 601 602 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 603 | (mask_m[18] << 26) | (mask_m[18] << 24) 604 | (mask_m[20] << 22) | (mask_m[20] << 20) 605 | (mask_m[22] << 18) | (mask_m[22] << 16) 606 | (mask_m[24] << 14) | (mask_m[24] << 12) 607 | (mask_m[25] << 10) | (mask_m[26] << 8) 608 | (mask_m[27] << 6) | (mask_m[28] << 4) 609 | (mask_m[29] << 2) | (mask_m[30] << 0); 610 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 611 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 612 613 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 614 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 615 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 616 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 617 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 618 | (mask_m[10] << 10) | (mask_m[11] << 8) 619 | (mask_m[12] << 6) | (mask_m[13] << 4) 620 | (mask_m[14] << 2) | (mask_m[15] << 0); 621 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 622 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 623 624 tmp_mask = (mask_p[15] << 28) 625 | (mask_p[14] << 26) | (mask_p[13] << 24) 626 | (mask_p[12] << 22) | (mask_p[11] << 20) 627 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 628 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 629 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 630 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 631 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 632 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 633 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 634 635 tmp_mask = (mask_p[30] << 28) 636 | (mask_p[29] << 26) | (mask_p[28] << 24) 637 | (mask_p[27] << 22) | (mask_p[26] << 20) 638 | (mask_p[25] << 18) | (mask_p[24] << 16) 639 | (mask_p[23] << 14) | (mask_p[22] << 12) 640 | (mask_p[21] << 10) | (mask_p[20] << 8) 641 | (mask_p[19] << 6) | (mask_p[18] << 4) 642 | (mask_p[17] << 2) | (mask_p[16] << 0); 643 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 644 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 645 646 tmp_mask = (mask_p[45] << 28) 647 | (mask_p[44] << 26) | (mask_p[43] << 24) 648 | (mask_p[42] << 22) | (mask_p[41] << 20) 649 | (mask_p[40] << 18) | (mask_p[39] << 16) 650 | (mask_p[38] << 14) | (mask_p[37] << 12) 651 | (mask_p[36] << 10) | (mask_p[35] << 8) 652 | (mask_p[34] << 6) | (mask_p[33] << 4) 653 | (mask_p[32] << 2) | (mask_p[31] << 0); 654 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 655 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 656 657 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 658 | (mask_p[59] << 26) | (mask_p[58] << 24) 659 | (mask_p[57] << 22) | (mask_p[56] << 20) 660 | (mask_p[55] << 18) | (mask_p[54] << 16) 661 | (mask_p[53] << 14) | (mask_p[52] << 12) 662 | (mask_p[51] << 10) | (mask_p[50] << 8) 663 | (mask_p[49] << 6) | (mask_p[48] << 4) 664 | (mask_p[47] << 2) | (mask_p[46] << 0); 665 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 666 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 667} 668 669/* 670 * Fill all software cached or static hardware state information. 671 * Return failure if capabilities are to come from EEPROM and 672 * cannot be read. 673 */ 674static HAL_BOOL 675ar9280FillCapabilityInfo(struct ath_hal *ah) 676{ 677 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 678 679 if (!ar5416FillCapabilityInfo(ah)) 680 return AH_FALSE; 681 pCap->halNumGpioPins = 10; 682 pCap->halWowSupport = AH_TRUE; 683 pCap->halWowMatchPatternExact = AH_TRUE; 684#if 0 685 pCap->halWowMatchPatternDword = AH_TRUE; 686#endif 687 /* AR9280 is a 2x2 stream device */ 688 pCap->halTxStreams = 2; 689 pCap->halRxStreams = 2; 690 691 pCap->halCSTSupport = AH_TRUE; 692 pCap->halRifsRxSupport = AH_TRUE; 693 pCap->halRifsTxSupport = AH_TRUE; 694 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 695 pCap->halExtChanDfsSupport = AH_TRUE; 696#if 0 697 /* XXX bluetooth */ 698 pCap->halBtCoexSupport = AH_TRUE; 699#endif 700 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 701 pCap->hal4kbSplitTransSupport = AH_FALSE; 702 pCap->halRxStbcSupport = 1; 703 pCap->halTxStbcSupport = 1; 704 705 return AH_TRUE; 706} 707 708/* 709 * This has been disabled - having the HAL flip chainmasks on/off 710 * when attempting to implement 11n disrupts things. For now, just 711 * leave this flipped off and worry about implementing TX diversity 712 * for legacy and MCS0-7 when 11n is fully functioning. 713 */ 714HAL_BOOL 715ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 716{ 717#define ANTENNA0_CHAINMASK 0x1 718#define ANTENNA1_CHAINMASK 0x2 719#if 0 720 struct ath_hal_5416 *ahp = AH5416(ah); 721 722 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 723 switch (settings) { 724 case HAL_ANT_FIXED_A: 725 /* Enable first antenna only */ 726 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 727 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 728 break; 729 case HAL_ANT_FIXED_B: 730 /* Enable second antenna only, after checking capability */ 731 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 732 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 733 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 734 break; 735 case HAL_ANT_VARIABLE: 736 /* Restore original chainmask settings */ 737 /* XXX */ 738 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 739 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 740 break; 741 } 742 743 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 744 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 745 746#endif 747 return AH_TRUE; 748#undef ANTENNA0_CHAINMASK 749#undef ANTENNA1_CHAINMASK 750} 751 752static const char* 753ar9280Probe(uint16_t vendorid, uint16_t devid) 754{ 755 if (vendorid == ATHEROS_VENDOR_ID && 756 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 757 return "Atheros 9280"; 758 return AH_NULL; 759} 760AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 761