ar9280_attach.c revision 217631
1189747Ssam/* 2189747Ssam * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3189747Ssam * Copyright (c) 2008 Atheros Communications, Inc. 4189747Ssam * 5189747Ssam * Permission to use, copy, modify, and/or distribute this software for any 6189747Ssam * purpose with or without fee is hereby granted, provided that the above 7189747Ssam * copyright notice and this permission notice appear in all copies. 8189747Ssam * 9189747Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10189747Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11189747Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12189747Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13189747Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14189747Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15189747Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16189747Ssam * 17189747Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 217631 2011-01-20 09:03:40Z adrian $ 18189747Ssam */ 19189747Ssam#include "opt_ah.h" 20189747Ssam 21189747Ssam#include "ah.h" 22189747Ssam#include "ah_internal.h" 23189747Ssam#include "ah_devid.h" 24189747Ssam 25189747Ssam#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26189747Ssam 27217631Sadrian#include "ar9002/ar9280.h" 28189747Ssam#include "ar5416/ar5416reg.h" 29189747Ssam#include "ar5416/ar5416phy.h" 30189747Ssam 31217631Sadrian#include "ar9002/ar9280v1.ini" 32217631Sadrian#include "ar9002/ar9280v2.ini" 33189747Ssam 34189747Ssamstatic const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 35189747Ssam .calName = "IQ", .calType = IQ_MISMATCH_CAL, 36189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 37189747Ssam .calCountMax = PER_MAX_LOG_COUNT, 38189747Ssam .calCollect = ar5416IQCalCollect, 39189747Ssam .calPostProc = ar5416IQCalibration 40189747Ssam}; 41189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 42189747Ssam .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 43189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 44189747Ssam .calCountMax = PER_MIN_LOG_COUNT, 45189747Ssam .calCollect = ar5416AdcGainCalCollect, 46189747Ssam .calPostProc = ar5416AdcGainCalibration 47189747Ssam}; 48189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 49189747Ssam .calName = "ADC DC", .calType = ADC_DC_CAL, 50189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 51189747Ssam .calCountMax = PER_MIN_LOG_COUNT, 52189747Ssam .calCollect = ar5416AdcDcCalCollect, 53189747Ssam .calPostProc = ar5416AdcDcCalibration 54189747Ssam}; 55189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 56189747Ssam .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 57189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 58189747Ssam .calCountMax = INIT_LOG_COUNT, 59189747Ssam .calCollect = ar5416AdcDcCalCollect, 60189747Ssam .calPostProc = ar5416AdcDcCalibration 61189747Ssam}; 62189747Ssam 63189747Ssamstatic void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 64189747Ssamstatic HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 65189747Ssamstatic void ar9280WriteIni(struct ath_hal *ah, 66189747Ssam const struct ieee80211_channel *chan); 67189747Ssam 68189747Ssamstatic void 69189747Ssamar9280AniSetup(struct ath_hal *ah) 70189747Ssam{ 71189747Ssam /* NB: disable ANI for reliable RIFS rx */ 72189747Ssam ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE); 73189747Ssam} 74189747Ssam 75189747Ssam/* 76189747Ssam * Attach for an AR9280 part. 77189747Ssam */ 78189747Ssamstatic struct ath_hal * 79189747Ssamar9280Attach(uint16_t devid, HAL_SOFTC sc, 80217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 81217624Sadrian HAL_STATUS *status) 82189747Ssam{ 83189747Ssam struct ath_hal_9280 *ahp9280; 84189747Ssam struct ath_hal_5212 *ahp; 85189747Ssam struct ath_hal *ah; 86189747Ssam uint32_t val; 87189747Ssam HAL_STATUS ecode; 88189747Ssam HAL_BOOL rfStatus; 89189747Ssam 90189747Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 91189747Ssam __func__, sc, (void*) st, (void*) sh); 92189747Ssam 93189747Ssam /* NB: memory is returned zero'd */ 94189747Ssam ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 95189747Ssam if (ahp9280 == AH_NULL) { 96189747Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 97189747Ssam "%s: cannot allocate memory for state block\n", __func__); 98189747Ssam *status = HAL_ENOMEM; 99189747Ssam return AH_NULL; 100189747Ssam } 101189747Ssam ahp = AH5212(ahp9280); 102189747Ssam ah = &ahp->ah_priv.h; 103189747Ssam 104189747Ssam ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 105189747Ssam 106189747Ssam /* XXX override with 9280 specific state */ 107189747Ssam /* override 5416 methods for our needs */ 108189747Ssam ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 109189747Ssam ah->ah_configPCIE = ar9280ConfigPCIE; 110189747Ssam 111189747Ssam AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 112189747Ssam AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 113189747Ssam AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 114189747Ssam AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 115189747Ssam AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 116189747Ssam 117189747Ssam AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 118189747Ssam AH5416(ah)->ah_writeIni = ar9280WriteIni; 119189747Ssam AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 120189747Ssam AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 121189747Ssam 122189747Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 123189747Ssam /* reset chip */ 124189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 125189747Ssam __func__); 126189747Ssam ecode = HAL_EIO; 127189747Ssam goto bad; 128189747Ssam } 129189747Ssam 130189747Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 131189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 132189747Ssam __func__); 133189747Ssam ecode = HAL_EIO; 134189747Ssam goto bad; 135189747Ssam } 136189747Ssam /* Read Revisions from Chips before taking out of reset */ 137189747Ssam val = OS_REG_READ(ah, AR_SREV); 138189747Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 139189747Ssam "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 140189747Ssam __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 141189747Ssam MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 142189747Ssam /* NB: include chip type to differentiate from pre-Sowl versions */ 143189747Ssam AH_PRIVATE(ah)->ah_macVersion = 144189747Ssam (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 145189747Ssam AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 146189747Ssam AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 147189747Ssam 148189747Ssam /* setup common ini data; rf backends handle remainder */ 149203882Srpaulo if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 150189747Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 151189747Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 152189747Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 153189747Ssam ar9280PciePhy_clkreq_always_on_L1_v2, 2); 154189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 155189747Ssam ar9280Modes_fast_clock_v2, 3); 156189747Ssam } else { 157189747Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 158189747Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 159189747Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 160189747Ssam ar9280PciePhy_v1, 2); 161189747Ssam } 162189747Ssam ar5416AttachPCIE(ah); 163189747Ssam 164203882Srpaulo ecode = ath_hal_v14EepromAttach(ah); 165189747Ssam if (ecode != HAL_OK) 166189747Ssam goto bad; 167189747Ssam 168189747Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 169189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 170189747Ssam ecode = HAL_EIO; 171189747Ssam goto bad; 172189747Ssam } 173189747Ssam 174189747Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 175189747Ssam 176189747Ssam if (!ar5212ChipTest(ah)) { 177189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 178189747Ssam __func__); 179189747Ssam ecode = HAL_ESELFTEST; 180189747Ssam goto bad; 181189747Ssam } 182189747Ssam 183189747Ssam /* 184189747Ssam * Set correct Baseband to analog shift 185189747Ssam * setting to access analog chips. 186189747Ssam */ 187189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 188189747Ssam 189189747Ssam /* Read Radio Chip Rev Extract */ 190189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 191189747Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 192189747Ssam case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 193189747Ssam case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 194189747Ssam break; 195189747Ssam default: 196189747Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 197189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 198189747Ssam AR_RAD5133_SREV_MAJOR; 199189747Ssam break; 200189747Ssam } 201189747Ssam#ifdef AH_DEBUG 202189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 203189747Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 204189747Ssam "this driver\n", __func__, 205189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 206189747Ssam ecode = HAL_ENOTSUPP; 207189747Ssam goto bad; 208189747Ssam#endif 209189747Ssam } 210189747Ssam rfStatus = ar9280RfAttach(ah, &ecode); 211189747Ssam if (!rfStatus) { 212189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 213189747Ssam __func__, ecode); 214189747Ssam goto bad; 215189747Ssam } 216189747Ssam 217189747Ssam if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 218189747Ssam /* setup rxgain table */ 219189747Ssam switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 220189747Ssam case AR5416_EEP_RXGAIN_13dB_BACKOFF: 221189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 222189747Ssam ar9280Modes_backoff_13db_rxgain_v2, 6); 223189747Ssam break; 224189747Ssam case AR5416_EEP_RXGAIN_23dB_BACKOFF: 225189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 226189747Ssam ar9280Modes_backoff_23db_rxgain_v2, 6); 227189747Ssam break; 228189747Ssam case AR5416_EEP_RXGAIN_ORIG: 229189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 230189747Ssam ar9280Modes_original_rxgain_v2, 6); 231189747Ssam break; 232189747Ssam default: 233189747Ssam HALASSERT(AH_FALSE); 234189747Ssam goto bad; /* XXX ? try to continue */ 235189747Ssam } 236189747Ssam } 237203882Srpaulo if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 238189747Ssam /* setp txgain table */ 239189747Ssam switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 240189747Ssam case AR5416_EEP_TXGAIN_HIGH_POWER: 241189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_txgain, 242189747Ssam ar9280Modes_high_power_tx_gain_v2, 6); 243189747Ssam break; 244189747Ssam case AR5416_EEP_TXGAIN_ORIG: 245189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_txgain, 246189747Ssam ar9280Modes_original_tx_gain_v2, 6); 247189747Ssam break; 248189747Ssam default: 249189747Ssam HALASSERT(AH_FALSE); 250189747Ssam goto bad; /* XXX ? try to continue */ 251189747Ssam } 252189747Ssam } 253189747Ssam 254189747Ssam /* 255189747Ssam * Got everything we need now to setup the capabilities. 256189747Ssam */ 257189747Ssam if (!ar9280FillCapabilityInfo(ah)) { 258189747Ssam ecode = HAL_EEREAD; 259189747Ssam goto bad; 260189747Ssam } 261189747Ssam 262189747Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 263189747Ssam if (ecode != HAL_OK) { 264189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 265189747Ssam "%s: error getting mac address from EEPROM\n", __func__); 266189747Ssam goto bad; 267189747Ssam } 268189747Ssam /* XXX How about the serial number ? */ 269189747Ssam /* Read Reg Domain */ 270189747Ssam AH_PRIVATE(ah)->ah_currentRD = 271189747Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 272189747Ssam 273189747Ssam /* 274189747Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 275189747Ssam * starting from griffin. Set here to make sure that 276189747Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 277189747Ssam * placed into hardware. 278189747Ssam */ 279189747Ssam if (ahp->ah_miscMode != 0) 280189747Ssam OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 281189747Ssam 282189747Ssam ar9280AniSetup(ah); /* Anti Noise Immunity */ 283203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 284189747Ssam 285189747Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 286189747Ssam 287189747Ssam return ah; 288189747Ssambad: 289189747Ssam if (ah != AH_NULL) 290189747Ssam ah->ah_detach(ah); 291189747Ssam if (status) 292189747Ssam *status = ecode; 293189747Ssam return AH_NULL; 294189747Ssam} 295189747Ssam 296189747Ssamstatic void 297189747Ssamar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 298189747Ssam{ 299189747Ssam if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 300189747Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 301189747Ssam OS_DELAY(1000); 302189747Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 303203882Srpaulo OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 304189747Ssam } 305189747Ssam} 306189747Ssam 307189747Ssamstatic void 308189747Ssamar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 309189747Ssam{ 310189747Ssam u_int modesIndex, freqIndex; 311189747Ssam int regWrites = 0; 312189747Ssam 313189747Ssam /* Setup the indices for the next set of register array writes */ 314189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 315189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 316189747Ssam freqIndex = 2; 317189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 318189747Ssam modesIndex = 3; 319189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 320189747Ssam modesIndex = 5; 321189747Ssam else 322189747Ssam modesIndex = 4; 323189747Ssam } else { 324189747Ssam freqIndex = 1; 325189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 326189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 327189747Ssam modesIndex = 2; 328189747Ssam else 329189747Ssam modesIndex = 1; 330189747Ssam } 331189747Ssam 332189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 333189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 334189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 335189747Ssam 336189747Ssam /* XXX Merlin ini fixups */ 337189747Ssam /* XXX Merlin 100us delay for shift registers */ 338189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 339189747Ssam modesIndex, regWrites); 340189747Ssam if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 341189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 342189747Ssam modesIndex, regWrites); 343189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 344189747Ssam modesIndex, regWrites); 345189747Ssam } 346189747Ssam /* XXX Merlin 100us delay for shift registers */ 347189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 348189747Ssam 1, regWrites); 349189747Ssam 350189747Ssam if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 351189747Ssam /* 5GHz channels w/ Fast Clock use different modal values */ 352189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 353189747Ssam modesIndex, regWrites); 354189747Ssam } 355189747Ssam} 356189747Ssam 357189747Ssam#define AR_BASE_FREQ_2GHZ 2300 358189747Ssam#define AR_BASE_FREQ_5GHZ 4900 359189747Ssam#define AR_SPUR_FEEQ_BOUND_HT40 19 360189747Ssam#define AR_SPUR_FEEQ_BOUND_HT20 10 361189747Ssam 362203930Srpaulovoid 363189747Ssamar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 364189747Ssam{ 365189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 366189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 367189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 368189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 369189747Ssam static int inc[4] = { 0, 100, 0, 0 }; 370189747Ssam 371189747Ssam int bb_spur = AR_NO_SPUR; 372189747Ssam int freq; 373189747Ssam int bin, cur_bin; 374189747Ssam int bb_spur_off, spur_subchannel_sd; 375189747Ssam int spur_freq_sd; 376189747Ssam int spur_delta_phase; 377189747Ssam int denominator; 378189747Ssam int upper, lower, cur_vit_mask; 379189747Ssam int tmp, newVal; 380189747Ssam int i; 381189747Ssam CHAN_CENTERS centers; 382189747Ssam 383189747Ssam int8_t mask_m[123]; 384189747Ssam int8_t mask_p[123]; 385189747Ssam int8_t mask_amt; 386189747Ssam int tmp_mask; 387189747Ssam int cur_bb_spur; 388189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 389189747Ssam 390189747Ssam OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 391189747Ssam OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 392189747Ssam 393189747Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 394189747Ssam freq = centers.synth_center; 395189747Ssam 396189747Ssam /* 397189747Ssam * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 398189747Ssam * otherwise spur is out-of-band and can be ignored. 399189747Ssam */ 400189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 401189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 402189747Ssam /* Get actual spur freq in MHz from EEPROM read value */ 403189747Ssam if (is2GHz) { 404189747Ssam cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 405189747Ssam } else { 406189747Ssam cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 407189747Ssam } 408189747Ssam 409189747Ssam if (AR_NO_SPUR == cur_bb_spur) 410189747Ssam break; 411189747Ssam cur_bb_spur = cur_bb_spur - freq; 412189747Ssam 413189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 414189747Ssam if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 415189747Ssam (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 416189747Ssam bb_spur = cur_bb_spur; 417189747Ssam break; 418189747Ssam } 419189747Ssam } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 420189747Ssam (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 421189747Ssam bb_spur = cur_bb_spur; 422189747Ssam break; 423189747Ssam } 424189747Ssam } 425189747Ssam 426189747Ssam if (AR_NO_SPUR == bb_spur) { 427189747Ssam#if 1 428189747Ssam /* 429189747Ssam * MRC CCK can interfere with beacon detection and cause deaf/mute. 430189747Ssam * Disable MRC CCK for now. 431189747Ssam */ 432189747Ssam OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 433189747Ssam#else 434189747Ssam /* Enable MRC CCK if no spur is found in this channel. */ 435189747Ssam OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 436189747Ssam#endif 437189747Ssam return; 438189747Ssam } else { 439189747Ssam /* 440189747Ssam * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 441189747Ssam * is found in this channel. 442189747Ssam */ 443189747Ssam OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 444189747Ssam } 445189747Ssam 446189747Ssam bin = bb_spur * 320; 447189747Ssam 448189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 449189747Ssam 450189747Ssam newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 451189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 452189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 453189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 454189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 455189747Ssam 456189747Ssam newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 457189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 458189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 459189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 460189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 461189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 462189747Ssam 463189747Ssam /* Pick control or extn channel to cancel the spur */ 464189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 465189747Ssam if (bb_spur < 0) { 466189747Ssam spur_subchannel_sd = 1; 467189747Ssam bb_spur_off = bb_spur + 10; 468189747Ssam } else { 469189747Ssam spur_subchannel_sd = 0; 470189747Ssam bb_spur_off = bb_spur - 10; 471189747Ssam } 472189747Ssam } else { 473189747Ssam spur_subchannel_sd = 0; 474189747Ssam bb_spur_off = bb_spur; 475189747Ssam } 476189747Ssam 477189747Ssam /* 478189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 479189747Ssam * /80 for dyn2040. 480189747Ssam */ 481189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 482189747Ssam spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 483189747Ssam else 484189747Ssam spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 485189747Ssam 486189747Ssam /* 487189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 488189747Ssam * it should be 44 in 11G 489189747Ssam */ 490189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 491189747Ssam spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 492189747Ssam 493189747Ssam newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 494189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 495189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 496189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 497189747Ssam 498189747Ssam /* Choose to cancel between control and extension channels */ 499189747Ssam newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 500189747Ssam OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 501189747Ssam 502189747Ssam /* 503189747Ssam * ============================================ 504189747Ssam * Set Pilot and Channel Masks 505189747Ssam * 506189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 507189747Ssam * pilot mask 2 [19:0] = +26..+7 508189747Ssam * 509189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 510189747Ssam * channel mask 2 [19:0] = +26..+7 511189747Ssam */ 512189747Ssam cur_bin = -6000; 513189747Ssam upper = bin + 100; 514189747Ssam lower = bin - 100; 515189747Ssam 516189747Ssam for (i = 0; i < 4; i++) { 517189747Ssam int pilot_mask = 0; 518189747Ssam int chan_mask = 0; 519189747Ssam int bp = 0; 520189747Ssam for (bp = 0; bp < 30; bp++) { 521189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 522189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 523189747Ssam chan_mask = chan_mask | 0x1 << bp; 524189747Ssam } 525189747Ssam cur_bin += 100; 526189747Ssam } 527189747Ssam cur_bin += inc[i]; 528189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 529189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 530189747Ssam } 531189747Ssam 532189747Ssam /* ================================================= 533189747Ssam * viterbi mask 1 based on channel magnitude 534189747Ssam * four levels 0-3 535189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 536189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 537189747Ssam * - enable_mask_ppm, all bins move with freq 538189747Ssam * 539189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 540189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 541189747Ssam * choose which mask to use mask or mask2 542189747Ssam */ 543189747Ssam 544189747Ssam /* 545189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 546189747Ssam * four levels 0-3 547189747Ssam * - mask_select, 8 bits for rates (reg 67) 548189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 549189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 550189747Ssam */ 551189747Ssam cur_vit_mask = 6100; 552189747Ssam upper = bin + 120; 553189747Ssam lower = bin - 120; 554189747Ssam 555189747Ssam for (i = 0; i < 123; i++) { 556189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 557189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 558189747Ssam mask_amt = 1; 559189747Ssam } else { 560189747Ssam mask_amt = 0; 561189747Ssam } 562189747Ssam if (cur_vit_mask < 0) { 563189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 564189747Ssam } else { 565189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 566189747Ssam } 567189747Ssam } 568189747Ssam cur_vit_mask -= 100; 569189747Ssam } 570189747Ssam 571189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 572189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 573189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 574189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 575189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 576189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 577189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 578189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 579189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 580189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 581189747Ssam 582189747Ssam tmp_mask = (mask_m[31] << 28) 583189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 584189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 585189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 586189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 587189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 588189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 589189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 590189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 591189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 592189747Ssam 593189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 594189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 595189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 596189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 597189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 598189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 599189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 600189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 601189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 602189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 603189747Ssam 604189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 605189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 606189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 607189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 608189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 609189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 610189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 611189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 612189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 613189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 614189747Ssam 615189747Ssam tmp_mask = (mask_p[15] << 28) 616189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 617189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 618189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 619189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 620189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 621189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 622189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 623189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 624189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 625189747Ssam 626189747Ssam tmp_mask = (mask_p[30] << 28) 627189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 628189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 629189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 630189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 631189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 632189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 633189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 634189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 635189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 636189747Ssam 637189747Ssam tmp_mask = (mask_p[45] << 28) 638189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 639189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 640189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 641189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 642189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 643189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 644189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 645189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 646189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 647189747Ssam 648189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 649189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 650189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 651189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 652189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 653189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 654189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 655189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 656189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 657189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 658189747Ssam} 659189747Ssam 660189747Ssam/* 661189747Ssam * Fill all software cached or static hardware state information. 662189747Ssam * Return failure if capabilities are to come from EEPROM and 663189747Ssam * cannot be read. 664189747Ssam */ 665189747Ssamstatic HAL_BOOL 666189747Ssamar9280FillCapabilityInfo(struct ath_hal *ah) 667189747Ssam{ 668189747Ssam HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 669189747Ssam 670189747Ssam if (!ar5416FillCapabilityInfo(ah)) 671189747Ssam return AH_FALSE; 672203882Srpaulo pCap->halNumGpioPins = 10; 673189747Ssam pCap->halWowSupport = AH_TRUE; 674189747Ssam pCap->halWowMatchPatternExact = AH_TRUE; 675189747Ssam#if 0 676189747Ssam pCap->halWowMatchPatternDword = AH_TRUE; 677189747Ssam#endif 678189747Ssam pCap->halCSTSupport = AH_TRUE; 679189747Ssam pCap->halRifsRxSupport = AH_TRUE; 680189747Ssam pCap->halRifsTxSupport = AH_TRUE; 681189747Ssam pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 682189747Ssam pCap->halExtChanDfsSupport = AH_TRUE; 683189747Ssam#if 0 684189747Ssam /* XXX bluetooth */ 685189747Ssam pCap->halBtCoexSupport = AH_TRUE; 686189747Ssam#endif 687189747Ssam pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 688189747Ssam#if 0 689189747Ssam pCap->hal4kbSplitTransSupport = AH_FALSE; 690189747Ssam#endif 691189747Ssam pCap->halRxStbcSupport = 1; 692189747Ssam pCap->halTxStbcSupport = 1; 693189747Ssam 694189747Ssam return AH_TRUE; 695189747Ssam} 696189747Ssam 697189747SsamHAL_BOOL 698189747Ssamar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 699189747Ssam{ 700189747Ssam#define ANTENNA0_CHAINMASK 0x1 701189747Ssam#define ANTENNA1_CHAINMASK 0x2 702189747Ssam struct ath_hal_5416 *ahp = AH5416(ah); 703189747Ssam 704189747Ssam /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 705189747Ssam switch (settings) { 706189747Ssam case HAL_ANT_FIXED_A: 707189747Ssam /* Enable first antenna only */ 708189747Ssam ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 709189747Ssam ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 710189747Ssam break; 711189747Ssam case HAL_ANT_FIXED_B: 712189747Ssam /* Enable second antenna only, after checking capability */ 713189747Ssam if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 714189747Ssam ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 715189747Ssam ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 716189747Ssam break; 717189747Ssam case HAL_ANT_VARIABLE: 718189747Ssam /* Restore original chainmask settings */ 719189747Ssam /* XXX */ 720189747Ssam ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 721189747Ssam ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 722189747Ssam break; 723189747Ssam } 724189747Ssam return AH_TRUE; 725189747Ssam#undef ANTENNA0_CHAINMASK 726189747Ssam#undef ANTENNA1_CHAINMASK 727189747Ssam} 728189747Ssam 729189747Ssamstatic const char* 730189747Ssamar9280Probe(uint16_t vendorid, uint16_t devid) 731189747Ssam{ 732203882Srpaulo if (vendorid == ATHEROS_VENDOR_ID && 733203882Srpaulo (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 734203882Srpaulo return "Atheros 9280"; 735189747Ssam return AH_NULL; 736189747Ssam} 737189747SsamAH_CHIP(AR9280, ar9280Probe, ar9280Attach); 738