1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38#define AH_MAX_CHAINS 3 39#define AH_MIMO_MAX_EVM_PILOTS 6 40 41/* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48#ifndef __ahdecl 49#define __ahdecl 50#endif 51 52/* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77} HAL_STATUS; 78 79typedef enum { 80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82} HAL_BOOL; 83 84typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 HAL_CAP_RIFS_RX = 39, 123 HAL_CAP_RIFS_TX = 40, 124 HAL_CAP_FORCE_PPM = 41, 125 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130 131 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132 automatically after waking up to receive TIM */ 133 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136 HAL_CAP_BB_RIFS_HANG = 52, 137 HAL_CAP_RIFS_RX_ENABLED = 53, 138 HAL_CAP_BB_DFS_HANG = 54, 139 140 HAL_CAP_RX_STBC = 58, 141 HAL_CAP_TX_STBC = 59, 142 143 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 144 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 145 146 HAL_CAP_DS = 67, /* 2 stream */ 147 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 148 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 149 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 150 151 HAL_CAP_TS = 72, /* 3 stream */ 152 153 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 154 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 155 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 156 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 157 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 158 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 159 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 160 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 161 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 162 HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 163 164 HAL_CAP_BB_PANIC_WATCHDOG = 92, 165 166 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 167 168 HAL_CAP_LDPC = 99, 169 170 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 171 172 HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */ 173 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 174 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 175 HAL_CAP_LDPCWAR = 108, 176 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 177 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 178 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 179 HAL_CAP_PCIE_LCR_OFFSET = 112, 180 181 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 182 HAL_CAP_MCI = 118, 183 HAL_CAP_SMARTANTENNA = 119, 184 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 185 HAL_CAP_TX_DIVERSITY = 121, 186 HAL_CAP_CRDC = 122, 187 188 /* The following are private to the FreeBSD HAL (224 onward) */ 189 190 HAL_CAP_INTMIT = 229, /* interference mitigation */ 191 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 192 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 193 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 194 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 195 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 196 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 197 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 198 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 199 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 200 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 201 HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */ 202} HAL_CAPABILITY_TYPE; 203 204/* 205 * "States" for setting the LED. These correspond to 206 * the possible 802.11 operational states and there may 207 * be a many-to-one mapping between these states and the 208 * actual hardware state for the LED's (i.e. the hardware 209 * may have fewer states). 210 */ 211typedef enum { 212 HAL_LED_INIT = 0, 213 HAL_LED_SCAN = 1, 214 HAL_LED_AUTH = 2, 215 HAL_LED_ASSOC = 3, 216 HAL_LED_RUN = 4 217} HAL_LED_STATE; 218 219/* 220 * Transmit queue types/numbers. These are used to tag 221 * each transmit queue in the hardware and to identify a set 222 * of transmit queues for operations such as start/stop dma. 223 */ 224typedef enum { 225 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 226 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 227 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 228 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 229 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 230 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 231 HAL_TX_QUEUE_CFEND = 6, 232 HAL_TX_QUEUE_PAPRD = 7, 233} HAL_TX_QUEUE; 234 235#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 236 237/* 238 * Receive queue types. These are used to tag 239 * each transmit queue in the hardware and to identify a set 240 * of transmit queues for operations such as start/stop dma. 241 */ 242typedef enum { 243 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 244 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 245} HAL_RX_QUEUE; 246 247#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 248 249#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 250 251/* 252 * Transmit queue subtype. These map directly to 253 * WME Access Categories (except for UPSD). Refer 254 * to Table 5 of the WME spec. 255 */ 256typedef enum { 257 HAL_WME_AC_BK = 0, /* background access category */ 258 HAL_WME_AC_BE = 1, /* best effort access category*/ 259 HAL_WME_AC_VI = 2, /* video access category */ 260 HAL_WME_AC_VO = 3, /* voice access category */ 261 HAL_WME_UPSD = 4, /* uplink power save */ 262} HAL_TX_QUEUE_SUBTYPE; 263 264/* 265 * Transmit queue flags that control various 266 * operational parameters. 267 */ 268typedef enum { 269 /* 270 * Per queue interrupt enables. When set the associated 271 * interrupt may be delivered for packets sent through 272 * the queue. Without these enabled no interrupts will 273 * be delivered for transmits through the queue. 274 */ 275 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 276 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 277 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 278 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 279 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 280 /* 281 * Enable hardware compression for packets sent through 282 * the queue. The compression buffer must be setup and 283 * packets must have a key entry marked in the tx descriptor. 284 */ 285 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 286 /* 287 * Disable queue when veol is hit or ready time expires. 288 * By default the queue is disabled only on reaching the 289 * physical end of queue (i.e. a null link ptr in the 290 * descriptor chain). 291 */ 292 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 293 /* 294 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 295 * event. Frames will be transmitted only when this timer 296 * fires, e.g to transmit a beacon in ap or adhoc modes. 297 */ 298 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 299 /* 300 * Each transmit queue has a counter that is incremented 301 * each time the queue is enabled and decremented when 302 * the list of frames to transmit is traversed (or when 303 * the ready time for the queue expires). This counter 304 * must be non-zero for frames to be scheduled for 305 * transmission. The following controls disable bumping 306 * this counter under certain conditions. Typically this 307 * is used to gate frames based on the contents of another 308 * queue (e.g. CAB traffic may only follow a beacon frame). 309 * These are meaningful only when frames are scheduled 310 * with a non-ASAP policy (e.g. DBA-gated). 311 */ 312 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 313 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 314 315 /* 316 * Fragment burst backoff policy. Normally the no backoff 317 * is done after a successful transmission, the next fragment 318 * is sent at SIFS. If this flag is set backoff is done 319 * after each fragment, regardless whether it was ack'd or 320 * not, after the backoff count reaches zero a normal channel 321 * access procedure is done before the next transmit (i.e. 322 * wait AIFS instead of SIFS). 323 */ 324 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 325 /* 326 * Disable post-tx backoff following each frame. 327 */ 328 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 329 /* 330 * DCU arbiter lockout control. This controls how 331 * lower priority tx queues are handled with respect to 332 * to a specific queue when multiple queues have frames 333 * to send. No lockout means lower priority queues arbitrate 334 * concurrently with this queue. Intra-frame lockout 335 * means lower priority queues are locked out until the 336 * current frame transmits (e.g. including backoffs and bursting). 337 * Global lockout means nothing lower can arbitrary so 338 * long as there is traffic activity on this queue (frames, 339 * backoff, etc). 340 */ 341 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 342 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 343 344 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 345 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 346} HAL_TX_QUEUE_FLAGS; 347 348typedef struct { 349 uint32_t tqi_ver; /* hal TXQ version */ 350 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 351 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 352 uint32_t tqi_priority; /* (not used) */ 353 uint32_t tqi_aifs; /* aifs */ 354 uint32_t tqi_cwmin; /* cwMin */ 355 uint32_t tqi_cwmax; /* cwMax */ 356 uint16_t tqi_shretry; /* rts retry limit */ 357 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 358 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 359 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 360 uint32_t tqi_burstTime; /* max burst duration (us) */ 361 uint32_t tqi_readyTime; /* frame schedule time (us) */ 362 uint32_t tqi_compBuf; /* comp buffer phys addr */ 363} HAL_TXQ_INFO; 364 365#define HAL_TQI_NONVAL 0xffff 366 367/* token to use for aifs, cwmin, cwmax */ 368#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 369 370/* compression definitions */ 371#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 372#define HAL_COMP_BUF_ALIGN_SIZE 512 373 374/* 375 * Transmit packet types. This belongs in ah_desc.h, but 376 * is here so we can give a proper type to various parameters 377 * (and not require everyone include the file). 378 * 379 * NB: These values are intentionally assigned for 380 * direct use when setting up h/w descriptors. 381 */ 382typedef enum { 383 HAL_PKT_TYPE_NORMAL = 0, 384 HAL_PKT_TYPE_ATIM = 1, 385 HAL_PKT_TYPE_PSPOLL = 2, 386 HAL_PKT_TYPE_BEACON = 3, 387 HAL_PKT_TYPE_PROBE_RESP = 4, 388 HAL_PKT_TYPE_CHIRP = 5, 389 HAL_PKT_TYPE_GRP_POLL = 6, 390 HAL_PKT_TYPE_AMPDU = 7, 391} HAL_PKT_TYPE; 392 393/* Rx Filter Frame Types */ 394typedef enum { 395 /* 396 * These bits correspond to AR_RX_FILTER for all chips. 397 * Not all bits are supported by all chips. 398 */ 399 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 400 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 401 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 402 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 403 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 404 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 405 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 406 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 407 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 408 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 409 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 410 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 411 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 412 /* Allow all mcast/bcast frames */ 413 414 /* 415 * Magic RX filter flags that aren't targetting hardware bits 416 * but instead the HAL sets individual bits - eg PHYERR will result 417 * in OFDM/CCK timing error frames being received. 418 */ 419 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 420} HAL_RX_FILTER; 421 422typedef enum { 423 HAL_PM_AWAKE = 0, 424 HAL_PM_FULL_SLEEP = 1, 425 HAL_PM_NETWORK_SLEEP = 2, 426 HAL_PM_UNDEFINED = 3 427} HAL_POWER_MODE; 428 429/* 430 * Enterprise mode flags 431 */ 432#define AH_ENT_DUAL_BAND_DISABLE 0x00000001 433#define AH_ENT_CHAIN2_DISABLE 0x00000002 434#define AH_ENT_5MHZ_DISABLE 0x00000004 435#define AH_ENT_10MHZ_DISABLE 0x00000008 436#define AH_ENT_49GHZ_DISABLE 0x00000010 437#define AH_ENT_LOOPBACK_DISABLE 0x00000020 438#define AH_ENT_TPC_PERF_DISABLE 0x00000040 439#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 440#define AH_ENT_SPECTRAL_PRECISION 0x00000300 441#define AH_ENT_SPECTRAL_PRECISION_S 8 442#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 443 444#define AH_FIRST_DESC_NDELIMS 60 445 446/* 447 * NOTE WELL: 448 * These are mapped to take advantage of the common locations for many of 449 * the bits on all of the currently supported MAC chips. This is to make 450 * the ISR as efficient as possible, while still abstracting HW differences. 451 * When new hardware breaks this commonality this enumerated type, as well 452 * as the HAL functions using it, must be modified. All values are directly 453 * mapped unless commented otherwise. 454 */ 455typedef enum { 456 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 457 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 458 HAL_INT_RXERR = 0x00000004, 459 HAL_INT_RXHP = 0x00000001, /* EDMA */ 460 HAL_INT_RXLP = 0x00000002, /* EDMA */ 461 HAL_INT_RXNOFRM = 0x00000008, 462 HAL_INT_RXEOL = 0x00000010, 463 HAL_INT_RXORN = 0x00000020, 464 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 465 HAL_INT_TXDESC = 0x00000080, 466 HAL_INT_TIM_TIMER= 0x00000100, 467 HAL_INT_MCI = 0x00000200, 468 HAL_INT_BBPANIC = 0x00000400, 469 HAL_INT_TXURN = 0x00000800, 470 HAL_INT_MIB = 0x00001000, 471 HAL_INT_RXPHY = 0x00004000, 472 HAL_INT_RXKCM = 0x00008000, 473 HAL_INT_SWBA = 0x00010000, 474 HAL_INT_BRSSI = 0x00020000, 475 HAL_INT_BMISS = 0x00040000, 476 HAL_INT_BNR = 0x00100000, 477 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 478 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 479 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 480 HAL_INT_GPIO = 0x01000000, 481 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 482 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 483 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 484 /* Atheros ref driver has a generic timer interrupt now..*/ 485 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 486 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 487 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 488 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 489#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 490 HAL_INT_BMISC = HAL_INT_TIM 491 | HAL_INT_DTIM 492 | HAL_INT_DTIMSYNC 493 | HAL_INT_CABEND 494 | HAL_INT_TBTT, 495 496 /* Interrupt bits that map directly to ISR/IMR bits */ 497 HAL_INT_COMMON = HAL_INT_RXNOFRM 498 | HAL_INT_RXDESC 499 | HAL_INT_RXEOL 500 | HAL_INT_RXORN 501 | HAL_INT_TXDESC 502 | HAL_INT_TXURN 503 | HAL_INT_MIB 504 | HAL_INT_RXPHY 505 | HAL_INT_RXKCM 506 | HAL_INT_SWBA 507 | HAL_INT_BMISS 508 | HAL_INT_BRSSI 509 | HAL_INT_BNR 510 | HAL_INT_GPIO, 511} HAL_INT; 512 513/* 514 * MSI vector assignments 515 */ 516typedef enum { 517 HAL_MSIVEC_MISC = 0, 518 HAL_MSIVEC_TX = 1, 519 HAL_MSIVEC_RXLP = 2, 520 HAL_MSIVEC_RXHP = 3, 521} HAL_MSIVEC; 522 523typedef enum { 524 HAL_INT_LINE = 0, 525 HAL_INT_MSI = 1, 526} HAL_INT_TYPE; 527 528/* For interrupt mitigation registers */ 529typedef enum { 530 HAL_INT_RX_FIRSTPKT=0, 531 HAL_INT_RX_LASTPKT, 532 HAL_INT_TX_FIRSTPKT, 533 HAL_INT_TX_LASTPKT, 534 HAL_INT_THRESHOLD 535} HAL_INT_MITIGATION; 536 537/* XXX this is duplicate information! */ 538typedef struct { 539 u_int32_t cyclecnt_diff; /* delta cycle count */ 540 u_int32_t rxclr_cnt; /* rx clear count */ 541 u_int32_t txframecnt_diff; /* delta tx frame count */ 542 u_int32_t rxframecnt_diff; /* delta rx frame count */ 543 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 544 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 545 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 546 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 547 HAL_BOOL valid; /* if the stats are valid*/ 548} HAL_ANISTATS; 549 550typedef struct { 551 u_int8_t txctl_offset; 552 u_int8_t txctl_numwords; 553 u_int8_t txstatus_offset; 554 u_int8_t txstatus_numwords; 555 556 u_int8_t rxctl_offset; 557 u_int8_t rxctl_numwords; 558 u_int8_t rxstatus_offset; 559 u_int8_t rxstatus_numwords; 560 561 u_int8_t macRevision; 562} HAL_DESC_INFO; 563 564typedef enum { 565 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 566 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 567 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 568 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 569 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 570 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 571 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6, 572 573 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 574 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 575 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 576 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 577 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 578 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 579 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 580 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 581 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 582 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 583 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 584 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 585 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 586 HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES 587} HAL_GPIO_MUX_TYPE; 588 589typedef enum { 590 HAL_GPIO_INTR_LOW = 0, 591 HAL_GPIO_INTR_HIGH = 1, 592 HAL_GPIO_INTR_DISABLE = 2 593} HAL_GPIO_INTR_TYPE; 594 595typedef struct halCounters { 596 u_int32_t tx_frame_count; 597 u_int32_t rx_frame_count; 598 u_int32_t rx_clear_count; 599 u_int32_t cycle_count; 600 u_int8_t is_rx_active; // true (1) or false (0) 601 u_int8_t is_tx_active; // true (1) or false (0) 602} HAL_COUNTERS; 603 604typedef enum { 605 HAL_RFGAIN_INACTIVE = 0, 606 HAL_RFGAIN_READ_REQUESTED = 1, 607 HAL_RFGAIN_NEED_CHANGE = 2 608} HAL_RFGAIN; 609 610typedef uint16_t HAL_CTRY_CODE; /* country code */ 611typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 612 613#define HAL_ANTENNA_MIN_MODE 0 614#define HAL_ANTENNA_FIXED_A 1 615#define HAL_ANTENNA_FIXED_B 2 616#define HAL_ANTENNA_MAX_MODE 3 617 618typedef struct { 619 uint32_t ackrcv_bad; 620 uint32_t rts_bad; 621 uint32_t rts_good; 622 uint32_t fcs_bad; 623 uint32_t beacons; 624} HAL_MIB_STATS; 625 626/* 627 * These bits represent what's in ah_currentRDext. 628 */ 629typedef enum { 630 REG_EXT_FCC_MIDBAND = 0, 631 REG_EXT_JAPAN_MIDBAND = 1, 632 REG_EXT_FCC_DFS_HT40 = 2, 633 REG_EXT_JAPAN_NONDFS_HT40 = 3, 634 REG_EXT_JAPAN_DFS_HT40 = 4 635} REG_EXT_BITMAP; 636 637enum { 638 HAL_MODE_11A = 0x001, /* 11a channels */ 639 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 640 HAL_MODE_11B = 0x004, /* 11b channels */ 641 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 642#ifdef notdef 643 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 644#else 645 HAL_MODE_11G = 0x008, /* XXX historical */ 646#endif 647 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 648 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 649 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 650 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 651 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 652 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 653 HAL_MODE_11NG_HT20 = 0x008000, 654 HAL_MODE_11NA_HT20 = 0x010000, 655 HAL_MODE_11NG_HT40PLUS = 0x020000, 656 HAL_MODE_11NG_HT40MINUS = 0x040000, 657 HAL_MODE_11NA_HT40PLUS = 0x080000, 658 HAL_MODE_11NA_HT40MINUS = 0x100000, 659 HAL_MODE_ALL = 0xffffff 660}; 661 662typedef struct { 663 int rateCount; /* NB: for proper padding */ 664 uint8_t rateCodeToIndex[256]; /* back mapping */ 665 struct { 666 uint8_t valid; /* valid for rate control use */ 667 uint8_t phy; /* CCK/OFDM/XR */ 668 uint32_t rateKbps; /* transfer rate in kbs */ 669 uint8_t rateCode; /* rate for h/w descriptors */ 670 uint8_t shortPreamble; /* mask for enabling short 671 * preamble in CCK rate code */ 672 uint8_t dot11Rate; /* value for supported rates 673 * info element of MLME */ 674 uint8_t controlRate; /* index of next lower basic 675 * rate; used for dur. calcs */ 676 uint16_t lpAckDuration; /* long preamble ACK duration */ 677 uint16_t spAckDuration; /* short preamble ACK duration*/ 678 } info[64]; 679} HAL_RATE_TABLE; 680 681typedef struct { 682 u_int rs_count; /* number of valid entries */ 683 uint8_t rs_rates[64]; /* rates */ 684} HAL_RATE_SET; 685 686/* 687 * 802.11n specific structures and enums 688 */ 689typedef enum { 690 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 691 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 692} HAL_CHAIN_TYPE; 693 694typedef struct { 695 u_int Tries; 696 u_int Rate; /* hardware rate code */ 697 u_int RateIndex; /* rate series table index */ 698 u_int PktDuration; 699 u_int ChSel; 700 u_int RateFlags; 701#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 702#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 703#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 704#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 705 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 706} HAL_11N_RATE_SERIES; 707 708typedef enum { 709 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 710 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 711} HAL_HT_MACMODE; 712 713typedef enum { 714 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 715 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 716} HAL_HT_PHYMODE; 717 718typedef enum { 719 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 720 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 721} HAL_HT_EXTPROTSPACING; 722 723 724typedef enum { 725 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 726 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 727} HAL_HT_RXCLEAR; 728 729typedef enum { 730 HAL_FREQ_BAND_5GHZ = 0, 731 HAL_FREQ_BAND_2GHZ = 1, 732} HAL_FREQ_BAND; 733 734/* 735 * Antenna switch control. By default antenna selection 736 * enables multiple (2) antenna use. To force use of the 737 * A or B antenna only specify a fixed setting. Fixing 738 * the antenna will also disable any diversity support. 739 */ 740typedef enum { 741 HAL_ANT_VARIABLE = 0, /* variable by programming */ 742 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 743 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 744} HAL_ANT_SETTING; 745 746typedef enum { 747 HAL_M_STA = 1, /* infrastructure station */ 748 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 749 HAL_M_HOSTAP = 6, /* Software Access Point */ 750 HAL_M_MONITOR = 8 /* Monitor mode */ 751} HAL_OPMODE; 752 753typedef struct { 754 uint8_t kv_type; /* one of HAL_CIPHER */ 755 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 756 uint16_t kv_len; /* length in bits */ 757 uint8_t kv_val[16]; /* enough for 128-bit keys */ 758 uint8_t kv_mic[8]; /* TKIP MIC key */ 759 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 760} HAL_KEYVAL; 761 762/* 763 * This is the TX descriptor field which marks the key padding requirement. 764 * The naming is unfortunately unclear. 765 */ 766#define AH_KEYTYPE_MASK 0x0F 767typedef enum { 768 HAL_KEY_TYPE_CLEAR, 769 HAL_KEY_TYPE_WEP, 770 HAL_KEY_TYPE_AES, 771 HAL_KEY_TYPE_TKIP, 772} HAL_KEY_TYPE; 773 774typedef enum { 775 HAL_CIPHER_WEP = 0, 776 HAL_CIPHER_AES_OCB = 1, 777 HAL_CIPHER_AES_CCM = 2, 778 HAL_CIPHER_CKIP = 3, 779 HAL_CIPHER_TKIP = 4, 780 HAL_CIPHER_CLR = 5, /* no encryption */ 781 782 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 783} HAL_CIPHER; 784 785enum { 786 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 787 HAL_SLOT_TIME_9 = 9, 788 HAL_SLOT_TIME_20 = 20, 789}; 790 791/* 792 * Per-station beacon timer state. Note that the specified 793 * beacon interval (given in TU's) can also include flags 794 * to force a TSF reset and to enable the beacon xmit logic. 795 * If bs_cfpmaxduration is non-zero the hardware is setup to 796 * coexist with a PCF-capable AP. 797 */ 798typedef struct { 799 uint32_t bs_nexttbtt; /* next beacon in TU */ 800 uint32_t bs_nextdtim; /* next DTIM in TU */ 801 uint32_t bs_intval; /* beacon interval+flags */ 802/* 803 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 804 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 805 * register. 806 */ 807#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 808#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 809#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 810#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 811#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 812 uint32_t bs_dtimperiod; 813 uint16_t bs_cfpperiod; /* CFP period in TU */ 814 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 815 uint32_t bs_cfpnext; /* next CFP in TU */ 816 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 817 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 818 uint32_t bs_sleepduration; /* max sleep duration */ 819 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 820} HAL_BEACON_STATE; 821 822/* 823 * Like HAL_BEACON_STATE but for non-station mode setup. 824 * NB: see above flag definitions for bt_intval. 825 */ 826typedef struct { 827 uint32_t bt_intval; /* beacon interval+flags */ 828 uint32_t bt_nexttbtt; /* next beacon in TU */ 829 uint32_t bt_nextatim; /* next ATIM in TU */ 830 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 831 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 832 uint32_t bt_flags; /* timer enables */ 833#define HAL_BEACON_TBTT_EN 0x00000001 834#define HAL_BEACON_DBA_EN 0x00000002 835#define HAL_BEACON_SWBA_EN 0x00000004 836} HAL_BEACON_TIMERS; 837 838/* 839 * Per-node statistics maintained by the driver for use in 840 * optimizing signal quality and other operational aspects. 841 */ 842typedef struct { 843 uint32_t ns_avgbrssi; /* average beacon rssi */ 844 uint32_t ns_avgrssi; /* average data rssi */ 845 uint32_t ns_avgtxrssi; /* average tx rssi */ 846} HAL_NODE_STATS; 847 848#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 849 850 851struct ath_desc; 852struct ath_tx_status; 853struct ath_rx_status; 854struct ieee80211_channel; 855 856/* 857 * This is a channel survey sample entry. 858 * 859 * The AR5212 ANI routines fill these samples. The ANI code then uses it 860 * when calculating listen time; it is also exported via a diagnostic 861 * API. 862 */ 863typedef struct { 864 uint32_t seq_num; 865 uint32_t tx_busy; 866 uint32_t rx_busy; 867 uint32_t chan_busy; 868 uint32_t ext_chan_busy; 869 uint32_t cycle_count; 870 /* XXX TODO */ 871 uint32_t ofdm_phyerr_count; 872 uint32_t cck_phyerr_count; 873} HAL_SURVEY_SAMPLE; 874 875/* 876 * This provides 3.2 seconds of sample space given an 877 * ANI time of 1/10th of a second. This may not be enough! 878 */ 879#define CHANNEL_SURVEY_SAMPLE_COUNT 32 880 881typedef struct { 882 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 883 uint32_t cur_sample; /* current sample in sequence */ 884 uint32_t cur_seq; /* current sequence number */ 885} HAL_CHANNEL_SURVEY; 886 887/* 888 * ANI commands. 889 * 890 * These are used both internally and externally via the diagnostic 891 * API. 892 * 893 * Note that this is NOT the ANI commands being used via the INTMIT 894 * capability - that has a different mapping for some reason. 895 */ 896typedef enum { 897 HAL_ANI_PRESENT = 0, /* is ANI support present */ 898 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 899 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 900 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 901 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 902 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 903 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 904 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 905 HAL_ANI_MRC_CCK = 8, 906} HAL_ANI_CMD; 907 908#define HAL_ANI_ALL 0xffffffff 909 910/* 911 * This is the layout of the ANI INTMIT capability. 912 * 913 * Notice that the command values differ to HAL_ANI_CMD. 914 */ 915typedef enum { 916 HAL_CAP_INTMIT_PRESENT = 0, 917 HAL_CAP_INTMIT_ENABLE = 1, 918 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 919 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 920 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 921 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 922 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 923} HAL_CAP_INTMIT_CMD; 924 925typedef struct { 926 int32_t pe_firpwr; /* FIR pwr out threshold */ 927 int32_t pe_rrssi; /* Radar rssi thresh */ 928 int32_t pe_height; /* Pulse height thresh */ 929 int32_t pe_prssi; /* Pulse rssi thresh */ 930 int32_t pe_inband; /* Inband thresh */ 931 932 /* The following params are only for AR5413 and later */ 933 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 934 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 935 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 936 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 937 int32_t pe_blockradar; /* 938 * Enable to block radar check if pkt detect is done via OFDM 939 * weak signal detect or pkt is detected immediately after tx 940 * to rx transition 941 */ 942 int32_t pe_enmaxrssi; /* 943 * Enable to use the max rssi instead of the last rssi during 944 * fine gain changes for radar detection 945 */ 946 int32_t pe_extchannel; /* Enable DFS on ext channel */ 947 int32_t pe_enabled; /* Whether radar detection is enabled */ 948 int32_t pe_enrelpwr; 949 int32_t pe_en_relstep_check; 950} HAL_PHYERR_PARAM; 951 952#define HAL_PHYERR_PARAM_NOVAL 65535 953 954typedef struct { 955 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 956 u_int16_t ss_period; /* Spectral scan period */ 957 u_int16_t ss_count; /* # of reports to return from ss_active */ 958 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 959 u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 960 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 961 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 962 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 963 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 964 int ss_enabled; 965 int ss_active; 966} HAL_SPECTRAL_PARAM; 967#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 968#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 969 970/* 971 * DFS operating mode flags. 972 */ 973typedef enum { 974 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 975 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 976 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 977 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 978} HAL_DFS_DOMAIN; 979 980 981/* 982 * MFP decryption options for initializing the MAC. 983 */ 984typedef enum { 985 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 986 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 987 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 988} HAL_MFP_OPT_T; 989 990/* LNA config supported */ 991typedef enum { 992 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 993 HAL_ANT_DIV_COMB_LNA2 = 1, 994 HAL_ANT_DIV_COMB_LNA1 = 2, 995 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 996} HAL_ANT_DIV_COMB_LNA_CONF; 997 998typedef struct { 999 u_int8_t main_lna_conf; 1000 u_int8_t alt_lna_conf; 1001 u_int8_t fast_div_bias; 1002 u_int8_t main_gaintb; 1003 u_int8_t alt_gaintb; 1004 u_int8_t antdiv_configgroup; 1005 int8_t lna1_lna2_delta; 1006} HAL_ANT_COMB_CONFIG; 1007 1008#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 1009#define HAL_ANTDIV_CONFIG_GROUP_1 0x01 1010#define HAL_ANTDIV_CONFIG_GROUP_2 0x02 1011#define HAL_ANTDIV_CONFIG_GROUP_3 0x03 1012 1013/* 1014 * Flag for setting QUIET period 1015 */ 1016typedef enum { 1017 HAL_QUIET_DISABLE = 0x0, 1018 HAL_QUIET_ENABLE = 0x1, 1019 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1020 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1021} HAL_QUIET_FLAG; 1022 1023#define HAL_DFS_EVENT_PRICH 0x0000001 1024#define HAL_DFS_EVENT_EXTCH 0x0000002 1025#define HAL_DFS_EVENT_EXTEARLY 0x0000004 1026#define HAL_DFS_EVENT_ISDC 0x0000008 1027 1028struct hal_dfs_event { 1029 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1030 uint32_t re_ts; /* Original 15 bit recv timestamp */ 1031 uint8_t re_rssi; /* rssi of radar event */ 1032 uint8_t re_dur; /* duration of radar pulse */ 1033 uint32_t re_flags; /* Flags (see above) */ 1034}; 1035typedef struct hal_dfs_event HAL_DFS_EVENT; 1036 1037/* 1038 * Generic Timer domain 1039 */ 1040typedef enum { 1041 HAL_GEN_TIMER_TSF = 0, 1042 HAL_GEN_TIMER_TSF2, 1043 HAL_GEN_TIMER_TSF_ANY 1044} HAL_GEN_TIMER_DOMAIN; 1045 1046typedef enum { 1047 HAL_RESET_NONE = 0x0, 1048 HAL_RESET_BBPANIC = 0x1, 1049} HAL_RESET_TYPE; 1050 1051/* 1052 * BT Co-existence definitions 1053 */ 1054typedef enum { 1055 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 1056 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 1057 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 1058 HAL_MAX_BT_MODULES 1059} HAL_BT_MODULE; 1060 1061typedef struct { 1062 HAL_BT_MODULE bt_module; 1063 u_int8_t bt_coex_config; 1064 u_int8_t bt_gpio_bt_active; 1065 u_int8_t bt_gpio_bt_priority; 1066 u_int8_t bt_gpio_wlan_active; 1067 u_int8_t bt_active_polarity; 1068 HAL_BOOL bt_single_ant; 1069 u_int8_t bt_dutyCycle; 1070 u_int8_t bt_isolation; 1071 u_int8_t bt_period; 1072} HAL_BT_COEX_INFO; 1073 1074typedef enum { 1075 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 1076 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 1077 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 1078 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 1079} HAL_BT_COEX_MODE; 1080 1081typedef enum { 1082 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 1083 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 1084 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 1085 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 1086 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 1087 HAL_BT_COEX_CFG_MCI /* MCI */ 1088} HAL_BT_COEX_CFG; 1089 1090typedef enum { 1091 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 1092 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 1093 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 1094 HAL_BT_COEX_MCI_MAX_TX_PWR, /* Set max tx power for concurrent tx */ 1095 HAL_BT_COEX_MCI_FTP_STOMP_RX, /* Use a different weight for stomp low */ 1096} HAL_BT_COEX_SET_PARAMETER; 1097 1098#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 1099#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 1100/* Check Rx Diversity is allowed */ 1101#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 1102/* Check Diversity is on or off */ 1103#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 1104 1105#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 1106/* main: LNA1, alt: LNA2 */ 1107#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 1108#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 1109#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 1110#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 1111#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 1112 1113#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 1114 1115#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 1116 1117#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 1118 1119#define HAL_BT_COEX_LOW_ACK_POWER 0x0 1120#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 1121 1122typedef enum { 1123 HAL_BT_COEX_NO_STOMP = 0, 1124 HAL_BT_COEX_STOMP_ALL, 1125 HAL_BT_COEX_STOMP_LOW, 1126 HAL_BT_COEX_STOMP_NONE, 1127 HAL_BT_COEX_STOMP_ALL_FORCE, 1128 HAL_BT_COEX_STOMP_LOW_FORCE, 1129} HAL_BT_COEX_STOMP_TYPE; 1130 1131typedef struct { 1132 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 1133 u_int8_t bt_time_extend; 1134 1135 /* 1136 * extend rx_clear as long as txsm is 1137 * transmitting or waiting for ack. 1138 */ 1139 HAL_BOOL bt_txstate_extend; 1140 1141 /* 1142 * extend rx_clear so that when tx_frame 1143 * is asserted, rx_clear will drop. 1144 */ 1145 HAL_BOOL bt_txframe_extend; 1146 1147 /* 1148 * coexistence mode 1149 */ 1150 HAL_BT_COEX_MODE bt_mode; 1151 1152 /* 1153 * treat BT high priority traffic as 1154 * a quiet collision 1155 */ 1156 HAL_BOOL bt_quiet_collision; 1157 1158 /* 1159 * invert rx_clear as WLAN_ACTIVE 1160 */ 1161 HAL_BOOL bt_rxclear_polarity; 1162 1163 /* 1164 * slotted mode only. indicate the time in usec 1165 * from the rising edge of BT_ACTIVE to the time 1166 * BT_PRIORITY can be sampled to indicate priority. 1167 */ 1168 u_int8_t bt_priority_time; 1169 1170 /* 1171 * slotted mode only. indicate the time in usec 1172 * from the rising edge of BT_ACTIVE to the time 1173 * BT_PRIORITY can be sampled to indicate tx/rx and 1174 * BT_FREQ is sampled. 1175 */ 1176 u_int8_t bt_first_slot_time; 1177 1178 /* 1179 * slotted mode only. rx_clear and bt_ant decision 1180 * will be held the entire time that BT_ACTIVE is asserted, 1181 * otherwise the decision is made before every slot boundry. 1182 */ 1183 HAL_BOOL bt_hold_rxclear; 1184} HAL_BT_COEX_CONFIG; 1185 1186struct hal_bb_panic_info { 1187 u_int32_t status; 1188 u_int32_t tsf; 1189 u_int32_t phy_panic_wd_ctl1; 1190 u_int32_t phy_panic_wd_ctl2; 1191 u_int32_t phy_gen_ctrl; 1192 u_int32_t rxc_pcnt; 1193 u_int32_t rxf_pcnt; 1194 u_int32_t txf_pcnt; 1195 u_int32_t cycles; 1196 u_int32_t wd; 1197 u_int32_t det; 1198 u_int32_t rdar; 1199 u_int32_t r_odfm; 1200 u_int32_t r_cck; 1201 u_int32_t t_odfm; 1202 u_int32_t t_cck; 1203 u_int32_t agc; 1204 u_int32_t src; 1205}; 1206 1207/* Serialize Register Access Mode */ 1208typedef enum { 1209 SER_REG_MODE_OFF = 0, 1210 SER_REG_MODE_ON = 1, 1211 SER_REG_MODE_AUTO = 2, 1212} SER_REG_MODE; 1213 1214typedef struct 1215{ 1216 int ah_debug; /* only used if AH_DEBUG is defined */ 1217 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1218 1219 /* NB: these are deprecated; they exist for now for compatibility */ 1220 int ah_dma_beacon_response_time;/* in TU's */ 1221 int ah_sw_beacon_response_time; /* in TU's */ 1222 int ah_additional_swba_backoff; /* in TU's */ 1223 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1224 int ah_serialise_reg_war; /* force serialisation of register IO */ 1225 1226 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1227 int ath_hal_desc_tpc; /* Per-packet TPC */ 1228 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1229 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1230 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1231 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1232 1233 /* I'm not sure what the default values for these should be */ 1234 int ath_hal_pll_pwr_save; 1235 int ath_hal_pcie_power_save_enable; 1236 int ath_hal_intr_mitigation_rx; 1237 int ath_hal_intr_mitigation_tx; 1238 1239 int ath_hal_pcie_clock_req; 1240#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1241#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1242#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1243 1244 int ath_hal_pcie_waen; 1245 int ath_hal_pcie_ser_des_write; 1246 1247 /* these are important for correct AR9300 behaviour */ 1248 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1249 int ath_hal_diversity_control; 1250 int ath_hal_antenna_switch_swap; 1251 int ath_hal_ext_lna_ctl_gpio; 1252 int ath_hal_spur_mode; 1253 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1254 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1255 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1256 1257 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1258 int ath_hal_mfp_support; 1259 1260 int ath_hal_enable_ani; /* should set this.. */ 1261 int ath_hal_cwm_ignore_ext_cca; 1262 int ath_hal_show_bb_panic; 1263 int ath_hal_ant_ctrl_comm2g_switch_enable; 1264 int ath_hal_ext_atten_margin_cfg; 1265 int ath_hal_war70c; 1266 uint32_t ath_hal_mci_config; 1267} HAL_OPS_CONFIG; 1268 1269/* 1270 * Hardware Access Layer (HAL) API. 1271 * 1272 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1273 * ath_hal structure for use with the device. Hardware-related operations 1274 * that follow must call back into the HAL through interface, supplying 1275 * the reference as the first parameter. Note that before using the 1276 * reference returned by ath_hal_attach the caller should verify the 1277 * ABI version number. 1278 */ 1279struct ath_hal { 1280 uint32_t ah_magic; /* consistency check magic number */ 1281 uint16_t ah_devid; /* PCI device ID */ 1282 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1283 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1284 HAL_BUS_TAG ah_st; /* params for register r+w */ 1285 HAL_BUS_HANDLE ah_sh; 1286 HAL_CTRY_CODE ah_countryCode; 1287 1288 uint32_t ah_macVersion; /* MAC version id */ 1289 uint16_t ah_macRev; /* MAC revision */ 1290 uint16_t ah_phyRev; /* PHY revision */ 1291 /* NB: when only one radio is present the rev is in 5Ghz */ 1292 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1293 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1294 1295 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1296 1297 uint32_t ah_intrstate[8]; /* last int state */ 1298 uint32_t ah_syncstate; /* last sync intr state */ 1299 1300 HAL_OPS_CONFIG ah_config; 1301 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1302 u_int mode); 1303 void __ahdecl(*ah_detach)(struct ath_hal*); 1304 1305 /* Reset functions */ 1306 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1307 struct ieee80211_channel *, 1308 HAL_BOOL bChannelChange, HAL_STATUS *status); 1309 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1310 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1311 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1312 HAL_BOOL power_off); 1313 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1314 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1315 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1316 struct ieee80211_channel *, HAL_BOOL *); 1317 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1318 struct ieee80211_channel *, u_int chainMask, 1319 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1320 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1321 const struct ieee80211_channel *); 1322 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1323 const struct ieee80211_channel *, uint16_t *); 1324 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1325 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1326 const struct ieee80211_channel *); 1327 1328 /* Transmit functions */ 1329 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1330 HAL_BOOL incTrigLevel); 1331 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1332 const HAL_TXQ_INFO *qInfo); 1333 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1334 const HAL_TXQ_INFO *qInfo); 1335 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1336 HAL_TXQ_INFO *qInfo); 1337 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1338 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1339 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1340 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1341 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1342 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1343 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1344 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1345 u_int pktLen, u_int hdrLen, 1346 HAL_PKT_TYPE type, u_int txPower, 1347 u_int txRate0, u_int txTries0, 1348 u_int keyIx, u_int antMode, u_int flags, 1349 u_int rtsctsRate, u_int rtsctsDuration, 1350 u_int compicvLen, u_int compivLen, 1351 u_int comp); 1352 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1353 u_int txRate1, u_int txTries1, 1354 u_int txRate2, u_int txTries2, 1355 u_int txRate3, u_int txTries3); 1356 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1357 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1358 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1359 HAL_BOOL lastSeg, const struct ath_desc *); 1360 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1361 struct ath_desc *, struct ath_tx_status *); 1362 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1363 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1364 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1365 const struct ath_desc *ds, int *rates, int *tries); 1366 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1367 uint32_t link); 1368 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1369 uint32_t *link); 1370 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1371 uint32_t **linkptr); 1372 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1373 void *ts_start, uint32_t ts_paddr_start, 1374 uint16_t size); 1375 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1376 1377 /* Receive Functions */ 1378 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1379 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1380 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1381 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1382 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1383 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1384 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1385 uint32_t filter0, uint32_t filter1); 1386 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1387 uint32_t index); 1388 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1389 uint32_t index); 1390 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1391 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1392 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1393 uint32_t size, u_int flags); 1394 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1395 struct ath_desc *, uint32_t phyAddr, 1396 struct ath_desc *next, uint64_t tsf, 1397 struct ath_rx_status *); 1398 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1399 const HAL_NODE_STATS *, 1400 const struct ieee80211_channel *); 1401 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1402 const struct ieee80211_channel *); 1403 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1404 const HAL_NODE_STATS *); 1405 1406 /* Misc Functions */ 1407 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1408 HAL_CAPABILITY_TYPE, uint32_t capability, 1409 uint32_t *result); 1410 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1411 HAL_CAPABILITY_TYPE, uint32_t capability, 1412 uint32_t setting, HAL_STATUS *); 1413 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1414 const void *args, uint32_t argsize, 1415 void **result, uint32_t *resultsize); 1416 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1417 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1418 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1419 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1420 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1421 uint16_t, HAL_STATUS *); 1422 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1423 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1424 const uint8_t *bssid, uint16_t assocId); 1425 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1426 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1427 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1428 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1429 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1430 uint32_t gpio, uint32_t val); 1431 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1432 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1433 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1434 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1435 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1436 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1437 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1438 HAL_MIB_STATS*); 1439 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1440 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1441 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1442 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1443 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1444 HAL_ANT_SETTING); 1445 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1446 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1447 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1448 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1449 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1450 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1451 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1452 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1453 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1454 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1455 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1456 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1457 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1458 uint32_t duration, uint32_t nextStart, 1459 HAL_QUIET_FLAG flag); 1460 void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1461 uint32_t, uint32_t); 1462 1463 /* DFS functions */ 1464 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1465 HAL_PHYERR_PARAM *pe); 1466 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1467 HAL_PHYERR_PARAM *pe); 1468 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1469 HAL_PHYERR_PARAM *pe); 1470 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1471 struct ath_rx_status *rxs, uint64_t fulltsf, 1472 const char *buf, HAL_DFS_EVENT *event); 1473 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1474 1475 /* Spectral Scan functions */ 1476 void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1477 HAL_SPECTRAL_PARAM *sp); 1478 void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1479 HAL_SPECTRAL_PARAM *sp); 1480 void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1481 void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1482 HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1483 HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1484 /* XXX getNfPri() and getNfExt() */ 1485 1486 /* Key Cache Functions */ 1487 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1488 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1489 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1490 uint16_t); 1491 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1492 uint16_t, const HAL_KEYVAL *, 1493 const uint8_t *, int); 1494 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1495 uint16_t, const uint8_t *); 1496 1497 /* Power Management Functions */ 1498 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1499 HAL_POWER_MODE mode, int setChip); 1500 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1501 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1502 const struct ieee80211_channel *); 1503 1504 /* Beacon Management Functions */ 1505 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1506 const HAL_BEACON_TIMERS *); 1507 /* NB: deprecated, use ah_setBeaconTimers instead */ 1508 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1509 uint32_t nexttbtt, uint32_t intval); 1510 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1511 const HAL_BEACON_STATE *); 1512 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1513 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1514 1515 /* 802.11n Functions */ 1516 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1517 struct ath_desc *, 1518 HAL_DMA_ADDR *bufAddrList, 1519 uint32_t *segLenList, 1520 u_int, u_int, HAL_PKT_TYPE, 1521 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1522 HAL_BOOL, HAL_BOOL); 1523 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1524 struct ath_desc *, u_int, u_int, u_int, 1525 u_int, u_int, u_int, u_int, u_int); 1526 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1527 struct ath_desc *, const struct ath_desc *); 1528 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1529 struct ath_desc *, u_int, u_int, 1530 HAL_11N_RATE_SERIES [], u_int, u_int); 1531 1532 /* 1533 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1534 * to the EDMA HAL. Descriptors are chained together by 1535 * using filltxdesc (not ChainTxDesc) and then setting the 1536 * aggregate flags appropriately using first/middle/last. 1537 */ 1538 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1539 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1540 u_int); 1541 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1542 struct ath_desc *, u_int, u_int); 1543 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1544 struct ath_desc *, u_int); 1545 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1546 struct ath_desc *); 1547 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1548 struct ath_desc *); 1549 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1550 struct ath_desc *, u_int); 1551 void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1552 struct ath_desc *, u_int); 1553 1554 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1555 HAL_SURVEY_SAMPLE *); 1556 1557 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1558 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1559 HAL_HT_MACMODE); 1560 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1561 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1562 HAL_HT_RXCLEAR); 1563 1564 /* Interrupt functions */ 1565 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1566 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1567 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1568 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1569 1570 /* Bluetooth Coexistence functions */ 1571 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1572 HAL_BT_COEX_INFO *); 1573 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1574 HAL_BT_COEX_CONFIG *); 1575 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1576 int); 1577 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1578 uint32_t); 1579 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1580 uint32_t); 1581 void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *, 1582 uint32_t, uint32_t); 1583 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1584 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1585 1586 /* LNA diversity configuration */ 1587 void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *, 1588 HAL_ANT_COMB_CONFIG *); 1589 void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *, 1590 HAL_ANT_COMB_CONFIG *); 1591}; 1592 1593/* 1594 * Check the PCI vendor ID and device ID against Atheros' values 1595 * and return a printable description for any Atheros hardware. 1596 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1597 */ 1598extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1599 1600/* 1601 * Attach the HAL for use with the specified device. The device is 1602 * defined by the PCI device ID. The caller provides an opaque pointer 1603 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1604 * HAL state block for later use. Hardware register accesses are done 1605 * using the specified bus tag and handle. On successful return a 1606 * reference to a state block is returned that must be supplied in all 1607 * subsequent HAL calls. Storage associated with this reference is 1608 * dynamically allocated and must be freed by calling the ah_detach 1609 * method when the client is done. If the attach operation fails a 1610 * null (AH_NULL) reference will be returned and a status code will 1611 * be returned if the status parameter is non-zero. 1612 */ 1613extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1614 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1615 1616extern const char *ath_hal_mac_name(struct ath_hal *); 1617extern const char *ath_hal_rf_name(struct ath_hal *); 1618 1619/* 1620 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1621 * request a set of channels for a particular country code and/or 1622 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1623 * this list is constructed according to the contents of the EEPROM. 1624 * ath_hal_getchannels acts similarly but does not alter the operating 1625 * state; this can be used to collect information for a particular 1626 * regulatory configuration. Finally ath_hal_set_channels installs a 1627 * channel list constructed outside the driver. The HAL will adopt the 1628 * channel list and setup internal state according to the specified 1629 * regulatory configuration (e.g. conformance test limits). 1630 * 1631 * For all interfaces the channel list is returned in the supplied array. 1632 * maxchans defines the maximum size of this array. nchans contains the 1633 * actual number of channels returned. If a problem occurred then a 1634 * status code != HAL_OK is returned. 1635 */ 1636struct ieee80211_channel; 1637 1638/* 1639 * Return a list of channels according to the specified regulatory. 1640 */ 1641extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1642 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1643 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1644 HAL_BOOL enableExtendedChannels); 1645 1646/* 1647 * Return a list of channels and install it as the current operating 1648 * regulatory list. 1649 */ 1650extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1651 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1652 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1653 HAL_BOOL enableExtendedChannels); 1654 1655/* 1656 * Install the list of channels as the current operating regulatory 1657 * and setup related state according to the country code and sku. 1658 */ 1659extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1660 struct ieee80211_channel *chans, int nchans, 1661 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1662 1663/* 1664 * Fetch the ctl/ext noise floor values reported by a MIMO 1665 * radio. Returns 1 for valid results, 0 for invalid channel. 1666 */ 1667extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1668 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1669 int16_t *nf_ext); 1670 1671/* 1672 * Calibrate noise floor data following a channel scan or similar. 1673 * This must be called prior retrieving noise floor data. 1674 */ 1675extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1676 1677/* 1678 * Return bit mask of wireless modes supported by the hardware. 1679 */ 1680extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1681 1682/* 1683 * Get the HAL wireless mode for the given channel. 1684 */ 1685extern int ath_hal_get_curmode(struct ath_hal *ah, 1686 const struct ieee80211_channel *chan); 1687 1688/* 1689 * Calculate the packet TX time for a legacy or 11n frame 1690 */ 1691extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1692 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1693 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1694 1695/* 1696 * Calculate the duration of an 11n frame. 1697 */ 1698extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1699 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1700 1701/* 1702 * Calculate the transmit duration of a legacy frame. 1703 */ 1704extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1705 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1706 uint16_t rateix, HAL_BOOL shortPreamble); 1707 1708/* 1709 * Adjust the TSF. 1710 */ 1711extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1712 1713/* 1714 * Enable or disable CCA. 1715 */ 1716void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1717 1718/* 1719 * Get CCA setting. 1720 */ 1721int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1722 1723/* 1724 * Read EEPROM data from ah_eepromdata 1725 */ 1726HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1727 u_int off, uint16_t *data); 1728 1729/* 1730 * For now, simply pass through MFP frames. 1731 */ 1732static inline u_int32_t 1733ath_hal_get_mfp_qos(struct ath_hal *ah) 1734{ 1735 //return AH_PRIVATE(ah)->ah_mfp_qos; 1736 return HAL_MFP_QOSDATA; 1737} 1738 1739#endif /* _ATH_AH_H_ */ 1740