1/*- 2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/ata/ata-all.h> 50#include <dev/ata/ata-pci.h> 51#include <ata_if.h> 52 53/* local prototypes */ 54static int ata_nvidia_chipinit(device_t dev); 55static int ata_nvidia_ch_attach(device_t dev); 56static int ata_nvidia_ch_attach_dumb(device_t dev); 57static int ata_nvidia_status(device_t dev); 58static void ata_nvidia_reset(device_t dev); 59static int ata_nvidia_setmode(device_t dev, int target, int mode); 60 61/* misc defines */ 62#define NV4 0x01 63#define NVQ 0x02 64#define NVAHCI 0x04 65#define NVNOFORCE 0x08 66 67static int force_ahci = 1; 68TUNABLE_INT("hw.ahci.force", &force_ahci); 69 70/* 71 * nVidia chipset support functions 72 */ 73static int 74ata_nvidia_probe(device_t dev) 75{ 76 struct ata_pci_controller *ctlr = device_get_softc(dev); 77 static const struct ata_chip_id ids[] = 78 {{ ATA_NFORCE1, 0, 0, 0, ATA_UDMA5, "nForce" }, 79 { ATA_NFORCE2, 0, 0, 0, ATA_UDMA6, "nForce2" }, 80 { ATA_NFORCE2_PRO, 0, 0, 0, ATA_UDMA6, "nForce2 Pro" }, 81 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 82 { ATA_NFORCE3, 0, 0, 0, ATA_UDMA6, "nForce3" }, 83 { ATA_NFORCE3_PRO, 0, 0, 0, ATA_UDMA6, "nForce3 Pro" }, 84 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 85 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 86 { ATA_NFORCE_MCP04, 0, 0, 0, ATA_UDMA6, "nForce MCP" }, 87 { ATA_NFORCE_MCP04_S1, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 88 { ATA_NFORCE_MCP04_S2, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 89 { ATA_NFORCE_CK804, 0, 0, 0, ATA_UDMA6, "nForce CK804" }, 90 { ATA_NFORCE_CK804_S1, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 91 { ATA_NFORCE_CK804_S2, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 92 { ATA_NFORCE_MCP51, 0, 0, 0, ATA_UDMA6, "nForce MCP51" }, 93 { ATA_NFORCE_MCP51_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 94 { ATA_NFORCE_MCP51_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 95 { ATA_NFORCE_MCP55, 0, 0, 0, ATA_UDMA6, "nForce MCP55" }, 96 { ATA_NFORCE_MCP55_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 97 { ATA_NFORCE_MCP55_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 98 { ATA_NFORCE_MCP61, 0, 0, 0, ATA_UDMA6, "nForce MCP61" }, 99 { ATA_NFORCE_MCP61_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 100 { ATA_NFORCE_MCP61_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 101 { ATA_NFORCE_MCP61_S3, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 102 { ATA_NFORCE_MCP65, 0, 0, 0, ATA_UDMA6, "nForce MCP65" }, 103 { ATA_NFORCE_MCP65_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 104 { ATA_NFORCE_MCP65_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 105 { ATA_NFORCE_MCP65_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 106 { ATA_NFORCE_MCP65_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 107 { ATA_NFORCE_MCP65_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 108 { ATA_NFORCE_MCP65_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 109 { ATA_NFORCE_MCP65_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 110 { ATA_NFORCE_MCP65_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 111 { ATA_NFORCE_MCP67, 0, 0, 0, ATA_UDMA6, "nForce MCP67" }, 112 { ATA_NFORCE_MCP67_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 113 { ATA_NFORCE_MCP67_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 114 { ATA_NFORCE_MCP67_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 115 { ATA_NFORCE_MCP67_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 116 { ATA_NFORCE_MCP67_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 117 { ATA_NFORCE_MCP67_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 118 { ATA_NFORCE_MCP67_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 119 { ATA_NFORCE_MCP67_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 120 { ATA_NFORCE_MCP67_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 121 { ATA_NFORCE_MCP67_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 122 { ATA_NFORCE_MCP67_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 123 { ATA_NFORCE_MCP67_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 124 { ATA_NFORCE_MCP67_AC, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 125 { ATA_NFORCE_MCP73, 0, 0, 0, ATA_UDMA6, "nForce MCP73" }, 126 { ATA_NFORCE_MCP73_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 127 { ATA_NFORCE_MCP73_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 128 { ATA_NFORCE_MCP73_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 129 { ATA_NFORCE_MCP73_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 130 { ATA_NFORCE_MCP73_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 131 { ATA_NFORCE_MCP73_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 132 { ATA_NFORCE_MCP73_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 133 { ATA_NFORCE_MCP73_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 134 { ATA_NFORCE_MCP73_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 135 { ATA_NFORCE_MCP73_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 136 { ATA_NFORCE_MCP73_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 137 { ATA_NFORCE_MCP73_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 138 { ATA_NFORCE_MCP77, 0, 0, 0, ATA_UDMA6, "nForce MCP77" }, 139 { ATA_NFORCE_MCP77_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 140 { ATA_NFORCE_MCP77_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 141 { ATA_NFORCE_MCP77_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 142 { ATA_NFORCE_MCP77_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 143 { ATA_NFORCE_MCP77_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 144 { ATA_NFORCE_MCP77_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 145 { ATA_NFORCE_MCP77_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 146 { ATA_NFORCE_MCP77_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 147 { ATA_NFORCE_MCP77_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 148 { ATA_NFORCE_MCP77_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 149 { ATA_NFORCE_MCP77_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 150 { ATA_NFORCE_MCP77_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 151 { ATA_NFORCE_MCP79_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 152 { ATA_NFORCE_MCP79_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 153 { ATA_NFORCE_MCP79_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 154 { ATA_NFORCE_MCP79_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 155 { ATA_NFORCE_MCP79_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 156 { ATA_NFORCE_MCP79_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 157 { ATA_NFORCE_MCP79_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 158 { ATA_NFORCE_MCP79_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 159 { ATA_NFORCE_MCP79_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 160 { ATA_NFORCE_MCP79_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 161 { ATA_NFORCE_MCP79_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 162 { ATA_NFORCE_MCP79_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 163 { ATA_NFORCE_MCP89_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 164 { ATA_NFORCE_MCP89_A1, 0, NVAHCI|NVNOFORCE, 0, ATA_SA300, "nForce MCP89" }, 165 { ATA_NFORCE_MCP89_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 166 { ATA_NFORCE_MCP89_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 167 { ATA_NFORCE_MCP89_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 168 { ATA_NFORCE_MCP89_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 169 { ATA_NFORCE_MCP89_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 170 { ATA_NFORCE_MCP89_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 171 { ATA_NFORCE_MCP89_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 172 { ATA_NFORCE_MCP89_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 173 { ATA_NFORCE_MCP89_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 174 { ATA_NFORCE_MCP89_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 175 { 0, 0, 0, 0, 0, 0}} ; 176 177 if (pci_get_vendor(dev) != ATA_NVIDIA_ID) 178 return ENXIO; 179 180 if (!(ctlr->chip = ata_match_chip(dev, ids))) 181 return ENXIO; 182 183 ata_set_desc(dev); 184 if ((ctlr->chip->cfg1 & NVAHCI) && 185 ((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) || 186 pci_get_subclass(dev) != PCIS_STORAGE_IDE)) 187 ctlr->chipinit = ata_ahci_chipinit; 188 else 189 ctlr->chipinit = ata_nvidia_chipinit; 190 return (BUS_PROBE_DEFAULT); 191} 192 193static int 194ata_nvidia_chipinit(device_t dev) 195{ 196 struct ata_pci_controller *ctlr = device_get_softc(dev); 197 198 if (ata_setup_interrupt(dev, ata_generic_intr)) 199 return ENXIO; 200 201 if (ctlr->chip->cfg1 & NVAHCI) { 202 ctlr->ch_attach = ata_nvidia_ch_attach_dumb; 203 ctlr->setmode = ata_sata_setmode; 204 } else if (ctlr->chip->max_dma >= ATA_SA150) { 205 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 206 ctlr->r_type2 = SYS_RES_IOPORT; 207 else 208 ctlr->r_type2 = SYS_RES_MEMORY; 209 ctlr->r_rid2 = PCIR_BAR(5); 210 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 211 &ctlr->r_rid2, RF_ACTIVE))) { 212 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 213 214 ctlr->ch_attach = ata_nvidia_ch_attach; 215 ctlr->ch_detach = ata_pci_ch_detach; 216 ctlr->reset = ata_nvidia_reset; 217 218 /* enable control access */ 219 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 220 /* MCP55 seems to need some time to allow r_res2 read. */ 221 DELAY(10); 222 if (ctlr->chip->cfg1 & NVQ) { 223 /* clear interrupt status */ 224 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 225 226 /* enable device and PHY state change interrupts */ 227 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 228 229 /* disable NCQ support */ 230 ATA_OUTL(ctlr->r_res2, 0x0400, 231 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 232 } 233 else { 234 /* clear interrupt status */ 235 ATA_OUTB(ctlr->r_res2, offset, 0xff); 236 237 /* enable device and PHY state change interrupts */ 238 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 239 } 240 } 241 ctlr->setmode = ata_sata_setmode; 242 ctlr->getrev = ata_sata_getrev; 243 } 244 else { 245 /* disable prefetch, postwrite */ 246 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 247 ctlr->setmode = ata_nvidia_setmode; 248 } 249 return 0; 250} 251 252static int 253ata_nvidia_ch_attach(device_t dev) 254{ 255 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 256 struct ata_channel *ch = device_get_softc(dev); 257 258 /* setup the usual register normal pci style */ 259 if (ata_pci_ch_attach(dev)) 260 return ENXIO; 261 262 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 263 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 264 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 265 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 266 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 267 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 268 269 ch->hw.status = ata_nvidia_status; 270 ch->flags |= ATA_NO_SLAVE; 271 ch->flags |= ATA_SATA; 272 return 0; 273} 274 275static int 276ata_nvidia_ch_attach_dumb(device_t dev) 277{ 278 struct ata_channel *ch = device_get_softc(dev); 279 280 if (ata_pci_ch_attach(dev)) 281 return ENXIO; 282 ch->flags |= ATA_SATA; 283 return 0; 284} 285 286static int 287ata_nvidia_status(device_t dev) 288{ 289 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 290 struct ata_channel *ch = device_get_softc(dev); 291 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 292 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); 293 u_int32_t istatus; 294 295 /* get interrupt status */ 296 if (ctlr->chip->cfg1 & NVQ) 297 istatus = ATA_INL(ctlr->r_res2, offset); 298 else 299 istatus = ATA_INB(ctlr->r_res2, offset); 300 301 /* do we have any PHY events ? */ 302 if (istatus & (0x0c << shift)) 303 ata_sata_phy_check_events(dev, -1); 304 305 /* clear interrupt(s) */ 306 if (ctlr->chip->cfg1 & NVQ) 307 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 308 else 309 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 310 311 /* do we have any device action ? */ 312 return (istatus & (0x01 << shift)); 313} 314 315static void 316ata_nvidia_reset(device_t dev) 317{ 318 struct ata_channel *ch = device_get_softc(dev); 319 320 if (ata_sata_phy_reset(dev, -1, 1)) 321 ata_generic_reset(dev); 322 else 323 ch->devices = 0; 324} 325 326static int 327ata_nvidia_setmode(device_t dev, int target, int mode) 328{ 329 device_t parent = device_get_parent(dev); 330 struct ata_pci_controller *ctlr = device_get_softc(parent); 331 struct ata_channel *ch = device_get_softc(dev); 332 int devno = (ch->unit << 1) + target; 333 int piomode; 334 static const uint8_t timings[] = 335 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 336 static const uint8_t modes[] = 337 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }; 338 int reg = 0x63 - devno; 339 340 mode = min(mode, ctlr->chip->max_dma); 341 342 if (mode >= ATA_UDMA0) { 343 pci_write_config(parent, reg, modes[mode & ATA_MODE_MASK], 1); 344 piomode = ATA_PIO4; 345 } else { 346 pci_write_config(parent, reg, 0x8b, 1); 347 piomode = mode; 348 } 349 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1); 350 return (mode); 351} 352 353ATA_DECLARE_DRIVER(ata_nvidia); 354MODULE_DEPEND(ata_nvidia, ata_ahci, 1, 1, 1); 355