1183567Sstas/*- 2183567Sstas * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 3183567Sstas * All rights reserved. 4183567Sstas * 5183567Sstas * Redistribution and use in source and binary forms, with or without 6183567Sstas * modification, are permitted provided that the following conditions 7183567Sstas * are met: 8183567Sstas * 1. Redistributions of source code must retain the above copyright 9183567Sstas * notice, this list of conditions and the following disclaimer. 10183567Sstas * 2. Redistributions in binary form must reproduce the above copyright 11183567Sstas * notice, this list of conditions and the following disclaimer in the 12183567Sstas * documentation and/or other materials provided with the distribution. 13183567Sstas * 14183567Sstas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15183567Sstas * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16183567Sstas * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17183567Sstas * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18183567Sstas * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19183567Sstas * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20183567Sstas * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21183567Sstas * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22183567Sstas * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23183567Sstas * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24183567Sstas * 25183567Sstas * $FreeBSD$ 26183567Sstas */ 27183567Sstas 28183567Sstas/* 29183567Sstas * Master configuration register 30183567Sstas */ 31183567Sstas#define AE_MASTER_REG 0x1400 32183567Sstas 33183567Sstas#define AE_MASTER_SOFT_RESET 0x1 /* Reset adapter. */ 34183567Sstas#define AE_MASTER_MTIMER_EN 0x2 /* Unknown. */ 35183567Sstas#define AE_MASTER_IMT_EN 0x4 /* Interrupt moderation timer enable. */ 36183567Sstas#define AE_MASTER_MANUAL_INT 0x8 /* Software manual interrupt. */ 37183567Sstas#define AE_MASTER_REVNUM_SHIFT 16 /* Chip revision number. */ 38183567Sstas#define AE_MASTER_REVNUM_MASK 0xff 39183567Sstas#define AE_MASTER_DEVID_SHIFT 24 /* PCI device id. */ 40183567Sstas#define AE_MASTER_DEVID_MASK 0xff 41183567Sstas 42183567Sstas/* 43183567Sstas * Interrupt status register 44183567Sstas */ 45183567Sstas#define AE_ISR_REG 0x1600 46183567Sstas#define AE_ISR_TIMER 0x00000001 /* Counter expired. */ 47183567Sstas#define AE_ISR_MANUAL 0x00000002 /* Manual interrupt occuried. */ 48183567Sstas#define AE_ISR_RXF_OVERFLOW 0x00000004 /* RxF overflow occuried. */ 49183567Sstas#define AE_ISR_TXF_UNDERRUN 0x00000008 /* TxF underrun occuried. */ 50183567Sstas#define AE_ISR_TXS_OVERFLOW 0x00000010 /* TxS overflow occuried. */ 51183567Sstas#define AE_ISR_RXS_OVERFLOW 0x00000020 /* Internal RxS ring overflow. */ 52183567Sstas#define AE_ISR_LINK_CHG 0x00000040 /* Link state changed. */ 53183567Sstas#define AE_ISR_TXD_UNDERRUN 0x00000080 /* TxD underrun occuried. */ 54183567Sstas#define AE_ISR_RXD_OVERFLOW 0x00000100 /* RxD overflow occuried. */ 55183567Sstas#define AE_ISR_DMAR_TIMEOUT 0x00000200 /* DMA read timeout. */ 56183567Sstas#define AE_ISR_DMAW_TIMEOUT 0x00000400 /* DMA write timeout. */ 57183567Sstas#define AE_ISR_PHY 0x00000800 /* PHY interrupt. */ 58183567Sstas#define AE_ISR_TXS_UPDATED 0x00010000 /* Tx status updated. */ 59183567Sstas#define AE_ISR_RXD_UPDATED 0x00020000 /* Rx status updated. */ 60183567Sstas#define AE_ISR_TX_EARLY 0x00040000 /* TxMAC started transmit. */ 61183567Sstas#define AE_ISR_FIFO_UNDERRUN 0x01000000 /* FIFO underrun. */ 62183567Sstas#define AE_ISR_FRAME_ERROR 0x02000000 /* Frame receive error. */ 63183567Sstas#define AE_ISR_FRAME_SUCCESS 0x04000000 /* Frame receive success. */ 64183567Sstas#define AE_ISR_CRC_ERROR 0x08000000 /* CRC error occuried. */ 65183567Sstas#define AE_ISR_PHY_LINKDOWN 0x10000000 /* PHY link down. */ 66183567Sstas#define AE_ISR_DISABLE 0x80000000 /* Disable interrupts. */ 67183567Sstas 68183567Sstas#define AE_ISR_TX_EVENT (AE_ISR_TXF_UNDERRUN | AE_ISR_TXS_OVERFLOW | \ 69183567Sstas AE_ISR_TXD_UNDERRUN | AE_ISR_TXS_UPDATED | \ 70183567Sstas AE_ISR_TX_EARLY) 71183567Sstas#define AE_ISR_RX_EVENT (AE_ISR_RXF_OVERFLOW | AE_ISR_RXS_OVERFLOW | \ 72183567Sstas AE_ISR_RXD_OVERFLOW | AE_ISR_RXD_UPDATED) 73183567Sstas 74183567Sstas/* Interrupt mask register. */ 75183567Sstas#define AE_IMR_REG 0x1604 76183567Sstas 77183567Sstas#define AE_IMR_DEFAULT (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | \ 78183567Sstas AE_ISR_PHY_LINKDOWN | \ 79183567Sstas AE_ISR_TXS_UPDATED | AE_ISR_RXD_UPDATED ) 80183567Sstas 81183567Sstas/* 82183567Sstas * Ethernet address register. 83183567Sstas */ 84183567Sstas#define AE_EADDR0_REG 0x1488 /* 5 - 2 bytes */ 85183567Sstas#define AE_EADDR1_REG 0x148c /* 1 - 0 bytes */ 86183567Sstas 87183567Sstas/* 88183567Sstas * Desriptor rings registers. 89183567Sstas * L2 supports 64-bit addressing but all rings base addresses 90183567Sstas * should have the same high 32 bits of address. 91183567Sstas */ 92183567Sstas#define AE_DESC_ADDR_HI_REG 0x1540 /* High 32 bits of ring base address. */ 93183567Sstas#define AE_RXD_ADDR_LO_REG 0x1554 /* Low 32 bits of RxD ring address. */ 94183567Sstas#define AE_TXD_ADDR_LO_REG 0x1544 /* Low 32 bits of TxD ring address. */ 95183567Sstas#define AE_TXS_ADDR_LO_REG 0x154c /* Low 32 bits of TxS ring address. */ 96183567Sstas#define AE_RXD_COUNT_REG 0x1558 /* Number of RxD descriptors in ring. 97183567Sstas Should be 120-byte aligned (i.e. 98183567Sstas the 'data' field of RxD should 99183567Sstas have 128-byte alignment). */ 100183567Sstas#define AE_TXD_BUFSIZE_REG 0x1548 /* Size of TxD ring in 4-byte units. 101183567Sstas Should be 4-byte aligned. */ 102183567Sstas#define AE_TXS_COUNT_REG 0x1550 /* Number of TxS descriptors in ring. 103183567Sstas 4 byte alignment. */ 104183567Sstas#define AE_RXD_COUNT_MIN 16 105183567Sstas#define AE_RXD_COUNT_MAX 512 106183567Sstas#define AE_RXD_COUNT_DEFAULT 64 107253406Syongari/* Padding to align frames on a 128-byte boundary. */ 108253406Syongari#define AE_RXD_PADDING 120 109183567Sstas 110183567Sstas#define AE_TXD_BUFSIZE_MIN 4096 111183567Sstas#define AE_TXD_BUFSIZE_MAX 65536 112183567Sstas#define AE_TXD_BUFSIZE_DEFAULT 8192 113183567Sstas 114183567Sstas#define AE_TXS_COUNT_MIN 8 /* Not sure. */ 115183567Sstas#define AE_TXS_COUNT_MAX 160 116183567Sstas#define AE_TXS_COUNT_DEFAULT 64 /* AE_TXD_BUFSIZE_DEFAULT / 128 */ 117183567Sstas 118183567Sstas/* 119183567Sstas * Inter-frame gap configuration register. 120183567Sstas */ 121183567Sstas#define AE_IFG_REG 0x1484 122183567Sstas 123183567Sstas#define AE_IFG_TXIPG_DEFAULT 0x60 /* 96-bit IFG time. */ 124183567Sstas#define AE_IFG_TXIPG_SHIFT 0 125183567Sstas#define AE_IFG_TXIPG_MASK 0x7f 126183567Sstas 127183567Sstas#define AE_IFG_RXIPG_DEFAULT 0x50 /* 80-bit IFG time. */ 128183567Sstas#define AE_IFG_RXIPG_SHIFT 8 129183567Sstas#define AE_IFG_RXIPG_MASK 0xff00 130183567Sstas 131183567Sstas#define AE_IFG_IPGR1_DEFAULT 0x40 /* Carrier-sense window. */ 132183567Sstas#define AE_IFG_IPGR1_SHIFT 16 133183567Sstas#define AE_IFG_IPGR1_MASK 0x7f0000 134183567Sstas 135183567Sstas#define AE_IFG_IPGR2_DEFAULT 0x60 /* IFG window. */ 136183567Sstas#define AE_IFG_IPGR2_SHIFT 24 137183567Sstas#define AE_IFG_IPGR2_MASK 0x7f000000 138183567Sstas 139183567Sstas/* 140183567Sstas * Half-duplex mode configuration register. 141183567Sstas */ 142183567Sstas#define AE_HDPX_REG 0x1498 143183567Sstas 144183567Sstas/* Collision window. */ 145183567Sstas#define AE_HDPX_LCOL_SHIFT 0 146183567Sstas#define AE_HDPX_LCOL_MASK 0x000003ff 147183567Sstas#define AE_HDPX_LCOL_DEFAULT 0x37 148183567Sstas 149183567Sstas/* Max retransmission time, after that the packet will be discarded. */ 150183567Sstas#define AE_HDPX_RETRY_SHIFT 12 151183567Sstas#define AE_HDPX_RETRY_MASK 0x0000f000 152183567Sstas#define AE_HDPX_RETRY_DEFAULT 0x0f 153183567Sstas 154183567Sstas/* Alternative binary exponential back-off time. */ 155183567Sstas#define AE_HDPX_ABEBT_SHIFT 20 156183567Sstas#define AE_HDPX_ABEBT_MASK 0x00f00000 157183567Sstas#define AE_HDPX_ABEBT_DEFAULT 0x0a 158183567Sstas 159183567Sstas/* IFG to start JAM for collision based flow control (8-bit time units).*/ 160183567Sstas#define AE_HDPX_JAMIPG_SHIFT 24 161183567Sstas#define AE_HDPX_JAMIPG_MASK 0x0f000000 162183567Sstas#define AE_HDPX_JAMIPG_DEFAULT 0x07 163183567Sstas 164183567Sstas/* Allow the transmission of a packet which has been excessively deferred. */ 165183567Sstas#define AE_HDPX_EXC_EN 0x00010000 166183567Sstas/* No back-off on collision, immediately start the retransmission. */ 167183567Sstas#define AE_HDPX_NO_BACK_C 0x00020000 168183567Sstas/* No back-off on backpressure, immediately start the transmission. */ 169183567Sstas#define AE_HDPX_NO_BACK_P 0x00040000 170183567Sstas/* Alternative binary exponential back-off enable. */ 171183567Sstas#define AE_HDPX_ABEBE 0x00080000 172183567Sstas 173183567Sstas/* 174183567Sstas * Interrupt moderation timer configuration register. 175183567Sstas */ 176183567Sstas#define AE_IMT_REG 0x1408 /* Timer value in 2 us units. */ 177183567Sstas#define AE_IMT_MAX 65000 178183567Sstas#define AE_IMT_MIN 50 179183567Sstas#define AE_IMT_DEFAULT 100 /* 200 microseconds. */ 180183567Sstas 181183567Sstas/* 182183567Sstas * Interrupt clearing timer configuration register. 183183567Sstas */ 184183567Sstas#define AE_ICT_REG 0x140e /* Maximum time allowed to clear 185183567Sstas interrupt. In 2 us units. */ 186183567Sstas#define AE_ICT_DEFAULT 50000 /* 100ms */ 187183567Sstas 188183567Sstas/* 189183567Sstas * MTU configuration register. 190183567Sstas */ 191183567Sstas#define AE_MTU_REG 0x149c /* MTU size in bytes. */ 192183567Sstas 193183567Sstas/* 194183567Sstas * Cut-through configuration register. 195183567Sstas */ 196183567Sstas#define AE_CUT_THRESH_REG 0x1590 /* Cut-through threshold in unknown units. */ 197183567Sstas#define AE_CUT_THRESH_DEFAULT 0x177 198183567Sstas 199183567Sstas/* 200183567Sstas * Flow-control configuration registers. 201183567Sstas */ 202183567Sstas#define AE_FLOW_THRESH_HI_REG 0x15a8 /* High watermark of RxD 203183567Sstas overflow threshold. */ 204183567Sstas#define AE_FLOW_THRESH_LO_REG 0x15aa /* Lower watermark of RxD 205183567Sstas overflow threshold */ 206183567Sstas 207183567Sstas/* 208183567Sstas * Mailbox configuration registers. 209183567Sstas*/ 210183567Sstas#define AE_MB_TXD_IDX_REG 0x15f0 /* TxD read index. */ 211183567Sstas#define AE_MB_RXD_IDX_REG 0x15f4 /* RxD write index. */ 212183567Sstas 213183567Sstas/* 214183567Sstas * DMA configuration registers. 215183567Sstas */ 216183567Sstas#define AE_DMAREAD_REG 0x1580 /* Read DMA configuration register. */ 217183567Sstas#define AE_DMAREAD_EN 1 218183567Sstas#define AE_DMAWRITE_REG 0x15a0 /* Write DMA configuration register. */ 219183567Sstas#define AE_DMAWRITE_EN 1 220183567Sstas 221183567Sstas/* 222183567Sstas * MAC configuration register. 223183567Sstas */ 224183567Sstas#define AE_MAC_REG 0x1480 225183567Sstas 226183567Sstas#define AE_MAC_TX_EN 0x00000001 /* Enable transmit. */ 227183567Sstas#define AE_MAC_RX_EN 0x00000002 /* Enable receive. */ 228183567Sstas#define AE_MAC_TX_FLOW_EN 0x00000004 /* Enable Tx flow control. */ 229183567Sstas#define AE_MAC_RX_FLOW_EN 0x00000008 /* Enable Rx flow control. */ 230183567Sstas#define AE_MAC_LOOPBACK 0x00000010 /* Loopback at MII. */ 231183567Sstas#define AE_MAC_FULL_DUPLEX 0x00000020 /* Enable full-duplex. */ 232183567Sstas#define AE_MAC_TX_CRC_EN 0x00000040 /* Enable CRC generation. */ 233183567Sstas#define AE_MAC_TX_AUTOPAD 0x00000080 /* Pad short frames. */ 234183567Sstas#define AE_MAC_PREAMBLE_MASK 0x00003c00 /* Preamble length. */ 235183567Sstas#define AE_MAC_PREAMBLE_SHIFT 10 236183567Sstas#define AE_MAC_PREAMBLE_DEFAULT 0x07 /* By standard. */ 237183567Sstas#define AE_MAC_RMVLAN_EN 0x00004000 /* Remove VLAN tags in 238183567Sstas incoming packets. */ 239183567Sstas#define AE_MAC_PROMISC_EN 0x00008000 /* Enable promiscue mode. */ 240183567Sstas#define AE_MAC_TX_MAXBACKOFF 0x00100000 /* Unknown. */ 241183567Sstas#define AE_MAC_MCAST_EN 0x02000000 /* Pass all multicast frames. */ 242183567Sstas#define AE_MAC_BCAST_EN 0x04000000 /* Pass all broadcast frames. */ 243183567Sstas#define AE_MAC_CLK_PHY 0x08000000 /* If 1 uses loopback clock 244183567Sstas PHY, if 0 - system clock. */ 245183567Sstas#define AE_HALFBUF_MASK 0xf0000000 /* Half-duplex retry buffer. */ 246183567Sstas#define AE_HALFBUF_SHIFT 28 247183567Sstas#define AE_HALFBUF_DEFAULT 2 /* XXX: From Linux. */ 248183567Sstas 249183567Sstas/* 250183567Sstas * MDIO control register. 251183567Sstas */ 252183567Sstas#define AE_MDIO_REG 0x1414 253183567Sstas#define AE_MDIO_DATA_MASK 0xffff 254183567Sstas#define AE_MDIO_DATA_SHIFT 0 255183567Sstas#define AE_MDIO_REGADDR_MASK 0x1f0000 256183567Sstas#define AE_MDIO_REGADDR_SHIFT 16 257183567Sstas#define AE_MDIO_READ 0x00200000 /* Read operation. */ 258183567Sstas#define AE_MDIO_SUP_PREAMBLE 0x00400000 /* Suppress preamble. */ 259183567Sstas#define AE_MDIO_START 0x00800000 /* Initiate MDIO transfer. */ 260183567Sstas#define AE_MDIO_CLK_SHIFT 24 /* Clock selection. */ 261183567Sstas#define AE_MDIO_CLK_MASK 0x07000000 /* Clock selection. */ 262183567Sstas#define AE_MDIO_CLK_25_4 0 /* Dividers? */ 263183567Sstas#define AE_MDIO_CLK_25_6 2 264183567Sstas#define AE_MDIO_CLK_25_8 3 265183567Sstas#define AE_MDIO_CLK_25_10 4 266183567Sstas#define AE_MDIO_CLK_25_14 5 267183567Sstas#define AE_MDIO_CLK_25_20 6 268183567Sstas#define AE_MDIO_CLK_25_28 7 269183567Sstas#define AE_MDIO_BUSY 0x08000000 /* MDIO is busy. */ 270183567Sstas 271183567Sstas/* 272183567Sstas * Idle status register. 273183567Sstas */ 274183567Sstas#define AE_IDLE_REG 0x1410 275183567Sstas 276183567Sstas/* 277183567Sstas * Idle status bits. 278183567Sstas * If bit is set then the corresponding module is in non-idle state. 279183567Sstas */ 280183567Sstas#define AE_IDLE_RXMAC 1 281183567Sstas#define AE_IDLE_TXMAC 2 282183567Sstas#define AE_IDLE_DMAREAD 8 283183567Sstas#define AE_IDLE_DMAWRITE 4 284183567Sstas 285183567Sstas/* 286183567Sstas * Multicast hash tables registers. 287183567Sstas */ 288183567Sstas#define AE_REG_MHT0 0x1490 289183567Sstas#define AE_REG_MHT1 0x1494 290183567Sstas 291183567Sstas/* 292183567Sstas * Wake on lan (WOL). 293183567Sstas */ 294183567Sstas#define AE_WOL_REG 0x14a0 295183567Sstas#define AE_WOL_MAGIC 0x00000004 296183567Sstas#define AE_WOL_MAGIC_PME 0x00000008 297183567Sstas#define AE_WOL_LNKCHG 0x00000010 298183567Sstas#define AE_WOL_LNKCHG_PME 0x00000020 299183567Sstas 300183567Sstas/* 301183567Sstas * PCIE configuration registers. Descriptions unknown. 302183567Sstas */ 303183567Sstas#define AE_PCIE_LTSSM_TESTMODE_REG 0x12fc 304183567Sstas#define AE_PCIE_LTSSM_TESTMODE_DEFAULT 0x6500 305183567Sstas#define AE_PCIE_DLL_TX_CTRL_REG 0x1104 306183567Sstas#define AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK 0x0400 307183567Sstas#define AE_PCIE_DLL_TX_CTRL_DEFAULT 0x0568 308183567Sstas#define AE_PCIE_PHYMISC_REG 0x1000 309183567Sstas#define AE_PCIE_PHYMISC_FORCE_RCV_DET 0x4 310183567Sstas 311183567Sstas/* 312183567Sstas * PHY enable register. 313183567Sstas */ 314183567Sstas#define AE_PHY_ENABLE_REG 0x140c 315183567Sstas#define AE_PHY_ENABLE 1 316183567Sstas 317183567Sstas/* 318183567Sstas * VPD registers. 319183567Sstas */ 320183567Sstas#define AE_VPD_CAP_REG 0x6c /* Command register. */ 321183567Sstas#define AE_VPD_CAP_ID_MASK 0xff 322183567Sstas#define AE_VPD_CAP_ID_SHIFT 0 323183567Sstas#define AE_VPD_CAP_NEXT_MASK 0xff00 324183567Sstas#define AE_VPD_CAP_NEXT_SHIFT 8 325183567Sstas#define AE_VPD_CAP_ADDR_MASK 0x7fff0000 326183567Sstas#define AE_VPD_CAP_ADDR_SHIFT 16 327183567Sstas#define AE_VPD_CAP_DONE 0x80000000 328183567Sstas 329183567Sstas#define AE_VPD_DATA_REG 0x70 /* Data register. */ 330183567Sstas 331183567Sstas#define AE_VPD_NREGS 64 /* Maximum number of VPD regs. */ 332183567Sstas#define AE_VPD_SIG_MASK 0xff 333183567Sstas#define AE_VPD_SIG 0x5a /* VPD block signature. */ 334183567Sstas#define AE_VPD_REG_SHIFT 16 /* Register id offset. */ 335183567Sstas 336183567Sstas/* 337183567Sstas * SPI registers. 338183567Sstas */ 339183567Sstas#define AE_SPICTL_REG 0x200 340183567Sstas#define AE_SPICTL_VPD_EN 0x2000 /* Enable VPD. */ 341183567Sstas 342183567Sstas/* 343183567Sstas * PHY-specific registers constants. 344183567Sstas */ 345183567Sstas#define AE_PHY_DBG_ADDR 0x1d 346183567Sstas#define AE_PHY_DBG_DATA 0x1e 347183567Sstas#define AE_PHY_DBG_POWERSAVE 0x1000 348183567Sstas 349183567Sstas/* 350183567Sstas * TxD flags. 351183567Sstas */ 352183567Sstas#define AE_TXD_INSERT_VTAG 0x8000 /* Insert VLAN tag on transfer. */ 353183567Sstas 354183567Sstas/* 355183567Sstas * TxS flags. 356183567Sstas */ 357183567Sstas#define AE_TXS_SUCCESS 0x0001 /* Packed transmitted successfully. */ 358183567Sstas#define AE_TXS_BCAST 0x0002 /* Transmitted broadcast frame. */ 359183567Sstas#define AE_TXS_MCAST 0x0004 /* Transmitted multicast frame. */ 360183567Sstas#define AE_TXS_PAUSE 0x0008 /* Transmitted pause frame. */ 361183567Sstas#define AE_TXS_CTRL 0x0010 /* Transmitted control frame. */ 362183567Sstas#define AE_TXS_DEFER 0x0020 /* Frame transmitted with defer. */ 363183567Sstas#define AE_TXS_EXCDEFER 0x0040 /* Excessive collision. */ 364183567Sstas#define AE_TXS_SINGLECOL 0x0080 /* Single collision occuried. */ 365183567Sstas#define AE_TXS_MULTICOL 0x0100 /* Multiple collisions occuried. */ 366183567Sstas#define AE_TXS_LATECOL 0x0200 /* Late collision occuried. */ 367183567Sstas#define AE_TXS_ABORTCOL 0x0400 /* Frame abort due to collisions. */ 368183567Sstas#define AE_TXS_UNDERRUN 0x0800 /* Tx SRAM underrun occuried. */ 369183567Sstas#define AE_TXS_UPDATE 0x8000 370183567Sstas 371183567Sstas/* 372183567Sstas * RxD flags. 373183567Sstas */ 374183567Sstas#define AE_RXD_SUCCESS 0x0001 375183567Sstas#define AE_RXD_BCAST 0x0002 /* Broadcast frame received. */ 376183567Sstas#define AE_RXD_MCAST 0x0004 /* Multicast frame received. */ 377183567Sstas#define AE_RXD_PAUSE 0x0008 /* Pause frame received. */ 378183567Sstas#define AE_RXD_CTRL 0x0010 /* Control frame received. */ 379183567Sstas#define AE_RXD_CRCERR 0x0020 /* Invalid frame CRC. */ 380183567Sstas#define AE_RXD_CODEERR 0x0040 /* Invalid frame opcode. */ 381183567Sstas#define AE_RXD_RUNT 0x0080 /* Runt frame received. */ 382183567Sstas#define AE_RXD_FRAG 0x0100 /* Collision fragment received. */ 383183567Sstas#define AE_RXD_TRUNC 0x0200 /* The frame was truncated due 384183567Sstas to Rx SRAM underrun. */ 385183567Sstas#define AE_RXD_ALIGN 0x0400 /* Frame alignment error. */ 386183567Sstas#define AE_RXD_HAS_VLAN 0x0800 /* VLAN tag present. */ 387183567Sstas#define AE_RXD_UPDATE 0x8000 388