cvmx-zip-defs.h revision 215990
11541Srgrimes/***********************license start*************** 21541Srgrimes * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 31541Srgrimes * reserved. 41541Srgrimes * 51541Srgrimes * 61541Srgrimes * Redistribution and use in source and binary forms, with or without 71541Srgrimes * modification, are permitted provided that the following conditions are 81541Srgrimes * met: 91541Srgrimes * 101541Srgrimes * * Redistributions of source code must retain the above copyright 111541Srgrimes * notice, this list of conditions and the following disclaimer. 121541Srgrimes * 131541Srgrimes * * Redistributions in binary form must reproduce the above 141541Srgrimes * copyright notice, this list of conditions and the following 151541Srgrimes * disclaimer in the documentation and/or other materials provided 161541Srgrimes * with the distribution. 171541Srgrimes 181541Srgrimes * * Neither the name of Cavium Networks nor the names of 191541Srgrimes * its contributors may be used to endorse or promote products 201541Srgrimes * derived from this software without specific prior written 211541Srgrimes * permission. 221541Srgrimes 231541Srgrimes * This Software, including technical data, may be subject to U.S. export control 241541Srgrimes * laws, including the U.S. Export Administration Act and its associated 251541Srgrimes * regulations, and may be subject to export or import regulations in other 261541Srgrimes * countries. 271541Srgrimes 281541Srgrimes * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 291541Srgrimes * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 301541Srgrimes * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 311541Srgrimes * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 321541Srgrimes * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 331541Srgrimes * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 3444510Swollman * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 351541Srgrimes * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 361541Srgrimes * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37116182Sobrien * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38116182Sobrien ***********************license end**************************************/ 39116182Sobrien 40247777Sdavide 41187664Srwatson/** 42247777Sdavide * cvmx-zip-defs.h 43247777Sdavide * 44247777Sdavide * Configuration and status register (CSR) type definitions for 45187664Srwatson * Octeon zip. 461541Srgrimes * 471541Srgrimes * This file is auto generated. Do not edit. 48177859Sjeff * 4933392Sphk * <hr>$Revision$<hr> 50177859Sjeff * 511541Srgrimes */ 52133229Srwatson#ifndef __CVMX_ZIP_TYPEDEFS_H__ 5374914Sjhb#define __CVMX_ZIP_TYPEDEFS_H__ 54177859Sjeff 5568840Sjhb#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56150188Sjhb#define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC() 57187664Srwatsonstatic inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void) 58171053Sattilio{ 59115810Sphk if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60177859Sjeff cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n"); 611541Srgrimes return CVMX_ADD_IO_SEG(0x0001180038000080ull); 62220456Sattilio} 63220456Sattilio#else 64220456Sattilio#define CVMX_ZIP_CMD_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180038000080ull)) 65220456Sattilio#endif 66247777Sdavide#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67247777Sdavide#define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC() 68247777Sdavidestatic inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void) 69247777Sdavide{ 70187664Srwatson if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71211616Srpaulo cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n"); 72187664Srwatson return CVMX_ADD_IO_SEG(0x0001180038000008ull); 73187664Srwatson} 74211616Srpaulo#else 75187664Srwatson#define CVMX_ZIP_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180038000008ull)) 76187664Srwatson#endif 77187664Srwatson#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78247777Sdavide#define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC() 79115810Sphkstatic inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void) 80115810Sphk{ 81115810Sphk if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 82115810Sphk cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n"); 83115810Sphk return CVMX_ADD_IO_SEG(0x0001180038000000ull); 84115810Sphk} 85173760Sattilio#else 86173760Sattilio#define CVMX_ZIP_CMD_CTL (CVMX_ADD_IO_SEG(0x0001180038000000ull)) 87173760Sattilio#endif 88115810Sphk#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89115810Sphk#define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC() 90115810Sphkstatic inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void) 91247777Sdavide{ 92247777Sdavide if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 93247777Sdavide cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n"); 94247777Sdavide return CVMX_ADD_IO_SEG(0x00011800380000A0ull); 95247777Sdavide} 96247777Sdavide#else 97247777Sdavide#define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull)) 98247777Sdavide#endif 99247777Sdavide#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100247777Sdavide#define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC() 101247777Sdavidestatic inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void) 102247777Sdavide{ 103247777Sdavide if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 10433392Sphk cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n"); 10533392Sphk return CVMX_ADD_IO_SEG(0x0001180038000098ull); 10633392Sphk} 10733392Sphk#else 108247715Sdavide#define CVMX_ZIP_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180038000098ull)) 1092112Swollman#endif 110200510Sluigi#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111247777Sdavide#define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC() 112247777Sdavidestatic inline uint64_t CVMX_ZIP_ERROR_FUNC(void) 113247777Sdavide{ 114247777Sdavide if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 115247777Sdavide cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n"); 116247777Sdavide return CVMX_ADD_IO_SEG(0x0001180038000088ull); 117220456Sattilio} 118220456Sattilio#else 119220456Sattilio#define CVMX_ZIP_ERROR (CVMX_ADD_IO_SEG(0x0001180038000088ull)) 120247777Sdavide#endif 121247777Sdavide#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122247777Sdavide#define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC() 123220456Sattiliostatic inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void) 124247777Sdavide{ 125247777Sdavide if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 126247777Sdavide cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n"); 127247777Sdavide return CVMX_ADD_IO_SEG(0x0001180038000090ull); 128220456Sattilio} 129247813Sdavide#else 130247813Sdavide#define CVMX_ZIP_INT_MASK (CVMX_ADD_IO_SEG(0x0001180038000090ull)) 131220456Sattilio#endif 132247467Sdavide#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133220456Sattilio#define CVMX_ZIP_THROTTLE CVMX_ZIP_THROTTLE_FUNC() 134200510Sluigistatic inline uint64_t CVMX_ZIP_THROTTLE_FUNC(void) 135200510Sluigi{ 136200510Sluigi if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 137177859Sjeff cvmx_warn("CVMX_ZIP_THROTTLE not supported on this chip\n"); 138242402Sattilio return CVMX_ADD_IO_SEG(0x0001180038000010ull); 139247777Sdavide} 140177859Sjeff#else 141247777Sdavide#define CVMX_ZIP_THROTTLE (CVMX_ADD_IO_SEG(0x0001180038000010ull)) 142247777Sdavide#endif 143247777Sdavide 144247777Sdavide/** 145247777Sdavide * cvmx_zip_cmd_bist_result 146177859Sjeff * 147247777Sdavide * Notes: 148177859Sjeff * Access to the internal BiST results 149128024Scperciva * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 150247777Sdavide */ 151247777Sdavideunion cvmx_zip_cmd_bist_result 152247777Sdavide{ 153247777Sdavide uint64_t u64; 154247777Sdavide struct cvmx_zip_cmd_bist_result_s 155247777Sdavide { 156247777Sdavide#if __BYTE_ORDER == __BIG_ENDIAN 157247777Sdavide uint64_t reserved_43_63 : 21; 158247777Sdavide uint64_t zip_core : 39; /**< BiST result of the ZIP_CORE memories */ 159177859Sjeff uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */ 160247777Sdavide#else 161247777Sdavide uint64_t zip_ctl : 4; 162247777Sdavide uint64_t zip_core : 39; 163247777Sdavide uint64_t reserved_43_63 : 21; 164247777Sdavide#endif 165247777Sdavide } s; 166247777Sdavide struct cvmx_zip_cmd_bist_result_cn31xx 167247777Sdavide { 168220456Sattilio#if __BYTE_ORDER == __BIG_ENDIAN 169177859Sjeff uint64_t reserved_31_63 : 33; 170220456Sattilio uint64_t zip_core : 27; /**< BiST result of the ZIP_CORE memories */ 171177859Sjeff uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */ 172177859Sjeff#else 173177859Sjeff uint64_t zip_ctl : 4; 174177859Sjeff uint64_t zip_core : 27; 175177859Sjeff uint64_t reserved_31_63 : 33; 176177859Sjeff#endif 177177859Sjeff } cn31xx; 178177859Sjeff struct cvmx_zip_cmd_bist_result_cn31xx cn38xx; 179177859Sjeff struct cvmx_zip_cmd_bist_result_cn31xx cn38xxp2; 180220456Sattilio struct cvmx_zip_cmd_bist_result_cn31xx cn56xx; 181177859Sjeff struct cvmx_zip_cmd_bist_result_cn31xx cn56xxp1; 182177859Sjeff struct cvmx_zip_cmd_bist_result_cn31xx cn58xx; 183177859Sjeff struct cvmx_zip_cmd_bist_result_cn31xx cn58xxp1; 184247777Sdavide struct cvmx_zip_cmd_bist_result_s cn63xx; 185247777Sdavide struct cvmx_zip_cmd_bist_result_s cn63xxp1; 186247777Sdavide}; 187247777Sdavidetypedef union cvmx_zip_cmd_bist_result cvmx_zip_cmd_bist_result_t; 188247777Sdavide 189247777Sdavide/** 190227293Sed * cvmx_zip_cmd_buf 191177859Sjeff * 192139831Scperciva * Notes: 193177859Sjeff * Sets the command buffer parameters 194247777Sdavide * The size of the command buffer segments is measured in uint64s. The pool specifies (1 of 8 free 195247777Sdavide * lists to be used when freeing command buffer segments. The PTR field is overwritten with the next 196177859Sjeff * pointer each time that the command buffer segment is exhausted. 197127969Scperciva * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite 198247777Sdavide * this register to effectively reset the command buffer state machine. New commands will then be 199141428Siedowse * read from the newly specified command buffer pointer. 200141428Siedowse */ 201173760Sattiliounion cvmx_zip_cmd_buf 202155957Sjhb{ 203247777Sdavide uint64_t u64; 204177859Sjeff struct cvmx_zip_cmd_buf_s 205155957Sjhb { 206247777Sdavide#if __BYTE_ORDER == __BIG_ENDIAN 207127969Scperciva uint64_t reserved_58_63 : 6; 208128024Scperciva uint64_t dwb : 9; /**< Number of DontWriteBacks */ 2091541Srgrimes uint64_t pool : 3; /**< Free list used to free command buffer segments */ 210247777Sdavide uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 211220456Sattilio uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */ 212220456Sattilio#else 213247777Sdavide uint64_t ptr : 33; 214220456Sattilio uint64_t size : 13; 215220456Sattilio uint64_t pool : 3; 216247777Sdavide uint64_t dwb : 9; 217247777Sdavide uint64_t reserved_58_63 : 6; 218247777Sdavide#endif 219247777Sdavide } s; 220220456Sattilio struct cvmx_zip_cmd_buf_s cn31xx; 221247777Sdavide struct cvmx_zip_cmd_buf_s cn38xx; 222247777Sdavide struct cvmx_zip_cmd_buf_s cn38xxp2; 223247777Sdavide struct cvmx_zip_cmd_buf_s cn56xx; 224247777Sdavide struct cvmx_zip_cmd_buf_s cn56xxp1; 225220456Sattilio struct cvmx_zip_cmd_buf_s cn58xx; 226220456Sattilio struct cvmx_zip_cmd_buf_s cn58xxp1; 227220456Sattilio struct cvmx_zip_cmd_buf_s cn63xx; 228220456Sattilio struct cvmx_zip_cmd_buf_s cn63xxp1; 229220456Sattilio}; 230220456Sattiliotypedef union cvmx_zip_cmd_buf cvmx_zip_cmd_buf_t; 231220456Sattilio 232247777Sdavide/** 233220456Sattilio * cvmx_zip_cmd_ctl 234220456Sattilio */ 235220456Sattiliounion cvmx_zip_cmd_ctl 236247777Sdavide{ 237220456Sattilio uint64_t u64; 238220456Sattilio struct cvmx_zip_cmd_ctl_s 239220456Sattilio { 240220456Sattilio#if __BYTE_ORDER == __BIG_ENDIAN 241220456Sattilio uint64_t reserved_2_63 : 62; 242220456Sattilio uint64_t forceclk : 1; /**< Force zip_ctl__clock_on_b == 1 when set */ 243247698Smav uint64_t reset : 1; /**< Reset oneshot pulse for zip core */ 24482127Sdillon#else 24582127Sdillon uint64_t reset : 1; 24682127Sdillon uint64_t forceclk : 1; 24782127Sdillon uint64_t reserved_2_63 : 62; 24882127Sdillon#endif 24982127Sdillon } s; 25082127Sdillon struct cvmx_zip_cmd_ctl_s cn31xx; 251177859Sjeff struct cvmx_zip_cmd_ctl_s cn38xx; 252177859Sjeff struct cvmx_zip_cmd_ctl_s cn38xxp2; 253177859Sjeff struct cvmx_zip_cmd_ctl_s cn56xx; 254177859Sjeff struct cvmx_zip_cmd_ctl_s cn56xxp1; 25582127Sdillon struct cvmx_zip_cmd_ctl_s cn58xx; 256243853Salfred struct cvmx_zip_cmd_ctl_s cn58xxp1; 257243853Salfred struct cvmx_zip_cmd_ctl_s cn63xx; 25882127Sdillon struct cvmx_zip_cmd_ctl_s cn63xxp1; 259243853Salfred}; 26082127Sdillontypedef union cvmx_zip_cmd_ctl cvmx_zip_cmd_ctl_t; 26182127Sdillon 262177859Sjeff/** 263177859Sjeff * cvmx_zip_constants 264247777Sdavide * 265177859Sjeff * Notes: 26682127Sdillon * Note that this CSR is present only in chip revisions beginning with pass2. 26782127Sdillon * 26882127Sdillon */ 269177859Sjeffunion cvmx_zip_constants 270177859Sjeff{ 271177859Sjeff uint64_t u64; 272177859Sjeff struct cvmx_zip_constants_s 273177859Sjeff { 274177859Sjeff#if __BYTE_ORDER == __BIG_ENDIAN 275177859Sjeff uint64_t reserved_48_63 : 16; 276177859Sjeff uint64_t depth : 16; /**< Maximum search depth for compression */ 277247777Sdavide uint64_t onfsize : 12; /**< Output near full threshhold in bytes */ 278247777Sdavide uint64_t ctxsize : 12; /**< Context size in bytes */ 279247777Sdavide uint64_t reserved_1_7 : 7; 280247777Sdavide uint64_t disabled : 1; /**< 1=zip unit isdisabled, 0=zip unit not disabled */ 281247777Sdavide#else 282247777Sdavide uint64_t disabled : 1; 283177859Sjeff uint64_t reserved_1_7 : 7; 284177859Sjeff uint64_t ctxsize : 12; 285177859Sjeff uint64_t onfsize : 12; 286177859Sjeff uint64_t depth : 16; 287177859Sjeff uint64_t reserved_48_63 : 16; 288177859Sjeff#endif 289177859Sjeff } s; 290177859Sjeff struct cvmx_zip_constants_s cn31xx; 291177859Sjeff struct cvmx_zip_constants_s cn38xx; 292177859Sjeff struct cvmx_zip_constants_s cn38xxp2; 293220456Sattilio struct cvmx_zip_constants_s cn56xx; 29482127Sdillon struct cvmx_zip_constants_s cn56xxp1; 295220456Sattilio struct cvmx_zip_constants_s cn58xx; 296220456Sattilio struct cvmx_zip_constants_s cn58xxp1; 297220456Sattilio struct cvmx_zip_constants_s cn63xx; 298220456Sattilio struct cvmx_zip_constants_s cn63xxp1; 299220456Sattilio}; 300220456Sattiliotypedef union cvmx_zip_constants cvmx_zip_constants_t; 301220456Sattilio 302220456Sattilio/** 303220456Sattilio * cvmx_zip_debug0 304220456Sattilio * 305220456Sattilio * Notes: 306220456Sattilio * Note that this CSR is present only in chip revisions beginning with pass2. 307225057Sattilio * 308225057Sattilio */ 309225057Sattiliounion cvmx_zip_debug0 310225057Sattilio{ 311225057Sattilio uint64_t u64; 312220456Sattilio struct cvmx_zip_debug0_s 313225057Sattilio { 314220456Sattilio#if __BYTE_ORDER == __BIG_ENDIAN 315220456Sattilio uint64_t reserved_17_63 : 47; 316220456Sattilio uint64_t asserts : 17; /**< FIFO assertion checks */ 317225057Sattilio#else 318220456Sattilio uint64_t asserts : 17; 319220456Sattilio uint64_t reserved_17_63 : 47; 320220456Sattilio#endif 321220456Sattilio } s; 322220456Sattilio struct cvmx_zip_debug0_cn31xx 323220456Sattilio { 32482127Sdillon#if __BYTE_ORDER == __BIG_ENDIAN 32582127Sdillon uint64_t reserved_14_63 : 50; 32682127Sdillon uint64_t asserts : 14; /**< FIFO assertion checks */ 32782127Sdillon#else 32882127Sdillon uint64_t asserts : 14; 32982127Sdillon uint64_t reserved_14_63 : 50; 33082127Sdillon#endif 33182127Sdillon } cn31xx; 33282127Sdillon struct cvmx_zip_debug0_cn31xx cn38xx; 333177859Sjeff struct cvmx_zip_debug0_cn31xx cn38xxp2; 334177859Sjeff struct cvmx_zip_debug0_cn31xx cn56xx; 33582127Sdillon struct cvmx_zip_debug0_cn31xx cn56xxp1; 336177859Sjeff struct cvmx_zip_debug0_cn31xx cn58xx; 337177859Sjeff struct cvmx_zip_debug0_cn31xx cn58xxp1; 338177859Sjeff struct cvmx_zip_debug0_s cn63xx; 339177859Sjeff struct cvmx_zip_debug0_s cn63xxp1; 340177859Sjeff}; 341177859Sjefftypedef union cvmx_zip_debug0 cvmx_zip_debug0_t; 342177859Sjeff 343177859Sjeff/** 344177859Sjeff * cvmx_zip_error 345177859Sjeff * 346177859Sjeff * Notes: 347177859Sjeff * Note that this CSR is present only in chip revisions beginning with pass2. 348177859Sjeff * 349214746Sjhb */ 350177859Sjeffunion cvmx_zip_error 351177859Sjeff{ 352209059Sjhb uint64_t u64; 353177859Sjeff struct cvmx_zip_error_s 354177859Sjeff { 355177859Sjeff#if __BYTE_ORDER == __BIG_ENDIAN 356177859Sjeff uint64_t reserved_1_63 : 63; 357177859Sjeff uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 358177859Sjeff#else 359177859Sjeff uint64_t doorbell : 1; 360177859Sjeff uint64_t reserved_1_63 : 63; 361247777Sdavide#endif 362177859Sjeff } s; 363177859Sjeff struct cvmx_zip_error_s cn31xx; 36482127Sdillon struct cvmx_zip_error_s cn38xx; 365177859Sjeff struct cvmx_zip_error_s cn38xxp2; 366177859Sjeff struct cvmx_zip_error_s cn56xx; 367177859Sjeff struct cvmx_zip_error_s cn56xxp1; 368177859Sjeff struct cvmx_zip_error_s cn58xx; 369177859Sjeff struct cvmx_zip_error_s cn58xxp1; 370247777Sdavide struct cvmx_zip_error_s cn63xx; 371247777Sdavide struct cvmx_zip_error_s cn63xxp1; 372247777Sdavide}; 373247777Sdavidetypedef union cvmx_zip_error cvmx_zip_error_t; 374247777Sdavide 375247777Sdavide/** 376247777Sdavide * cvmx_zip_int_mask 377247777Sdavide * 378247777Sdavide * Notes: 379247777Sdavide * Note that this CSR is present only in chip revisions beginning with pass2. 380247777Sdavide * When a mask bit is set, the corresponding interrupt is enabled. 381247777Sdavide */ 382247777Sdavideunion cvmx_zip_int_mask 383247777Sdavide{ 384247777Sdavide uint64_t u64; 385247777Sdavide struct cvmx_zip_int_mask_s 386177859Sjeff { 387247777Sdavide#if __BYTE_ORDER == __BIG_ENDIAN 388177859Sjeff uint64_t reserved_1_63 : 63; 389247777Sdavide uint64_t doorbell : 1; /**< Bit mask corresponding to ZIP_ERROR[0] above */ 390177859Sjeff#else 391247777Sdavide uint64_t doorbell : 1; 392247777Sdavide uint64_t reserved_1_63 : 63; 393247777Sdavide#endif 394247777Sdavide } s; 395247777Sdavide struct cvmx_zip_int_mask_s cn31xx; 396247777Sdavide struct cvmx_zip_int_mask_s cn38xx; 397247777Sdavide struct cvmx_zip_int_mask_s cn38xxp2; 398177859Sjeff struct cvmx_zip_int_mask_s cn56xx; 399247777Sdavide struct cvmx_zip_int_mask_s cn56xxp1; 400247777Sdavide struct cvmx_zip_int_mask_s cn58xx; 401247777Sdavide struct cvmx_zip_int_mask_s cn58xxp1; 402247777Sdavide struct cvmx_zip_int_mask_s cn63xx; 403247777Sdavide struct cvmx_zip_int_mask_s cn63xxp1; 404247777Sdavide}; 405247777Sdavidetypedef union cvmx_zip_int_mask cvmx_zip_int_mask_t; 406247777Sdavide 407247777Sdavide/** 408247777Sdavide * cvmx_zip_throttle 409247777Sdavide * 410247777Sdavide * Notes: 411247777Sdavide * The maximum number of inflight data fetch transactions. Values > 8 are illegal. 412247777Sdavide * Writing 0 to this register causes the ZIP module to temporarily suspend NCB 413247777Sdavide * accesses; it is not recommended for normal operation, but may be useful for 414247777Sdavide * diagnostics. 415247777Sdavide */ 416247777Sdavideunion cvmx_zip_throttle 417247777Sdavide{ 418247777Sdavide uint64_t u64; 419247777Sdavide struct cvmx_zip_throttle_s 420247777Sdavide { 421177859Sjeff#if __BYTE_ORDER == __BIG_ENDIAN 422247777Sdavide uint64_t reserved_4_63 : 60; 423247777Sdavide uint64_t max_infl : 4; /**< Maximum number of inflight data fetch transactions on NCB */ 424177859Sjeff#else 425247777Sdavide uint64_t max_infl : 4; 426247777Sdavide uint64_t reserved_4_63 : 60; 427247777Sdavide#endif 428247777Sdavide } s; 429247777Sdavide struct cvmx_zip_throttle_s cn63xx; 430247777Sdavide struct cvmx_zip_throttle_s cn63xxp1; 431247777Sdavide}; 432247777Sdavidetypedef union cvmx_zip_throttle cvmx_zip_throttle_t; 433247777Sdavide 434247777Sdavide#endif 435247777Sdavide