1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * Support library for the hardware work queue timers. 50210284Sjmallett * 51232812Sjmallett * <hr>$Revision: 70030 $<hr> 52210284Sjmallett */ 53210284Sjmallett#include "executive-config.h" 54210284Sjmallett#include "cvmx-config.h" 55210284Sjmallett#include "cvmx.h" 56210284Sjmallett#include "cvmx-sysinfo.h" 57210284Sjmallett#include "cvmx-tim.h" 58210284Sjmallett#include "cvmx-bootmem.h" 59210284Sjmallett 60215990Sjmallett/* CSR typedefs have been moved to cvmx-tim-defs.h */ 61210284Sjmallett 62210284Sjmallett/** 63210284Sjmallett * Global structure holding the state of all timers. 64210284Sjmallett */ 65210284SjmallettCVMX_SHARED cvmx_tim_t cvmx_tim; 66210284Sjmallett 67210284Sjmallett 68210284Sjmallett#ifdef CVMX_ENABLE_TIMER_FUNCTIONS 69210284Sjmallett/** 70210284Sjmallett * Setup a timer for use. Must be called before the timer 71210284Sjmallett * can be used. 72210284Sjmallett * 73210284Sjmallett * @param tick Time between each bucket in microseconds. This must not be 74210284Sjmallett * smaller than 1024/(clock frequency in MHz). 75210284Sjmallett * @param max_ticks The maximum number of ticks the timer must be able 76210284Sjmallett * to schedule in the future. There are guaranteed to be enough 77210284Sjmallett * timer buckets such that: 78210284Sjmallett * number of buckets >= max_ticks. 79210284Sjmallett * @return Zero on success. Negative on error. Failures are possible 80210284Sjmallett * if the number of buckets needed is too large or memory 81210284Sjmallett * allocation fails for creating the buckets. 82210284Sjmallett */ 83210284Sjmallettint cvmx_tim_setup(uint64_t tick, uint64_t max_ticks) 84210284Sjmallett{ 85210284Sjmallett uint64_t timer_id; 86210284Sjmallett int error = -1; 87215990Sjmallett uint64_t tim_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_TIM); 88210284Sjmallett uint64_t hw_tick_ns; 89210284Sjmallett uint64_t hw_tick_ns_allowed; 90210284Sjmallett uint64_t tick_ns = 1000 * tick; 91210284Sjmallett int i; 92210284Sjmallett uint32_t temp; 93232812Sjmallett int timer_thr = 1024; 94210284Sjmallett 95210284Sjmallett /* for the simulator */ 96215990Sjmallett if (tim_clock_hz == 0) 97232812Sjmallett tim_clock_hz = 800000000; 98210284Sjmallett 99232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 100232812Sjmallett { 101232812Sjmallett cvmx_tim_fr_rn_tt_t fr_tt; 102232812Sjmallett fr_tt.u64 = cvmx_read_csr(CVMX_TIM_FR_RN_TT); 103232812Sjmallett timer_thr = fr_tt.s.fr_rn_tt; 104232812Sjmallett } 105232812Sjmallett 106232812Sjmallett hw_tick_ns = timer_thr * 1000000000ull / tim_clock_hz; 107215990Sjmallett /* 108215990Sjmallett * Double the minimal allowed tick to 2 * HW tick. tick between 109215990Sjmallett * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval 110210284Sjmallett * to zero, or 1024 cycles. This is not enough time for the timer unit 111215990Sjmallett * to fetch the bucket data, Resulting in timer ring error interrupt 112215990Sjmallett * be always generated. Avoid such setting in software. 113210284Sjmallett */ 114215990Sjmallett hw_tick_ns_allowed = hw_tick_ns * 2; 115210284Sjmallett 116210284Sjmallett /* Make sure the timers are stopped */ 117210284Sjmallett cvmx_tim_stop(); 118210284Sjmallett 119210284Sjmallett /* Reinitialize out timer state */ 120210284Sjmallett memset(&cvmx_tim, 0, sizeof(cvmx_tim)); 121210284Sjmallett 122232812Sjmallett if (tick_ns < hw_tick_ns_allowed) 123232812Sjmallett { 124232812Sjmallett cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than" 125232812Sjmallett " the minimal ticks allowed by hardware %lu(ns)\n", 126232812Sjmallett tick_ns, hw_tick_ns_allowed); 127232812Sjmallett return error; 128232812Sjmallett } 129232812Sjmallett else if (tick_ns > 4194304 * hw_tick_ns) 130232812Sjmallett { 131232812Sjmallett cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is greater than" 132232812Sjmallett " the max ticks %lu(ns)\n", tick_ns, hw_tick_ns); 133232812Sjmallett return error; 134232812Sjmallett } 135215990Sjmallett 136210284Sjmallett for (i=2; i<20; i++) 137210284Sjmallett { 138232812Sjmallett if (tick_ns < (hw_tick_ns << i)) 139232812Sjmallett break; 140210284Sjmallett } 141210284Sjmallett 142210284Sjmallett cvmx_tim.max_ticks = (uint32_t)max_ticks; 143210284Sjmallett cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10); 144215990Sjmallett cvmx_tim.tick_cycles = tick * tim_clock_hz / 1000000; 145210284Sjmallett 146210284Sjmallett temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift; 147210284Sjmallett 148210284Sjmallett /* round up to nearest power of 2 */ 149210284Sjmallett temp -= 1; 150210284Sjmallett temp = temp | (temp >> 1); 151210284Sjmallett temp = temp | (temp >> 2); 152210284Sjmallett temp = temp | (temp >> 4); 153210284Sjmallett temp = temp | (temp >> 8); 154210284Sjmallett temp = temp | (temp >> 16); 155210284Sjmallett cvmx_tim.num_buckets = temp + 1; 156210284Sjmallett 157210284Sjmallett /* ensure input params fall into permitted ranges */ 158210284Sjmallett if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576) 159210284Sjmallett { 160215990Sjmallett cvmx_dprintf("ERROR: cvmx_tim_setup: num_buckets out of range\n"); 161210284Sjmallett return error; 162210284Sjmallett } 163210284Sjmallett 164210284Sjmallett /* Allocate the timer buckets from hardware addressable memory */ 165210284Sjmallett cvmx_tim.bucket = cvmx_bootmem_alloc(CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets 166210284Sjmallett * sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE); 167210284Sjmallett if (cvmx_tim.bucket == NULL) 168210284Sjmallett { 169215990Sjmallett cvmx_dprintf("ERROR: cvmx_tim_setup: allocation problem\n"); 170210284Sjmallett return error; 171210284Sjmallett } 172210284Sjmallett memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t)); 173210284Sjmallett 174210284Sjmallett cvmx_tim.start_time = 0; 175210284Sjmallett 176210284Sjmallett /* Loop through all timers */ 177210284Sjmallett for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++) 178210284Sjmallett { 179232812Sjmallett int interval = ((1 << (cvmx_tim.bucket_shift - 10)) - 1); 180210284Sjmallett cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets; 181232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 182232812Sjmallett { 183232812Sjmallett cvmx_tim_ringx_ctl0_t ring_ctl0; 184232812Sjmallett cvmx_tim_ringx_ctl1_t ring_ctl1; 185232812Sjmallett cvmx_tim_ringx_ctl2_t ring_ctl2; 186232812Sjmallett cvmx_tim_reg_flags_t reg_flags; 187210284Sjmallett 188232812Sjmallett /* Tell the hardware where about the bucket array */ 189232812Sjmallett ring_ctl2.u64 = 0; 190232812Sjmallett ring_ctl2.s.csize = CVMX_FPA_TIMER_POOL_SIZE / 8; 191232812Sjmallett ring_ctl2.s.base = cvmx_ptr_to_phys(bucket) >> 5; 192232812Sjmallett cvmx_write_csr(CVMX_TIM_RINGX_CTL2(timer_id), ring_ctl2.u64); 193232812Sjmallett 194232812Sjmallett reg_flags.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS); 195232812Sjmallett ring_ctl1.u64 = 0; 196232812Sjmallett ring_ctl1.s.cpool = ((reg_flags.s.ena_dfb == 0) ? CVMX_FPA_TIMER_POOL : 0); 197232812Sjmallett ring_ctl1.s.bsize = cvmx_tim.num_buckets - 1; 198232812Sjmallett cvmx_write_csr(CVMX_TIM_RINGX_CTL1(timer_id), ring_ctl1.u64); 199232812Sjmallett 200232812Sjmallett ring_ctl0.u64 = 0; 201232812Sjmallett ring_ctl0.s.timercount = interval + timer_id * interval / CVMX_TIM_NUM_TIMERS; 202232812Sjmallett cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64); 203232812Sjmallett 204232812Sjmallett ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id)); 205232812Sjmallett ring_ctl0.s.ena = 1; 206232812Sjmallett ring_ctl0.s.interval = interval; 207232812Sjmallett cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64); 208232812Sjmallett ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id)); 209232812Sjmallett } 210232812Sjmallett else 211232812Sjmallett { 212232812Sjmallett cvmx_tim_mem_ring0_t config_ring0; 213232812Sjmallett cvmx_tim_mem_ring1_t config_ring1; 214232812Sjmallett /* Tell the hardware where about the bucket array */ 215232812Sjmallett config_ring0.u64 = 0; 216232812Sjmallett config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5; 217232812Sjmallett config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1; 218232812Sjmallett config_ring0.s.ring = timer_id; 219232812Sjmallett cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64); 220232812Sjmallett 221232812Sjmallett /* Tell the hardware the size of each chunk block in pointers */ 222232812Sjmallett config_ring1.u64 = 0; 223232812Sjmallett config_ring1.s.enable = 1; 224232812Sjmallett config_ring1.s.pool = CVMX_FPA_TIMER_POOL; 225232812Sjmallett config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8; 226232812Sjmallett config_ring1.s.interval = interval; 227232812Sjmallett config_ring1.s.ring = timer_id; 228232812Sjmallett cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64); 229232812Sjmallett } 230210284Sjmallett } 231210284Sjmallett 232210284Sjmallett return 0; 233210284Sjmallett} 234210284Sjmallett#endif 235210284Sjmallett 236210284Sjmallett/** 237210284Sjmallett * Start the hardware timer processing 238210284Sjmallett */ 239210284Sjmallettvoid cvmx_tim_start(void) 240210284Sjmallett{ 241210284Sjmallett cvmx_tim_control_t control; 242210284Sjmallett 243232812Sjmallett control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS); 244210284Sjmallett control.s.enable_dwb = 1; 245210284Sjmallett control.s.enable_timers = 1; 246210284Sjmallett 247210284Sjmallett /* Remember when we started the timers */ 248215990Sjmallett cvmx_tim.start_time = cvmx_clock_get_count(CVMX_CLOCK_TIM); 249210284Sjmallett cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64); 250210284Sjmallett} 251210284Sjmallett 252210284Sjmallett 253210284Sjmallett/** 254210284Sjmallett * Stop the hardware timer processing. Timers stay configured. 255210284Sjmallett */ 256210284Sjmallettvoid cvmx_tim_stop(void) 257210284Sjmallett{ 258210284Sjmallett cvmx_tim_control_t control; 259232812Sjmallett control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS); 260210284Sjmallett control.s.enable_dwb = 0; 261210284Sjmallett control.s.enable_timers = 0; 262210284Sjmallett cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64); 263210284Sjmallett} 264210284Sjmallett 265210284Sjmallett 266210284Sjmallett/** 267210284Sjmallett * Stop the timer. After this the timer must be setup again 268210284Sjmallett * before use. 269210284Sjmallett */ 270210284Sjmallett#ifdef CVMX_ENABLE_TIMER_FUNCTIONS 271210284Sjmallettvoid cvmx_tim_shutdown(void) 272210284Sjmallett{ 273210284Sjmallett uint32_t bucket; 274210284Sjmallett uint64_t timer_id; 275210284Sjmallett uint64_t entries_per_chunk; 276210284Sjmallett 277210284Sjmallett /* Make sure the timers are stopped */ 278210284Sjmallett cvmx_tim_stop(); 279210284Sjmallett 280210284Sjmallett entries_per_chunk = CVMX_FPA_TIMER_POOL_SIZE/8 - 1; 281210284Sjmallett 282210284Sjmallett /* Now walk all buckets freeing the chunks */ 283210284Sjmallett for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++) 284210284Sjmallett { 285210284Sjmallett for (bucket=0; bucket<cvmx_tim.num_buckets; bucket++) 286210284Sjmallett { 287210284Sjmallett uint64_t chunk_addr; 288210284Sjmallett uint64_t next_chunk_addr; 289210284Sjmallett cvmx_tim_bucket_entry_t *bucket_ptr = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets + bucket; 290210284Sjmallett CVMX_PREFETCH128(CAST64(bucket_ptr)); /* prefetch the next cacheline for future buckets */ 291210284Sjmallett 292210284Sjmallett /* Each bucket contains a list of chunks */ 293210284Sjmallett chunk_addr = bucket_ptr->first_chunk_addr; 294210284Sjmallett while (bucket_ptr->num_entries) 295210284Sjmallett { 296210284Sjmallett#ifdef DEBUG 297210284Sjmallett cvmx_dprintf("Freeing Timer Chunk 0x%llx\n", CAST64(chunk_addr)); 298210284Sjmallett#endif 299210284Sjmallett /* Read next chunk pointer from end of the current chunk */ 300210284Sjmallett next_chunk_addr = cvmx_read_csr(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, chunk_addr + CVMX_FPA_TIMER_POOL_SIZE - 8)); 301210284Sjmallett 302210284Sjmallett cvmx_fpa_free(cvmx_phys_to_ptr(chunk_addr), CVMX_FPA_TIMER_POOL, 0); 303210284Sjmallett chunk_addr = next_chunk_addr; 304210284Sjmallett if (bucket_ptr->num_entries > entries_per_chunk) 305210284Sjmallett bucket_ptr->num_entries -= entries_per_chunk; 306210284Sjmallett else 307210284Sjmallett bucket_ptr->num_entries = 0; 308210284Sjmallett } 309210284Sjmallett } 310210284Sjmallett } 311210284Sjmallett} 312210284Sjmallett 313210284Sjmallett#endif 314