cvmx-tim-defs.h revision 232812
1251876Speter/***********************license start*************** 2251876Speter * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3251876Speter * reserved. 4251876Speter * 5251876Speter * 6251876Speter * Redistribution and use in source and binary forms, with or without 7251876Speter * modification, are permitted provided that the following conditions are 8251876Speter * met: 9251876Speter * 10251876Speter * * Redistributions of source code must retain the above copyright 11251876Speter * notice, this list of conditions and the following disclaimer. 12251876Speter * 13251876Speter * * Redistributions in binary form must reproduce the above 14251876Speter * copyright notice, this list of conditions and the following 15251876Speter * disclaimer in the documentation and/or other materials provided 16251876Speter * with the distribution. 17251876Speter 18251876Speter * * Neither the name of Cavium Inc. nor the names of 19251876Speter * its contributors may be used to endorse or promote products 20251876Speter * derived from this software without specific prior written 21251876Speter * permission. 22251876Speter 23251876Speter * This Software, including technical data, may be subject to U.S. export control 24251876Speter * laws, including the U.S. Export Administration Act and its associated 25251876Speter * regulations, and may be subject to export or import regulations in other 26251876Speter * countries. 27251876Speter 28251876Speter * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29251876Speter * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30251876Speter * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31251876Speter * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32251876Speter * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33251876Speter * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34251876Speter * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35251876Speter * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36251876Speter * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37251876Speter * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38251876Speter ***********************license end**************************************/ 39251876Speter 40251876Speter 41251876Speter/** 42251876Speter * cvmx-tim-defs.h 43251876Speter * 44251876Speter * Configuration and status register (CSR) type definitions for 45251876Speter * Octeon tim. 46251876Speter * 47251876Speter * This file is auto generated. Do not edit. 48251876Speter * 49251876Speter * <hr>$Revision$<hr> 50251876Speter * 51251876Speter */ 52251876Speter#ifndef __CVMX_TIM_DEFS_H__ 53251876Speter#define __CVMX_TIM_DEFS_H__ 54251876Speter 55251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56251876Speter#define CVMX_TIM_BIST_RESULT CVMX_TIM_BIST_RESULT_FUNC() 57251876Speterstatic inline uint64_t CVMX_TIM_BIST_RESULT_FUNC(void) 58251876Speter{ 59251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 60251876Speter cvmx_warn("CVMX_TIM_BIST_RESULT not supported on this chip\n"); 61251876Speter return CVMX_ADD_IO_SEG(0x0001180058000020ull); 62251876Speter} 63251876Speter#else 64251876Speter#define CVMX_TIM_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000020ull)) 65251876Speter#endif 66251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67251876Speter#define CVMX_TIM_DBG2 CVMX_TIM_DBG2_FUNC() 68251876Speterstatic inline uint64_t CVMX_TIM_DBG2_FUNC(void) 69251876Speter{ 70251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 71251876Speter cvmx_warn("CVMX_TIM_DBG2 not supported on this chip\n"); 72251876Speter return CVMX_ADD_IO_SEG(0x00011800580000A0ull); 73251876Speter} 74251876Speter#else 75251876Speter#define CVMX_TIM_DBG2 (CVMX_ADD_IO_SEG(0x00011800580000A0ull)) 76251876Speter#endif 77251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78251876Speter#define CVMX_TIM_DBG3 CVMX_TIM_DBG3_FUNC() 79251876Speterstatic inline uint64_t CVMX_TIM_DBG3_FUNC(void) 80251876Speter{ 81251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 82251876Speter cvmx_warn("CVMX_TIM_DBG3 not supported on this chip\n"); 83251876Speter return CVMX_ADD_IO_SEG(0x00011800580000A8ull); 84251876Speter} 85251876Speter#else 86251876Speter#define CVMX_TIM_DBG3 (CVMX_ADD_IO_SEG(0x00011800580000A8ull)) 87251876Speter#endif 88251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89251876Speter#define CVMX_TIM_ECC_CFG CVMX_TIM_ECC_CFG_FUNC() 90251876Speterstatic inline uint64_t CVMX_TIM_ECC_CFG_FUNC(void) 91251876Speter{ 92251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 93251876Speter cvmx_warn("CVMX_TIM_ECC_CFG not supported on this chip\n"); 94251876Speter return CVMX_ADD_IO_SEG(0x0001180058000018ull); 95251876Speter} 96251876Speter#else 97251876Speter#define CVMX_TIM_ECC_CFG (CVMX_ADD_IO_SEG(0x0001180058000018ull)) 98251876Speter#endif 99251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100251876Speter#define CVMX_TIM_FR_RN_TT CVMX_TIM_FR_RN_TT_FUNC() 101251876Speterstatic inline uint64_t CVMX_TIM_FR_RN_TT_FUNC(void) 102251876Speter{ 103251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 104251876Speter cvmx_warn("CVMX_TIM_FR_RN_TT not supported on this chip\n"); 105251876Speter return CVMX_ADD_IO_SEG(0x0001180058000010ull); 106251876Speter} 107251876Speter#else 108251876Speter#define CVMX_TIM_FR_RN_TT (CVMX_ADD_IO_SEG(0x0001180058000010ull)) 109251876Speter#endif 110251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111251876Speter#define CVMX_TIM_GPIO_EN CVMX_TIM_GPIO_EN_FUNC() 112251876Speterstatic inline uint64_t CVMX_TIM_GPIO_EN_FUNC(void) 113251876Speter{ 114251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 115251876Speter cvmx_warn("CVMX_TIM_GPIO_EN not supported on this chip\n"); 116251876Speter return CVMX_ADD_IO_SEG(0x0001180058000080ull); 117251876Speter} 118251876Speter#else 119251876Speter#define CVMX_TIM_GPIO_EN (CVMX_ADD_IO_SEG(0x0001180058000080ull)) 120251876Speter#endif 121251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122251876Speter#define CVMX_TIM_INT0 CVMX_TIM_INT0_FUNC() 123251876Speterstatic inline uint64_t CVMX_TIM_INT0_FUNC(void) 124251876Speter{ 125251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 126251876Speter cvmx_warn("CVMX_TIM_INT0 not supported on this chip\n"); 127251876Speter return CVMX_ADD_IO_SEG(0x0001180058000030ull); 128251876Speter} 129251876Speter#else 130251876Speter#define CVMX_TIM_INT0 (CVMX_ADD_IO_SEG(0x0001180058000030ull)) 131251876Speter#endif 132251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133251876Speter#define CVMX_TIM_INT0_EN CVMX_TIM_INT0_EN_FUNC() 134251876Speterstatic inline uint64_t CVMX_TIM_INT0_EN_FUNC(void) 135251876Speter{ 136251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 137251876Speter cvmx_warn("CVMX_TIM_INT0_EN not supported on this chip\n"); 138251876Speter return CVMX_ADD_IO_SEG(0x0001180058000038ull); 139251876Speter} 140251876Speter#else 141251876Speter#define CVMX_TIM_INT0_EN (CVMX_ADD_IO_SEG(0x0001180058000038ull)) 142251876Speter#endif 143251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144251876Speter#define CVMX_TIM_INT0_EVENT CVMX_TIM_INT0_EVENT_FUNC() 145251876Speterstatic inline uint64_t CVMX_TIM_INT0_EVENT_FUNC(void) 146251876Speter{ 147251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 148251876Speter cvmx_warn("CVMX_TIM_INT0_EVENT not supported on this chip\n"); 149251876Speter return CVMX_ADD_IO_SEG(0x0001180058000040ull); 150251876Speter} 151251876Speter#else 152251876Speter#define CVMX_TIM_INT0_EVENT (CVMX_ADD_IO_SEG(0x0001180058000040ull)) 153251876Speter#endif 154251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155251876Speter#define CVMX_TIM_INT_ECCERR CVMX_TIM_INT_ECCERR_FUNC() 156251876Speterstatic inline uint64_t CVMX_TIM_INT_ECCERR_FUNC(void) 157251876Speter{ 158251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 159251876Speter cvmx_warn("CVMX_TIM_INT_ECCERR not supported on this chip\n"); 160251876Speter return CVMX_ADD_IO_SEG(0x0001180058000060ull); 161251876Speter} 162251876Speter#else 163251876Speter#define CVMX_TIM_INT_ECCERR (CVMX_ADD_IO_SEG(0x0001180058000060ull)) 164251876Speter#endif 165251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166251876Speter#define CVMX_TIM_INT_ECCERR_EN CVMX_TIM_INT_ECCERR_EN_FUNC() 167251876Speterstatic inline uint64_t CVMX_TIM_INT_ECCERR_EN_FUNC(void) 168251876Speter{ 169251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 170251876Speter cvmx_warn("CVMX_TIM_INT_ECCERR_EN not supported on this chip\n"); 171251876Speter return CVMX_ADD_IO_SEG(0x0001180058000068ull); 172251876Speter} 173251876Speter#else 174251876Speter#define CVMX_TIM_INT_ECCERR_EN (CVMX_ADD_IO_SEG(0x0001180058000068ull)) 175251876Speter#endif 176251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177251876Speter#define CVMX_TIM_INT_ECCERR_EVENT0 CVMX_TIM_INT_ECCERR_EVENT0_FUNC() 178251876Speterstatic inline uint64_t CVMX_TIM_INT_ECCERR_EVENT0_FUNC(void) 179251876Speter{ 180251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 181251876Speter cvmx_warn("CVMX_TIM_INT_ECCERR_EVENT0 not supported on this chip\n"); 182251876Speter return CVMX_ADD_IO_SEG(0x0001180058000070ull); 183251876Speter} 184251876Speter#else 185251876Speter#define CVMX_TIM_INT_ECCERR_EVENT0 (CVMX_ADD_IO_SEG(0x0001180058000070ull)) 186251876Speter#endif 187251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188251876Speter#define CVMX_TIM_INT_ECCERR_EVENT1 CVMX_TIM_INT_ECCERR_EVENT1_FUNC() 189251876Speterstatic inline uint64_t CVMX_TIM_INT_ECCERR_EVENT1_FUNC(void) 190251876Speter{ 191251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 192251876Speter cvmx_warn("CVMX_TIM_INT_ECCERR_EVENT1 not supported on this chip\n"); 193251876Speter return CVMX_ADD_IO_SEG(0x0001180058000078ull); 194251876Speter} 195251876Speter#else 196251876Speter#define CVMX_TIM_INT_ECCERR_EVENT1 (CVMX_ADD_IO_SEG(0x0001180058000078ull)) 197251876Speter#endif 198251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199251876Speter#define CVMX_TIM_MEM_DEBUG0 CVMX_TIM_MEM_DEBUG0_FUNC() 200251876Speterstatic inline uint64_t CVMX_TIM_MEM_DEBUG0_FUNC(void) 201251876Speter{ 202251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 203251876Speter cvmx_warn("CVMX_TIM_MEM_DEBUG0 not supported on this chip\n"); 204251876Speter return CVMX_ADD_IO_SEG(0x0001180058001100ull); 205251876Speter} 206251876Speter#else 207251876Speter#define CVMX_TIM_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180058001100ull)) 208251876Speter#endif 209251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210251876Speter#define CVMX_TIM_MEM_DEBUG1 CVMX_TIM_MEM_DEBUG1_FUNC() 211251876Speterstatic inline uint64_t CVMX_TIM_MEM_DEBUG1_FUNC(void) 212251876Speter{ 213251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 214251876Speter cvmx_warn("CVMX_TIM_MEM_DEBUG1 not supported on this chip\n"); 215251876Speter return CVMX_ADD_IO_SEG(0x0001180058001108ull); 216251876Speter} 217251876Speter#else 218251876Speter#define CVMX_TIM_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180058001108ull)) 219251876Speter#endif 220251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221251876Speter#define CVMX_TIM_MEM_DEBUG2 CVMX_TIM_MEM_DEBUG2_FUNC() 222251876Speterstatic inline uint64_t CVMX_TIM_MEM_DEBUG2_FUNC(void) 223251876Speter{ 224251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 225251876Speter cvmx_warn("CVMX_TIM_MEM_DEBUG2 not supported on this chip\n"); 226251876Speter return CVMX_ADD_IO_SEG(0x0001180058001110ull); 227251876Speter} 228251876Speter#else 229251876Speter#define CVMX_TIM_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180058001110ull)) 230251876Speter#endif 231251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232251876Speter#define CVMX_TIM_MEM_RING0 CVMX_TIM_MEM_RING0_FUNC() 233251876Speterstatic inline uint64_t CVMX_TIM_MEM_RING0_FUNC(void) 234251876Speter{ 235251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 236251876Speter cvmx_warn("CVMX_TIM_MEM_RING0 not supported on this chip\n"); 237251876Speter return CVMX_ADD_IO_SEG(0x0001180058001000ull); 238251876Speter} 239251876Speter#else 240251876Speter#define CVMX_TIM_MEM_RING0 (CVMX_ADD_IO_SEG(0x0001180058001000ull)) 241251876Speter#endif 242251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243251876Speter#define CVMX_TIM_MEM_RING1 CVMX_TIM_MEM_RING1_FUNC() 244251876Speterstatic inline uint64_t CVMX_TIM_MEM_RING1_FUNC(void) 245251876Speter{ 246251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 247251876Speter cvmx_warn("CVMX_TIM_MEM_RING1 not supported on this chip\n"); 248251876Speter return CVMX_ADD_IO_SEG(0x0001180058001008ull); 249251876Speter} 250251876Speter#else 251251876Speter#define CVMX_TIM_MEM_RING1 (CVMX_ADD_IO_SEG(0x0001180058001008ull)) 252251876Speter#endif 253251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254251876Speter#define CVMX_TIM_REG_BIST_RESULT CVMX_TIM_REG_BIST_RESULT_FUNC() 255251876Speterstatic inline uint64_t CVMX_TIM_REG_BIST_RESULT_FUNC(void) 256251876Speter{ 257251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 258251876Speter cvmx_warn("CVMX_TIM_REG_BIST_RESULT not supported on this chip\n"); 259251876Speter return CVMX_ADD_IO_SEG(0x0001180058000080ull); 260251876Speter} 261251876Speter#else 262251876Speter#define CVMX_TIM_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000080ull)) 263251876Speter#endif 264251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265251876Speter#define CVMX_TIM_REG_ERROR CVMX_TIM_REG_ERROR_FUNC() 266251876Speterstatic inline uint64_t CVMX_TIM_REG_ERROR_FUNC(void) 267251876Speter{ 268251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 269251876Speter cvmx_warn("CVMX_TIM_REG_ERROR not supported on this chip\n"); 270251876Speter return CVMX_ADD_IO_SEG(0x0001180058000088ull); 271251876Speter} 272251876Speter#else 273251876Speter#define CVMX_TIM_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180058000088ull)) 274251876Speter#endif 275251876Speter#define CVMX_TIM_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180058000000ull)) 276251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277251876Speter#define CVMX_TIM_REG_INT_MASK CVMX_TIM_REG_INT_MASK_FUNC() 278251876Speterstatic inline uint64_t CVMX_TIM_REG_INT_MASK_FUNC(void) 279251876Speter{ 280251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 281251876Speter cvmx_warn("CVMX_TIM_REG_INT_MASK not supported on this chip\n"); 282251876Speter return CVMX_ADD_IO_SEG(0x0001180058000090ull); 283251876Speter} 284251876Speter#else 285251876Speter#define CVMX_TIM_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180058000090ull)) 286251876Speter#endif 287251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 288251876Speter#define CVMX_TIM_REG_READ_IDX CVMX_TIM_REG_READ_IDX_FUNC() 289251876Speterstatic inline uint64_t CVMX_TIM_REG_READ_IDX_FUNC(void) 290251876Speter{ 291251876Speter if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 292251876Speter cvmx_warn("CVMX_TIM_REG_READ_IDX not supported on this chip\n"); 293251876Speter return CVMX_ADD_IO_SEG(0x0001180058000008ull); 294251876Speter} 295251876Speter#else 296251876Speter#define CVMX_TIM_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180058000008ull)) 297251876Speter#endif 298251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 299251876Speterstatic inline uint64_t CVMX_TIM_RINGX_CTL0(unsigned long offset) 300251876Speter{ 301251876Speter if (!( 302251876Speter (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 303251876Speter cvmx_warn("CVMX_TIM_RINGX_CTL0(%lu) is invalid on this chip\n", offset); 304251876Speter return CVMX_ADD_IO_SEG(0x0001180058002000ull) + ((offset) & 63) * 8; 305251876Speter} 306251876Speter#else 307251876Speter#define CVMX_TIM_RINGX_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180058002000ull) + ((offset) & 63) * 8) 308251876Speter#endif 309251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 310251876Speterstatic inline uint64_t CVMX_TIM_RINGX_CTL1(unsigned long offset) 311251876Speter{ 312251876Speter if (!( 313251876Speter (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 314251876Speter cvmx_warn("CVMX_TIM_RINGX_CTL1(%lu) is invalid on this chip\n", offset); 315251876Speter return CVMX_ADD_IO_SEG(0x0001180058002400ull) + ((offset) & 63) * 8; 316251876Speter} 317251876Speter#else 318251876Speter#define CVMX_TIM_RINGX_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180058002400ull) + ((offset) & 63) * 8) 319251876Speter#endif 320251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 321251876Speterstatic inline uint64_t CVMX_TIM_RINGX_CTL2(unsigned long offset) 322251876Speter{ 323251876Speter if (!( 324251876Speter (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 325251876Speter cvmx_warn("CVMX_TIM_RINGX_CTL2(%lu) is invalid on this chip\n", offset); 326251876Speter return CVMX_ADD_IO_SEG(0x0001180058002800ull) + ((offset) & 63) * 8; 327251876Speter} 328251876Speter#else 329251876Speter#define CVMX_TIM_RINGX_CTL2(offset) (CVMX_ADD_IO_SEG(0x0001180058002800ull) + ((offset) & 63) * 8) 330251876Speter#endif 331251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 332251876Speterstatic inline uint64_t CVMX_TIM_RINGX_DBG0(unsigned long offset) 333251876Speter{ 334251876Speter if (!( 335251876Speter (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 336251876Speter cvmx_warn("CVMX_TIM_RINGX_DBG0(%lu) is invalid on this chip\n", offset); 337251876Speter return CVMX_ADD_IO_SEG(0x0001180058003000ull) + ((offset) & 63) * 8; 338251876Speter} 339251876Speter#else 340251876Speter#define CVMX_TIM_RINGX_DBG0(offset) (CVMX_ADD_IO_SEG(0x0001180058003000ull) + ((offset) & 63) * 8) 341251876Speter#endif 342251876Speter#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 343251876Speterstatic inline uint64_t CVMX_TIM_RINGX_DBG1(unsigned long offset) 344251876Speter{ 345251876Speter if (!( 346251876Speter (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 347251876Speter cvmx_warn("CVMX_TIM_RINGX_DBG1(%lu) is invalid on this chip\n", offset); 348251876Speter return CVMX_ADD_IO_SEG(0x0001180058001200ull) + ((offset) & 63) * 8; 349251876Speter} 350251876Speter#else 351251876Speter#define CVMX_TIM_RINGX_DBG1(offset) (CVMX_ADD_IO_SEG(0x0001180058001200ull) + ((offset) & 63) * 8) 352251876Speter#endif 353251876Speter 354251876Speter/** 355251876Speter * cvmx_tim_bist_result 356251876Speter * 357251876Speter * Notes: 358251876Speter * Access to the internal BiST results 359251876Speter * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 360251876Speter */ 361251876Speterunion cvmx_tim_bist_result { 362251876Speter uint64_t u64; 363251876Speter struct cvmx_tim_bist_result_s { 364251876Speter#ifdef __BIG_ENDIAN_BITFIELD 365251876Speter uint64_t reserved_3_63 : 61; 366251876Speter uint64_t wqe_fifo : 1; /**< BIST result of the NCB_WQE FIFO (0=pass, !0=fail) */ 367251876Speter uint64_t lslr_fifo : 1; /**< BIST result of the NCB_LSLR FIFO (0=pass, !0=fail) */ 368251876Speter uint64_t rds_mem : 1; /**< BIST result of the RDS memory (0=pass, !0=fail) */ 369251876Speter#else 370251876Speter uint64_t rds_mem : 1; 371251876Speter uint64_t lslr_fifo : 1; 372251876Speter uint64_t wqe_fifo : 1; 373251876Speter uint64_t reserved_3_63 : 61; 374251876Speter#endif 375251876Speter } s; 376251876Speter struct cvmx_tim_bist_result_s cn68xx; 377251876Speter struct cvmx_tim_bist_result_s cn68xxp1; 378251876Speter}; 379251876Spetertypedef union cvmx_tim_bist_result cvmx_tim_bist_result_t; 380251876Speter 381251876Speter/** 382251876Speter * cvmx_tim_dbg2 383251876Speter */ 384251876Speterunion cvmx_tim_dbg2 { 385251876Speter uint64_t u64; 386251876Speter struct cvmx_tim_dbg2_s { 387251876Speter#ifdef __BIG_ENDIAN_BITFIELD 388251876Speter uint64_t mem_alloc_reg : 8; /**< NCB Load Memory Allocation status */ 389251876Speter uint64_t reserved_51_55 : 5; 390251876Speter uint64_t gnt_fifo_level : 3; /**< NCB GRANT FIFO level */ 391251876Speter uint64_t reserved_45_47 : 3; 392251876Speter uint64_t rwf_fifo_level : 5; /**< NCB requests FIFO level */ 393251876Speter uint64_t wqe_fifo_level : 8; /**< NCB WQE LD FIFO level */ 394251876Speter uint64_t reserved_16_31 : 16; 395251876Speter uint64_t fsm3_state : 4; /**< FSM 3 current state */ 396251876Speter uint64_t fsm2_state : 4; /**< FSM 2 current state */ 397251876Speter uint64_t fsm1_state : 4; /**< FSM 1 current state */ 398251876Speter uint64_t fsm0_state : 4; /**< FSM 0 current state */ 399251876Speter#else 400251876Speter uint64_t fsm0_state : 4; 401251876Speter uint64_t fsm1_state : 4; 402251876Speter uint64_t fsm2_state : 4; 403251876Speter uint64_t fsm3_state : 4; 404251876Speter uint64_t reserved_16_31 : 16; 405 uint64_t wqe_fifo_level : 8; 406 uint64_t rwf_fifo_level : 5; 407 uint64_t reserved_45_47 : 3; 408 uint64_t gnt_fifo_level : 3; 409 uint64_t reserved_51_55 : 5; 410 uint64_t mem_alloc_reg : 8; 411#endif 412 } s; 413 struct cvmx_tim_dbg2_s cn68xx; 414 struct cvmx_tim_dbg2_s cn68xxp1; 415}; 416typedef union cvmx_tim_dbg2 cvmx_tim_dbg2_t; 417 418/** 419 * cvmx_tim_dbg3 420 */ 421union cvmx_tim_dbg3 { 422 uint64_t u64; 423 struct cvmx_tim_dbg3_s { 424#ifdef __BIG_ENDIAN_BITFIELD 425 uint64_t rings_pending_vec : 64; /**< Pending rings vector. Indicates which ring in TIM are 426 pending traversal. Bit 0 represents ring 0 while bit 63 427 represents ring 63. */ 428#else 429 uint64_t rings_pending_vec : 64; 430#endif 431 } s; 432 struct cvmx_tim_dbg3_s cn68xx; 433 struct cvmx_tim_dbg3_s cn68xxp1; 434}; 435typedef union cvmx_tim_dbg3 cvmx_tim_dbg3_t; 436 437/** 438 * cvmx_tim_ecc_cfg 439 */ 440union cvmx_tim_ecc_cfg { 441 uint64_t u64; 442 struct cvmx_tim_ecc_cfg_s { 443#ifdef __BIG_ENDIAN_BITFIELD 444 uint64_t reserved_3_63 : 61; 445 uint64_t ecc_flp_syn : 2; /**< ECC Flip Syndrome. Flip the ECC's syndrome for testing 446 purposes, to test SBE and DBE ECC interrupts. */ 447 uint64_t ecc_en : 1; /**< Enable ECC correction of the Ring Data Structre memory. 448 ECC is enabled by default. */ 449#else 450 uint64_t ecc_en : 1; 451 uint64_t ecc_flp_syn : 2; 452 uint64_t reserved_3_63 : 61; 453#endif 454 } s; 455 struct cvmx_tim_ecc_cfg_s cn68xx; 456 struct cvmx_tim_ecc_cfg_s cn68xxp1; 457}; 458typedef union cvmx_tim_ecc_cfg cvmx_tim_ecc_cfg_t; 459 460/** 461 * cvmx_tim_fr_rn_tt 462 * 463 * Notes: 464 * For every 64 entries in a bucket interval should be at 465 * least 1us. 466 * Minimal recommended value for Threshold register is 1us 467 */ 468union cvmx_tim_fr_rn_tt { 469 uint64_t u64; 470 struct cvmx_tim_fr_rn_tt_s { 471#ifdef __BIG_ENDIAN_BITFIELD 472 uint64_t reserved_54_63 : 10; 473 uint64_t thld_gp : 22; /**< Free Running Timer Threshold. Defines the reset value 474 for the free running timer when it reaches zero during 475 it's count down. This threshold only applies to the 476 timer that is driven by GPIO edge as defined at 477 TIM_REG_FLAGS.GPIO_EDGE 478 ***NOTE: Added in pass 2.0 */ 479 uint64_t reserved_22_31 : 10; 480 uint64_t fr_rn_tt : 22; /**< Free Running Timer Threshold. Defines the reset value 481 for the free running timer when it reaches zero during 482 it's count down. 483 FR_RN_TT will be used in both cases where free running 484 clock is driven externally or internally. 485 Interval programming guidelines: 486 For every 64 entries in a bucket interval should be at 487 least 1us. 488 Minimal recommended value for FR_RN_TT is 1us. */ 489#else 490 uint64_t fr_rn_tt : 22; 491 uint64_t reserved_22_31 : 10; 492 uint64_t thld_gp : 22; 493 uint64_t reserved_54_63 : 10; 494#endif 495 } s; 496 struct cvmx_tim_fr_rn_tt_s cn68xx; 497 struct cvmx_tim_fr_rn_tt_cn68xxp1 { 498#ifdef __BIG_ENDIAN_BITFIELD 499 uint64_t reserved_22_63 : 42; 500 uint64_t fr_rn_tt : 22; /**< Free Running Timer Threshold. Defines the reset value 501 for the free running timer when it reaches zero during 502 it's count down. 503 FR_RN_TT will be used in both cases where free running 504 clock is driven externally or internally. 505 Interval programming guidelines: 506 For every 64 entries in a bucket interval should be at 507 least 1us. 508 Minimal recommended value for FR_RN_TT is 1us. */ 509#else 510 uint64_t fr_rn_tt : 22; 511 uint64_t reserved_22_63 : 42; 512#endif 513 } cn68xxp1; 514}; 515typedef union cvmx_tim_fr_rn_tt cvmx_tim_fr_rn_tt_t; 516 517/** 518 * cvmx_tim_gpio_en 519 */ 520union cvmx_tim_gpio_en { 521 uint64_t u64; 522 struct cvmx_tim_gpio_en_s { 523#ifdef __BIG_ENDIAN_BITFIELD 524 uint64_t gpio_en : 64; /**< Each bit correspond to rings [63:0] respectively. 525 This register reflects the values written to 526 TIM_RING63..0_CTL1.ENA_GPIO 527 ***NOTE: Added in pass 2.0 for debug only. RESERVED */ 528#else 529 uint64_t gpio_en : 64; 530#endif 531 } s; 532 struct cvmx_tim_gpio_en_s cn68xx; 533}; 534typedef union cvmx_tim_gpio_en cvmx_tim_gpio_en_t; 535 536/** 537 * cvmx_tim_int0 538 * 539 * Notes: 540 * A ring is in error if its interval has elapsed more than once without having been serviced. This is 541 * usually a programming error where number of entries in the bucket is too large for the interval 542 * specified for the ring. 543 * Any bit in the INT field should be cleared by writing '1' to it. 544 */ 545union cvmx_tim_int0 { 546 uint64_t u64; 547 struct cvmx_tim_int0_s { 548#ifdef __BIG_ENDIAN_BITFIELD 549 uint64_t int0 : 64; /**< Interrupt bit per ring. Each bit indicates the 550 ring number in error. Each bit in this reg is set 551 regardless of TIM_INT0_EN value. */ 552#else 553 uint64_t int0 : 64; 554#endif 555 } s; 556 struct cvmx_tim_int0_s cn68xx; 557 struct cvmx_tim_int0_s cn68xxp1; 558}; 559typedef union cvmx_tim_int0 cvmx_tim_int0_t; 560 561/** 562 * cvmx_tim_int0_en 563 * 564 * Notes: 565 * When bit at TIM_INT0_EN is set it enables the corresponding TIM_INTO's bit for interrupt generation 566 * If enable bit is cleared the corresponding bit at TIM_INT0 will still be set. 567 * Interrupt to the cores is generated by : |(TIM_INT0 & TIM_INT0_EN0) 568 */ 569union cvmx_tim_int0_en { 570 uint64_t u64; 571 struct cvmx_tim_int0_en_s { 572#ifdef __BIG_ENDIAN_BITFIELD 573 uint64_t int0_en : 64; /**< Bit enable corresponding to TIM_INT0. */ 574#else 575 uint64_t int0_en : 64; 576#endif 577 } s; 578 struct cvmx_tim_int0_en_s cn68xx; 579 struct cvmx_tim_int0_en_s cn68xxp1; 580}; 581typedef union cvmx_tim_int0_en cvmx_tim_int0_en_t; 582 583/** 584 * cvmx_tim_int0_event 585 */ 586union cvmx_tim_int0_event { 587 uint64_t u64; 588 struct cvmx_tim_int0_event_s { 589#ifdef __BIG_ENDIAN_BITFIELD 590 uint64_t reserved_6_63 : 58; 591 uint64_t ring_id : 6; /**< The first Ring ID where an interrupt occurred. */ 592#else 593 uint64_t ring_id : 6; 594 uint64_t reserved_6_63 : 58; 595#endif 596 } s; 597 struct cvmx_tim_int0_event_s cn68xx; 598 struct cvmx_tim_int0_event_s cn68xxp1; 599}; 600typedef union cvmx_tim_int0_event cvmx_tim_int0_event_t; 601 602/** 603 * cvmx_tim_int_eccerr 604 * 605 * Notes: 606 * Each bit in this reg is set regardless of TIM_INT_ECCERR_EN value. 607 * 608 */ 609union cvmx_tim_int_eccerr { 610 uint64_t u64; 611 struct cvmx_tim_int_eccerr_s { 612#ifdef __BIG_ENDIAN_BITFIELD 613 uint64_t reserved_2_63 : 62; 614 uint64_t dbe : 1; /**< TIM RDS memory had a Double Bit Error */ 615 uint64_t sbe : 1; /**< TIM RDS memory had a Single Bit Error */ 616#else 617 uint64_t sbe : 1; 618 uint64_t dbe : 1; 619 uint64_t reserved_2_63 : 62; 620#endif 621 } s; 622 struct cvmx_tim_int_eccerr_s cn68xx; 623 struct cvmx_tim_int_eccerr_s cn68xxp1; 624}; 625typedef union cvmx_tim_int_eccerr cvmx_tim_int_eccerr_t; 626 627/** 628 * cvmx_tim_int_eccerr_en 629 * 630 * Notes: 631 * When mask bit is set, the corresponding bit in TIM_INT_ECCERR is enabled. If mask bit is cleared the 632 * corresponding bit in TIM_INT_ECCERR will still be set but interrupt will not be reported. 633 */ 634union cvmx_tim_int_eccerr_en { 635 uint64_t u64; 636 struct cvmx_tim_int_eccerr_en_s { 637#ifdef __BIG_ENDIAN_BITFIELD 638 uint64_t reserved_2_63 : 62; 639 uint64_t dbe_en : 1; /**< Bit mask corresponding to TIM_REG_ECCERR.DBE */ 640 uint64_t sbe_en : 1; /**< Bit mask corresponding to TIM_REG_ECCERR.SBE */ 641#else 642 uint64_t sbe_en : 1; 643 uint64_t dbe_en : 1; 644 uint64_t reserved_2_63 : 62; 645#endif 646 } s; 647 struct cvmx_tim_int_eccerr_en_s cn68xx; 648 struct cvmx_tim_int_eccerr_en_s cn68xxp1; 649}; 650typedef union cvmx_tim_int_eccerr_en cvmx_tim_int_eccerr_en_t; 651 652/** 653 * cvmx_tim_int_eccerr_event0 654 */ 655union cvmx_tim_int_eccerr_event0 { 656 uint64_t u64; 657 struct cvmx_tim_int_eccerr_event0_s { 658#ifdef __BIG_ENDIAN_BITFIELD 659 uint64_t reserved_15_63 : 49; 660 uint64_t synd : 7; /**< ECC Syndrome */ 661 uint64_t add : 8; /**< Memory address where the Error occurred. */ 662#else 663 uint64_t add : 8; 664 uint64_t synd : 7; 665 uint64_t reserved_15_63 : 49; 666#endif 667 } s; 668 struct cvmx_tim_int_eccerr_event0_s cn68xx; 669 struct cvmx_tim_int_eccerr_event0_s cn68xxp1; 670}; 671typedef union cvmx_tim_int_eccerr_event0 cvmx_tim_int_eccerr_event0_t; 672 673/** 674 * cvmx_tim_int_eccerr_event1 675 */ 676union cvmx_tim_int_eccerr_event1 { 677 uint64_t u64; 678 struct cvmx_tim_int_eccerr_event1_s { 679#ifdef __BIG_ENDIAN_BITFIELD 680 uint64_t reserved_55_63 : 9; 681 uint64_t org_ecc : 7; /**< Original ECC bits where the error occured. */ 682 uint64_t org_rds_dat : 48; /**< Memory original data where the error occured. */ 683#else 684 uint64_t org_rds_dat : 48; 685 uint64_t org_ecc : 7; 686 uint64_t reserved_55_63 : 9; 687#endif 688 } s; 689 struct cvmx_tim_int_eccerr_event1_s cn68xx; 690 struct cvmx_tim_int_eccerr_event1_s cn68xxp1; 691}; 692typedef union cvmx_tim_int_eccerr_event1 cvmx_tim_int_eccerr_event1_t; 693 694/** 695 * cvmx_tim_mem_debug0 696 * 697 * Notes: 698 * Internal per-ring state intended for debug use only - tim.ctl[47:0] 699 * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 700 * CSR read operations to this address can be performed. 701 */ 702union cvmx_tim_mem_debug0 { 703 uint64_t u64; 704 struct cvmx_tim_mem_debug0_s { 705#ifdef __BIG_ENDIAN_BITFIELD 706 uint64_t reserved_48_63 : 16; 707 uint64_t ena : 1; /**< Ring timer enable */ 708 uint64_t reserved_46_46 : 1; 709 uint64_t count : 22; /**< Time offset for the ring 710 Set to INTERVAL and counts down by 1 every 1024 711 cycles when ENA==1. The HW forces a bucket 712 traversal (and resets COUNT to INTERVAL) whenever 713 the decrement would cause COUNT to go negative. 714 COUNT is unpredictable whenever ENA==0. 715 COUNT is reset to INTERVAL whenever TIM_MEM_RING1 716 is written for the ring. */ 717 uint64_t reserved_22_23 : 2; 718 uint64_t interval : 22; /**< Timer interval - 1 */ 719#else 720 uint64_t interval : 22; 721 uint64_t reserved_22_23 : 2; 722 uint64_t count : 22; 723 uint64_t reserved_46_46 : 1; 724 uint64_t ena : 1; 725 uint64_t reserved_48_63 : 16; 726#endif 727 } s; 728 struct cvmx_tim_mem_debug0_s cn30xx; 729 struct cvmx_tim_mem_debug0_s cn31xx; 730 struct cvmx_tim_mem_debug0_s cn38xx; 731 struct cvmx_tim_mem_debug0_s cn38xxp2; 732 struct cvmx_tim_mem_debug0_s cn50xx; 733 struct cvmx_tim_mem_debug0_s cn52xx; 734 struct cvmx_tim_mem_debug0_s cn52xxp1; 735 struct cvmx_tim_mem_debug0_s cn56xx; 736 struct cvmx_tim_mem_debug0_s cn56xxp1; 737 struct cvmx_tim_mem_debug0_s cn58xx; 738 struct cvmx_tim_mem_debug0_s cn58xxp1; 739 struct cvmx_tim_mem_debug0_s cn61xx; 740 struct cvmx_tim_mem_debug0_s cn63xx; 741 struct cvmx_tim_mem_debug0_s cn63xxp1; 742 struct cvmx_tim_mem_debug0_s cn66xx; 743 struct cvmx_tim_mem_debug0_s cnf71xx; 744}; 745typedef union cvmx_tim_mem_debug0 cvmx_tim_mem_debug0_t; 746 747/** 748 * cvmx_tim_mem_debug1 749 * 750 * Notes: 751 * Internal per-ring state intended for debug use only - tim.sta[63:0] 752 * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 753 * CSR read operations to this address can be performed. 754 */ 755union cvmx_tim_mem_debug1 { 756 uint64_t u64; 757 struct cvmx_tim_mem_debug1_s { 758#ifdef __BIG_ENDIAN_BITFIELD 759 uint64_t bucket : 13; /**< Current bucket[12:0] 760 Reset to 0 whenever TIM_MEM_RING0 is written for 761 the ring. Incremented (modulo BSIZE) once per 762 bucket traversal. 763 See TIM_MEM_DEBUG2[BUCKET]. */ 764 uint64_t base : 31; /**< Pointer[35:5] to bucket[0] */ 765 uint64_t bsize : 20; /**< Number of buckets - 1 */ 766#else 767 uint64_t bsize : 20; 768 uint64_t base : 31; 769 uint64_t bucket : 13; 770#endif 771 } s; 772 struct cvmx_tim_mem_debug1_s cn30xx; 773 struct cvmx_tim_mem_debug1_s cn31xx; 774 struct cvmx_tim_mem_debug1_s cn38xx; 775 struct cvmx_tim_mem_debug1_s cn38xxp2; 776 struct cvmx_tim_mem_debug1_s cn50xx; 777 struct cvmx_tim_mem_debug1_s cn52xx; 778 struct cvmx_tim_mem_debug1_s cn52xxp1; 779 struct cvmx_tim_mem_debug1_s cn56xx; 780 struct cvmx_tim_mem_debug1_s cn56xxp1; 781 struct cvmx_tim_mem_debug1_s cn58xx; 782 struct cvmx_tim_mem_debug1_s cn58xxp1; 783 struct cvmx_tim_mem_debug1_s cn61xx; 784 struct cvmx_tim_mem_debug1_s cn63xx; 785 struct cvmx_tim_mem_debug1_s cn63xxp1; 786 struct cvmx_tim_mem_debug1_s cn66xx; 787 struct cvmx_tim_mem_debug1_s cnf71xx; 788}; 789typedef union cvmx_tim_mem_debug1 cvmx_tim_mem_debug1_t; 790 791/** 792 * cvmx_tim_mem_debug2 793 * 794 * Notes: 795 * Internal per-ring state intended for debug use only - tim.sta[95:64] 796 * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 797 * CSR read operations to this address can be performed. 798 */ 799union cvmx_tim_mem_debug2 { 800 uint64_t u64; 801 struct cvmx_tim_mem_debug2_s { 802#ifdef __BIG_ENDIAN_BITFIELD 803 uint64_t reserved_24_63 : 40; 804 uint64_t cpool : 3; /**< Free list used to free chunks */ 805 uint64_t csize : 13; /**< Number of words per chunk */ 806 uint64_t reserved_7_7 : 1; 807 uint64_t bucket : 7; /**< Current bucket[19:13] 808 See TIM_MEM_DEBUG1[BUCKET]. */ 809#else 810 uint64_t bucket : 7; 811 uint64_t reserved_7_7 : 1; 812 uint64_t csize : 13; 813 uint64_t cpool : 3; 814 uint64_t reserved_24_63 : 40; 815#endif 816 } s; 817 struct cvmx_tim_mem_debug2_s cn30xx; 818 struct cvmx_tim_mem_debug2_s cn31xx; 819 struct cvmx_tim_mem_debug2_s cn38xx; 820 struct cvmx_tim_mem_debug2_s cn38xxp2; 821 struct cvmx_tim_mem_debug2_s cn50xx; 822 struct cvmx_tim_mem_debug2_s cn52xx; 823 struct cvmx_tim_mem_debug2_s cn52xxp1; 824 struct cvmx_tim_mem_debug2_s cn56xx; 825 struct cvmx_tim_mem_debug2_s cn56xxp1; 826 struct cvmx_tim_mem_debug2_s cn58xx; 827 struct cvmx_tim_mem_debug2_s cn58xxp1; 828 struct cvmx_tim_mem_debug2_s cn61xx; 829 struct cvmx_tim_mem_debug2_s cn63xx; 830 struct cvmx_tim_mem_debug2_s cn63xxp1; 831 struct cvmx_tim_mem_debug2_s cn66xx; 832 struct cvmx_tim_mem_debug2_s cnf71xx; 833}; 834typedef union cvmx_tim_mem_debug2 cvmx_tim_mem_debug2_t; 835 836/** 837 * cvmx_tim_mem_ring0 838 * 839 * Notes: 840 * TIM_MEM_RING0 must not be written for a ring when TIM_MEM_RING1[ENA] is set for the ring. 841 * Every write to TIM_MEM_RING0 clears the current bucket for the ring. (The current bucket is 842 * readable via TIM_MEM_DEBUG2[BUCKET],TIM_MEM_DEBUG1[BUCKET].) 843 * BASE is a 32-byte aligned pointer[35:0]. Only pointer[35:5] are stored because pointer[4:0] = 0. 844 * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 845 * CSR read operations to this address can be performed. 846 */ 847union cvmx_tim_mem_ring0 { 848 uint64_t u64; 849 struct cvmx_tim_mem_ring0_s { 850#ifdef __BIG_ENDIAN_BITFIELD 851 uint64_t reserved_55_63 : 9; 852 uint64_t first_bucket : 31; /**< Pointer[35:5] to bucket[0] */ 853 uint64_t num_buckets : 20; /**< Number of buckets - 1 */ 854 uint64_t ring : 4; /**< Ring ID */ 855#else 856 uint64_t ring : 4; 857 uint64_t num_buckets : 20; 858 uint64_t first_bucket : 31; 859 uint64_t reserved_55_63 : 9; 860#endif 861 } s; 862 struct cvmx_tim_mem_ring0_s cn30xx; 863 struct cvmx_tim_mem_ring0_s cn31xx; 864 struct cvmx_tim_mem_ring0_s cn38xx; 865 struct cvmx_tim_mem_ring0_s cn38xxp2; 866 struct cvmx_tim_mem_ring0_s cn50xx; 867 struct cvmx_tim_mem_ring0_s cn52xx; 868 struct cvmx_tim_mem_ring0_s cn52xxp1; 869 struct cvmx_tim_mem_ring0_s cn56xx; 870 struct cvmx_tim_mem_ring0_s cn56xxp1; 871 struct cvmx_tim_mem_ring0_s cn58xx; 872 struct cvmx_tim_mem_ring0_s cn58xxp1; 873 struct cvmx_tim_mem_ring0_s cn61xx; 874 struct cvmx_tim_mem_ring0_s cn63xx; 875 struct cvmx_tim_mem_ring0_s cn63xxp1; 876 struct cvmx_tim_mem_ring0_s cn66xx; 877 struct cvmx_tim_mem_ring0_s cnf71xx; 878}; 879typedef union cvmx_tim_mem_ring0 cvmx_tim_mem_ring0_t; 880 881/** 882 * cvmx_tim_mem_ring1 883 * 884 * Notes: 885 * After a 1->0 transition on ENA, the HW will still complete a bucket traversal for the ring 886 * if it was pending or active prior to the transition. (SW must delay to ensure the completion 887 * of the traversal before reprogramming the ring.) 888 * Every write to TIM_MEM_RING1 resets the current time offset for the ring to the INTERVAL value. 889 * (The current time offset for the ring is readable via TIM_MEM_DEBUG0[COUNT].) 890 * CSIZE must be at least 16. It is illegal to program CSIZE to a value that is less than 16. 891 * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 892 * CSR read operations to this address can be performed. 893 */ 894union cvmx_tim_mem_ring1 { 895 uint64_t u64; 896 struct cvmx_tim_mem_ring1_s { 897#ifdef __BIG_ENDIAN_BITFIELD 898 uint64_t reserved_43_63 : 21; 899 uint64_t enable : 1; /**< Ring timer enable 900 When clear, the ring is disabled and TIM 901 will not traverse any new buckets for the ring. */ 902 uint64_t pool : 3; /**< Free list used to free chunks */ 903 uint64_t words_per_chunk : 13; /**< Number of words per chunk */ 904 uint64_t interval : 22; /**< Timer interval - 1, measured in 1024 cycle ticks */ 905 uint64_t ring : 4; /**< Ring ID */ 906#else 907 uint64_t ring : 4; 908 uint64_t interval : 22; 909 uint64_t words_per_chunk : 13; 910 uint64_t pool : 3; 911 uint64_t enable : 1; 912 uint64_t reserved_43_63 : 21; 913#endif 914 } s; 915 struct cvmx_tim_mem_ring1_s cn30xx; 916 struct cvmx_tim_mem_ring1_s cn31xx; 917 struct cvmx_tim_mem_ring1_s cn38xx; 918 struct cvmx_tim_mem_ring1_s cn38xxp2; 919 struct cvmx_tim_mem_ring1_s cn50xx; 920 struct cvmx_tim_mem_ring1_s cn52xx; 921 struct cvmx_tim_mem_ring1_s cn52xxp1; 922 struct cvmx_tim_mem_ring1_s cn56xx; 923 struct cvmx_tim_mem_ring1_s cn56xxp1; 924 struct cvmx_tim_mem_ring1_s cn58xx; 925 struct cvmx_tim_mem_ring1_s cn58xxp1; 926 struct cvmx_tim_mem_ring1_s cn61xx; 927 struct cvmx_tim_mem_ring1_s cn63xx; 928 struct cvmx_tim_mem_ring1_s cn63xxp1; 929 struct cvmx_tim_mem_ring1_s cn66xx; 930 struct cvmx_tim_mem_ring1_s cnf71xx; 931}; 932typedef union cvmx_tim_mem_ring1 cvmx_tim_mem_ring1_t; 933 934/** 935 * cvmx_tim_reg_bist_result 936 * 937 * Notes: 938 * Access to the internal BiST results 939 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 940 */ 941union cvmx_tim_reg_bist_result { 942 uint64_t u64; 943 struct cvmx_tim_reg_bist_result_s { 944#ifdef __BIG_ENDIAN_BITFIELD 945 uint64_t reserved_4_63 : 60; 946 uint64_t sta : 2; /**< BiST result of the STA memories (0=pass, !0=fail) */ 947 uint64_t ncb : 1; /**< BiST result of the NCB memories (0=pass, !0=fail) */ 948 uint64_t ctl : 1; /**< BiST result of the CTL memories (0=pass, !0=fail) */ 949#else 950 uint64_t ctl : 1; 951 uint64_t ncb : 1; 952 uint64_t sta : 2; 953 uint64_t reserved_4_63 : 60; 954#endif 955 } s; 956 struct cvmx_tim_reg_bist_result_s cn30xx; 957 struct cvmx_tim_reg_bist_result_s cn31xx; 958 struct cvmx_tim_reg_bist_result_s cn38xx; 959 struct cvmx_tim_reg_bist_result_s cn38xxp2; 960 struct cvmx_tim_reg_bist_result_s cn50xx; 961 struct cvmx_tim_reg_bist_result_s cn52xx; 962 struct cvmx_tim_reg_bist_result_s cn52xxp1; 963 struct cvmx_tim_reg_bist_result_s cn56xx; 964 struct cvmx_tim_reg_bist_result_s cn56xxp1; 965 struct cvmx_tim_reg_bist_result_s cn58xx; 966 struct cvmx_tim_reg_bist_result_s cn58xxp1; 967 struct cvmx_tim_reg_bist_result_s cn61xx; 968 struct cvmx_tim_reg_bist_result_s cn63xx; 969 struct cvmx_tim_reg_bist_result_s cn63xxp1; 970 struct cvmx_tim_reg_bist_result_s cn66xx; 971 struct cvmx_tim_reg_bist_result_s cnf71xx; 972}; 973typedef union cvmx_tim_reg_bist_result cvmx_tim_reg_bist_result_t; 974 975/** 976 * cvmx_tim_reg_error 977 * 978 * Notes: 979 * A ring is in error if its interval has elapsed more than once without having been serviced. 980 * During a CSR write to this register, the write data is used as a mask to clear the selected mask 981 * bits (mask'[15:0] = mask[15:0] & ~write_data[15:0]). 982 */ 983union cvmx_tim_reg_error { 984 uint64_t u64; 985 struct cvmx_tim_reg_error_s { 986#ifdef __BIG_ENDIAN_BITFIELD 987 uint64_t reserved_16_63 : 48; 988 uint64_t mask : 16; /**< Bit mask indicating the rings in error */ 989#else 990 uint64_t mask : 16; 991 uint64_t reserved_16_63 : 48; 992#endif 993 } s; 994 struct cvmx_tim_reg_error_s cn30xx; 995 struct cvmx_tim_reg_error_s cn31xx; 996 struct cvmx_tim_reg_error_s cn38xx; 997 struct cvmx_tim_reg_error_s cn38xxp2; 998 struct cvmx_tim_reg_error_s cn50xx; 999 struct cvmx_tim_reg_error_s cn52xx; 1000 struct cvmx_tim_reg_error_s cn52xxp1; 1001 struct cvmx_tim_reg_error_s cn56xx; 1002 struct cvmx_tim_reg_error_s cn56xxp1; 1003 struct cvmx_tim_reg_error_s cn58xx; 1004 struct cvmx_tim_reg_error_s cn58xxp1; 1005 struct cvmx_tim_reg_error_s cn61xx; 1006 struct cvmx_tim_reg_error_s cn63xx; 1007 struct cvmx_tim_reg_error_s cn63xxp1; 1008 struct cvmx_tim_reg_error_s cn66xx; 1009 struct cvmx_tim_reg_error_s cnf71xx; 1010}; 1011typedef union cvmx_tim_reg_error cvmx_tim_reg_error_t; 1012 1013/** 1014 * cvmx_tim_reg_flags 1015 * 1016 * 13e20 reserved 1017 * 1018 * 1019 * Notes: 1020 * TIM has a counter that causes a periodic tick every 1024 cycles. This counter is shared by all 1021 * rings. (Each tick causes the HW to decrement the time offset (i.e. COUNT) for all enabled rings.) 1022 * When ENA_TIM==0, the HW stops this shared periodic counter, so there are no more ticks, and there 1023 * are no more new bucket traversals (for any ring). 1024 * 1025 * If ENA_TIM transitions 1->0, TIM will no longer create new bucket traversals, but there may 1026 * have been previous ones. If there are ring bucket traversals that were already pending but 1027 * not currently active (i.e. bucket traversals that need to be done by the HW, but haven't been yet) 1028 * during this ENA_TIM 1->0 transition, then these bucket traversals will remain pending until 1029 * ENA_TIM is later set to one. Bucket traversals that were already in progress will complete 1030 * after the 1->0 ENA_TIM transition, though. 1031 */ 1032union cvmx_tim_reg_flags { 1033 uint64_t u64; 1034 struct cvmx_tim_reg_flags_s { 1035#ifdef __BIG_ENDIAN_BITFIELD 1036 uint64_t reserved_7_63 : 57; 1037 uint64_t gpio_edge : 2; /**< Edge used for GPIO timing 1038 2'b10 - TIM counts high to low transitions 1039 2'b01 - TIM counts low to high transitions 1040 2'b11 - TIM counts Both low to high and high to low 1041 transitions */ 1042 uint64_t ena_gpio : 1; /**< Enable the external control of GPIO over the free 1043 running timer. 1044 When set, free running timer will be driven by GPIO. 1045 Free running timer will count posedge or negedge of the 1046 GPIO pin based on GPIO_EDGE register. */ 1047 uint64_t ena_dfb : 1; /**< Enable Don't Free Buffer. When set chunk buffer 1048 would not be released by the TIM back to FPA. */ 1049 uint64_t reset : 1; /**< Reset oneshot pulse for free-running structures */ 1050 uint64_t enable_dwb : 1; /**< Enables non-zero DonwWriteBacks when set 1051 When set, enables the use of 1052 DontWriteBacks during the buffer freeing 1053 operations. */ 1054 uint64_t enable_timers : 1; /**< Enables the TIM section when set 1055 When set, TIM is in normal operation. 1056 When clear, time is effectively stopped for all 1057 rings in TIM. */ 1058#else 1059 uint64_t enable_timers : 1; 1060 uint64_t enable_dwb : 1; 1061 uint64_t reset : 1; 1062 uint64_t ena_dfb : 1; 1063 uint64_t ena_gpio : 1; 1064 uint64_t gpio_edge : 2; 1065 uint64_t reserved_7_63 : 57; 1066#endif 1067 } s; 1068 struct cvmx_tim_reg_flags_cn30xx { 1069#ifdef __BIG_ENDIAN_BITFIELD 1070 uint64_t reserved_3_63 : 61; 1071 uint64_t reset : 1; /**< Reset oneshot pulse for free-running structures */ 1072 uint64_t enable_dwb : 1; /**< Enables non-zero DonwWriteBacks when set 1073 When set, enables the use of 1074 DontWriteBacks during the buffer freeing 1075 operations. */ 1076 uint64_t enable_timers : 1; /**< Enables the TIM section when set 1077 When set, TIM is in normal operation. 1078 When clear, time is effectively stopped for all 1079 rings in TIM. */ 1080#else 1081 uint64_t enable_timers : 1; 1082 uint64_t enable_dwb : 1; 1083 uint64_t reset : 1; 1084 uint64_t reserved_3_63 : 61; 1085#endif 1086 } cn30xx; 1087 struct cvmx_tim_reg_flags_cn30xx cn31xx; 1088 struct cvmx_tim_reg_flags_cn30xx cn38xx; 1089 struct cvmx_tim_reg_flags_cn30xx cn38xxp2; 1090 struct cvmx_tim_reg_flags_cn30xx cn50xx; 1091 struct cvmx_tim_reg_flags_cn30xx cn52xx; 1092 struct cvmx_tim_reg_flags_cn30xx cn52xxp1; 1093 struct cvmx_tim_reg_flags_cn30xx cn56xx; 1094 struct cvmx_tim_reg_flags_cn30xx cn56xxp1; 1095 struct cvmx_tim_reg_flags_cn30xx cn58xx; 1096 struct cvmx_tim_reg_flags_cn30xx cn58xxp1; 1097 struct cvmx_tim_reg_flags_cn30xx cn61xx; 1098 struct cvmx_tim_reg_flags_cn30xx cn63xx; 1099 struct cvmx_tim_reg_flags_cn30xx cn63xxp1; 1100 struct cvmx_tim_reg_flags_cn30xx cn66xx; 1101 struct cvmx_tim_reg_flags_s cn68xx; 1102 struct cvmx_tim_reg_flags_s cn68xxp1; 1103 struct cvmx_tim_reg_flags_cn30xx cnf71xx; 1104}; 1105typedef union cvmx_tim_reg_flags cvmx_tim_reg_flags_t; 1106 1107/** 1108 * cvmx_tim_reg_int_mask 1109 * 1110 * Notes: 1111 * Note that this CSR is present only in chip revisions beginning with pass2. 1112 * When mask bit is set, the interrupt is enabled. 1113 */ 1114union cvmx_tim_reg_int_mask { 1115 uint64_t u64; 1116 struct cvmx_tim_reg_int_mask_s { 1117#ifdef __BIG_ENDIAN_BITFIELD 1118 uint64_t reserved_16_63 : 48; 1119 uint64_t mask : 16; /**< Bit mask corresponding to TIM_REG_ERROR.MASK above */ 1120#else 1121 uint64_t mask : 16; 1122 uint64_t reserved_16_63 : 48; 1123#endif 1124 } s; 1125 struct cvmx_tim_reg_int_mask_s cn30xx; 1126 struct cvmx_tim_reg_int_mask_s cn31xx; 1127 struct cvmx_tim_reg_int_mask_s cn38xx; 1128 struct cvmx_tim_reg_int_mask_s cn38xxp2; 1129 struct cvmx_tim_reg_int_mask_s cn50xx; 1130 struct cvmx_tim_reg_int_mask_s cn52xx; 1131 struct cvmx_tim_reg_int_mask_s cn52xxp1; 1132 struct cvmx_tim_reg_int_mask_s cn56xx; 1133 struct cvmx_tim_reg_int_mask_s cn56xxp1; 1134 struct cvmx_tim_reg_int_mask_s cn58xx; 1135 struct cvmx_tim_reg_int_mask_s cn58xxp1; 1136 struct cvmx_tim_reg_int_mask_s cn61xx; 1137 struct cvmx_tim_reg_int_mask_s cn63xx; 1138 struct cvmx_tim_reg_int_mask_s cn63xxp1; 1139 struct cvmx_tim_reg_int_mask_s cn66xx; 1140 struct cvmx_tim_reg_int_mask_s cnf71xx; 1141}; 1142typedef union cvmx_tim_reg_int_mask cvmx_tim_reg_int_mask_t; 1143 1144/** 1145 * cvmx_tim_reg_read_idx 1146 * 1147 * Notes: 1148 * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 1149 * as memories. The names of these CSRs begin with the prefix "TIM_MEM_". 1150 * IDX[7:0] is the read index. INC[7:0] is an increment that is added to IDX[7:0] after any CSR read. 1151 * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 1152 * contents of a CSR memory can be read with consecutive CSR read commands. 1153 */ 1154union cvmx_tim_reg_read_idx { 1155 uint64_t u64; 1156 struct cvmx_tim_reg_read_idx_s { 1157#ifdef __BIG_ENDIAN_BITFIELD 1158 uint64_t reserved_16_63 : 48; 1159 uint64_t inc : 8; /**< Increment to add to current index for next index */ 1160 uint64_t index : 8; /**< Index to use for next memory CSR read */ 1161#else 1162 uint64_t index : 8; 1163 uint64_t inc : 8; 1164 uint64_t reserved_16_63 : 48; 1165#endif 1166 } s; 1167 struct cvmx_tim_reg_read_idx_s cn30xx; 1168 struct cvmx_tim_reg_read_idx_s cn31xx; 1169 struct cvmx_tim_reg_read_idx_s cn38xx; 1170 struct cvmx_tim_reg_read_idx_s cn38xxp2; 1171 struct cvmx_tim_reg_read_idx_s cn50xx; 1172 struct cvmx_tim_reg_read_idx_s cn52xx; 1173 struct cvmx_tim_reg_read_idx_s cn52xxp1; 1174 struct cvmx_tim_reg_read_idx_s cn56xx; 1175 struct cvmx_tim_reg_read_idx_s cn56xxp1; 1176 struct cvmx_tim_reg_read_idx_s cn58xx; 1177 struct cvmx_tim_reg_read_idx_s cn58xxp1; 1178 struct cvmx_tim_reg_read_idx_s cn61xx; 1179 struct cvmx_tim_reg_read_idx_s cn63xx; 1180 struct cvmx_tim_reg_read_idx_s cn63xxp1; 1181 struct cvmx_tim_reg_read_idx_s cn66xx; 1182 struct cvmx_tim_reg_read_idx_s cnf71xx; 1183}; 1184typedef union cvmx_tim_reg_read_idx cvmx_tim_reg_read_idx_t; 1185 1186/** 1187 * cvmx_tim_ring#_ctl0 1188 * 1189 * Notes: 1190 * This CSR is a memory of 64 entries 1191 * After a 1 to 0 transition on ENA, the HW will still complete a bucket traversal for the ring 1192 * if it was pending or active prior to the transition. (SW must delay to ensure the completion 1193 * of the traversal before reprogramming the ring.) 1194 */ 1195union cvmx_tim_ringx_ctl0 { 1196 uint64_t u64; 1197 struct cvmx_tim_ringx_ctl0_s { 1198#ifdef __BIG_ENDIAN_BITFIELD 1199 uint64_t reserved_47_63 : 17; 1200 uint64_t ena : 1; /**< Ring timer enable */ 1201 uint64_t intc : 2; /**< Interval count for Error. Defines how many intervals 1202 could elapse from bucket expiration till actual 1203 bucket traversal before HW asserts an error. 1204 Typical value is 0,1,2. */ 1205 uint64_t timercount : 22; /**< Timer Count represents the ring offset; how many timer 1206 ticks have left till the interval expiration. 1207 Typical initialization value should be Interval/Constant, 1208 it is recommended that constant should be unique per ring 1209 This will create an offset between the rings. 1210 Once ENA is set, 1211 TIMERCOUNT counts down timer ticks. When TIMERCOUNT 1212 reaches zero, ring's interval expired and the HW forces 1213 a bucket traversal (and resets TIMERCOUNT to INTERVAL) 1214 TIMERCOUNT is unpredictable whenever ENA==0. 1215 It is SW responsibility to set TIMERCOUNT before 1216 TIM_RINGX_CTL0.ENA transitions from 0 to 1. 1217 When the field is set to X it would take X+1 timer tick 1218 for the interval to expire. */ 1219 uint64_t interval : 22; /**< Timer interval. Measured in Timer Ticks, where timer 1220 ticks are defined by TIM_FR_RN_TT.FR_RN_TT. */ 1221#else 1222 uint64_t interval : 22; 1223 uint64_t timercount : 22; 1224 uint64_t intc : 2; 1225 uint64_t ena : 1; 1226 uint64_t reserved_47_63 : 17; 1227#endif 1228 } s; 1229 struct cvmx_tim_ringx_ctl0_s cn68xx; 1230 struct cvmx_tim_ringx_ctl0_s cn68xxp1; 1231}; 1232typedef union cvmx_tim_ringx_ctl0 cvmx_tim_ringx_ctl0_t; 1233 1234/** 1235 * cvmx_tim_ring#_ctl1 1236 * 1237 * Notes: 1238 * This CSR is a memory of 64 entries 1239 * ***NOTE: Added fields in pass 2.0 1240 */ 1241union cvmx_tim_ringx_ctl1 { 1242 uint64_t u64; 1243 struct cvmx_tim_ringx_ctl1_s { 1244#ifdef __BIG_ENDIAN_BITFIELD 1245 uint64_t reserved_47_63 : 17; 1246 uint64_t ena_gpio : 1; /**< When set, ring's timer tick will be generated by the 1247 GPIO Timer. GPIO edge is defined by 1248 TIM_REG_FLAGS.GPIO_EDGE 1249 Default value zero means that timer ticks will 1250 be genearated from the Internal Timer */ 1251 uint64_t ena_prd : 1; /**< Enable Periodic Mode which would disable the memory 1252 write of zeros to num_entries and chunk_remainder 1253 when a bucket is traveresed. */ 1254 uint64_t ena_dwb : 1; /**< When set, enables the use of Dont Write Back during 1255 FPA buffer freeing operations */ 1256 uint64_t ena_dfb : 1; /**< Enable Don't Free Buffer. When set chunk buffer 1257 would not be released by the TIM back to FPA. */ 1258 uint64_t cpool : 3; /**< FPA Free list to free chunks to. */ 1259 uint64_t bucket : 20; /**< Current bucket. Should be set to zero by SW at 1260 enable time. 1261 Incremented once per bucket traversal. */ 1262 uint64_t bsize : 20; /**< Number of buckets minus one. If BSIZE==0 there is 1263 only one bucket in the ring. */ 1264#else 1265 uint64_t bsize : 20; 1266 uint64_t bucket : 20; 1267 uint64_t cpool : 3; 1268 uint64_t ena_dfb : 1; 1269 uint64_t ena_dwb : 1; 1270 uint64_t ena_prd : 1; 1271 uint64_t ena_gpio : 1; 1272 uint64_t reserved_47_63 : 17; 1273#endif 1274 } s; 1275 struct cvmx_tim_ringx_ctl1_s cn68xx; 1276 struct cvmx_tim_ringx_ctl1_cn68xxp1 { 1277#ifdef __BIG_ENDIAN_BITFIELD 1278 uint64_t reserved_43_63 : 21; 1279 uint64_t cpool : 3; /**< FPA Free list to free chunks to. */ 1280 uint64_t bucket : 20; /**< Current bucket. Should be set to zero by SW at 1281 enable time. 1282 Incremented once per bucket traversal. */ 1283 uint64_t bsize : 20; /**< Number of buckets minus one. If BSIZE==0 there is 1284 only one bucket in the ring. */ 1285#else 1286 uint64_t bsize : 20; 1287 uint64_t bucket : 20; 1288 uint64_t cpool : 3; 1289 uint64_t reserved_43_63 : 21; 1290#endif 1291 } cn68xxp1; 1292}; 1293typedef union cvmx_tim_ringx_ctl1 cvmx_tim_ringx_ctl1_t; 1294 1295/** 1296 * cvmx_tim_ring#_ctl2 1297 * 1298 * Notes: 1299 * BASE is a 32-byte aligned pointer[35:0]. Only pointer[35:5] are stored because pointer[4:0] = 0. 1300 * This CSR is a memory of 64 entries 1301 */ 1302union cvmx_tim_ringx_ctl2 { 1303 uint64_t u64; 1304 struct cvmx_tim_ringx_ctl2_s { 1305#ifdef __BIG_ENDIAN_BITFIELD 1306 uint64_t reserved_47_63 : 17; 1307 uint64_t csize : 13; /**< Number of words per chunk. CSIZE mod(16) should be 1308 zero. */ 1309 uint64_t reserved_31_33 : 3; 1310 uint64_t base : 31; /**< Pointer[35:5] to bucket[0] */ 1311#else 1312 uint64_t base : 31; 1313 uint64_t reserved_31_33 : 3; 1314 uint64_t csize : 13; 1315 uint64_t reserved_47_63 : 17; 1316#endif 1317 } s; 1318 struct cvmx_tim_ringx_ctl2_s cn68xx; 1319 struct cvmx_tim_ringx_ctl2_s cn68xxp1; 1320}; 1321typedef union cvmx_tim_ringx_ctl2 cvmx_tim_ringx_ctl2_t; 1322 1323/** 1324 * cvmx_tim_ring#_dbg0 1325 */ 1326union cvmx_tim_ringx_dbg0 { 1327 uint64_t u64; 1328 struct cvmx_tim_ringx_dbg0_s { 1329#ifdef __BIG_ENDIAN_BITFIELD 1330 uint64_t fr_rn_ht : 22; /**< Free Running Hardware Timer. Shared by all rings and is 1331 used to generate the Timer Tick based on 1332 FR_RN_TT. */ 1333 uint64_t timercount : 22; /**< Timer Count represents the ring's offset. 1334 Refer to TIM_RINGX_CTL0. */ 1335 uint64_t cur_bucket : 20; /**< Current bucket. Indicates the ring's current bucket. 1336 Refer to TIM_RINGX_CTL1.BUCKET. */ 1337#else 1338 uint64_t cur_bucket : 20; 1339 uint64_t timercount : 22; 1340 uint64_t fr_rn_ht : 22; 1341#endif 1342 } s; 1343 struct cvmx_tim_ringx_dbg0_s cn68xx; 1344 struct cvmx_tim_ringx_dbg0_s cn68xxp1; 1345}; 1346typedef union cvmx_tim_ringx_dbg0 cvmx_tim_ringx_dbg0_t; 1347 1348/** 1349 * cvmx_tim_ring#_dbg1 1350 */ 1351union cvmx_tim_ringx_dbg1 { 1352 uint64_t u64; 1353 struct cvmx_tim_ringx_dbg1_s { 1354#ifdef __BIG_ENDIAN_BITFIELD 1355 uint64_t reserved_2_63 : 62; 1356 uint64_t ring_esr : 2; /**< Ring Expiration Status Register. 1357 This register hold the expiration status of the ring. 1358 2'b00 - Ring was recently traversed. 1359 2'b01 - Interval expired. Ring is queued to be traversed. 1360 2'b10 - 1st interval expiration while ring is queued to be 1361 traversed. 1362 2'b11 - 2nd interval expiration while ring is queued to be 1363 traversed. */ 1364#else 1365 uint64_t ring_esr : 2; 1366 uint64_t reserved_2_63 : 62; 1367#endif 1368 } s; 1369 struct cvmx_tim_ringx_dbg1_s cn68xx; 1370 struct cvmx_tim_ringx_dbg1_s cn68xxp1; 1371}; 1372typedef union cvmx_tim_ringx_dbg1 cvmx_tim_ringx_dbg1_t; 1373 1374#endif 1375