cvmx-sriox-defs.h revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-sriox-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon sriox. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_SRIOX_TYPEDEFS_H__ 53#define __CVMX_SRIOX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_SRIOX_ACC_CTRL(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 60 cvmx_warn("CVMX_SRIOX_ACC_CTRL(%lu) is invalid on this chip\n", block_id); 61 return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull; 62} 63#else 64#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67static inline uint64_t CVMX_SRIOX_ASMBLY_ID(unsigned long block_id) 68{ 69 if (!( 70 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 71 cvmx_warn("CVMX_SRIOX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); 72 return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull; 73} 74#else 75#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78static inline uint64_t CVMX_SRIOX_ASMBLY_INFO(unsigned long block_id) 79{ 80 if (!( 81 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 82 cvmx_warn("CVMX_SRIOX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); 83 return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull; 84} 85#else 86#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89static inline uint64_t CVMX_SRIOX_BELL_RESP_CTRL(unsigned long block_id) 90{ 91 if (!( 92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 93 cvmx_warn("CVMX_SRIOX_BELL_RESP_CTRL(%lu) is invalid on this chip\n", block_id); 94 return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull; 95} 96#else 97#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100static inline uint64_t CVMX_SRIOX_BIST_STATUS(unsigned long block_id) 101{ 102 if (!( 103 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 104 cvmx_warn("CVMX_SRIOX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 105 return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull; 106} 107#else 108#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111static inline uint64_t CVMX_SRIOX_IMSG_CTRL(unsigned long block_id) 112{ 113 if (!( 114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 115 cvmx_warn("CVMX_SRIOX_IMSG_CTRL(%lu) is invalid on this chip\n", block_id); 116 return CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 1) * 0x1000000ull; 117} 118#else 119#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 1) * 0x1000000ull) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_SRIOX_IMSG_INST_HDRX(unsigned long offset, unsigned long block_id) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 126 cvmx_warn("CVMX_SRIOX_IMSG_INST_HDRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 127 return CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 1) * 0x200000ull) * 8; 128} 129#else 130#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 1) * 0x200000ull) * 8) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_SRIOX_IMSG_QOS_GRPX(unsigned long offset, unsigned long block_id) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 31)) && ((block_id <= 1)))))) 137 cvmx_warn("CVMX_SRIOX_IMSG_QOS_GRPX(%lu,%lu) is invalid on this chip\n", offset, block_id); 138 return CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8; 139} 140#else 141#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144static inline uint64_t CVMX_SRIOX_IMSG_STATUSX(unsigned long offset, unsigned long block_id) 145{ 146 if (!( 147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 23)) && ((block_id <= 1)))))) 148 cvmx_warn("CVMX_SRIOX_IMSG_STATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id); 149 return CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8; 150} 151#else 152#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155static inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR(unsigned long block_id) 156{ 157 if (!( 158 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 159 cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR(%lu) is invalid on this chip\n", block_id); 160 return CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 1) * 0x1000000ull; 161} 162#else 163#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 1) * 0x1000000ull) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166static inline uint64_t CVMX_SRIOX_INT2_ENABLE(unsigned long block_id) 167{ 168 if (!( 169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 170 cvmx_warn("CVMX_SRIOX_INT2_ENABLE(%lu) is invalid on this chip\n", block_id); 171 return CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 1) * 0x1000000ull; 172} 173#else 174#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 1) * 0x1000000ull) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177static inline uint64_t CVMX_SRIOX_INT2_REG(unsigned long block_id) 178{ 179 if (!( 180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 181 cvmx_warn("CVMX_SRIOX_INT2_REG(%lu) is invalid on this chip\n", block_id); 182 return CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 1) * 0x1000000ull; 183} 184#else 185#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 1) * 0x1000000ull) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188static inline uint64_t CVMX_SRIOX_INT_ENABLE(unsigned long block_id) 189{ 190 if (!( 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 192 cvmx_warn("CVMX_SRIOX_INT_ENABLE(%lu) is invalid on this chip\n", block_id); 193 return CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 1) * 0x1000000ull; 194} 195#else 196#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 1) * 0x1000000ull) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_SRIOX_INT_INFO0(unsigned long block_id) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 203 cvmx_warn("CVMX_SRIOX_INT_INFO0(%lu) is invalid on this chip\n", block_id); 204 return CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 1) * 0x1000000ull; 205} 206#else 207#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 1) * 0x1000000ull) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210static inline uint64_t CVMX_SRIOX_INT_INFO1(unsigned long block_id) 211{ 212 if (!( 213 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 214 cvmx_warn("CVMX_SRIOX_INT_INFO1(%lu) is invalid on this chip\n", block_id); 215 return CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 1) * 0x1000000ull; 216} 217#else 218#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 1) * 0x1000000ull) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221static inline uint64_t CVMX_SRIOX_INT_INFO2(unsigned long block_id) 222{ 223 if (!( 224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 225 cvmx_warn("CVMX_SRIOX_INT_INFO2(%lu) is invalid on this chip\n", block_id); 226 return CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 1) * 0x1000000ull; 227} 228#else 229#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 1) * 0x1000000ull) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232static inline uint64_t CVMX_SRIOX_INT_INFO3(unsigned long block_id) 233{ 234 if (!( 235 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 236 cvmx_warn("CVMX_SRIOX_INT_INFO3(%lu) is invalid on this chip\n", block_id); 237 return CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 1) * 0x1000000ull; 238} 239#else 240#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 1) * 0x1000000ull) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_SRIOX_INT_REG(unsigned long block_id) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 247 cvmx_warn("CVMX_SRIOX_INT_REG(%lu) is invalid on this chip\n", block_id); 248 return CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 1) * 0x1000000ull; 249} 250#else 251#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 1) * 0x1000000ull) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254static inline uint64_t CVMX_SRIOX_IP_FEATURE(unsigned long block_id) 255{ 256 if (!( 257 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 258 cvmx_warn("CVMX_SRIOX_IP_FEATURE(%lu) is invalid on this chip\n", block_id); 259 return CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 1) * 0x1000000ull; 260} 261#else 262#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 1) * 0x1000000ull) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265static inline uint64_t CVMX_SRIOX_MAC_BUFFERS(unsigned long block_id) 266{ 267 if (!( 268 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 269 cvmx_warn("CVMX_SRIOX_MAC_BUFFERS(%lu) is invalid on this chip\n", block_id); 270 return CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 1) * 0x1000000ull; 271} 272#else 273#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 1) * 0x1000000ull) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276static inline uint64_t CVMX_SRIOX_MAINT_OP(unsigned long block_id) 277{ 278 if (!( 279 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 280 cvmx_warn("CVMX_SRIOX_MAINT_OP(%lu) is invalid on this chip\n", block_id); 281 return CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 1) * 0x1000000ull; 282} 283#else 284#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 1) * 0x1000000ull) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287static inline uint64_t CVMX_SRIOX_MAINT_RD_DATA(unsigned long block_id) 288{ 289 if (!( 290 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 291 cvmx_warn("CVMX_SRIOX_MAINT_RD_DATA(%lu) is invalid on this chip\n", block_id); 292 return CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 1) * 0x1000000ull; 293} 294#else 295#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 1) * 0x1000000ull) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298static inline uint64_t CVMX_SRIOX_MCE_TX_CTL(unsigned long block_id) 299{ 300 if (!( 301 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 302 cvmx_warn("CVMX_SRIOX_MCE_TX_CTL(%lu) is invalid on this chip\n", block_id); 303 return CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 1) * 0x1000000ull; 304} 305#else 306#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 1) * 0x1000000ull) 307#endif 308#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309static inline uint64_t CVMX_SRIOX_MEM_OP_CTRL(unsigned long block_id) 310{ 311 if (!( 312 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 313 cvmx_warn("CVMX_SRIOX_MEM_OP_CTRL(%lu) is invalid on this chip\n", block_id); 314 return CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 1) * 0x1000000ull; 315} 316#else 317#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 1) * 0x1000000ull) 318#endif 319#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320static inline uint64_t CVMX_SRIOX_OMSG_CTRLX(unsigned long offset, unsigned long block_id) 321{ 322 if (!( 323 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 324 cvmx_warn("CVMX_SRIOX_OMSG_CTRLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 325 return CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 326} 327#else 328#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 329#endif 330#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331static inline uint64_t CVMX_SRIOX_OMSG_DONE_COUNTSX(unsigned long offset, unsigned long block_id) 332{ 333 if (!( 334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 335 cvmx_warn("CVMX_SRIOX_OMSG_DONE_COUNTSX(%lu,%lu) is invalid on this chip\n", offset, block_id); 336 return CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 337} 338#else 339#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342static inline uint64_t CVMX_SRIOX_OMSG_FMP_MRX(unsigned long offset, unsigned long block_id) 343{ 344 if (!( 345 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 346 cvmx_warn("CVMX_SRIOX_OMSG_FMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 347 return CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 348} 349#else 350#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 351#endif 352#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353static inline uint64_t CVMX_SRIOX_OMSG_NMP_MRX(unsigned long offset, unsigned long block_id) 354{ 355 if (!( 356 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 357 cvmx_warn("CVMX_SRIOX_OMSG_NMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 358 return CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 359} 360#else 361#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 362#endif 363#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364static inline uint64_t CVMX_SRIOX_OMSG_PORTX(unsigned long offset, unsigned long block_id) 365{ 366 if (!( 367 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 368 cvmx_warn("CVMX_SRIOX_OMSG_PORTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 369 return CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 370} 371#else 372#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 373#endif 374#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375static inline uint64_t CVMX_SRIOX_OMSG_SILO_THR(unsigned long block_id) 376{ 377 if (!( 378 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 379 cvmx_warn("CVMX_SRIOX_OMSG_SILO_THR(%lu) is invalid on this chip\n", block_id); 380 return CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 1) * 0x1000000ull; 381} 382#else 383#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 1) * 0x1000000ull) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386static inline uint64_t CVMX_SRIOX_OMSG_SP_MRX(unsigned long offset, unsigned long block_id) 387{ 388 if (!( 389 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 390 cvmx_warn("CVMX_SRIOX_OMSG_SP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 391 return CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 392} 393#else 394#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 395#endif 396#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397static inline uint64_t CVMX_SRIOX_PRIOX_IN_USE(unsigned long offset, unsigned long block_id) 398{ 399 if (!( 400 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))))) 401 cvmx_warn("CVMX_SRIOX_PRIOX_IN_USE(%lu,%lu) is invalid on this chip\n", offset, block_id); 402 return CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x200000ull) * 8; 403} 404#else 405#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x200000ull) * 8) 406#endif 407#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408static inline uint64_t CVMX_SRIOX_RX_BELL(unsigned long block_id) 409{ 410 if (!( 411 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 412 cvmx_warn("CVMX_SRIOX_RX_BELL(%lu) is invalid on this chip\n", block_id); 413 return CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 1) * 0x1000000ull; 414} 415#else 416#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 1) * 0x1000000ull) 417#endif 418#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419static inline uint64_t CVMX_SRIOX_RX_BELL_SEQ(unsigned long block_id) 420{ 421 if (!( 422 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 423 cvmx_warn("CVMX_SRIOX_RX_BELL_SEQ(%lu) is invalid on this chip\n", block_id); 424 return CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 1) * 0x1000000ull; 425} 426#else 427#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 1) * 0x1000000ull) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430static inline uint64_t CVMX_SRIOX_RX_STATUS(unsigned long block_id) 431{ 432 if (!( 433 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 434 cvmx_warn("CVMX_SRIOX_RX_STATUS(%lu) is invalid on this chip\n", block_id); 435 return CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 1) * 0x1000000ull; 436} 437#else 438#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 1) * 0x1000000ull) 439#endif 440#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441static inline uint64_t CVMX_SRIOX_S2M_TYPEX(unsigned long offset, unsigned long block_id) 442{ 443 if (!( 444 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))))) 445 cvmx_warn("CVMX_SRIOX_S2M_TYPEX(%lu,%lu) is invalid on this chip\n", offset, block_id); 446 return CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8; 447} 448#else 449#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8) 450#endif 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452static inline uint64_t CVMX_SRIOX_SEQ(unsigned long block_id) 453{ 454 if (!( 455 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 456 cvmx_warn("CVMX_SRIOX_SEQ(%lu) is invalid on this chip\n", block_id); 457 return CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 1) * 0x1000000ull; 458} 459#else 460#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 1) * 0x1000000ull) 461#endif 462#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463static inline uint64_t CVMX_SRIOX_STATUS_REG(unsigned long block_id) 464{ 465 if (!( 466 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 467 cvmx_warn("CVMX_SRIOX_STATUS_REG(%lu) is invalid on this chip\n", block_id); 468 return CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 1) * 0x1000000ull; 469} 470#else 471#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 1) * 0x1000000ull) 472#endif 473#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474static inline uint64_t CVMX_SRIOX_TAG_CTRL(unsigned long block_id) 475{ 476 if (!( 477 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 478 cvmx_warn("CVMX_SRIOX_TAG_CTRL(%lu) is invalid on this chip\n", block_id); 479 return CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 1) * 0x1000000ull; 480} 481#else 482#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 1) * 0x1000000ull) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485static inline uint64_t CVMX_SRIOX_TLP_CREDITS(unsigned long block_id) 486{ 487 if (!( 488 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 489 cvmx_warn("CVMX_SRIOX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id); 490 return CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 1) * 0x1000000ull; 491} 492#else 493#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 1) * 0x1000000ull) 494#endif 495#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496static inline uint64_t CVMX_SRIOX_TX_BELL(unsigned long block_id) 497{ 498 if (!( 499 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 500 cvmx_warn("CVMX_SRIOX_TX_BELL(%lu) is invalid on this chip\n", block_id); 501 return CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 1) * 0x1000000ull; 502} 503#else 504#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 1) * 0x1000000ull) 505#endif 506#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507static inline uint64_t CVMX_SRIOX_TX_BELL_INFO(unsigned long block_id) 508{ 509 if (!( 510 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 511 cvmx_warn("CVMX_SRIOX_TX_BELL_INFO(%lu) is invalid on this chip\n", block_id); 512 return CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 1) * 0x1000000ull; 513} 514#else 515#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 1) * 0x1000000ull) 516#endif 517#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518static inline uint64_t CVMX_SRIOX_TX_CTRL(unsigned long block_id) 519{ 520 if (!( 521 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 522 cvmx_warn("CVMX_SRIOX_TX_CTRL(%lu) is invalid on this chip\n", block_id); 523 return CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 1) * 0x1000000ull; 524} 525#else 526#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 1) * 0x1000000ull) 527#endif 528#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529static inline uint64_t CVMX_SRIOX_TX_EMPHASIS(unsigned long block_id) 530{ 531 if (!( 532 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 533 cvmx_warn("CVMX_SRIOX_TX_EMPHASIS(%lu) is invalid on this chip\n", block_id); 534 return CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 1) * 0x1000000ull; 535} 536#else 537#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 1) * 0x1000000ull) 538#endif 539#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540static inline uint64_t CVMX_SRIOX_TX_STATUS(unsigned long block_id) 541{ 542 if (!( 543 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 544 cvmx_warn("CVMX_SRIOX_TX_STATUS(%lu) is invalid on this chip\n", block_id); 545 return CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 1) * 0x1000000ull; 546} 547#else 548#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 1) * 0x1000000ull) 549#endif 550#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551static inline uint64_t CVMX_SRIOX_WR_DONE_COUNTS(unsigned long block_id) 552{ 553 if (!( 554 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 555 cvmx_warn("CVMX_SRIOX_WR_DONE_COUNTS(%lu) is invalid on this chip\n", block_id); 556 return CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 1) * 0x1000000ull; 557} 558#else 559#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 1) * 0x1000000ull) 560#endif 561 562/** 563 * cvmx_srio#_acc_ctrl 564 * 565 * SRIO_ACC_CTRL = SRIO Access Control 566 * 567 * General access control of the incoming BAR registers. 568 * 569 * Notes: 570 * This register controls write access to the BAR registers via SRIO Maintenance Operations. At 571 * powerup the BAR registers can be accessed via RSL and Maintenance Operations. If the DENY_BAR* 572 * bits are set then Maintenance Writes to the corresponding BAR registers are ignored. This 573 * register does not effect read operations. 574 * 575 * Clk_Rst: SRIO(0..1)_ACC_CTRL hclk hrst_n 576 */ 577union cvmx_sriox_acc_ctrl 578{ 579 uint64_t u64; 580 struct cvmx_sriox_acc_ctrl_s 581 { 582#if __BYTE_ORDER == __BIG_ENDIAN 583 uint64_t reserved_3_63 : 61; 584 uint64_t deny_bar2 : 1; /**< Deny SRIO Write Access to BAR2 Registers */ 585 uint64_t deny_bar1 : 1; /**< Deny SRIO Write Access to BAR1 Registers */ 586 uint64_t deny_bar0 : 1; /**< Deny SRIO Write Access to BAR0 Registers */ 587#else 588 uint64_t deny_bar0 : 1; 589 uint64_t deny_bar1 : 1; 590 uint64_t deny_bar2 : 1; 591 uint64_t reserved_3_63 : 61; 592#endif 593 } s; 594 struct cvmx_sriox_acc_ctrl_s cn63xx; 595 struct cvmx_sriox_acc_ctrl_s cn63xxp1; 596}; 597typedef union cvmx_sriox_acc_ctrl cvmx_sriox_acc_ctrl_t; 598 599/** 600 * cvmx_srio#_asmbly_id 601 * 602 * SRIO_ASMBLY_ID = SRIO Assembly ID 603 * 604 * The Assembly ID register controls the Assembly ID and Vendor 605 * 606 * Notes: 607 * This register specifies the Assembly ID and Vendor visible in SRIOMAINT(0..1)_ASMBLY_ID register. The 608 * Assembly Vendor ID is typically supplied by the RapidIO Trade Association. This register is only 609 * reset during COLD boot and may only be modified while SRIO(0..1)_STATUS_REG.ACCESS is zero. 610 * 611 * Clk_Rst: SRIO(0..1)_ASMBLY_ID sclk srst_cold_n 612 */ 613union cvmx_sriox_asmbly_id 614{ 615 uint64_t u64; 616 struct cvmx_sriox_asmbly_id_s 617 { 618#if __BYTE_ORDER == __BIG_ENDIAN 619 uint64_t reserved_32_63 : 32; 620 uint64_t assy_id : 16; /**< Assembly Identifer */ 621 uint64_t assy_ven : 16; /**< Assembly Vendor Identifer */ 622#else 623 uint64_t assy_ven : 16; 624 uint64_t assy_id : 16; 625 uint64_t reserved_32_63 : 32; 626#endif 627 } s; 628 struct cvmx_sriox_asmbly_id_s cn63xx; 629 struct cvmx_sriox_asmbly_id_s cn63xxp1; 630}; 631typedef union cvmx_sriox_asmbly_id cvmx_sriox_asmbly_id_t; 632 633/** 634 * cvmx_srio#_asmbly_info 635 * 636 * SRIO_ASMBLY_INFO = SRIO Assembly Information 637 * 638 * The Assembly Info register controls the Assembly Revision 639 * 640 * Notes: 641 * The Assembly Info register controls the Assembly Revision visible in the ASSY_REV field of the 642 * SRIOMAINT(0..1)_ASMBLY_INFO register. This register is only reset during COLD boot and may only be 643 * modified while SRIO(0..1)_STATUS_REG.ACCESS is zero. 644 * 645 * Clk_Rst: SRIO(0..1)_ASMBLY_INFO sclk srst_cold_n 646 */ 647union cvmx_sriox_asmbly_info 648{ 649 uint64_t u64; 650 struct cvmx_sriox_asmbly_info_s 651 { 652#if __BYTE_ORDER == __BIG_ENDIAN 653 uint64_t reserved_32_63 : 32; 654 uint64_t assy_rev : 16; /**< Assembly Revision */ 655 uint64_t reserved_0_15 : 16; 656#else 657 uint64_t reserved_0_15 : 16; 658 uint64_t assy_rev : 16; 659 uint64_t reserved_32_63 : 32; 660#endif 661 } s; 662 struct cvmx_sriox_asmbly_info_s cn63xx; 663 struct cvmx_sriox_asmbly_info_s cn63xxp1; 664}; 665typedef union cvmx_sriox_asmbly_info cvmx_sriox_asmbly_info_t; 666 667/** 668 * cvmx_srio#_bell_resp_ctrl 669 * 670 * SRIO_BELL_RESP_CTRL = SRIO Doorbell Response Control 671 * 672 * The SRIO Doorbell Response Control Register 673 * 674 * Notes: 675 * This register is used to override the response priority of the outgoing doorbell responses. 676 * 677 * Clk_Rst: SRIO(0..1)_BELL_RESP_CTRL hclk hrst_n 678 */ 679union cvmx_sriox_bell_resp_ctrl 680{ 681 uint64_t u64; 682 struct cvmx_sriox_bell_resp_ctrl_s 683 { 684#if __BYTE_ORDER == __BIG_ENDIAN 685 uint64_t reserved_6_63 : 58; 686 uint64_t rp1_sid : 1; /**< Sets response priority for incomimg doorbells 687 of priority 1 on the secondary ID (0=2, 1=3) */ 688 uint64_t rp0_sid : 2; /**< Sets response priority for incomimg doorbells 689 of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 690 uint64_t rp1_pid : 1; /**< Sets response priority for incomimg doorbells 691 of priority 1 on the primary ID (0=2, 1=3) */ 692 uint64_t rp0_pid : 2; /**< Sets response priority for incomimg doorbells 693 of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 694#else 695 uint64_t rp0_pid : 2; 696 uint64_t rp1_pid : 1; 697 uint64_t rp0_sid : 2; 698 uint64_t rp1_sid : 1; 699 uint64_t reserved_6_63 : 58; 700#endif 701 } s; 702 struct cvmx_sriox_bell_resp_ctrl_s cn63xx; 703 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; 704}; 705typedef union cvmx_sriox_bell_resp_ctrl cvmx_sriox_bell_resp_ctrl_t; 706 707/** 708 * cvmx_srio#_bist_status 709 * 710 * SRIO_BIST_STATUS = SRIO Bist Status 711 * 712 * Results from BIST runs of SRIO's memories. 713 * 714 * Notes: 715 * BIST Results. 716 * 717 * Clk_Rst: SRIO(0..1)_BIST_STATUS hclk hrst_n 718 */ 719union cvmx_sriox_bist_status 720{ 721 uint64_t u64; 722 struct cvmx_sriox_bist_status_s 723 { 724#if __BYTE_ORDER == __BIG_ENDIAN 725 uint64_t reserved_44_63 : 20; 726 uint64_t mram : 2; /**< Incoming Message SLI FIFO. */ 727 uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */ 728 uint64_t bell : 2; /**< Incoming Doorbell FIFO. */ 729 uint64_t otag : 2; /**< Outgoing Tag Data. */ 730 uint64_t itag : 1; /**< Incoming TAG Data. */ 731 uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */ 732 uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */ 733 uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */ 734 uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */ 735 uint64_t reserved_22_23 : 2; 736 uint64_t rxbuf2 : 2; /**< Additional Incoming SRIO MAC Buffers (Pass 2). */ 737 uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */ 738 uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */ 739 uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */ 740 uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */ 741 uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */ 742 uint64_t imsg : 5; /**< Incoming Message RAMs. */ 743 uint64_t omsg : 7; /**< Outgoing Message RAMs. */ 744#else 745 uint64_t omsg : 7; 746 uint64_t imsg : 5; 747 uint64_t rxbuf : 2; 748 uint64_t txbuf : 2; 749 uint64_t ospf : 1; 750 uint64_t ispf : 1; 751 uint64_t oarb : 2; 752 uint64_t rxbuf2 : 2; 753 uint64_t reserved_22_23 : 2; 754 uint64_t optrs : 4; 755 uint64_t obulk : 4; 756 uint64_t rtn : 2; 757 uint64_t ofree : 1; 758 uint64_t itag : 1; 759 uint64_t otag : 2; 760 uint64_t bell : 2; 761 uint64_t cram : 2; 762 uint64_t mram : 2; 763 uint64_t reserved_44_63 : 20; 764#endif 765 } s; 766 struct cvmx_sriox_bist_status_s cn63xx; 767 struct cvmx_sriox_bist_status_cn63xxp1 768 { 769#if __BYTE_ORDER == __BIG_ENDIAN 770 uint64_t reserved_44_63 : 20; 771 uint64_t mram : 2; /**< Incoming Message SLI FIFO. */ 772 uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */ 773 uint64_t bell : 2; /**< Incoming Doorbell FIFO. */ 774 uint64_t otag : 2; /**< Outgoing Tag Data. */ 775 uint64_t itag : 1; /**< Incoming TAG Data. */ 776 uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */ 777 uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */ 778 uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */ 779 uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */ 780 uint64_t reserved_20_23 : 4; 781 uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */ 782 uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */ 783 uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */ 784 uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */ 785 uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */ 786 uint64_t imsg : 5; /**< Incoming Message RAMs. */ 787 uint64_t omsg : 7; /**< Outgoing Message RAMs. */ 788#else 789 uint64_t omsg : 7; 790 uint64_t imsg : 5; 791 uint64_t rxbuf : 2; 792 uint64_t txbuf : 2; 793 uint64_t ospf : 1; 794 uint64_t ispf : 1; 795 uint64_t oarb : 2; 796 uint64_t reserved_20_23 : 4; 797 uint64_t optrs : 4; 798 uint64_t obulk : 4; 799 uint64_t rtn : 2; 800 uint64_t ofree : 1; 801 uint64_t itag : 1; 802 uint64_t otag : 2; 803 uint64_t bell : 2; 804 uint64_t cram : 2; 805 uint64_t mram : 2; 806 uint64_t reserved_44_63 : 20; 807#endif 808 } cn63xxp1; 809}; 810typedef union cvmx_sriox_bist_status cvmx_sriox_bist_status_t; 811 812/** 813 * cvmx_srio#_imsg_ctrl 814 * 815 * SRIO_IMSG_CTRL = SRIO Incoming Message Control 816 * 817 * The SRIO Incoming Message Control Register 818 * 819 * Notes: 820 * RSP_THR should not typically be modified from reset value. 821 * 822 * Clk_Rst: SRIO(0..1)_IMSG_CTRL hclk hrst_n 823 */ 824union cvmx_sriox_imsg_ctrl 825{ 826 uint64_t u64; 827 struct cvmx_sriox_imsg_ctrl_s 828 { 829#if __BYTE_ORDER == __BIG_ENDIAN 830 uint64_t reserved_32_63 : 32; 831 uint64_t to_mode : 1; /**< MP message timeout mode: 832 - 0: The timeout counter gets reset whenever the 833 next sequential segment is received, regardless 834 of whether it is accepted 835 - 1: The timeout counter gets reset only when the 836 next sequential segment is received and 837 accepted */ 838 uint64_t reserved_30_30 : 1; 839 uint64_t rsp_thr : 6; /**< Sets max number of msg responses in queue before 840 sending link-layer retries (field value is added 841 to 16 to create threshold value) */ 842 uint64_t reserved_22_23 : 2; 843 uint64_t rp1_sid : 1; /**< Sets msg response priority for incomimg messages 844 of priority 1 on the secondary ID (0=2, 1=3) */ 845 uint64_t rp0_sid : 2; /**< Sets msg response priority for incomimg messages 846 of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 847 uint64_t rp1_pid : 1; /**< Sets msg response priority for incomimg messages 848 of priority 1 on the primary ID (0=2, 1=3) */ 849 uint64_t rp0_pid : 2; /**< Sets msg response priority for incomimg messages 850 of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 851 uint64_t reserved_15_15 : 1; 852 uint64_t prt_sel : 3; /**< Port/Controller selection method: 853 - 0: Table lookup based on mailbox 854 - 1: Table lookup based on priority 855 - 2: Table lookup based on letter 856 - 3: Size-based (SP to port 0, MP to port 1) 857 - 4: ID-based (pri ID to port 0, sec ID to port 1) */ 858 uint64_t lttr : 4; /**< Port/Controller selection letter table */ 859 uint64_t prio : 4; /**< Port/Controller selection priority table */ 860 uint64_t mbox : 4; /**< Port/Controller selection mailbox table */ 861#else 862 uint64_t mbox : 4; 863 uint64_t prio : 4; 864 uint64_t lttr : 4; 865 uint64_t prt_sel : 3; 866 uint64_t reserved_15_15 : 1; 867 uint64_t rp0_pid : 2; 868 uint64_t rp1_pid : 1; 869 uint64_t rp0_sid : 2; 870 uint64_t rp1_sid : 1; 871 uint64_t reserved_22_23 : 2; 872 uint64_t rsp_thr : 6; 873 uint64_t reserved_30_30 : 1; 874 uint64_t to_mode : 1; 875 uint64_t reserved_32_63 : 32; 876#endif 877 } s; 878 struct cvmx_sriox_imsg_ctrl_s cn63xx; 879 struct cvmx_sriox_imsg_ctrl_s cn63xxp1; 880}; 881typedef union cvmx_sriox_imsg_ctrl cvmx_sriox_imsg_ctrl_t; 882 883/** 884 * cvmx_srio#_imsg_inst_hdr# 885 * 886 * SRIO_IMSG_INST_HDRX = SRIO Incoming Message Packet Instruction Header 887 * 888 * The SRIO Port/Controller X Incoming Message Packet Instruction Header Register 889 * 890 * Notes: 891 * SRIO HW generates most of the SRIO_WORD1 fields from these values. SRIO_WORD1 is the 2nd of two 892 * header words that SRIO inserts in front of all received messages. SRIO_WORD1 may commonly be used 893 * as a PIP/IPD PKT_INST_HDR. This CSR matches the PIP/IPD PKT_INST_HDR format except for the QOS 894 * and GRP fields. SRIO*_IMSG_QOS_GRP*[QOS*,GRP*] supply the QOS and GRP fields. 895 * 896 * Clk_Rst: SRIO(0..1)_IMSG_INST_HDR[0:1] hclk hrst_n 897 */ 898union cvmx_sriox_imsg_inst_hdrx 899{ 900 uint64_t u64; 901 struct cvmx_sriox_imsg_inst_hdrx_s 902 { 903#if __BYTE_ORDER == __BIG_ENDIAN 904 uint64_t r : 1; /**< Port/Controller X R */ 905 uint64_t reserved_58_62 : 5; 906 uint64_t pm : 2; /**< Port/Controller X PM */ 907 uint64_t reserved_55_55 : 1; 908 uint64_t sl : 7; /**< Port/Controller X SL */ 909 uint64_t reserved_46_47 : 2; 910 uint64_t nqos : 1; /**< Port/Controller X NQOS */ 911 uint64_t ngrp : 1; /**< Port/Controller X NGRP */ 912 uint64_t ntt : 1; /**< Port/Controller X NTT */ 913 uint64_t ntag : 1; /**< Port/Controller X NTAG */ 914 uint64_t reserved_35_41 : 7; 915 uint64_t rs : 1; /**< Port/Controller X RS */ 916 uint64_t tt : 2; /**< Port/Controller X TT */ 917 uint64_t tag : 32; /**< Port/Controller X TAG */ 918#else 919 uint64_t tag : 32; 920 uint64_t tt : 2; 921 uint64_t rs : 1; 922 uint64_t reserved_35_41 : 7; 923 uint64_t ntag : 1; 924 uint64_t ntt : 1; 925 uint64_t ngrp : 1; 926 uint64_t nqos : 1; 927 uint64_t reserved_46_47 : 2; 928 uint64_t sl : 7; 929 uint64_t reserved_55_55 : 1; 930 uint64_t pm : 2; 931 uint64_t reserved_58_62 : 5; 932 uint64_t r : 1; 933#endif 934 } s; 935 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; 936 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; 937}; 938typedef union cvmx_sriox_imsg_inst_hdrx cvmx_sriox_imsg_inst_hdrx_t; 939 940/** 941 * cvmx_srio#_imsg_qos_grp# 942 * 943 * SRIO_IMSG_QOS_GRPX = SRIO Incoming Message QOS/GRP Table 944 * 945 * The SRIO Incoming Message QOS/GRP Table Entry X 946 * 947 * Notes: 948 * The QOS/GRP table contains 32 entries with 8 QOS/GRP pairs per entry - 256 pairs total. 949 * HW selects the table entry by the concatenation of SRIO_WORD0[PRIO,DIS,MBOX], thus entry 0 is 950 * used for messages with PRIO=0,DIS=0,MBOX=0, entry 1 is for PRIO=0,DIS=0,MBOX=1, etc. HW 951 * selects the QOS/GRP pair from the table entry by the concatenation of SRIO_WORD0[ID,LETTER] as 952 * shown above. HW then inserts the QOS/GRP pair into SRIO_WORD1[QOS,GRP], which may commonly 953 * be used for the PIP/IPD PKT_INST_HDR[QOS,GRP] fields. 954 * 955 * Clk_Rst: SRIO(0..1)_IMSG_QOS_GRP[0:1] hclk hrst_n 956 */ 957union cvmx_sriox_imsg_qos_grpx 958{ 959 uint64_t u64; 960 struct cvmx_sriox_imsg_qos_grpx_s 961 { 962#if __BYTE_ORDER == __BIG_ENDIAN 963 uint64_t reserved_63_63 : 1; 964 uint64_t qos7 : 3; /**< Entry X:7 QOS (ID=1, LETTER=3) */ 965 uint64_t grp7 : 4; /**< Entry X:7 GRP (ID=1, LETTER=3) */ 966 uint64_t reserved_55_55 : 1; 967 uint64_t qos6 : 3; /**< Entry X:6 QOS (ID=1, LETTER=2) */ 968 uint64_t grp6 : 4; /**< Entry X:6 GRP (ID=1, LETTER=2) */ 969 uint64_t reserved_47_47 : 1; 970 uint64_t qos5 : 3; /**< Entry X:5 QOS (ID=1, LETTER=1) */ 971 uint64_t grp5 : 4; /**< Entry X:5 GRP (ID=1, LETTER=1) */ 972 uint64_t reserved_39_39 : 1; 973 uint64_t qos4 : 3; /**< Entry X:4 QOS (ID=1, LETTER=0) */ 974 uint64_t grp4 : 4; /**< Entry X:4 GRP (ID=1, LETTER=0) */ 975 uint64_t reserved_31_31 : 1; 976 uint64_t qos3 : 3; /**< Entry X:3 QOS (ID=0, LETTER=3) */ 977 uint64_t grp3 : 4; /**< Entry X:3 GRP (ID=0, LETTER=3) */ 978 uint64_t reserved_23_23 : 1; 979 uint64_t qos2 : 3; /**< Entry X:2 QOS (ID=0, LETTER=2) */ 980 uint64_t grp2 : 4; /**< Entry X:2 GRP (ID=0, LETTER=2) */ 981 uint64_t reserved_15_15 : 1; 982 uint64_t qos1 : 3; /**< Entry X:1 QOS (ID=0, LETTER=1) */ 983 uint64_t grp1 : 4; /**< Entry X:1 GRP (ID=0, LETTER=1) */ 984 uint64_t reserved_7_7 : 1; 985 uint64_t qos0 : 3; /**< Entry X:0 QOS (ID=0, LETTER=0) */ 986 uint64_t grp0 : 4; /**< Entry X:0 GRP (ID=0, LETTER=0) */ 987#else 988 uint64_t grp0 : 4; 989 uint64_t qos0 : 3; 990 uint64_t reserved_7_7 : 1; 991 uint64_t grp1 : 4; 992 uint64_t qos1 : 3; 993 uint64_t reserved_15_15 : 1; 994 uint64_t grp2 : 4; 995 uint64_t qos2 : 3; 996 uint64_t reserved_23_23 : 1; 997 uint64_t grp3 : 4; 998 uint64_t qos3 : 3; 999 uint64_t reserved_31_31 : 1; 1000 uint64_t grp4 : 4; 1001 uint64_t qos4 : 3; 1002 uint64_t reserved_39_39 : 1; 1003 uint64_t grp5 : 4; 1004 uint64_t qos5 : 3; 1005 uint64_t reserved_47_47 : 1; 1006 uint64_t grp6 : 4; 1007 uint64_t qos6 : 3; 1008 uint64_t reserved_55_55 : 1; 1009 uint64_t grp7 : 4; 1010 uint64_t qos7 : 3; 1011 uint64_t reserved_63_63 : 1; 1012#endif 1013 } s; 1014 struct cvmx_sriox_imsg_qos_grpx_s cn63xx; 1015 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; 1016}; 1017typedef union cvmx_sriox_imsg_qos_grpx cvmx_sriox_imsg_qos_grpx_t; 1018 1019/** 1020 * cvmx_srio#_imsg_status# 1021 * 1022 * SRIO_IMSG_STATUSX = SRIO Incoming Message Status Table 1023 * 1024 * The SRIO Incoming Message Status Table Entry X 1025 * 1026 * Notes: 1027 * Clk_Rst: SRIO(0..1)_IMSG_STATUS[0:1] hclk hrst_n 1028 * 1029 */ 1030union cvmx_sriox_imsg_statusx 1031{ 1032 uint64_t u64; 1033 struct cvmx_sriox_imsg_statusx_s 1034 { 1035#if __BYTE_ORDER == __BIG_ENDIAN 1036 uint64_t val1 : 1; /**< Entry X:1 Valid */ 1037 uint64_t err1 : 1; /**< Entry X:1 Error */ 1038 uint64_t toe1 : 1; /**< Entry X:1 Timeout Error */ 1039 uint64_t toc1 : 1; /**< Entry X:1 Timeout Count */ 1040 uint64_t prt1 : 1; /**< Entry X:1 Port */ 1041 uint64_t reserved_58_58 : 1; 1042 uint64_t tt1 : 1; /**< Entry X:1 TT ID */ 1043 uint64_t dis1 : 1; /**< Entry X:1 Dest ID */ 1044 uint64_t seg1 : 4; /**< Entry X:1 Next Segment */ 1045 uint64_t mbox1 : 2; /**< Entry X:1 Mailbox */ 1046 uint64_t lttr1 : 2; /**< Entry X:1 Letter */ 1047 uint64_t sid1 : 16; /**< Entry X:1 Source ID */ 1048 uint64_t val0 : 1; /**< Entry X:0 Valid */ 1049 uint64_t err0 : 1; /**< Entry X:0 Error */ 1050 uint64_t toe0 : 1; /**< Entry X:0 Timeout Error */ 1051 uint64_t toc0 : 1; /**< Entry X:0 Timeout Count */ 1052 uint64_t prt0 : 1; /**< Entry X:0 Port */ 1053 uint64_t reserved_26_26 : 1; 1054 uint64_t tt0 : 1; /**< Entry X:0 TT ID */ 1055 uint64_t dis0 : 1; /**< Entry X:0 Dest ID */ 1056 uint64_t seg0 : 4; /**< Entry X:0 Next Segment */ 1057 uint64_t mbox0 : 2; /**< Entry X:0 Mailbox */ 1058 uint64_t lttr0 : 2; /**< Entry X:0 Letter */ 1059 uint64_t sid0 : 16; /**< Entry X:0 Source ID */ 1060#else 1061 uint64_t sid0 : 16; 1062 uint64_t lttr0 : 2; 1063 uint64_t mbox0 : 2; 1064 uint64_t seg0 : 4; 1065 uint64_t dis0 : 1; 1066 uint64_t tt0 : 1; 1067 uint64_t reserved_26_26 : 1; 1068 uint64_t prt0 : 1; 1069 uint64_t toc0 : 1; 1070 uint64_t toe0 : 1; 1071 uint64_t err0 : 1; 1072 uint64_t val0 : 1; 1073 uint64_t sid1 : 16; 1074 uint64_t lttr1 : 2; 1075 uint64_t mbox1 : 2; 1076 uint64_t seg1 : 4; 1077 uint64_t dis1 : 1; 1078 uint64_t tt1 : 1; 1079 uint64_t reserved_58_58 : 1; 1080 uint64_t prt1 : 1; 1081 uint64_t toc1 : 1; 1082 uint64_t toe1 : 1; 1083 uint64_t err1 : 1; 1084 uint64_t val1 : 1; 1085#endif 1086 } s; 1087 struct cvmx_sriox_imsg_statusx_s cn63xx; 1088 struct cvmx_sriox_imsg_statusx_s cn63xxp1; 1089}; 1090typedef union cvmx_sriox_imsg_statusx cvmx_sriox_imsg_statusx_t; 1091 1092/** 1093 * cvmx_srio#_imsg_vport_thr 1094 * 1095 * SRIO_IMSG_VPORT_THR = SRIO Incoming Message Virtual Port Threshold 1096 * 1097 * The SRIO Incoming Message Virtual Port Threshold Register 1098 * 1099 * Notes: 1100 * SRIO0_IMSG_VPORT_THR.MAX_TOT must be >= SRIO0_IMSG_VPORT_THR.BUF_THR + SRIO1_IMSG_VPORT_THR.BUF_THR 1101 * This register can be accessed regardless of the value in SRIO(0..1)_STATUS_REG.ACCESS and is not 1102 * effected by MAC reset. 1103 * 1104 * Clk_Rst: SRIO(0..1)_IMSG_VPORT_THR sclk srst_n 1105 */ 1106union cvmx_sriox_imsg_vport_thr 1107{ 1108 uint64_t u64; 1109 struct cvmx_sriox_imsg_vport_thr_s 1110 { 1111#if __BYTE_ORDER == __BIG_ENDIAN 1112 uint64_t reserved_54_63 : 10; 1113 uint64_t max_tot : 6; /**< Sets max number of vports available to SRIO0+SRIO1 1114 This field is only used in SRIO0. 1115 SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_TOT]. */ 1116 uint64_t reserved_46_47 : 2; 1117 uint64_t max_s1 : 6; /**< Sets max number of vports available to SRIO1 1118 This field is only used in SRIO0. 1119 SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_S1]. */ 1120 uint64_t reserved_38_39 : 2; 1121 uint64_t max_s0 : 6; /**< Sets max number of vports available to SRIO0 1122 This field is only used in SRIO0. 1123 SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_S0]. */ 1124 uint64_t sp_vport : 1; /**< Single-segment vport pre-allocation. 1125 When set, single-segment messages use pre-allocated 1126 vport slots (that do not count toward thresholds). 1127 When clear, single-segment messages must allocate 1128 vport slots just like multi-segment messages do. */ 1129 uint64_t reserved_20_30 : 11; 1130 uint64_t buf_thr : 4; /**< Sets number of vports to be buffered by this 1131 interface. BUF_THR must not be zero when receiving 1132 messages. The max BUF_THR value is 8. 1133 Recommend BUF_THR values 1-4. If the 46 available 1134 vports are not statically-allocated across the two 1135 SRIO's, smaller BUF_THR values may leave more 1136 vports available for the other SRIO. Lack of a 1137 buffered vport can force a retry for a received 1138 first segment, so, particularly if SP_VPORT=0 1139 (which is not recommended) or the segment size is 1140 small, larger BUF_THR values may improve 1141 performance. */ 1142 uint64_t reserved_14_15 : 2; 1143 uint64_t max_p1 : 6; /**< Sets max number of open vports in port 1 */ 1144 uint64_t reserved_6_7 : 2; 1145 uint64_t max_p0 : 6; /**< Sets max number of open vports in port 0 */ 1146#else 1147 uint64_t max_p0 : 6; 1148 uint64_t reserved_6_7 : 2; 1149 uint64_t max_p1 : 6; 1150 uint64_t reserved_14_15 : 2; 1151 uint64_t buf_thr : 4; 1152 uint64_t reserved_20_30 : 11; 1153 uint64_t sp_vport : 1; 1154 uint64_t max_s0 : 6; 1155 uint64_t reserved_38_39 : 2; 1156 uint64_t max_s1 : 6; 1157 uint64_t reserved_46_47 : 2; 1158 uint64_t max_tot : 6; 1159 uint64_t reserved_54_63 : 10; 1160#endif 1161 } s; 1162 struct cvmx_sriox_imsg_vport_thr_s cn63xx; 1163 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; 1164}; 1165typedef union cvmx_sriox_imsg_vport_thr cvmx_sriox_imsg_vport_thr_t; 1166 1167/** 1168 * cvmx_srio#_int2_enable 1169 * 1170 * SRIO_INT2_ENABLE = SRIO Interrupt 2 Enable (Pass 2) 1171 * 1172 * Allows SRIO to generate additional interrupts when corresponding enable bit is set. 1173 * 1174 * Notes: 1175 * This register enables interrupts in SRIO(0..1)_INT2_REG that can be asserted while the MAC is in reset. 1176 * The register can be accessed/modified regardless of the value of SRIO(0..1)_STATUS_REG.ACCESS. 1177 * 1178 * Clk_Rst: SRIO(0..1)_INT2_ENABLE sclk srst_n 1179 */ 1180union cvmx_sriox_int2_enable 1181{ 1182 uint64_t u64; 1183 struct cvmx_sriox_int2_enable_s 1184 { 1185#if __BYTE_ORDER == __BIG_ENDIAN 1186 uint64_t reserved_1_63 : 63; 1187 uint64_t pko_rst : 1; /**< PKO Reset Error Enable */ 1188#else 1189 uint64_t pko_rst : 1; 1190 uint64_t reserved_1_63 : 63; 1191#endif 1192 } s; 1193 struct cvmx_sriox_int2_enable_s cn63xx; 1194}; 1195typedef union cvmx_sriox_int2_enable cvmx_sriox_int2_enable_t; 1196 1197/** 1198 * cvmx_srio#_int2_reg 1199 * 1200 * SRIO_INT2_REG = SRIO Interrupt 2 Register (Pass 2) 1201 * 1202 * Displays and clears which enabled interrupts have occured 1203 * 1204 * Notes: 1205 * This register provides interrupt status. Unlike SRIO*_INT_REG, SRIO*_INT2_REG can be accessed 1206 * whenever the SRIO is present, regardless of whether the corresponding SRIO is in reset or not. 1207 * INT_SUM shows the status of the interrupts in SRIO(0..1)_INT_REG. Any set bits written to this 1208 * register clear the corresponding interrupt. The register can be accessed/modified regardless of 1209 * the value of SRIO(0..1)_STATUS_REG.ACCESS and probably should be the first register read when an SRIO 1210 * interrupt occurs. 1211 * 1212 * Clk_Rst: SRIO(0..1)_INT2_REG sclk srst_n 1213 */ 1214union cvmx_sriox_int2_reg 1215{ 1216 uint64_t u64; 1217 struct cvmx_sriox_int2_reg_s 1218 { 1219#if __BYTE_ORDER == __BIG_ENDIAN 1220 uint64_t reserved_32_63 : 32; 1221 uint64_t int_sum : 1; /**< Interrupt Set and Enabled in SRIO(0..1)_INT_REG */ 1222 uint64_t reserved_1_30 : 30; 1223 uint64_t pko_rst : 1; /**< PKO Reset Error - Message Received from PKO while 1224 MAC in reset. */ 1225#else 1226 uint64_t pko_rst : 1; 1227 uint64_t reserved_1_30 : 30; 1228 uint64_t int_sum : 1; 1229 uint64_t reserved_32_63 : 32; 1230#endif 1231 } s; 1232 struct cvmx_sriox_int2_reg_s cn63xx; 1233}; 1234typedef union cvmx_sriox_int2_reg cvmx_sriox_int2_reg_t; 1235 1236/** 1237 * cvmx_srio#_int_enable 1238 * 1239 * SRIO_INT_ENABLE = SRIO Interrupt Enable 1240 * 1241 * Allows SRIO to generate interrupts when corresponding enable bit is set. 1242 * 1243 * Notes: 1244 * This register enables interrupts. 1245 * 1246 * Clk_Rst: SRIO(0..1)_INT_ENABLE hclk hrst_n 1247 */ 1248union cvmx_sriox_int_enable 1249{ 1250 uint64_t u64; 1251 struct cvmx_sriox_int_enable_s 1252 { 1253#if __BYTE_ORDER == __BIG_ENDIAN 1254 uint64_t reserved_26_63 : 38; 1255 uint64_t ttl_tout : 1; /**< Outgoing Packet Time to Live Timeout (Pass 2) */ 1256 uint64_t fail : 1; /**< ERB Error Rate reached Fail Count (Pass 2) */ 1257 uint64_t degrade : 1; /**< ERB Error Rate reached Degrade Count (Pass 2) */ 1258 uint64_t mac_buf : 1; /**< SRIO MAC Buffer CRC Error (Pass 2) */ 1259 uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1260 uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded */ 1261 uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1262 uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error */ 1263 uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1264 uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1265 uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1266 uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1267 uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB */ 1268 uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB */ 1269 uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1270 uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1271 uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1272 uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1273 uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1274 uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. */ 1275 uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1276 uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1277 uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. */ 1278 uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. */ 1279 uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. */ 1280 uint64_t txbell : 1; /**< Outgoing Doorbell Complete. */ 1281#else 1282 uint64_t txbell : 1; 1283 uint64_t bell_err : 1; 1284 uint64_t rxbell : 1; 1285 uint64_t maint_op : 1; 1286 uint64_t bar_err : 1; 1287 uint64_t deny_wr : 1; 1288 uint64_t sli_err : 1; 1289 uint64_t wr_done : 1; 1290 uint64_t mce_tx : 1; 1291 uint64_t mce_rx : 1; 1292 uint64_t soft_tx : 1; 1293 uint64_t soft_rx : 1; 1294 uint64_t log_erb : 1; 1295 uint64_t phy_erb : 1; 1296 uint64_t link_dwn : 1; 1297 uint64_t link_up : 1; 1298 uint64_t omsg0 : 1; 1299 uint64_t omsg1 : 1; 1300 uint64_t omsg_err : 1; 1301 uint64_t pko_err : 1; 1302 uint64_t rtry_err : 1; 1303 uint64_t f_error : 1; 1304 uint64_t mac_buf : 1; 1305 uint64_t degrade : 1; 1306 uint64_t fail : 1; 1307 uint64_t ttl_tout : 1; 1308 uint64_t reserved_26_63 : 38; 1309#endif 1310 } s; 1311 struct cvmx_sriox_int_enable_s cn63xx; 1312 struct cvmx_sriox_int_enable_cn63xxp1 1313 { 1314#if __BYTE_ORDER == __BIG_ENDIAN 1315 uint64_t reserved_22_63 : 42; 1316 uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1317 uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded */ 1318 uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1319 uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error */ 1320 uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1321 uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1322 uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1323 uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1324 uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB */ 1325 uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB */ 1326 uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1327 uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1328 uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1329 uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1330 uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1331 uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. */ 1332 uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1333 uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1334 uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. */ 1335 uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. */ 1336 uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. */ 1337 uint64_t txbell : 1; /**< Outgoing Doorbell Complete. */ 1338#else 1339 uint64_t txbell : 1; 1340 uint64_t bell_err : 1; 1341 uint64_t rxbell : 1; 1342 uint64_t maint_op : 1; 1343 uint64_t bar_err : 1; 1344 uint64_t deny_wr : 1; 1345 uint64_t sli_err : 1; 1346 uint64_t wr_done : 1; 1347 uint64_t mce_tx : 1; 1348 uint64_t mce_rx : 1; 1349 uint64_t soft_tx : 1; 1350 uint64_t soft_rx : 1; 1351 uint64_t log_erb : 1; 1352 uint64_t phy_erb : 1; 1353 uint64_t link_dwn : 1; 1354 uint64_t link_up : 1; 1355 uint64_t omsg0 : 1; 1356 uint64_t omsg1 : 1; 1357 uint64_t omsg_err : 1; 1358 uint64_t pko_err : 1; 1359 uint64_t rtry_err : 1; 1360 uint64_t f_error : 1; 1361 uint64_t reserved_22_63 : 42; 1362#endif 1363 } cn63xxp1; 1364}; 1365typedef union cvmx_sriox_int_enable cvmx_sriox_int_enable_t; 1366 1367/** 1368 * cvmx_srio#_int_info0 1369 * 1370 * SRIO_INT_INFO0 = SRIO Interrupt Information 1371 * 1372 * The SRIO Interrupt Information 1373 * 1374 * Notes: 1375 * This register contains the first header word of the illegal s2m transaction associated with the 1376 * SLI_ERR interrupt. The remaining information is located in SRIO(0..1)_INT_INFO1. This register is 1377 * only updated when the SLI_ERR is initially detected. Once the interrupt is cleared then 1378 * additional information can be captured. 1379 * Common Errors Include: 1380 * 1. Load/Stores with Length over 32 1381 * 2. Load/Stores that translate to Maintenance Ops with a length over 8 1382 * 3. Load Ops that translate to Atomic Ops with other than 1, 2 and 4 byte accesses 1383 * 4. Load/Store Ops with a Length 0 1384 * 5. Unexpected Responses 1385 * 1386 * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1387 */ 1388union cvmx_sriox_int_info0 1389{ 1390 uint64_t u64; 1391 struct cvmx_sriox_int_info0_s 1392 { 1393#if __BYTE_ORDER == __BIG_ENDIAN 1394 uint64_t cmd : 4; /**< Command 1395 0 = Load, Outgoing Read Request 1396 4 = Store, Outgoing Write Request 1397 8 = Response, Outgoing Read Response 1398 All Others are reserved and generate errors */ 1399 uint64_t type : 4; /**< Command Type 1400 Load/Store SRIO_S2M_TYPE used 1401 Response (Reserved) */ 1402 uint64_t tag : 8; /**< Internal Transaction Number */ 1403 uint64_t reserved_42_47 : 6; 1404 uint64_t length : 10; /**< Data Length in 64-bit Words (Load/Store Only) */ 1405 uint64_t status : 3; /**< Response Status 1406 0 = Success 1407 1 = Error 1408 All others reserved */ 1409 uint64_t reserved_16_28 : 13; 1410 uint64_t be0 : 8; /**< First 64-bit Word Byte Enables (Load/Store Only) */ 1411 uint64_t be1 : 8; /**< Last 64-bit Word Byte Enables (Load/Store Only) */ 1412#else 1413 uint64_t be1 : 8; 1414 uint64_t be0 : 8; 1415 uint64_t reserved_16_28 : 13; 1416 uint64_t status : 3; 1417 uint64_t length : 10; 1418 uint64_t reserved_42_47 : 6; 1419 uint64_t tag : 8; 1420 uint64_t type : 4; 1421 uint64_t cmd : 4; 1422#endif 1423 } s; 1424 struct cvmx_sriox_int_info0_s cn63xx; 1425 struct cvmx_sriox_int_info0_s cn63xxp1; 1426}; 1427typedef union cvmx_sriox_int_info0 cvmx_sriox_int_info0_t; 1428 1429/** 1430 * cvmx_srio#_int_info1 1431 * 1432 * SRIO_INT_INFO1 = SRIO Interrupt Information 1433 * 1434 * The SRIO Interrupt Information 1435 * 1436 * Notes: 1437 * This register contains the second header word of the illegal s2m transaction associated with the 1438 * SLI_ERR interrupt. The remaining information is located in SRIO(0..1)_INT_INFO0. This register is 1439 * only updated when the SLI_ERR is initially detected. Once the interrupt is cleared then 1440 * additional information can be captured. 1441 * 1442 * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1443 */ 1444union cvmx_sriox_int_info1 1445{ 1446 uint64_t u64; 1447 struct cvmx_sriox_int_info1_s 1448 { 1449#if __BYTE_ORDER == __BIG_ENDIAN 1450 uint64_t info1 : 64; /**< Address (Load/Store) or First 64-bit Word of 1451 Response Data Associated with Interrupt */ 1452#else 1453 uint64_t info1 : 64; 1454#endif 1455 } s; 1456 struct cvmx_sriox_int_info1_s cn63xx; 1457 struct cvmx_sriox_int_info1_s cn63xxp1; 1458}; 1459typedef union cvmx_sriox_int_info1 cvmx_sriox_int_info1_t; 1460 1461/** 1462 * cvmx_srio#_int_info2 1463 * 1464 * SRIO_INT_INFO2 = SRIO Interrupt Information 1465 * 1466 * The SRIO Interrupt Information 1467 * 1468 * Notes: 1469 * This register contains the invalid outbound message descriptor associated with the OMSG_ERR 1470 * interrupt. This register is only updated when the OMSG_ERR is initially detected. Once the 1471 * interrupt is cleared then additional information can be captured. 1472 * 1473 * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1474 */ 1475union cvmx_sriox_int_info2 1476{ 1477 uint64_t u64; 1478 struct cvmx_sriox_int_info2_s 1479 { 1480#if __BYTE_ORDER == __BIG_ENDIAN 1481 uint64_t prio : 2; /**< PRIO field of outbound message descriptor 1482 associated with the OMSG_ERR interrupt */ 1483 uint64_t tt : 1; /**< TT field of outbound message descriptor 1484 associated with the OMSG_ERR interrupt */ 1485 uint64_t sis : 1; /**< SIS field of outbound message descriptor 1486 associated with the OMSG_ERR interrupt */ 1487 uint64_t ssize : 4; /**< SSIZE field of outbound message descriptor 1488 associated with the OMSG_ERR interrupt */ 1489 uint64_t did : 16; /**< DID field of outbound message descriptor 1490 associated with the OMSG_ERR interrupt */ 1491 uint64_t xmbox : 4; /**< XMBOX field of outbound message descriptor 1492 associated with the OMSG_ERR interrupt */ 1493 uint64_t mbox : 2; /**< MBOX field of outbound message descriptor 1494 associated with the OMSG_ERR interrupt */ 1495 uint64_t letter : 2; /**< LETTER field of outbound message descriptor 1496 associated with the OMSG_ERR interrupt */ 1497 uint64_t rsrvd : 30; /**< RSRVD field of outbound message descriptor 1498 associated with the OMSG_ERR interrupt */ 1499 uint64_t lns : 1; /**< LNS field of outbound message descriptor 1500 associated with the OMSG_ERR interrupt */ 1501 uint64_t intr : 1; /**< INT field of outbound message descriptor 1502 associated with the OMSG_ERR interrupt */ 1503#else 1504 uint64_t intr : 1; 1505 uint64_t lns : 1; 1506 uint64_t rsrvd : 30; 1507 uint64_t letter : 2; 1508 uint64_t mbox : 2; 1509 uint64_t xmbox : 4; 1510 uint64_t did : 16; 1511 uint64_t ssize : 4; 1512 uint64_t sis : 1; 1513 uint64_t tt : 1; 1514 uint64_t prio : 2; 1515#endif 1516 } s; 1517 struct cvmx_sriox_int_info2_s cn63xx; 1518 struct cvmx_sriox_int_info2_s cn63xxp1; 1519}; 1520typedef union cvmx_sriox_int_info2 cvmx_sriox_int_info2_t; 1521 1522/** 1523 * cvmx_srio#_int_info3 1524 * 1525 * SRIO_INT_INFO3 = SRIO Interrupt Information 1526 * 1527 * The SRIO Interrupt Information 1528 * 1529 * Notes: 1530 * This register contains the retry response associated with the RTRY_ERR interrupt. This register 1531 * is only updated when the RTRY_ERR is initially detected. Once the interrupt is cleared then 1532 * additional information can be captured. 1533 * 1534 * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1535 */ 1536union cvmx_sriox_int_info3 1537{ 1538 uint64_t u64; 1539 struct cvmx_sriox_int_info3_s 1540 { 1541#if __BYTE_ORDER == __BIG_ENDIAN 1542 uint64_t prio : 2; /**< Priority of received retry response message */ 1543 uint64_t tt : 2; /**< TT of received retry response message */ 1544 uint64_t type : 4; /**< Type of received retry response message 1545 (should be 13) */ 1546 uint64_t other : 48; /**< Other fields of received retry response message 1547 If TT==0 (8-bit ID's) 1548 OTHER<47:40> => destination ID 1549 OTHER<39:32> => source ID 1550 OTHER<31:28> => transaction (should be 1 - msg) 1551 OTHER<27:24> => status (should be 3 - retry) 1552 OTHER<23:22> => letter 1553 OTHER<21:20> => mbox 1554 OTHER<19:16> => msgseg 1555 OTHER<15:0> => unused 1556 If TT==1 (16-bit ID's) 1557 OTHER<47:32> => destination ID 1558 OTHER<31:16> => source ID 1559 OTHER<15:12> => transaction (should be 1 - msg) 1560 OTHER<11:8> => status (should be 3 - retry) 1561 OTHER<7:6> => letter 1562 OTHER<5:4> => mbox 1563 OTHER<3:0> => msgseg */ 1564 uint64_t reserved_0_7 : 8; 1565#else 1566 uint64_t reserved_0_7 : 8; 1567 uint64_t other : 48; 1568 uint64_t type : 4; 1569 uint64_t tt : 2; 1570 uint64_t prio : 2; 1571#endif 1572 } s; 1573 struct cvmx_sriox_int_info3_s cn63xx; 1574 struct cvmx_sriox_int_info3_s cn63xxp1; 1575}; 1576typedef union cvmx_sriox_int_info3 cvmx_sriox_int_info3_t; 1577 1578/** 1579 * cvmx_srio#_int_reg 1580 * 1581 * SRIO_INT_REG = SRIO Interrupt Register 1582 * 1583 * Displays and clears which enabled interrupts have occured 1584 * 1585 * Notes: 1586 * This register provides interrupt status. Like most SRIO CSRs, this register can only 1587 * be read/written when the corresponding SRIO is both present and not in reset. (SRIO*_INT2_REG 1588 * can be accessed when SRIO is in reset.) Any set bits written to this register clear the 1589 * corresponding interrupt. The RXBELL interrupt is cleared by reading all the entries in the 1590 * incoming Doorbell FIFO. The LOG_ERB interrupt must be cleared before writing zeroes 1591 * to clear the bits in the SRIOMAINT*_ERB_LT_ERR_DET register. Otherwise a new interrupt may be 1592 * lost. The PHY_ERB interrupt must be cleared before writing a zero to 1593 * SRIOMAINT*_ERB_ATTR_CAPT[VALID]. Otherwise, a new interrupt may be lost. OMSG_ERR is set when an 1594 * invalid outbound message descriptor is received. The descriptor is deemed to be invalid if the 1595 * SSIZE field is set to a reserved value, the SSIZE field combined with the packet length would 1596 * result in more than 16 message segments, or the packet only contains a descriptor (no data). 1597 * 1598 * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1599 */ 1600union cvmx_sriox_int_reg 1601{ 1602 uint64_t u64; 1603 struct cvmx_sriox_int_reg_s 1604 { 1605#if __BYTE_ORDER == __BIG_ENDIAN 1606 uint64_t reserved_32_63 : 32; 1607 uint64_t int2_sum : 1; /**< Interrupt Set and Enabled in SRIO(0..1)_INT2_REG 1608 (Pass 2) */ 1609 uint64_t reserved_26_30 : 5; 1610 uint64_t ttl_tout : 1; /**< Outgoing Packet Time to Live Timeout (Pass 2) 1611 See SRIOMAINT(0..1)_DROP_PACKET */ 1612 uint64_t fail : 1; /**< ERB Error Rate reached Fail Count (Pass 2) 1613 See SRIOMAINT(0..1)_ERB_ERR_RATE */ 1614 uint64_t degrad : 1; /**< ERB Error Rate reached Degrade Count (Pass 2) 1615 See SRIOMAINT(0..1)_ERB_ERR_RATE */ 1616 uint64_t mac_buf : 1; /**< SRIO MAC Buffer CRC Error (Pass 2) 1617 See SRIO(0..1)_MAC_BUFFERS */ 1618 uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1619 uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded 1620 See SRIO(0..1)_INT_INFO3 1621 When one or more of the segments in an outgoing 1622 message have a RTRY_ERR, SRIO will not set 1623 OMSG* after the message "transfer". */ 1624 uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1625 uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error 1626 See SRIO(0..1)_INT_INFO2 */ 1627 uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1628 uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1629 uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1630 uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1631 uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB 1632 See SRIOMAINT*_ERB_ATTR_CAPT */ 1633 uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB 1634 See SRIOMAINT(0..1)_ERB_LT_ERR_DET */ 1635 uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1636 uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1637 uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1638 uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1639 uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1640 uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. 1641 See SRIO(0..1)_INT_INFO[1:0] */ 1642 uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1643 uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1644 uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. 1645 See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */ 1646 uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. 1647 Read SRIO(0..1)_RX_BELL to empty FIFO */ 1648 uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. 1649 See SRIO(0..1)_TX_BELL_INFO */ 1650 uint64_t txbell : 1; /**< Outgoing Doorbell Complete. 1651 TXBELL will not be asserted if a Timeout, Retry or 1652 Error occurs. */ 1653#else 1654 uint64_t txbell : 1; 1655 uint64_t bell_err : 1; 1656 uint64_t rxbell : 1; 1657 uint64_t maint_op : 1; 1658 uint64_t bar_err : 1; 1659 uint64_t deny_wr : 1; 1660 uint64_t sli_err : 1; 1661 uint64_t wr_done : 1; 1662 uint64_t mce_tx : 1; 1663 uint64_t mce_rx : 1; 1664 uint64_t soft_tx : 1; 1665 uint64_t soft_rx : 1; 1666 uint64_t log_erb : 1; 1667 uint64_t phy_erb : 1; 1668 uint64_t link_dwn : 1; 1669 uint64_t link_up : 1; 1670 uint64_t omsg0 : 1; 1671 uint64_t omsg1 : 1; 1672 uint64_t omsg_err : 1; 1673 uint64_t pko_err : 1; 1674 uint64_t rtry_err : 1; 1675 uint64_t f_error : 1; 1676 uint64_t mac_buf : 1; 1677 uint64_t degrad : 1; 1678 uint64_t fail : 1; 1679 uint64_t ttl_tout : 1; 1680 uint64_t reserved_26_30 : 5; 1681 uint64_t int2_sum : 1; 1682 uint64_t reserved_32_63 : 32; 1683#endif 1684 } s; 1685 struct cvmx_sriox_int_reg_s cn63xx; 1686 struct cvmx_sriox_int_reg_cn63xxp1 1687 { 1688#if __BYTE_ORDER == __BIG_ENDIAN 1689 uint64_t reserved_22_63 : 42; 1690 uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1691 uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded 1692 See SRIO(0..1)_INT_INFO3 1693 When one or more of the segments in an outgoing 1694 message have a RTRY_ERR, SRIO will not set 1695 OMSG* after the message "transfer". */ 1696 uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1697 uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error 1698 See SRIO(0..1)_INT_INFO2 */ 1699 uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1700 uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1701 uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1702 uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1703 uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB 1704 See SRIOMAINT*_ERB_ATTR_CAPT */ 1705 uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB 1706 See SRIOMAINT(0..1)_ERB_LT_ERR_DET */ 1707 uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1708 uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1709 uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1710 uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1711 uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1712 uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. 1713 See SRIO(0..1)_INT_INFO[1:0] */ 1714 uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1715 uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1716 uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. 1717 See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */ 1718 uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. 1719 Read SRIO(0..1)_RX_BELL to empty FIFO */ 1720 uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. 1721 See SRIO(0..1)_TX_BELL_INFO */ 1722 uint64_t txbell : 1; /**< Outgoing Doorbell Complete. 1723 TXBELL will not be asserted if a Timeout, Retry or 1724 Error occurs. */ 1725#else 1726 uint64_t txbell : 1; 1727 uint64_t bell_err : 1; 1728 uint64_t rxbell : 1; 1729 uint64_t maint_op : 1; 1730 uint64_t bar_err : 1; 1731 uint64_t deny_wr : 1; 1732 uint64_t sli_err : 1; 1733 uint64_t wr_done : 1; 1734 uint64_t mce_tx : 1; 1735 uint64_t mce_rx : 1; 1736 uint64_t soft_tx : 1; 1737 uint64_t soft_rx : 1; 1738 uint64_t log_erb : 1; 1739 uint64_t phy_erb : 1; 1740 uint64_t link_dwn : 1; 1741 uint64_t link_up : 1; 1742 uint64_t omsg0 : 1; 1743 uint64_t omsg1 : 1; 1744 uint64_t omsg_err : 1; 1745 uint64_t pko_err : 1; 1746 uint64_t rtry_err : 1; 1747 uint64_t f_error : 1; 1748 uint64_t reserved_22_63 : 42; 1749#endif 1750 } cn63xxp1; 1751}; 1752typedef union cvmx_sriox_int_reg cvmx_sriox_int_reg_t; 1753 1754/** 1755 * cvmx_srio#_ip_feature 1756 * 1757 * SRIO_IP_FEATURE = SRIO IP Feature Select 1758 * 1759 * Debug Register used to enable IP Core Features 1760 * 1761 * Notes: 1762 * This register is used to override powerup values used by the SRIOMAINT Registers and QLM 1763 * configuration. The register is only reset during COLD boot. It should only be modified only 1764 * while SRIO(0..1)_STATUS_REG.ACCESS is zero. 1765 * 1766 * Clk_Rst: SRIO(0..1)_IP_FEATURE sclk srst_cold_n 1767 */ 1768union cvmx_sriox_ip_feature 1769{ 1770 uint64_t u64; 1771 struct cvmx_sriox_ip_feature_s 1772 { 1773#if __BYTE_ORDER == __BIG_ENDIAN 1774 uint64_t ops : 32; /**< Reset Value for the OPs fields in both the 1775 SRIOMAINT(0..1)_SRC_OPS and SRIOMAINT(0..1)_DST_OPS 1776 registers. */ 1777 uint64_t reserved_14_31 : 18; 1778 uint64_t a66 : 1; /**< 66-bit Address Support. Value for bit 2 of the 1779 EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */ 1780 uint64_t a50 : 1; /**< 50-bit Address Support. Value for bit 1 of the 1781 EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */ 1782 uint64_t reserved_11_11 : 1; 1783 uint64_t tx_flow : 1; /**< Reset Value for the TX_FLOW field in the 1784 SRIOMAINT(0..1)_IR_BUFFER_CONFIG register. */ 1785 uint64_t pt_width : 2; /**< Value for the PT_WIDTH field in the 1786 SRIOMAINT(0..1)_PORT_0_CTL register. */ 1787 uint64_t tx_pol : 4; /**< TX Serdes Polarity Lanes 3-0 1788 0 = Normal Operation 1789 1 = Invert, Swap +/- Tx SERDES Pins */ 1790 uint64_t rx_pol : 4; /**< RX Serdes Polarity Lanes 3-0 1791 0 = Normal Operation 1792 1 = Invert, Swap +/- Rx SERDES Pins */ 1793#else 1794 uint64_t rx_pol : 4; 1795 uint64_t tx_pol : 4; 1796 uint64_t pt_width : 2; 1797 uint64_t tx_flow : 1; 1798 uint64_t reserved_11_11 : 1; 1799 uint64_t a50 : 1; 1800 uint64_t a66 : 1; 1801 uint64_t reserved_14_31 : 18; 1802 uint64_t ops : 32; 1803#endif 1804 } s; 1805 struct cvmx_sriox_ip_feature_s cn63xx; 1806 struct cvmx_sriox_ip_feature_s cn63xxp1; 1807}; 1808typedef union cvmx_sriox_ip_feature cvmx_sriox_ip_feature_t; 1809 1810/** 1811 * cvmx_srio#_mac_buffers 1812 * 1813 * SRIO_MAC_BUFFERS = SRIO MAC Buffer Control (Pass 2) 1814 * 1815 * Reports errors and controls buffer usage on the main MAC buffers 1816 * 1817 * Notes: 1818 * Register displays errors status for each of the eight RX and TX buffers and controls use of the 1819 * buffer in future operations. It also displays the number of RX and TX buffers currently used by 1820 * the MAC. 1821 * 1822 * Clk_Rst: SRIO(0..1)_MAC_BUFFERS hclk hrst_n 1823 */ 1824union cvmx_sriox_mac_buffers 1825{ 1826 uint64_t u64; 1827 struct cvmx_sriox_mac_buffers_s 1828 { 1829#if __BYTE_ORDER == __BIG_ENDIAN 1830 uint64_t reserved_56_63 : 8; 1831 uint64_t tx_enb : 8; /**< TX Buffer Enable. Each bit enables a specific TX 1832 Buffer. At least 2 of these bits must be set for 1833 proper operation. These bits must be cleared to 1834 and then set again to reuese the buffer after an 1835 error occurs. */ 1836 uint64_t reserved_44_47 : 4; 1837 uint64_t tx_inuse : 4; /**< Number of TX buffers containing packets waiting 1838 to be transmitted or to be acknowledged. */ 1839 uint64_t tx_stat : 8; /**< Errors detected in main SRIO Transmit Buffers. 1840 CRC error detected in buffer sets bit of buffer \# 1841 until the corresponding TX_ENB is disabled. Each 1842 bit set causes the SRIO(0..1)_INT_REG.MAC_BUF 1843 interrupt. */ 1844 uint64_t reserved_24_31 : 8; 1845 uint64_t rx_enb : 8; /**< RX Buffer Enable. Each bit enables a specific RX 1846 Buffer. At least 2 of these bits must be set for 1847 proper operation. These bits must be cleared to 1848 and then set again to reuese the buffer after an 1849 error occurs. */ 1850 uint64_t reserved_12_15 : 4; 1851 uint64_t rx_inuse : 4; /**< Number of RX buffers containing valid packets 1852 waiting to be processed by the logical layer. */ 1853 uint64_t rx_stat : 8; /**< Errors detected in main SRIO Receive Buffers. CRC 1854 error detected in buffer sets bit of buffer \# 1855 until the corresponding RX_ENB is disabled. Each 1856 bit set causes the SRIO(0..1)_INT_REG.MAC_BUF 1857 interrupt. */ 1858#else 1859 uint64_t rx_stat : 8; 1860 uint64_t rx_inuse : 4; 1861 uint64_t reserved_12_15 : 4; 1862 uint64_t rx_enb : 8; 1863 uint64_t reserved_24_31 : 8; 1864 uint64_t tx_stat : 8; 1865 uint64_t tx_inuse : 4; 1866 uint64_t reserved_44_47 : 4; 1867 uint64_t tx_enb : 8; 1868 uint64_t reserved_56_63 : 8; 1869#endif 1870 } s; 1871 struct cvmx_sriox_mac_buffers_s cn63xx; 1872}; 1873typedef union cvmx_sriox_mac_buffers cvmx_sriox_mac_buffers_t; 1874 1875/** 1876 * cvmx_srio#_maint_op 1877 * 1878 * SRIO_MAINT_OP = SRIO Maintenance Operation 1879 * 1880 * Allows access to maintenance registers. 1881 * 1882 * Notes: 1883 * This register allows write access to the local SRIOMAINT registers. A write to this register 1884 * posts a read or write operation selected by the OP bit to the local SRIOMAINT register selected by 1885 * ADDR. This write also sets the PENDING bit. The PENDING bit is cleared by hardware when the 1886 * operation is complete. The MAINT_OP Interrupt is also set as the PENDING bit is cleared. While 1887 * this bit is set, additional writes to this register stall the RSL. The FAIL bit is set with the 1888 * clearing of the PENDING bit when an illegal address is selected. WR_DATA is used only during write 1889 * operations. Only 32-bit Maintenance Operations are supported. 1890 * 1891 * Clk_Rst: SRIO(0..1)_MAINT_OP hclk hrst_n 1892 */ 1893union cvmx_sriox_maint_op 1894{ 1895 uint64_t u64; 1896 struct cvmx_sriox_maint_op_s 1897 { 1898#if __BYTE_ORDER == __BIG_ENDIAN 1899 uint64_t wr_data : 32; /**< Write Data[31:0]. */ 1900 uint64_t reserved_27_31 : 5; 1901 uint64_t fail : 1; /**< Maintenance Operation Address Error */ 1902 uint64_t pending : 1; /**< Maintenance Operation Pending */ 1903 uint64_t op : 1; /**< Operation. 0=Read, 1=Write */ 1904 uint64_t addr : 24; /**< Address. Addr[1:0] are ignored. */ 1905#else 1906 uint64_t addr : 24; 1907 uint64_t op : 1; 1908 uint64_t pending : 1; 1909 uint64_t fail : 1; 1910 uint64_t reserved_27_31 : 5; 1911 uint64_t wr_data : 32; 1912#endif 1913 } s; 1914 struct cvmx_sriox_maint_op_s cn63xx; 1915 struct cvmx_sriox_maint_op_s cn63xxp1; 1916}; 1917typedef union cvmx_sriox_maint_op cvmx_sriox_maint_op_t; 1918 1919/** 1920 * cvmx_srio#_maint_rd_data 1921 * 1922 * SRIO_MAINT_RD_DATA = SRIO Maintenance Read Data 1923 * 1924 * Allows read access of maintenance registers. 1925 * 1926 * Notes: 1927 * This register allows read access of the local SRIOMAINT registers. A write to the SRIO(0..1)_MAINT_OP 1928 * register with the OP bit set to zero initiates a read request and clears the VALID bit. The 1929 * resulting read is returned here and the VALID bit is set. Access to the register will not stall 1930 * the RSL but the VALID bit should be read. 1931 * 1932 * Clk_Rst: SRIO(0..1)_MAINT_RD_DATA hclk hrst_n 1933 */ 1934union cvmx_sriox_maint_rd_data 1935{ 1936 uint64_t u64; 1937 struct cvmx_sriox_maint_rd_data_s 1938 { 1939#if __BYTE_ORDER == __BIG_ENDIAN 1940 uint64_t reserved_33_63 : 31; 1941 uint64_t valid : 1; /**< Read Data Valid. */ 1942 uint64_t rd_data : 32; /**< Read Data[31:0]. */ 1943#else 1944 uint64_t rd_data : 32; 1945 uint64_t valid : 1; 1946 uint64_t reserved_33_63 : 31; 1947#endif 1948 } s; 1949 struct cvmx_sriox_maint_rd_data_s cn63xx; 1950 struct cvmx_sriox_maint_rd_data_s cn63xxp1; 1951}; 1952typedef union cvmx_sriox_maint_rd_data cvmx_sriox_maint_rd_data_t; 1953 1954/** 1955 * cvmx_srio#_mce_tx_ctl 1956 * 1957 * SRIO_MCE_TX_CTL = SRIO Multicast Event Transmit Control 1958 * 1959 * Multicast Event TX Control 1960 * 1961 * Notes: 1962 * Writes to this register cause the SRIO device to generate a Multicast Event. Setting the MCE bit 1963 * requests the logic to generate the Multicast Event Symbol. Reading the MCS bit shows the status 1964 * of the transmit event. The hardware will clear the bit when the event has been transmitted and 1965 * set the MCS_TX Interrupt. 1966 * 1967 * Clk_Rst: SRIO(0..1)_MCE_TX_CTL hclk hrst_n 1968 */ 1969union cvmx_sriox_mce_tx_ctl 1970{ 1971 uint64_t u64; 1972 struct cvmx_sriox_mce_tx_ctl_s 1973 { 1974#if __BYTE_ORDER == __BIG_ENDIAN 1975 uint64_t reserved_1_63 : 63; 1976 uint64_t mce : 1; /**< Multicast Event Transmit. */ 1977#else 1978 uint64_t mce : 1; 1979 uint64_t reserved_1_63 : 63; 1980#endif 1981 } s; 1982 struct cvmx_sriox_mce_tx_ctl_s cn63xx; 1983 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; 1984}; 1985typedef union cvmx_sriox_mce_tx_ctl cvmx_sriox_mce_tx_ctl_t; 1986 1987/** 1988 * cvmx_srio#_mem_op_ctrl 1989 * 1990 * SRIO_MEM_OP_CTRL = SRIO Memory Operation Control 1991 * 1992 * The SRIO Memory Operation Control 1993 * 1994 * Notes: 1995 * This register is used to control memory operations. Bits are provided to override the priority of 1996 * the outgoing responses to memory operations. The memory operations with responses include NREAD, 1997 * NWRITE_R, ATOMIC_INC, ATOMIC_DEC, ATOMIC_SET and ATOMIC_CLR. 1998 * 1999 * Clk_Rst: SRIO(0..1)_MEM_OP_CTRL hclk hrst_n 2000 */ 2001union cvmx_sriox_mem_op_ctrl 2002{ 2003 uint64_t u64; 2004 struct cvmx_sriox_mem_op_ctrl_s 2005 { 2006#if __BYTE_ORDER == __BIG_ENDIAN 2007 uint64_t reserved_10_63 : 54; 2008 uint64_t rr_ro : 1; /**< Read Response Relaxed Ordering. Controls ordering 2009 rules for incoming memory operations 2010 0 = Normal Ordering 2011 1 = Relaxed Ordering */ 2012 uint64_t w_ro : 1; /**< Write Relaxed Ordering. Controls ordering rules 2013 for incoming memory operations 2014 0 = Normal Ordering 2015 1 = Relaxed Ordering */ 2016 uint64_t reserved_6_7 : 2; 2017 uint64_t rp1_sid : 1; /**< Sets response priority for incomimg memory ops 2018 of priority 1 on the secondary ID (0=2, 1=3) */ 2019 uint64_t rp0_sid : 2; /**< Sets response priority for incomimg memory ops 2020 of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 2021 uint64_t rp1_pid : 1; /**< Sets response priority for incomimg memory ops 2022 of priority 1 on the primary ID (0=2, 1=3) */ 2023 uint64_t rp0_pid : 2; /**< Sets response priority for incomimg memory ops 2024 of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 2025#else 2026 uint64_t rp0_pid : 2; 2027 uint64_t rp1_pid : 1; 2028 uint64_t rp0_sid : 2; 2029 uint64_t rp1_sid : 1; 2030 uint64_t reserved_6_7 : 2; 2031 uint64_t w_ro : 1; 2032 uint64_t rr_ro : 1; 2033 uint64_t reserved_10_63 : 54; 2034#endif 2035 } s; 2036 struct cvmx_sriox_mem_op_ctrl_s cn63xx; 2037 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; 2038}; 2039typedef union cvmx_sriox_mem_op_ctrl cvmx_sriox_mem_op_ctrl_t; 2040 2041/** 2042 * cvmx_srio#_omsg_ctrl# 2043 * 2044 * SRIO_OMSG_CTRLX = SRIO Outbound Message Control 2045 * 2046 * The SRIO Controller X Outbound Message Control Register 2047 * 2048 * Notes: 2049 * 1) If IDM_TT, IDM_SIS, and IDM_DID are all clear, then the "ID match" will always be false. 2050 * 2) LTTR_SP and LTTR_MP must be non-zero at all times, otherwise the message output queue can 2051 * get blocked 2052 * 3) TESTMODE has no function on controller 1 2053 * 4) When IDM_TT=0, it is possible for an ID match to match an 8-bit DID with a 16-bit DID - SRIO 2054 * zero-extends all 8-bit DID's, and the DID comparisons are always 16-bits. 2055 * 2056 * Clk_Rst: SRIO(0..1)_OMSG_CTRL[0:1] hclk hrst_n 2057 */ 2058union cvmx_sriox_omsg_ctrlx 2059{ 2060 uint64_t u64; 2061 struct cvmx_sriox_omsg_ctrlx_s 2062 { 2063#if __BYTE_ORDER == __BIG_ENDIAN 2064 uint64_t testmode : 1; /**< Controller X test mode (keep as RSVD in HRM) */ 2065 uint64_t reserved_37_62 : 26; 2066 uint64_t silo_max : 5; /**< Sets max number outgoing segments for controller X 2067 (Pass 2) */ 2068 uint64_t rtry_thr : 16; /**< Controller X Retry threshold */ 2069 uint64_t rtry_en : 1; /**< Controller X Retry threshold enable */ 2070 uint64_t reserved_11_14 : 4; 2071 uint64_t idm_tt : 1; /**< Controller X ID match includes TT ID */ 2072 uint64_t idm_sis : 1; /**< Controller X ID match includes SIS */ 2073 uint64_t idm_did : 1; /**< Controller X ID match includes DID */ 2074 uint64_t lttr_sp : 4; /**< Controller X SP allowable letters in dynamic 2075 letter select mode (LNS) */ 2076 uint64_t lttr_mp : 4; /**< Controller X MP allowable letters in dynamic 2077 letter select mode (LNS) */ 2078#else 2079 uint64_t lttr_mp : 4; 2080 uint64_t lttr_sp : 4; 2081 uint64_t idm_did : 1; 2082 uint64_t idm_sis : 1; 2083 uint64_t idm_tt : 1; 2084 uint64_t reserved_11_14 : 4; 2085 uint64_t rtry_en : 1; 2086 uint64_t rtry_thr : 16; 2087 uint64_t silo_max : 5; 2088 uint64_t reserved_37_62 : 26; 2089 uint64_t testmode : 1; 2090#endif 2091 } s; 2092 struct cvmx_sriox_omsg_ctrlx_s cn63xx; 2093 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 2094 { 2095#if __BYTE_ORDER == __BIG_ENDIAN 2096 uint64_t testmode : 1; /**< Controller X test mode (keep as RSVD in HRM) */ 2097 uint64_t reserved_32_62 : 31; 2098 uint64_t rtry_thr : 16; /**< Controller X Retry threshold */ 2099 uint64_t rtry_en : 1; /**< Controller X Retry threshold enable */ 2100 uint64_t reserved_11_14 : 4; 2101 uint64_t idm_tt : 1; /**< Controller X ID match includes TT ID */ 2102 uint64_t idm_sis : 1; /**< Controller X ID match includes SIS */ 2103 uint64_t idm_did : 1; /**< Controller X ID match includes DID */ 2104 uint64_t lttr_sp : 4; /**< Controller X SP allowable letters in dynamic 2105 letter select mode (LNS) */ 2106 uint64_t lttr_mp : 4; /**< Controller X MP allowable letters in dynamic 2107 letter select mode (LNS) */ 2108#else 2109 uint64_t lttr_mp : 4; 2110 uint64_t lttr_sp : 4; 2111 uint64_t idm_did : 1; 2112 uint64_t idm_sis : 1; 2113 uint64_t idm_tt : 1; 2114 uint64_t reserved_11_14 : 4; 2115 uint64_t rtry_en : 1; 2116 uint64_t rtry_thr : 16; 2117 uint64_t reserved_32_62 : 31; 2118 uint64_t testmode : 1; 2119#endif 2120 } cn63xxp1; 2121}; 2122typedef union cvmx_sriox_omsg_ctrlx cvmx_sriox_omsg_ctrlx_t; 2123 2124/** 2125 * cvmx_srio#_omsg_done_counts# 2126 * 2127 * SRIO_OMSG_DONE_COUNTSX = SRIO Outbound Message Complete Counts (Pass 2) 2128 * 2129 * The SRIO Controller X Outbound Message Complete Counts Register 2130 * 2131 * Notes: 2132 * This register shows the number of successful and unsuccessful Outgoing Messages issued through 2133 * this controller. The only messages considered are the ones with the INT field set in the PKO 2134 * message header. This register is typically not written while Outbound SRIO Memory traffic is 2135 * enabled. The sum of the GOOD and BAD counts should equal the number of messages sent unless 2136 * the MAC has been reset. 2137 * 2138 * Clk_Rst: SRIO(0..1)_OMSG_DONE_COUNTS[0:1] hclk hrst_n 2139 */ 2140union cvmx_sriox_omsg_done_countsx 2141{ 2142 uint64_t u64; 2143 struct cvmx_sriox_omsg_done_countsx_s 2144 { 2145#if __BYTE_ORDER == __BIG_ENDIAN 2146 uint64_t reserved_32_63 : 32; 2147 uint64_t bad : 16; /**< Number of Outbound Messages requesting an INT that 2148 did not increment GOOD. (One or more segment of the 2149 message either timed out, reached the retry limit, 2150 or received an ERROR response.) */ 2151 uint64_t good : 16; /**< Number of Outbound Messages requesting an INT that 2152 received a DONE response for every segment. */ 2153#else 2154 uint64_t good : 16; 2155 uint64_t bad : 16; 2156 uint64_t reserved_32_63 : 32; 2157#endif 2158 } s; 2159 struct cvmx_sriox_omsg_done_countsx_s cn63xx; 2160}; 2161typedef union cvmx_sriox_omsg_done_countsx cvmx_sriox_omsg_done_countsx_t; 2162 2163/** 2164 * cvmx_srio#_omsg_fmp_mr# 2165 * 2166 * SRIO_OMSG_FMP_MRX = SRIO Outbound Message FIRSTMP Message Restriction 2167 * 2168 * The SRIO Controller X Outbound Message FIRSTMP Message Restriction Register 2169 * 2170 * Notes: 2171 * This CSR controls when FMP candidate message segments (from the two different controllers) can enter 2172 * the message segment silo to be sent out. A segment remains in the silo until after is has 2173 * been transmitted and either acknowledged or errored out. 2174 * 2175 * Candidates and silo entries are one of 4 types: 2176 * SP - a single-segment message 2177 * FMP - the first segment of a multi-segment message 2178 * NMP - the other segments in a multi-segment message 2179 * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2180 * a multi-segment message into the silo and can match against segments generated by 2181 * the other controller 2182 * 2183 * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2184 * By default (i.e. zeroes in this CSR), the FMP candidate matches against all entries in the 2185 * silo. When fields in this CSR are set, FMP candidate segments will match fewer silo entries and 2186 * can enter the silo more freely, probably providing better performance. 2187 * 2188 * Clk_Rst: SRIO(0..1)_OMSG_FMP_MR[0:1] hclk hrst_n 2189 */ 2190union cvmx_sriox_omsg_fmp_mrx 2191{ 2192 uint64_t u64; 2193 struct cvmx_sriox_omsg_fmp_mrx_s 2194 { 2195#if __BYTE_ORDER == __BIG_ENDIAN 2196 uint64_t reserved_15_63 : 49; 2197 uint64_t ctlr_sp : 1; /**< Controller X FIRSTMP enable controller SP 2198 When set, the FMP candidate message segment can 2199 only match siloed SP segments that were created 2200 by the same controller. When clear, this FMP-SP 2201 match can also occur when the segments were 2202 created by the other controller. 2203 Not used by the hardware when ALL_SP is set. */ 2204 uint64_t ctlr_fmp : 1; /**< Controller X FIRSTMP enable controller FIRSTMP 2205 When set, the FMP candidate message segment can 2206 only match siloed FMP segments that were created 2207 by the same controller. When clear, this FMP-FMP 2208 match can also occur when the segments were 2209 created by the other controller. 2210 Not used by the hardware when ALL_FMP is set. */ 2211 uint64_t ctlr_nmp : 1; /**< Controller X FIRSTMP enable controller NFIRSTMP 2212 When set, the FMP candidate message segment can 2213 only match siloed NMP segments that were created 2214 by the same controller. When clear, this FMP-NMP 2215 match can also occur when the segments were 2216 created by the other controller. 2217 Not used by the hardware when ALL_NMP is set. */ 2218 uint64_t id_sp : 1; /**< Controller X FIRSTMP enable ID SP 2219 When set, the FMP candidate message segment can 2220 only match siloed SP segments that "ID match" the 2221 candidate. When clear, this FMP-SP match can occur 2222 with any ID values. 2223 Not used by the hardware when ALL_SP is set. */ 2224 uint64_t id_fmp : 1; /**< Controller X FIRSTMP enable ID FIRSTMP 2225 When set, the FMP candidate message segment can 2226 only match siloed FMP segments that "ID match" the 2227 candidate. When clear, this FMP-FMP match can occur 2228 with any ID values. 2229 Not used by the hardware when ALL_FMP is set. */ 2230 uint64_t id_nmp : 1; /**< Controller X FIRSTMP enable ID NFIRSTMP 2231 When set, the FMP candidate message segment can 2232 only match siloed NMP segments that "ID match" the 2233 candidate. When clear, this FMP-NMP match can occur 2234 with any ID values. 2235 Not used by the hardware when ALL_NMP is set. */ 2236 uint64_t id_psd : 1; /**< Controller X FIRSTMP enable ID PSEUDO 2237 When set, the FMP candidate message segment can 2238 only match the silo pseudo (for the other 2239 controller) when it is an "ID match". When clear, 2240 this FMP-PSD match can occur with any ID values. 2241 Not used by the hardware when ALL_PSD is set. */ 2242 uint64_t mbox_sp : 1; /**< Controller X FIRSTMP enable MBOX SP 2243 When set, the FMP candidate message segment can 2244 only match siloed SP segments with the same 2-bit 2245 mbox value as the candidate. When clear, this 2246 FMP-SP match can occur with any mbox values. 2247 Not used by the hardware when ALL_SP is set. */ 2248 uint64_t mbox_fmp : 1; /**< Controller X FIRSTMP enable MBOX FIRSTMP 2249 When set, the FMP candidate message segment can 2250 only match siloed FMP segments with the same 2-bit 2251 mbox value as the candidate. When clear, this 2252 FMP-FMP match can occur with any mbox values. 2253 Not used by the hardware when ALL_FMP is set. */ 2254 uint64_t mbox_nmp : 1; /**< Controller X FIRSTMP enable MBOX NFIRSTMP 2255 When set, the FMP candidate message segment can 2256 only match siloed NMP segments with the same 2-bit 2257 mbox value as the candidate. When clear, this 2258 FMP-NMP match can occur with any mbox values. 2259 Not used by the hardware when ALL_NMP is set. */ 2260 uint64_t mbox_psd : 1; /**< Controller X FIRSTMP enable MBOX PSEUDO 2261 When set, the FMP candidate message segment can 2262 only match the silo pseudo (for the other 2263 controller) if the pseudo has the same 2-bit mbox 2264 value as the candidate. When clear, this FMP-PSD 2265 match can occur with any mbox values. 2266 Not used by the hardware when ALL_PSD is set. */ 2267 uint64_t all_sp : 1; /**< Controller X FIRSTMP enable all SP 2268 When set, no FMP candidate message segments ever 2269 match siloed SP segments and ID_SP 2270 and MBOX_SP are not used. When clear, FMP-SP 2271 matches can occur. */ 2272 uint64_t all_fmp : 1; /**< Controller X FIRSTMP enable all FIRSTMP 2273 When set, no FMP candidate message segments ever 2274 match siloed FMP segments and ID_FMP and MBOX_FMP 2275 are not used. When clear, FMP-FMP matches can 2276 occur. */ 2277 uint64_t all_nmp : 1; /**< Controller X FIRSTMP enable all NFIRSTMP 2278 When set, no FMP candidate message segments ever 2279 match siloed NMP segments and ID_NMP and MBOX_NMP 2280 are not used. When clear, FMP-NMP matches can 2281 occur. */ 2282 uint64_t all_psd : 1; /**< Controller X FIRSTMP enable all PSEUDO 2283 When set, no FMP candidate message segments ever 2284 match the silo pseudo (for the other controller) 2285 and ID_PSD and MBOX_PSD are not used. When clear, 2286 FMP-PSD matches can occur. */ 2287#else 2288 uint64_t all_psd : 1; 2289 uint64_t all_nmp : 1; 2290 uint64_t all_fmp : 1; 2291 uint64_t all_sp : 1; 2292 uint64_t mbox_psd : 1; 2293 uint64_t mbox_nmp : 1; 2294 uint64_t mbox_fmp : 1; 2295 uint64_t mbox_sp : 1; 2296 uint64_t id_psd : 1; 2297 uint64_t id_nmp : 1; 2298 uint64_t id_fmp : 1; 2299 uint64_t id_sp : 1; 2300 uint64_t ctlr_nmp : 1; 2301 uint64_t ctlr_fmp : 1; 2302 uint64_t ctlr_sp : 1; 2303 uint64_t reserved_15_63 : 49; 2304#endif 2305 } s; 2306 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; 2307 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; 2308}; 2309typedef union cvmx_sriox_omsg_fmp_mrx cvmx_sriox_omsg_fmp_mrx_t; 2310 2311/** 2312 * cvmx_srio#_omsg_nmp_mr# 2313 * 2314 * SRIO_OMSG_NMP_MRX = SRIO Outbound Message NFIRSTMP Message Restriction 2315 * 2316 * The SRIO Controller X Outbound Message NFIRSTMP Message Restriction Register 2317 * 2318 * Notes: 2319 * This CSR controls when NMP candidate message segments (from the two different controllers) can enter 2320 * the message segment silo to be sent out. A segment remains in the silo until after is has 2321 * been transmitted and either acknowledged or errored out. 2322 * 2323 * Candidates and silo entries are one of 4 types: 2324 * SP - a single-segment message 2325 * FMP - the first segment of a multi-segment message 2326 * NMP - the other segments in a multi-segment message 2327 * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2328 * a multi-segment message into the silo and can match against segments generated by 2329 * the other controller 2330 * 2331 * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2332 * By default (i.e. zeroes in this CSR), the NMP candidate matches against all entries in the 2333 * silo. When fields in this CSR are set, NMP candidate segments will match fewer silo entries and 2334 * can enter the silo more freely, probably providing better performance. 2335 * 2336 * Clk_Rst: SRIO(0..1)_OMSG_NMP_MR[0:1] hclk hrst_n 2337 */ 2338union cvmx_sriox_omsg_nmp_mrx 2339{ 2340 uint64_t u64; 2341 struct cvmx_sriox_omsg_nmp_mrx_s 2342 { 2343#if __BYTE_ORDER == __BIG_ENDIAN 2344 uint64_t reserved_15_63 : 49; 2345 uint64_t ctlr_sp : 1; /**< Controller X NFIRSTMP enable controller SP 2346 When set, the NMP candidate message segment can 2347 only match siloed SP segments that were created 2348 by the same controller. When clear, this NMP-SP 2349 match can also occur when the segments were 2350 created by the other controller. 2351 Not used by the hardware when ALL_SP is set. */ 2352 uint64_t ctlr_fmp : 1; /**< Controller X NFIRSTMP enable controller FIRSTMP 2353 When set, the NMP candidate message segment can 2354 only match siloed FMP segments that were created 2355 by the same controller. When clear, this NMP-FMP 2356 match can also occur when the segments were 2357 created by the other controller. 2358 Not used by the hardware when ALL_FMP is set. */ 2359 uint64_t ctlr_nmp : 1; /**< Controller X NFIRSTMP enable controller NFIRSTMP 2360 When set, the NMP candidate message segment can 2361 only match siloed NMP segments that were created 2362 by the same controller. When clear, this NMP-NMP 2363 match can also occur when the segments were 2364 created by the other controller. 2365 Not used by the hardware when ALL_NMP is set. */ 2366 uint64_t id_sp : 1; /**< Controller X NFIRSTMP enable ID SP 2367 When set, the NMP candidate message segment can 2368 only match siloed SP segments that "ID match" the 2369 candidate. When clear, this NMP-SP match can occur 2370 with any ID values. 2371 Not used by the hardware when ALL_SP is set. */ 2372 uint64_t id_fmp : 1; /**< Controller X NFIRSTMP enable ID FIRSTMP 2373 When set, the NMP candidate message segment can 2374 only match siloed FMP segments that "ID match" the 2375 candidate. When clear, this NMP-FMP match can occur 2376 with any ID values. 2377 Not used by the hardware when ALL_FMP is set. */ 2378 uint64_t id_nmp : 1; /**< Controller X NFIRSTMP enable ID NFIRSTMP 2379 When set, the NMP candidate message segment can 2380 only match siloed NMP segments that "ID match" the 2381 candidate. When clear, this NMP-NMP match can occur 2382 with any ID values. 2383 Not used by the hardware when ALL_NMP is set. */ 2384 uint64_t reserved_8_8 : 1; 2385 uint64_t mbox_sp : 1; /**< Controller X NFIRSTMP enable MBOX SP 2386 When set, the NMP candidate message segment can 2387 only match siloed SP segments with the same 2-bit 2388 mbox value as the candidate. When clear, this 2389 NMP-SP match can occur with any mbox values. 2390 Not used by the hardware when ALL_SP is set. */ 2391 uint64_t mbox_fmp : 1; /**< Controller X NFIRSTMP enable MBOX FIRSTMP 2392 When set, the NMP candidate message segment can 2393 only match siloed FMP segments with the same 2-bit 2394 mbox value as the candidate. When clear, this 2395 NMP-FMP match can occur with any mbox values. 2396 Not used by the hardware when ALL_FMP is set. */ 2397 uint64_t mbox_nmp : 1; /**< Controller X NFIRSTMP enable MBOX NFIRSTMP 2398 When set, the NMP candidate message segment can 2399 only match siloed NMP segments with the same 2-bit 2400 mbox value as the candidate. When clear, this 2401 NMP-NMP match can occur with any mbox values. 2402 Not used by the hardware when ALL_NMP is set. */ 2403 uint64_t reserved_4_4 : 1; 2404 uint64_t all_sp : 1; /**< Controller X NFIRSTMP enable all SP 2405 When set, no NMP candidate message segments ever 2406 match siloed SP segments and ID_SP 2407 and MBOX_SP are not used. When clear, NMP-SP 2408 matches can occur. */ 2409 uint64_t all_fmp : 1; /**< Controller X NFIRSTMP enable all FIRSTMP 2410 When set, no NMP candidate message segments ever 2411 match siloed FMP segments and ID_FMP and MBOX_FMP 2412 are not used. When clear, NMP-FMP matches can 2413 occur. */ 2414 uint64_t all_nmp : 1; /**< Controller X NFIRSTMP enable all NFIRSTMP 2415 When set, no NMP candidate message segments ever 2416 match siloed NMP segments and ID_NMP and MBOX_NMP 2417 are not used. When clear, NMP-NMP matches can 2418 occur. */ 2419 uint64_t reserved_0_0 : 1; 2420#else 2421 uint64_t reserved_0_0 : 1; 2422 uint64_t all_nmp : 1; 2423 uint64_t all_fmp : 1; 2424 uint64_t all_sp : 1; 2425 uint64_t reserved_4_4 : 1; 2426 uint64_t mbox_nmp : 1; 2427 uint64_t mbox_fmp : 1; 2428 uint64_t mbox_sp : 1; 2429 uint64_t reserved_8_8 : 1; 2430 uint64_t id_nmp : 1; 2431 uint64_t id_fmp : 1; 2432 uint64_t id_sp : 1; 2433 uint64_t ctlr_nmp : 1; 2434 uint64_t ctlr_fmp : 1; 2435 uint64_t ctlr_sp : 1; 2436 uint64_t reserved_15_63 : 49; 2437#endif 2438 } s; 2439 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; 2440 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; 2441}; 2442typedef union cvmx_sriox_omsg_nmp_mrx cvmx_sriox_omsg_nmp_mrx_t; 2443 2444/** 2445 * cvmx_srio#_omsg_port# 2446 * 2447 * SRIO_OMSG_PORTX = SRIO Outbound Message Port 2448 * 2449 * The SRIO Controller X Outbound Message Port Register 2450 * 2451 * Notes: 2452 * PORT maps the PKO port to SRIO interface \# / controller X as follows: 2453 * 2454 * 00 == PKO port 40 2455 * 01 == PKO port 41 2456 * 10 == PKO port 42 2457 * 11 == PKO port 43 2458 * 2459 * No two PORT fields among the enabled controllers (ENABLE == 1) may be set to the same value. 2460 * The register is only reset during COLD boot. The register can be accessed/modified regardless of 2461 * the value in SRIO(0..1)_STATUS_REG.ACCESS. 2462 * 2463 * Clk_Rst: SRIO(0..1)_OMSG_PORT[0:1] sclk srst_n 2464 */ 2465union cvmx_sriox_omsg_portx 2466{ 2467 uint64_t u64; 2468 struct cvmx_sriox_omsg_portx_s 2469 { 2470#if __BYTE_ORDER == __BIG_ENDIAN 2471 uint64_t reserved_32_63 : 32; 2472 uint64_t enable : 1; /**< Controller X enable */ 2473 uint64_t reserved_2_30 : 29; 2474 uint64_t port : 2; /**< Controller X PKO port */ 2475#else 2476 uint64_t port : 2; 2477 uint64_t reserved_2_30 : 29; 2478 uint64_t enable : 1; 2479 uint64_t reserved_32_63 : 32; 2480#endif 2481 } s; 2482 struct cvmx_sriox_omsg_portx_s cn63xx; 2483 struct cvmx_sriox_omsg_portx_s cn63xxp1; 2484}; 2485typedef union cvmx_sriox_omsg_portx cvmx_sriox_omsg_portx_t; 2486 2487/** 2488 * cvmx_srio#_omsg_silo_thr 2489 * 2490 * SRIO_OMSG_SILO_THR = SRIO Outgoing Message SILO Thresholds (Pass 2) 2491 * 2492 * The SRIO Outgoing Message SILO Thresholds 2493 * 2494 * Notes: 2495 * Limits the number of Outgoing Message Segments in flight at a time. This register is reserved in 2496 * pass 1 and the threshold is set to 16. 2497 * 2498 * Clk_Rst: SRIO(0..1)_OMSG_SILO_THR hclk hrst_n 2499 */ 2500union cvmx_sriox_omsg_silo_thr 2501{ 2502 uint64_t u64; 2503 struct cvmx_sriox_omsg_silo_thr_s 2504 { 2505#if __BYTE_ORDER == __BIG_ENDIAN 2506 uint64_t reserved_5_63 : 59; 2507 uint64_t tot_silo : 5; /**< Sets max number segments in flight for all 2508 controllers. */ 2509#else 2510 uint64_t tot_silo : 5; 2511 uint64_t reserved_5_63 : 59; 2512#endif 2513 } s; 2514 struct cvmx_sriox_omsg_silo_thr_s cn63xx; 2515}; 2516typedef union cvmx_sriox_omsg_silo_thr cvmx_sriox_omsg_silo_thr_t; 2517 2518/** 2519 * cvmx_srio#_omsg_sp_mr# 2520 * 2521 * SRIO_OMSG_SP_MRX = SRIO Outbound Message SP Message Restriction 2522 * 2523 * The SRIO Controller X Outbound Message SP Message Restriction Register 2524 * 2525 * Notes: 2526 * This CSR controls when SP candidate message segments (from the two different controllers) can enter 2527 * the message segment silo to be sent out. A segment remains in the silo until after is has 2528 * been transmitted and either acknowledged or errored out. 2529 * 2530 * Candidates and silo entries are one of 4 types: 2531 * SP - a single-segment message 2532 * FMP - the first segment of a multi-segment message 2533 * NMP - the other segments in a multi-segment message 2534 * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2535 * a multi-segment message into the silo and can match against segments generated by 2536 * the other controller 2537 * 2538 * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2539 * By default (i.e. zeroes in this CSR), the SP candidate matches against all entries in the 2540 * silo. When fields in this CSR are set, SP candidate segments will match fewer silo entries and 2541 * can enter the silo more freely, probably providing better performance. 2542 * 2543 * Clk_Rst: SRIO(0..1)_OMSG_SP_MR[0:1] hclk hrst_n 2544 */ 2545union cvmx_sriox_omsg_sp_mrx 2546{ 2547 uint64_t u64; 2548 struct cvmx_sriox_omsg_sp_mrx_s 2549 { 2550#if __BYTE_ORDER == __BIG_ENDIAN 2551 uint64_t reserved_16_63 : 48; 2552 uint64_t xmbox_sp : 1; /**< Controller X SP enable XMBOX SP 2553 When set, the SP candidate message can only 2554 match siloed SP segments with the same 4-bit xmbox 2555 value as the candidate. When clear, this SP-SP 2556 match can occur with any xmbox values. 2557 When XMBOX_SP is set, MBOX_SP will commonly be set. 2558 Not used by the hardware when ALL_SP is set. */ 2559 uint64_t ctlr_sp : 1; /**< Controller X SP enable controller SP 2560 When set, the SP candidate message can 2561 only match siloed SP segments that were created 2562 by the same controller. When clear, this SP-SP 2563 match can also occur when the segments were 2564 created by the other controller. 2565 Not used by the hardware when ALL_SP is set. */ 2566 uint64_t ctlr_fmp : 1; /**< Controller X SP enable controller FIRSTMP 2567 When set, the SP candidate message can 2568 only match siloed FMP segments that were created 2569 by the same controller. When clear, this SP-FMP 2570 match can also occur when the segments were 2571 created by the other controller. 2572 Not used by the hardware when ALL_FMP is set. */ 2573 uint64_t ctlr_nmp : 1; /**< Controller X SP enable controller NFIRSTMP 2574 When set, the SP candidate message can 2575 only match siloed NMP segments that were created 2576 by the same controller. When clear, this SP-NMP 2577 match can also occur when the segments were 2578 created by the other controller. 2579 Not used by the hardware when ALL_NMP is set. */ 2580 uint64_t id_sp : 1; /**< Controller X SP enable ID SP 2581 When set, the SP candidate message can 2582 only match siloed SP segments that "ID match" the 2583 candidate. When clear, this SP-SP match can occur 2584 with any ID values. 2585 Not used by the hardware when ALL_SP is set. */ 2586 uint64_t id_fmp : 1; /**< Controller X SP enable ID FIRSTMP 2587 When set, the SP candidate message can 2588 only match siloed FMP segments that "ID match" the 2589 candidate. When clear, this SP-FMP match can occur 2590 with any ID values. 2591 Not used by the hardware when ALL_FMP is set. */ 2592 uint64_t id_nmp : 1; /**< Controller X SP enable ID NFIRSTMP 2593 When set, the SP candidate message can 2594 only match siloed NMP segments that "ID match" the 2595 candidate. When clear, this SP-NMP match can occur 2596 with any ID values. 2597 Not used by the hardware when ALL_NMP is set. */ 2598 uint64_t id_psd : 1; /**< Controller X SP enable ID PSEUDO 2599 When set, the SP candidate message can 2600 only match the silo pseudo (for the other 2601 controller) when it is an "ID match". When clear, 2602 this SP-PSD match can occur with any ID values. 2603 Not used by the hardware when ALL_PSD is set. */ 2604 uint64_t mbox_sp : 1; /**< Controller X SP enable MBOX SP 2605 When set, the SP candidate message can only 2606 match siloed SP segments with the same 2-bit mbox 2607 value as the candidate. When clear, this SP-SP 2608 match can occur with any mbox values. 2609 Not used by the hardware when ALL_SP is set. */ 2610 uint64_t mbox_fmp : 1; /**< Controller X SP enable MBOX FIRSTMP 2611 When set, the SP candidate message can only 2612 match siloed FMP segments with the same 2-bit mbox 2613 value as the candidate. When clear, this SP-FMP 2614 match can occur with any mbox values. 2615 Not used by the hardware when ALL_FMP is set. */ 2616 uint64_t mbox_nmp : 1; /**< Controller X SP enable MBOX NFIRSTMP 2617 When set, the SP candidate message can only 2618 match siloed NMP segments with the same 2-bit mbox 2619 value as the candidate. When clear, this SP-NMP 2620 match can occur with any mbox values. 2621 Not used by the hardware when ALL_NMP is set. */ 2622 uint64_t mbox_psd : 1; /**< Controller X SP enable MBOX PSEUDO 2623 When set, the SP candidate message can only 2624 match the silo pseudo (for the other controller) 2625 if the pseudo has the same 2-bit mbox value as the 2626 candidate. When clear, this SP-PSD match can occur 2627 with any mbox values. 2628 Not used by the hardware when ALL_PSD is set. */ 2629 uint64_t all_sp : 1; /**< Controller X SP enable all SP 2630 When set, no SP candidate messages ever 2631 match siloed SP segments, and XMBOX_SP, ID_SP, 2632 and MBOX_SP are not used. When clear, SP-SP 2633 matches can occur. */ 2634 uint64_t all_fmp : 1; /**< Controller X SP enable all FIRSTMP 2635 When set, no SP candidate messages ever 2636 match siloed FMP segments and ID_FMP and MBOX_FMP 2637 are not used. When clear, SP-FMP matches can 2638 occur. */ 2639 uint64_t all_nmp : 1; /**< Controller X SP enable all NFIRSTMP 2640 When set, no SP candidate messages ever 2641 match siloed NMP segments and ID_NMP and MBOX_NMP 2642 are not used. When clear, SP-NMP matches can 2643 occur. */ 2644 uint64_t all_psd : 1; /**< Controller X SP enable all PSEUDO 2645 When set, no SP candidate messages ever 2646 match the silo pseudo (for the other controller) 2647 and ID_PSD and MBOX_PSD are not used. When clear, 2648 SP-PSD matches can occur. */ 2649#else 2650 uint64_t all_psd : 1; 2651 uint64_t all_nmp : 1; 2652 uint64_t all_fmp : 1; 2653 uint64_t all_sp : 1; 2654 uint64_t mbox_psd : 1; 2655 uint64_t mbox_nmp : 1; 2656 uint64_t mbox_fmp : 1; 2657 uint64_t mbox_sp : 1; 2658 uint64_t id_psd : 1; 2659 uint64_t id_nmp : 1; 2660 uint64_t id_fmp : 1; 2661 uint64_t id_sp : 1; 2662 uint64_t ctlr_nmp : 1; 2663 uint64_t ctlr_fmp : 1; 2664 uint64_t ctlr_sp : 1; 2665 uint64_t xmbox_sp : 1; 2666 uint64_t reserved_16_63 : 48; 2667#endif 2668 } s; 2669 struct cvmx_sriox_omsg_sp_mrx_s cn63xx; 2670 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; 2671}; 2672typedef union cvmx_sriox_omsg_sp_mrx cvmx_sriox_omsg_sp_mrx_t; 2673 2674/** 2675 * cvmx_srio#_prio#_in_use 2676 * 2677 * SRIO_PRIO[0:3]_IN_USE = S2M PRIORITY FIFO IN USE COUNTS (Pass 2) 2678 * 2679 * SRIO S2M Priority X FIFO Inuse counts 2680 * 2681 * Notes: 2682 * These registers provide status information on the number of read/write requests pending in the S2M 2683 * Priority FIFOs. The information can be used to help determine when an S2M_TYPE register can be 2684 * reallocated. For example, if an S2M_TYPE is used N times in a DMA write operation and the DMA has 2685 * completed. The register corresponding to the RD/WR_PRIOR of the S2M_TYPE can be read to determine 2686 * the START_CNT and then can be polled to see if the END_CNT equals the START_CNT or at least 2687 * START_CNT+N. These registers can be accessed regardless of the value of SRIO(0..1)_STATUS_REG.ACCESS 2688 * but are reset by either the MAC or Core being reset. 2689 * 2690 * Clk_Rst: SRIO(0..1)_PRIO[0:3]_IN_USE sclk srst_n, hrst_n 2691 */ 2692union cvmx_sriox_priox_in_use 2693{ 2694 uint64_t u64; 2695 struct cvmx_sriox_priox_in_use_s 2696 { 2697#if __BYTE_ORDER == __BIG_ENDIAN 2698 uint64_t reserved_32_63 : 32; 2699 uint64_t end_cnt : 16; /**< Count of Packets with S2M_TYPES completed for this 2700 Priority X FIFO */ 2701 uint64_t start_cnt : 16; /**< Count of Packets with S2M_TYPES started for this 2702 Priority X FIFO */ 2703#else 2704 uint64_t start_cnt : 16; 2705 uint64_t end_cnt : 16; 2706 uint64_t reserved_32_63 : 32; 2707#endif 2708 } s; 2709 struct cvmx_sriox_priox_in_use_s cn63xx; 2710}; 2711typedef union cvmx_sriox_priox_in_use cvmx_sriox_priox_in_use_t; 2712 2713/** 2714 * cvmx_srio#_rx_bell 2715 * 2716 * SRIO_RX_BELL = SRIO Receive Doorbell 2717 * 2718 * The SRIO Incoming (RX) Doorbell 2719 * 2720 * Notes: 2721 * This register contains the SRIO Information, Device ID, Transaction Type and Priority of the 2722 * incoming Doorbell Transaction as well as the number of transactions waiting to be read. Reading 2723 * this register causes a Doorbell to be removed from the RX Bell FIFO and the COUNT to be 2724 * decremented. If the COUNT is zero then the FIFO is empty and the other fields should be 2725 * considered invalid. When the FIFO is full an ERROR is automatically issued. The RXBELL Interrupt 2726 * can be used to detect posts to this FIFO. 2727 * 2728 * Clk_Rst: SRIO(0..1)_RX_BELL hclk hrst_n 2729 */ 2730union cvmx_sriox_rx_bell 2731{ 2732 uint64_t u64; 2733 struct cvmx_sriox_rx_bell_s 2734 { 2735#if __BYTE_ORDER == __BIG_ENDIAN 2736 uint64_t reserved_48_63 : 16; 2737 uint64_t data : 16; /**< Information field from received doorbell */ 2738 uint64_t src_id : 16; /**< Doorbell Source Device ID[15:0] */ 2739 uint64_t count : 8; /**< RX Bell FIFO Count 2740 Note: Count must be > 0 for entry to be valid. */ 2741 uint64_t reserved_5_7 : 3; 2742 uint64_t dest_id : 1; /**< Destination Device ID 0=Primary, 1=Secondary */ 2743 uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 2744 uint64_t reserved_2_2 : 1; 2745 uint64_t priority : 2; /**< Doorbell Priority */ 2746#else 2747 uint64_t priority : 2; 2748 uint64_t reserved_2_2 : 1; 2749 uint64_t id16 : 1; 2750 uint64_t dest_id : 1; 2751 uint64_t reserved_5_7 : 3; 2752 uint64_t count : 8; 2753 uint64_t src_id : 16; 2754 uint64_t data : 16; 2755 uint64_t reserved_48_63 : 16; 2756#endif 2757 } s; 2758 struct cvmx_sriox_rx_bell_s cn63xx; 2759 struct cvmx_sriox_rx_bell_s cn63xxp1; 2760}; 2761typedef union cvmx_sriox_rx_bell cvmx_sriox_rx_bell_t; 2762 2763/** 2764 * cvmx_srio#_rx_bell_seq 2765 * 2766 * SRIO_RX_BELL_SEQ = SRIO Receive Doorbell Sequence Count 2767 * 2768 * The SRIO Incoming (RX) Doorbell Sequence Count 2769 * 2770 * Notes: 2771 * This register contains the value of the sequence counter when the doorbell was received and a 2772 * shadow copy of the Bell FIFO Count that can be read without emptying the FIFO. This register must 2773 * be read prior to SRIO(0..1)_RX_BELL to guarantee that the information corresponds to the correct 2774 * doorbell. 2775 * 2776 * Clk_Rst: SRIO(0..1)_RX_BELL_SEQ hclk hrst_n 2777 */ 2778union cvmx_sriox_rx_bell_seq 2779{ 2780 uint64_t u64; 2781 struct cvmx_sriox_rx_bell_seq_s 2782 { 2783#if __BYTE_ORDER == __BIG_ENDIAN 2784 uint64_t reserved_40_63 : 24; 2785 uint64_t count : 8; /**< RX Bell FIFO Count 2786 Note: Count must be > 0 for entry to be valid. */ 2787 uint64_t seq : 32; /**< 32-bit Sequence \# associated with Doorbell Message */ 2788#else 2789 uint64_t seq : 32; 2790 uint64_t count : 8; 2791 uint64_t reserved_40_63 : 24; 2792#endif 2793 } s; 2794 struct cvmx_sriox_rx_bell_seq_s cn63xx; 2795 struct cvmx_sriox_rx_bell_seq_s cn63xxp1; 2796}; 2797typedef union cvmx_sriox_rx_bell_seq cvmx_sriox_rx_bell_seq_t; 2798 2799/** 2800 * cvmx_srio#_rx_status 2801 * 2802 * SRIO_RX_STATUS = SRIO Inbound Credits/Response Status 2803 * 2804 * Specifies the current number of credits/responses by SRIO for Inbound Traffic 2805 * 2806 * Notes: 2807 * Debug Register specifying the number of credits/responses currently in use for Inbound Traffic. 2808 * The maximum value for COMP, N_POST and POST is set in SRIO(0..1)_TLP_CREDITS. When all inbound traffic 2809 * has stopped the values should eventually return to the maximum values. The RTN_PR[3:1] entry 2810 * counts should eventually return to the reset values. 2811 * 2812 * Clk_Rst: SRIO(0..1)_RX_STATUS hclk hrst_n 2813 */ 2814union cvmx_sriox_rx_status 2815{ 2816 uint64_t u64; 2817 struct cvmx_sriox_rx_status_s 2818 { 2819#if __BYTE_ORDER == __BIG_ENDIAN 2820 uint64_t rtn_pr3 : 8; /**< Number of pending Priority 3 Response Entries. */ 2821 uint64_t rtn_pr2 : 8; /**< Number of pending Priority 2 Response Entries. */ 2822 uint64_t rtn_pr1 : 8; /**< Number of pending Priority 1 Response Entries. */ 2823 uint64_t reserved_28_39 : 12; 2824 uint64_t mbox : 4; /**< Credits for Mailbox Data used in M2S. */ 2825 uint64_t comp : 8; /**< Credits for Read Completions used in M2S. */ 2826 uint64_t reserved_13_15 : 3; 2827 uint64_t n_post : 5; /**< Credits for Read Requests used in M2S. */ 2828 uint64_t post : 8; /**< Credits for Write Request Postings used in M2S. */ 2829#else 2830 uint64_t post : 8; 2831 uint64_t n_post : 5; 2832 uint64_t reserved_13_15 : 3; 2833 uint64_t comp : 8; 2834 uint64_t mbox : 4; 2835 uint64_t reserved_28_39 : 12; 2836 uint64_t rtn_pr1 : 8; 2837 uint64_t rtn_pr2 : 8; 2838 uint64_t rtn_pr3 : 8; 2839#endif 2840 } s; 2841 struct cvmx_sriox_rx_status_s cn63xx; 2842 struct cvmx_sriox_rx_status_s cn63xxp1; 2843}; 2844typedef union cvmx_sriox_rx_status cvmx_sriox_rx_status_t; 2845 2846/** 2847 * cvmx_srio#_s2m_type# 2848 * 2849 * SRIO_S2M_TYPE[0:15] = SLI to SRIO MAC Operation Type 2850 * 2851 * SRIO Operation Type selected by PP or DMA Accesses 2852 * 2853 * Notes: 2854 * This CSR table specifies how to convert a SLI/DPI MAC read or write into sRIO operations. 2855 * Each SLI/DPI read or write access supplies a 64-bit address (MACADD[63:0]), 2-bit ADDRTYPE, and 2856 * 2-bit endian-swap. This SRIO*_S2M_TYPE* CSR description specifies a table with 16 CSRs. SRIO 2857 * selects one of the table entries with TYPEIDX[3:0], which it creates from the SLI/DPI MAC memory 2858 * space read or write as follows: 2859 * TYPEIDX[1:0] = ADDRTYPE[1:0] (ADDRTYPE[1] is no-snoop to the PCIe MAC, 2860 * ADDRTYPE[0] is relaxed-ordering to the PCIe MAC) 2861 * TYPEIDX[2] = MACADD[50] 2862 * TYPEIDX[3] = MACADD[59] 2863 * 2864 * Clk_Rst: SRIO(0..1)_S2M_TYPE[0:15] hclk hrst_n 2865 */ 2866union cvmx_sriox_s2m_typex 2867{ 2868 uint64_t u64; 2869 struct cvmx_sriox_s2m_typex_s 2870 { 2871#if __BYTE_ORDER == __BIG_ENDIAN 2872 uint64_t reserved_19_63 : 45; 2873 uint64_t wr_op : 3; /**< sRIO operation for SLI/DPI writes 2874 2875 SLI/DPI hardware break MAC memory space writes 2876 that they generate into pieces of maximum size 2877 256B. For NWRITE/NWRITE_R/SWRITE WR_OP variants 2878 below, SRIO will, if necessary to obey sRIO 2879 requirements, automatically break the write into 2880 even smaller writes. The same is not true for 2881 MAINTENANCE writes and port-writes. Additional 2882 SW/usage restrictions are required for these 2883 MAINTENANCE WR_OP's to work correctly. SW must 2884 restrict the alignment and length of DPI pointers, 2885 limit the store sizes that the cores issue, and 2886 possibly also set SLI_MEM_ACCESS_SUBID*[NMERGE] 2887 so that all MAC memory space writes with 2888 MAINTENANCE write and port-write WR_OP's can be 2889 serviced in a single sRIO operation. 2890 2891 SRIO always sends the write data (64-bit) words 2892 out in order. 2893 2894 WR_OP = 0 = Normal Write (NWRITE) 2895 SRIO breaks a MAC memory space write into 2896 the minimum number of required sRIO NWRITE 2897 operations. This will be 1-5 total NWRITEs, 2898 depending on endian-swap, alignment, and 2899 length. 2900 2901 WR_OP = 1 = Normal Write w/Response (NWRITE_R) 2902 SRIO breaks a MAC memory space write into 2903 the minimum number of required sRIO 2904 NWRITE_R operations. This will be 1-5 total 2905 NWRITE_R's, depending on endian-swap, 2906 alignment, and length. 2907 2908 SRIO sets SRIO*_INT_REG[WR_DONE] after it 2909 receives the DONE response for the last 2910 NWRITE_R sent. 2911 2912 WR_OP = 2 = NWRITE, Streaming write (SWRITE), 2913 NWRITE 2914 SRIO attempts to turn the MAC memory space 2915 write into an SWRITE operation. There will 2916 be 1-5 total sRIO operations (0-2 NWRITE's 2917 followed by 0-1 SWRITE's followed by 0-2 2918 NWRITE's) generated to complete the MAC 2919 memory space write, depending on 2920 endian-swap, alignment, and length. 2921 2922 If the starting address is not 64-bit 2923 aligned, SRIO first creates 1-4 NWRITE's to 2924 either align it or complete the write. Then 2925 SRIO creates a SWRITE including all aligned 2926 64-bit words. (SRIO won't create an SWRITE 2927 when there are none.) If store data 2928 remains, SRIO finally creates another 1 or 2929 2 NWRITE's. 2930 2931 WR_OP = 3 = NWRITE, SWRITE, NWRITE_R 2932 SRIO attempts to turn the MAC memory space 2933 write into an SWRITE operation followed by 2934 a NWRITE_R operation. The last operation 2935 is always NWRITE_R. There will be 1-5 2936 total sRIO operations (0-2 NWRITE's, 2937 followed by 0-1 SWRITE, followed by 1-4 2938 NWRITE_R's) generated to service the MAC 2939 memory space write, depending on 2940 endian-swap, alignment, and length. 2941 2942 If the write is contained in one aligned 2943 64-bit word, SRIO will completely service 2944 the MAC memory space write with 1-4 2945 NWRITE_R's. 2946 2947 Otherwise, if the write spans multiple 2948 words, SRIO services the write as follows. 2949 First, if the start of the write is not 2950 word-aligned, SRIO creates 1 or 2 NWRITE's 2951 to align it. Then SRIO creates an SWRITE 2952 that includes all aligned 64-bit words, 2953 leaving data for the final NWRITE_R(s). 2954 (SRIO won't create the SWRITE when there is 2955 no data for it.) Then SRIO finally creates 2956 1 or 2 NWRITE_R's. 2957 2958 In any case, SRIO sets 2959 SRIO*_INT_REG[WR_DONE] after it receives 2960 the DONE response for the last NWRITE_R 2961 sent. 2962 2963 WR_OP = 4 = NWRITE, NWRITE_R 2964 SRIO attempts to turn the MAC memory space 2965 write into an NWRITE operation followed by 2966 a NWRITE_R operation. The last operation 2967 is always NWRITE_R. There will be 1-5 2968 total sRIO operations (0-3 NWRITE's 2969 followed by 1-4 NWRITE_R's) generated to 2970 service the MAC memory space write, 2971 depending on endian-swap, alignment, and 2972 length. 2973 2974 If the write is contained in one aligned 2975 64-bit word, SRIO will completely service 2976 the MAC memory space write with 1-4 2977 NWRITE_R's. 2978 2979 Otherwise, if the write spans multiple 2980 words, SRIO services the write as follows. 2981 First, if the start of the write is not 2982 word-aligned, SRIO creates 1 or 2 NWRITE's 2983 to align it. Then SRIO creates an NWRITE 2984 that includes all aligned 64-bit words, 2985 leaving data for the final NWRITE_R(s). 2986 (SRIO won't create this NWRITE when there 2987 is no data for it.) Then SRIO finally 2988 creates 1 or 2 NWRITE_R's. 2989 2990 In any case, SRIO sets 2991 SRIO*_INT_REG[WR_DONE] after it receives 2992 the DONE response for the last NWRITE_R 2993 sent. 2994 2995 WR_OP = 5 = Reserved 2996 2997 WR_OP = 6 = Maintenance Write 2998 - SRIO will create one sRIO MAINTENANCE write 2999 operation to service the MAC memory space 3000 write 3001 - IAOW_SEL must be zero. (see description 3002 below.) 3003 - MDS must be zero. (MDS is MACADD[63:62] - 3004 see IAOW_SEL description below.) 3005 - Hop Cnt is MACADD[31:24]/SRIOAddress[31:24] 3006 - MACADD[23:0]/SRIOAddress[23:0] selects 3007 maintenance register (i.e. config_offset) 3008 - sRIODestID[15:0] is MACADD[49:34]. 3009 (MACADD[49:42] unused when ID16=0) 3010 - Write size/alignment must obey sRIO rules 3011 (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte 3012 lengths allowed) 3013 3014 WR_OP = 7 = Maintenance Port Write 3015 - SRIO will create one sRIO MAINTENANCE port 3016 write operation to service the MAC memory 3017 space write 3018 - IAOW_SEL must be zero. (see description 3019 below.) 3020 - MDS must be zero. (MDS is MACADD[63:62] - 3021 see IAOW_SEL description below.) 3022 - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24] 3023 - MACADD[23:0]/sRIOAddress[23:0] MBZ 3024 (config_offset field reserved by sRIO) 3025 - sRIODestID[15:0] is MACADD[49:34]. 3026 (MACADD[49:42] unused when ID16=0) 3027 - Write size/alignment must obey sRIO rules 3028 (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte 3029 lengths allowed) */ 3030 uint64_t reserved_15_15 : 1; 3031 uint64_t rd_op : 3; /**< sRIO operation for SLI/DPI reads 3032 3033 SLI/DPI hardware and sRIO configuration 3034 restrictions guarantee that SRIO can service any 3035 MAC memory space read that it receives from SLI/DPI 3036 with a single NREAD, assuming that RD_OP selects 3037 NREAD. DPI will break a read into multiple MAC 3038 memory space reads to ensure this holds. The same 3039 is not true for the ATOMIC and MAINTENANCE RD_OP 3040 values. Additional SW/usage restrictions are 3041 required for ATOMIC and MAINTENANCE RD_OP to work 3042 correctly. SW must restrict the alignment and 3043 length of DPI pointers and limit the load sizes 3044 that the cores issue such that all MAC memory space 3045 reads with ATOMIC and MAINTENANCE RD_OP's can be 3046 serviced in a single sRIO operation. 3047 3048 RD_OP = 0 = Normal Read (NREAD) 3049 - SRIO will create one sRIO NREAD 3050 operation to service the MAC memory 3051 space read 3052 - Read size/alignment must obey sRIO rules 3053 (up to 256 byte lengths). (This requirement 3054 is guaranteed by SLI/DPI usage restrictions 3055 and configuration.) 3056 3057 RD_OP = 1 = Reserved 3058 3059 RD_OP = 2 = Atomic Set 3060 - SRIO will create one sRIO ATOMIC set 3061 operation to service the MAC memory 3062 space read 3063 - Read size/alignment must obey sRIO rules 3064 (1, 2, and 4 byte lengths allowed) 3065 3066 RD_OP = 3 = Atomic Clear 3067 - SRIO will create one sRIO ATOMIC clr 3068 operation to service the MAC memory 3069 space read 3070 - Read size/alignment must obey sRIO rules 3071 (1, 2, and 4 byte lengths allowed) 3072 3073 RD_OP = 4 = Atomic Increment 3074 - SRIO will create one sRIO ATOMIC inc 3075 operation to service the MAC memory 3076 space read 3077 - Read size/alignment must obey sRIO rules 3078 (1, 2, and 4 byte lengths allowed) 3079 3080 RD_OP = 5 = Atomic Decrement 3081 - SRIO will create one sRIO ATOMIC dec 3082 operation to service the MAC memory 3083 space read 3084 - Read size/alignment must obey sRIO rules 3085 (1, 2, and 4 byte lengths allowed) 3086 3087 RD_OP = 6 = Maintenance Read 3088 - SRIO will create one sRIO MAINTENANCE read 3089 operation to service the MAC memory 3090 space read 3091 - IAOW_SEL must be zero. (see description 3092 below.) 3093 - MDS must be zero. (MDS is MACADD[63:62] - 3094 see IAOW_SEL description below.) 3095 - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24] 3096 - MACADD[23:0]/sRIOAddress[23:0] selects 3097 maintenance register (i.e. config_offset) 3098 - sRIODestID[15:0] is MACADD[49:34]. 3099 (MACADD[49:42] unused when ID16=0) 3100 - Read size/alignment must obey sRIO rules 3101 (4, 8, 16, 32 and 64 byte lengths allowed) 3102 3103 RD_OP = 7 = Reserved */ 3104 uint64_t wr_prior : 2; /**< Transaction Priority 0-3 used for writes */ 3105 uint64_t rd_prior : 2; /**< Transaction Priority 0-3 used for reads/ATOMICs */ 3106 uint64_t reserved_6_7 : 2; 3107 uint64_t src_id : 1; /**< Source ID 3108 3109 0 = Use Primary ID as Source ID 3110 (SRIOMAINT*_PRI_DEV_ID[ID16 or ID8], depending 3111 on SRIO TT ID (i.e. ID16 below)) 3112 3113 1 = Use Secondary ID as Source ID 3114 (SRIOMAINT*_SEC_DEV_ID[ID16 or ID8], depending 3115 on SRIO TT ID (i.e. ID16 below)) */ 3116 uint64_t id16 : 1; /**< SRIO TT ID 0=8bit, 1=16-bit 3117 IAOW_SEL must not be 2 when ID16=1. */ 3118 uint64_t reserved_2_3 : 2; 3119 uint64_t iaow_sel : 2; /**< Internal Address Offset Width Select 3120 3121 IAOW_SEL determines how to convert the 3122 MACADD[63:62,58:51,49:0] recieved from SLI/DPI with 3123 read/write into an sRIO address (sRIOAddress[...]) 3124 and sRIO destination ID (sRIODestID[...]). The sRIO 3125 address width mode (SRIOMAINT_PE_LLC[EX_ADDR]) and 3126 ID16, determine the width of the sRIO address and 3127 ID in the outgoing request(s), respectively. 3128 3129 MACADD[61:60] is always unused. 3130 3131 MACADD[59] is always TYPEIDX[3] 3132 MACADD[50] is always TYPEIDX[2] 3133 (TYPEIDX[3:0] selects one of these 3134 SRIO*_S2M_TYPE* table entries.) 3135 3136 MACADD[17:0] always becomes sRIOAddress[17:0]. 3137 3138 IAOW_SEL = 0 = 34-bit Address Offset 3139 3140 Must be used when sRIO link is in 34-bit 3141 address width mode. 3142 When sRIO is in 50-bit address width mode, 3143 sRIOAddress[49:34]=0 in the outgoing request. 3144 When sRIO is in 66-bit address width mode, 3145 sRIOAddress[65:34]=0 in the outgoing request. 3146 3147 Usage of the SLI/DPI MAC address when 3148 IAOW_SEL = 0: 3149 MACADD[63:62] = Multi-Device Swap (MDS) 3150 MDS value affects MACADD[49:18] usage 3151 MACADD[58:51] => unused 3152 MACADD[49:18] usage depends on MDS value 3153 MDS = 0 3154 MACADD[49:34] => sRIODestID[15:0] 3155 (MACADD[49:42] unused when ID16=0) 3156 MACADD[33:18] => sRIOAddress[33:18] 3157 MDS = 1 3158 MACADD[49:42] => sRIODestID[15:8] 3159 (MACADD[49:42] unused when ID16 = 0) 3160 MACADD[41:34] => sRIOAddress[33:26] 3161 MACADD[33:26] => sRIODestID[7:0] 3162 MACADD[25:18] => sRIOAddress[25:18] 3163 MDS = 2 3164 ID16 must be one. 3165 MACADD[49:34] => sRIOAddress[33:18] 3166 MACADD[33:18] => sRIODestID[15:0] 3167 MDS = 3 = Reserved 3168 3169 IAOW_SEL = 1 = 42-bit Address Offset 3170 3171 Must not be used when sRIO link is in 34-bit 3172 address width mode. 3173 When sRIO is in 50-bit address width mode, 3174 sRIOAddress[49:42]=0 in the outgoing request. 3175 When sRIO is in 66-bit address width mode, 3176 sRIOAddress[65:42]=0 in the outgoing request. 3177 3178 Usage of the SLI/DPI MAC address when 3179 IAOW_SEL = 1: 3180 MACADD[63:62] => Multi-Device Swap (MDS) 3181 MDS value affects MACADD[58:51,49:42,33:18] 3182 use 3183 MACADD[41:34] => sRIOAddress[41:34] 3184 MACADD[58:51,49:42,33:18] usage depends on 3185 MDS value: 3186 MDS = 0 3187 MACADD[58:51] => sRIODestID[15:8] 3188 MACADD[49:42] => sRIODestID[7:0] 3189 (MACADD[58:51] unused when ID16=0) 3190 MACADD[33:18] => sRIOAddress[33:18] 3191 MDS = 1 3192 MACADD[58:51] => sRIODestID[15:8] 3193 (MACADD[58:51] unused when ID16 = 0) 3194 MACADD[49:42] => sRIOAddress[33:26] 3195 MACADD[33:26] => sRIODestID[7:0] 3196 MACADD[25:18] => sRIOAddress[25:18] 3197 MDS = 2 3198 ID16 must be one. 3199 MACADD[58:51] => sRIOAddress[33:26] 3200 MACADD[49:42] => sRIOAddress[25:18] 3201 MACADD[33:18] => sRIODestID[15:0] 3202 MDS = 3 = Reserved 3203 3204 IAOW_SEL = 2 = 50-bit Address Offset 3205 3206 Must not be used when sRIO link is in 34-bit 3207 address width mode. 3208 Must not be used when ID16=1. 3209 When sRIO is in 66-bit address width mode, 3210 sRIOAddress[65:50]=0 in the outgoing request. 3211 3212 Usage of the SLI/DPI MAC address when 3213 IAOW_SEL = 2: 3214 MACADD[63:62] => Multi-Device Swap (MDS) 3215 MDS value affects MACADD[58:51,33:26] use 3216 MDS value 3 is reserved 3217 MACADD[49:34] => sRIOAddress[49:34] 3218 MACADD[25:18] => sRIOAddress[25:18] 3219 MACADD[58:51,33:26] usage depends on 3220 MDS value: 3221 MDS = 0 3222 MACADD[58:51] => sRIODestID[7:0] 3223 MACADD[33:26] => sRIOAddress[33:26] 3224 MDS = 1 3225 MACADD[58:51] => sRIOAddress[33:26] 3226 MACADD[33:26] => sRIODestID[7:0] 3227 MDS = 2 = Reserved 3228 MDS = 3 = Reserved 3229 3230 IAOW_SEL = 3 = Reserved */ 3231#else 3232 uint64_t iaow_sel : 2; 3233 uint64_t reserved_2_3 : 2; 3234 uint64_t id16 : 1; 3235 uint64_t src_id : 1; 3236 uint64_t reserved_6_7 : 2; 3237 uint64_t rd_prior : 2; 3238 uint64_t wr_prior : 2; 3239 uint64_t rd_op : 3; 3240 uint64_t reserved_15_15 : 1; 3241 uint64_t wr_op : 3; 3242 uint64_t reserved_19_63 : 45; 3243#endif 3244 } s; 3245 struct cvmx_sriox_s2m_typex_s cn63xx; 3246 struct cvmx_sriox_s2m_typex_s cn63xxp1; 3247}; 3248typedef union cvmx_sriox_s2m_typex cvmx_sriox_s2m_typex_t; 3249 3250/** 3251 * cvmx_srio#_seq 3252 * 3253 * SRIO_SEQ = SRIO Sequence Count 3254 * 3255 * The SRIO Sequence Count 3256 * 3257 * Notes: 3258 * This register contains the current value of the sequence counter. This counter increments every 3259 * time a doorbell or the first segment of a message is accepted. 3260 * 3261 * Clk_Rst: SRIO(0..1)_SEQ hclk hrst_n 3262 */ 3263union cvmx_sriox_seq 3264{ 3265 uint64_t u64; 3266 struct cvmx_sriox_seq_s 3267 { 3268#if __BYTE_ORDER == __BIG_ENDIAN 3269 uint64_t reserved_32_63 : 32; 3270 uint64_t seq : 32; /**< 32-bit Sequence \# */ 3271#else 3272 uint64_t seq : 32; 3273 uint64_t reserved_32_63 : 32; 3274#endif 3275 } s; 3276 struct cvmx_sriox_seq_s cn63xx; 3277 struct cvmx_sriox_seq_s cn63xxp1; 3278}; 3279typedef union cvmx_sriox_seq cvmx_sriox_seq_t; 3280 3281/** 3282 * cvmx_srio#_status_reg 3283 * 3284 * SRIO_STATUS_REG = SRIO Status Register 3285 * 3286 * General status of the SRIO. 3287 * 3288 * Notes: 3289 * The SRIO field displays if the port has been configured for SRIO operation. This register can be 3290 * read regardless of whether the SRIO is selected or being reset. Although some other registers can 3291 * be accessed while the ACCESS bit is zero (see individual registers for details), the majority of 3292 * SRIO registers and all the SRIOMAINT registers can be used only when the ACCESS bit is asserted. 3293 * 3294 * Clk_Rst: SRIO(0..1)_STATUS_REG sclk srst_n 3295 */ 3296union cvmx_sriox_status_reg 3297{ 3298 uint64_t u64; 3299 struct cvmx_sriox_status_reg_s 3300 { 3301#if __BYTE_ORDER == __BIG_ENDIAN 3302 uint64_t reserved_2_63 : 62; 3303 uint64_t access : 1; /**< SRIO and SRIOMAINT Register Access. 3304 0 - Register Access Disabled. 3305 1 - Register Access Enabled. */ 3306 uint64_t srio : 1; /**< SRIO Port Enabled. 3307 0 - All SRIO functions disabled. 3308 1 - All SRIO Operations permitted. */ 3309#else 3310 uint64_t srio : 1; 3311 uint64_t access : 1; 3312 uint64_t reserved_2_63 : 62; 3313#endif 3314 } s; 3315 struct cvmx_sriox_status_reg_s cn63xx; 3316 struct cvmx_sriox_status_reg_s cn63xxp1; 3317}; 3318typedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t; 3319 3320/** 3321 * cvmx_srio#_tag_ctrl 3322 * 3323 * SRIO_TAG_CTRL = SRIO TAG Control 3324 * 3325 * The SRIO TAG Control 3326 * 3327 * Notes: 3328 * This register is used to show the state of the internal transaction tags and provides a manual 3329 * reset of the outgoing tags. 3330 * 3331 * Clk_Rst: SRIO(0..1)_TAG_CTRL hclk hrst_n 3332 */ 3333union cvmx_sriox_tag_ctrl 3334{ 3335 uint64_t u64; 3336 struct cvmx_sriox_tag_ctrl_s 3337 { 3338#if __BYTE_ORDER == __BIG_ENDIAN 3339 uint64_t reserved_17_63 : 47; 3340 uint64_t o_clr : 1; /**< Manual OTAG Clear. This bit manually resets the 3341 number of OTAGs back to 16 and loses track of any 3342 outgoing packets. This function is automatically 3343 performed when the SRIO MAC is reset but it may be 3344 necessary after a chip reset while the MAC is in 3345 operation. This bit must be set then cleared to 3346 return to normal operation. Typically, Outgoing 3347 SRIO packets must be halted 6 seconds prior to 3348 this bit is set to avoid generating duplicate tags 3349 and unexpected response errors. */ 3350 uint64_t reserved_13_15 : 3; 3351 uint64_t otag : 5; /**< Number of Available Outbound Tags. Tags are 3352 required for all outgoing memory and maintenance 3353 operations that require a response. (Max 16) */ 3354 uint64_t reserved_5_7 : 3; 3355 uint64_t itag : 5; /**< Number of Available Inbound Tags. Tags are 3356 required for all incoming memory operations that 3357 require a response. (Max 16) */ 3358#else 3359 uint64_t itag : 5; 3360 uint64_t reserved_5_7 : 3; 3361 uint64_t otag : 5; 3362 uint64_t reserved_13_15 : 3; 3363 uint64_t o_clr : 1; 3364 uint64_t reserved_17_63 : 47; 3365#endif 3366 } s; 3367 struct cvmx_sriox_tag_ctrl_s cn63xx; 3368 struct cvmx_sriox_tag_ctrl_s cn63xxp1; 3369}; 3370typedef union cvmx_sriox_tag_ctrl cvmx_sriox_tag_ctrl_t; 3371 3372/** 3373 * cvmx_srio#_tlp_credits 3374 * 3375 * SRIO_TLP_CREDITS = SRIO TLP Credits 3376 * 3377 * Specifies the number of credits the SRIO can use for incoming Commands and Messages. 3378 * 3379 * Notes: 3380 * Specifies the number of maximum credits the SRIO can use for incoming Commands and Messages. 3381 * 3382 * Clk_Rst: SRIO(0..1)_TLP_CREDITS hclk hrst_n 3383 */ 3384union cvmx_sriox_tlp_credits 3385{ 3386 uint64_t u64; 3387 struct cvmx_sriox_tlp_credits_s 3388 { 3389#if __BYTE_ORDER == __BIG_ENDIAN 3390 uint64_t reserved_28_63 : 36; 3391 uint64_t mbox : 4; /**< Credits for Mailbox Data used in M2S. 3392 Legal values are 0x2 to 0x8. */ 3393 uint64_t comp : 8; /**< Credits for Read Completions used in M2S. 3394 Legal values are 0x22 to 0x80. */ 3395 uint64_t reserved_13_15 : 3; 3396 uint64_t n_post : 5; /**< Credits for Read Requests used in M2S. 3397 Legal values are 0x4 to 0x10. */ 3398 uint64_t post : 8; /**< Credits for Write Request Postings used in M2S. 3399 Legal values are 0x22 to 0x80. */ 3400#else 3401 uint64_t post : 8; 3402 uint64_t n_post : 5; 3403 uint64_t reserved_13_15 : 3; 3404 uint64_t comp : 8; 3405 uint64_t mbox : 4; 3406 uint64_t reserved_28_63 : 36; 3407#endif 3408 } s; 3409 struct cvmx_sriox_tlp_credits_s cn63xx; 3410 struct cvmx_sriox_tlp_credits_s cn63xxp1; 3411}; 3412typedef union cvmx_sriox_tlp_credits cvmx_sriox_tlp_credits_t; 3413 3414/** 3415 * cvmx_srio#_tx_bell 3416 * 3417 * SRIO_TX_BELL = SRIO Transmit Doorbell 3418 * 3419 * The SRIO Outgoing (TX) Doorbell 3420 * 3421 * Notes: 3422 * This register specifies SRIO Information, Device ID, Transaction Type and Priority of the outgoing 3423 * Doorbell Transaction. Writes to this register causes the Doorbell to be issued using these bits. 3424 * The write also causes the PENDING bit to be set. The hardware automatically clears bit when the 3425 * Doorbell operation has been acknowledged. A write to this register while the PENDING bit is set 3426 * should be avoided as it will stall the RSL until the first Doorbell has completed. 3427 * 3428 * Clk_Rst: SRIO(0..1)_TX_BELL hclk hrst_n 3429 */ 3430union cvmx_sriox_tx_bell 3431{ 3432 uint64_t u64; 3433 struct cvmx_sriox_tx_bell_s 3434 { 3435#if __BYTE_ORDER == __BIG_ENDIAN 3436 uint64_t reserved_48_63 : 16; 3437 uint64_t data : 16; /**< Information field for next doorbell operation */ 3438 uint64_t dest_id : 16; /**< Doorbell Destination Device ID[15:0] */ 3439 uint64_t reserved_9_15 : 7; 3440 uint64_t pending : 1; /**< Doorbell Transmit in Progress */ 3441 uint64_t reserved_5_7 : 3; 3442 uint64_t src_id : 1; /**< Source Device ID 0=Primary, 1=Secondary */ 3443 uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 3444 uint64_t reserved_2_2 : 1; 3445 uint64_t priority : 2; /**< Doorbell Priority */ 3446#else 3447 uint64_t priority : 2; 3448 uint64_t reserved_2_2 : 1; 3449 uint64_t id16 : 1; 3450 uint64_t src_id : 1; 3451 uint64_t reserved_5_7 : 3; 3452 uint64_t pending : 1; 3453 uint64_t reserved_9_15 : 7; 3454 uint64_t dest_id : 16; 3455 uint64_t data : 16; 3456 uint64_t reserved_48_63 : 16; 3457#endif 3458 } s; 3459 struct cvmx_sriox_tx_bell_s cn63xx; 3460 struct cvmx_sriox_tx_bell_s cn63xxp1; 3461}; 3462typedef union cvmx_sriox_tx_bell cvmx_sriox_tx_bell_t; 3463 3464/** 3465 * cvmx_srio#_tx_bell_info 3466 * 3467 * SRIO_TX_BELL_INFO = SRIO Transmit Doorbell Interrupt Information 3468 * 3469 * The SRIO Outgoing (TX) Doorbell Interrupt Information 3470 * 3471 * Notes: 3472 * This register is only updated if the BELL_ERR bit is clear in SRIO(0..1)_INT_REG. This register 3473 * displays SRIO Information, Device ID, Transaction Type and Priority of the Doorbell Transaction 3474 * that generated the BELL_ERR Interrupt. The register includes either a RETRY, ERROR or TIMEOUT 3475 * Status. 3476 * 3477 * Clk_Rst: SRIO(0..1)_TX_BELL_INFO hclk hrst_n 3478 */ 3479union cvmx_sriox_tx_bell_info 3480{ 3481 uint64_t u64; 3482 struct cvmx_sriox_tx_bell_info_s 3483 { 3484#if __BYTE_ORDER == __BIG_ENDIAN 3485 uint64_t reserved_48_63 : 16; 3486 uint64_t data : 16; /**< Information field from last doorbell operation */ 3487 uint64_t dest_id : 16; /**< Doorbell Destination Device ID[15:0] */ 3488 uint64_t reserved_8_15 : 8; 3489 uint64_t timeout : 1; /**< Transmit Doorbell Failed with Timeout. */ 3490 uint64_t error : 1; /**< Transmit Doorbell Destination returned Error. */ 3491 uint64_t retry : 1; /**< Transmit Doorbell Requests a retransmission. */ 3492 uint64_t src_id : 1; /**< Source Device ID 0=Primary, 1=Secondary */ 3493 uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 3494 uint64_t reserved_2_2 : 1; 3495 uint64_t priority : 2; /**< Doorbell Priority */ 3496#else 3497 uint64_t priority : 2; 3498 uint64_t reserved_2_2 : 1; 3499 uint64_t id16 : 1; 3500 uint64_t src_id : 1; 3501 uint64_t retry : 1; 3502 uint64_t error : 1; 3503 uint64_t timeout : 1; 3504 uint64_t reserved_8_15 : 8; 3505 uint64_t dest_id : 16; 3506 uint64_t data : 16; 3507 uint64_t reserved_48_63 : 16; 3508#endif 3509 } s; 3510 struct cvmx_sriox_tx_bell_info_s cn63xx; 3511 struct cvmx_sriox_tx_bell_info_s cn63xxp1; 3512}; 3513typedef union cvmx_sriox_tx_bell_info cvmx_sriox_tx_bell_info_t; 3514 3515/** 3516 * cvmx_srio#_tx_ctrl 3517 * 3518 * SRIO_TX_CTRL = SRIO Transmit Control 3519 * 3520 * The SRIO Transmit Control 3521 * 3522 * Notes: 3523 * This register is used to control SRIO Outgoing Packet Allocation. TX_TH[2:0] set the thresholds 3524 * to allow each priority traffic to be queued for transmission. 8 TX Buffer are available. A 3525 * threshold greater than 8 stops all traffic on that priority and should be avoided. TAG_TH[2:0] 3526 * set the thresholds to allow priority traffic requiring responses to be queued based on the number 3527 * of outgoing tags (TIDs) available. 16 Tags are available. If a priority is blocked for lack of 3528 * tags then all lower priority packets are also blocked irregardless of whether they require tags. 3529 * 3530 * Clk_Rst: SRIO(0..1)_TX_CTRL hclk hrst_n 3531 */ 3532union cvmx_sriox_tx_ctrl 3533{ 3534 uint64_t u64; 3535 struct cvmx_sriox_tx_ctrl_s 3536 { 3537#if __BYTE_ORDER == __BIG_ENDIAN 3538 uint64_t reserved_53_63 : 11; 3539 uint64_t tag_th2 : 5; /**< Sets threshold for minimum number of OTAGs 3540 required before a packet of priority 2 requiring a 3541 response will be queued for transmission. (Max 16) 3542 There generally should be no priority 3 request 3543 packets which require a response/tag, so a TAG_THR 3544 value as low as 0 is allowed. */ 3545 uint64_t reserved_45_47 : 3; 3546 uint64_t tag_th1 : 5; /**< Sets threshold for minimum number of OTAGs 3547 required before a packet of priority 1 requiring a 3548 response will be queued for transmission. (Max 16) 3549 Generally, TAG_TH1 must be > TAG_TH2 to leave OTAGs 3550 for outgoing priority 2 (or 3) requests. */ 3551 uint64_t reserved_37_39 : 3; 3552 uint64_t tag_th0 : 5; /**< Sets threshold for minimum number of OTAGs 3553 required before a packet of priority 0 requiring a 3554 response will be queued for transmission. (Max 16) 3555 Generally, TAG_TH0 must be > TAG_TH1 to leave OTAGs 3556 for outgoing priority 1 or 2 (or 3) requests. */ 3557 uint64_t reserved_20_31 : 12; 3558 uint64_t tx_th2 : 4; /**< Sets threshold for minimum number of TX buffers 3559 before a Priority 2 Packet will be queued for 3560 transmission. (Max 8) 3561 Generally, TX_TH2 must be > 0 to leave space for 3562 outgoing priority 3 packets. */ 3563 uint64_t reserved_12_15 : 4; 3564 uint64_t tx_th1 : 4; /**< Sets threshold for minimum number of TX buffers 3565 before a Priority 1 Packet will be queued for 3566 transmission. (Max 8) 3567 Generally, TX_TH1 must be > TX_TH2 to leave space 3568 for outgoing priority 2 or 3 packets. */ 3569 uint64_t reserved_4_7 : 4; 3570 uint64_t tx_th0 : 4; /**< Sets threshold for minimum number of TX buffers 3571 before a Priority 0 Packet will be queued for 3572 transmission. (Max 8) 3573 Generally, TX_TH0 must be > TX_TH1 to leave space 3574 for outgoing priority 1 or 2 or 3 packets. */ 3575#else 3576 uint64_t tx_th0 : 4; 3577 uint64_t reserved_4_7 : 4; 3578 uint64_t tx_th1 : 4; 3579 uint64_t reserved_12_15 : 4; 3580 uint64_t tx_th2 : 4; 3581 uint64_t reserved_20_31 : 12; 3582 uint64_t tag_th0 : 5; 3583 uint64_t reserved_37_39 : 3; 3584 uint64_t tag_th1 : 5; 3585 uint64_t reserved_45_47 : 3; 3586 uint64_t tag_th2 : 5; 3587 uint64_t reserved_53_63 : 11; 3588#endif 3589 } s; 3590 struct cvmx_sriox_tx_ctrl_s cn63xx; 3591 struct cvmx_sriox_tx_ctrl_s cn63xxp1; 3592}; 3593typedef union cvmx_sriox_tx_ctrl cvmx_sriox_tx_ctrl_t; 3594 3595/** 3596 * cvmx_srio#_tx_emphasis 3597 * 3598 * SRIO_TX_EMPHASIS = SRIO TX Lane Emphasis (Pass 2) 3599 * 3600 * Controls TX Emphasis used by the SRIO SERDES 3601 * 3602 * Notes: 3603 * This controls the emphasis value used by the SRIO SERDES. This register is only reset during COLD 3604 * boot and may be modified regardless of the value in SRIO(0..1)_STATUS_REG.ACCESS. 3605 * 3606 * Clk_Rst: SRIO(0..1)_TX_EMPHASIS sclk srst_cold_n 3607 */ 3608union cvmx_sriox_tx_emphasis 3609{ 3610 uint64_t u64; 3611 struct cvmx_sriox_tx_emphasis_s 3612 { 3613#if __BYTE_ORDER == __BIG_ENDIAN 3614 uint64_t reserved_4_63 : 60; 3615 uint64_t emph : 4; /**< Emphasis Value used for all lanes. Default value 3616 is 0x0 for 1.25G b/s and 0xA for all other rates. */ 3617#else 3618 uint64_t emph : 4; 3619 uint64_t reserved_4_63 : 60; 3620#endif 3621 } s; 3622 struct cvmx_sriox_tx_emphasis_s cn63xx; 3623}; 3624typedef union cvmx_sriox_tx_emphasis cvmx_sriox_tx_emphasis_t; 3625 3626/** 3627 * cvmx_srio#_tx_status 3628 * 3629 * SRIO_TX_STATUS = SRIO Outbound Credits/Ops Status 3630 * 3631 * Specifies the current number of credits/ops by SRIO for Outbound Traffic 3632 * 3633 * Notes: 3634 * Debug Register specifying the number of credits/ops currently in use for Outbound Traffic. 3635 * When all outbound traffic has stopped the values should eventually return to the reset values. 3636 * 3637 * Clk_Rst: SRIO(0..1)_TX_STATUS hclk hrst_n 3638 */ 3639union cvmx_sriox_tx_status 3640{ 3641 uint64_t u64; 3642 struct cvmx_sriox_tx_status_s 3643 { 3644#if __BYTE_ORDER == __BIG_ENDIAN 3645 uint64_t reserved_32_63 : 32; 3646 uint64_t s2m_pr3 : 8; /**< Number of pending S2M Priority 3 Entries. */ 3647 uint64_t s2m_pr2 : 8; /**< Number of pending S2M Priority 2 Entries. */ 3648 uint64_t s2m_pr1 : 8; /**< Number of pending S2M Priority 1 Entries. */ 3649 uint64_t s2m_pr0 : 8; /**< Number of pending S2M Priority 0 Entries. */ 3650#else 3651 uint64_t s2m_pr0 : 8; 3652 uint64_t s2m_pr1 : 8; 3653 uint64_t s2m_pr2 : 8; 3654 uint64_t s2m_pr3 : 8; 3655 uint64_t reserved_32_63 : 32; 3656#endif 3657 } s; 3658 struct cvmx_sriox_tx_status_s cn63xx; 3659 struct cvmx_sriox_tx_status_s cn63xxp1; 3660}; 3661typedef union cvmx_sriox_tx_status cvmx_sriox_tx_status_t; 3662 3663/** 3664 * cvmx_srio#_wr_done_counts 3665 * 3666 * SRIO_WR_DONE_COUNTS = SRIO Outgoing Write Done Counts (Pass 2) 3667 * 3668 * The SRIO Outbound Write Done Counts 3669 * 3670 * Notes: 3671 * This register shows the number of successful and unsuccessful NwriteRs issued through this MAC. 3672 * These count only considers the last NwriteR generated by each Store Instruction. If any NwriteR 3673 * in the series receives an ERROR Status then it is reported in SRIOMAINT(0..1)_ERB_LT_ERR_DET.IO_ERR. 3674 * If any NwriteR does not receive a response within the timeout period then it is reported in 3675 * SRIOMAINT(0..1)_ERB_LT_ERR_DET.PKT_TOUT. Only errors on the last NwriteR's are counted as BAD. This 3676 * register is typically not written while Outbound SRIO Memory traffic is enabled. 3677 * 3678 * Clk_Rst: SRIO(0..1)_WR_DONE_COUNTS hclk hrst_n 3679 */ 3680union cvmx_sriox_wr_done_counts 3681{ 3682 uint64_t u64; 3683 struct cvmx_sriox_wr_done_counts_s 3684 { 3685#if __BYTE_ORDER == __BIG_ENDIAN 3686 uint64_t reserved_32_63 : 32; 3687 uint64_t bad : 16; /**< Count of the final outbound NwriteR in the series 3688 associated with a Store Operation that have timed 3689 out or received a response with an ERROR status. */ 3690 uint64_t good : 16; /**< Count of the final outbound NwriteR in the series 3691 associated with a Store operation that has 3692 received a response with a DONE status. */ 3693#else 3694 uint64_t good : 16; 3695 uint64_t bad : 16; 3696 uint64_t reserved_32_63 : 32; 3697#endif 3698 } s; 3699 struct cvmx_sriox_wr_done_counts_s cn63xx; 3700}; 3701typedef union cvmx_sriox_wr_done_counts cvmx_sriox_wr_done_counts_t; 3702 3703#endif 3704