1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-spxx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon spxx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_SPXX_DEFS_H__ 53232812Sjmallett#define __CVMX_SPXX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_SPXX_BCKPRS_CNT(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 61215976Sjmallett cvmx_warn("CVMX_SPXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id); 62215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull; 63215976Sjmallett} 64215976Sjmallett#else 65215976Sjmallett#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_SPXX_BIST_STAT(unsigned long block_id) 69215976Sjmallett{ 70215976Sjmallett if (!( 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 73215976Sjmallett cvmx_warn("CVMX_SPXX_BIST_STAT(%lu) is invalid on this chip\n", block_id); 74215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull; 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallettstatic inline uint64_t CVMX_SPXX_CLK_CTL(unsigned long block_id) 81215976Sjmallett{ 82215976Sjmallett if (!( 83215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 84215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 85215976Sjmallett cvmx_warn("CVMX_SPXX_CLK_CTL(%lu) is invalid on this chip\n", block_id); 86215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull; 87215976Sjmallett} 88215976Sjmallett#else 89215976Sjmallett#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull) 90215976Sjmallett#endif 91215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92215976Sjmallettstatic inline uint64_t CVMX_SPXX_CLK_STAT(unsigned long block_id) 93215976Sjmallett{ 94215976Sjmallett if (!( 95215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 96215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 97215976Sjmallett cvmx_warn("CVMX_SPXX_CLK_STAT(%lu) is invalid on this chip\n", block_id); 98215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallettstatic inline uint64_t CVMX_SPXX_DBG_DESKEW_CTL(unsigned long block_id) 105215976Sjmallett{ 106215976Sjmallett if (!( 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 109215976Sjmallett cvmx_warn("CVMX_SPXX_DBG_DESKEW_CTL(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_SPXX_DBG_DESKEW_STATE(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 121215976Sjmallett cvmx_warn("CVMX_SPXX_DBG_DESKEW_STATE(%lu) is invalid on this chip\n", block_id); 122215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull; 123215976Sjmallett} 124215976Sjmallett#else 125215976Sjmallett#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull) 126215976Sjmallett#endif 127215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128215976Sjmallettstatic inline uint64_t CVMX_SPXX_DRV_CTL(unsigned long block_id) 129215976Sjmallett{ 130215976Sjmallett if (!( 131215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 132215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 133215976Sjmallett cvmx_warn("CVMX_SPXX_DRV_CTL(%lu) is invalid on this chip\n", block_id); 134215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull; 135215976Sjmallett} 136215976Sjmallett#else 137215976Sjmallett#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull) 138215976Sjmallett#endif 139215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 140215976Sjmallettstatic inline uint64_t CVMX_SPXX_ERR_CTL(unsigned long block_id) 141215976Sjmallett{ 142215976Sjmallett if (!( 143215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 144215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 145215976Sjmallett cvmx_warn("CVMX_SPXX_ERR_CTL(%lu) is invalid on this chip\n", block_id); 146215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull; 147215976Sjmallett} 148215976Sjmallett#else 149215976Sjmallett#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull) 150215976Sjmallett#endif 151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152215976Sjmallettstatic inline uint64_t CVMX_SPXX_INT_DAT(unsigned long block_id) 153215976Sjmallett{ 154215976Sjmallett if (!( 155215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 156215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 157215976Sjmallett cvmx_warn("CVMX_SPXX_INT_DAT(%lu) is invalid on this chip\n", block_id); 158215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull; 159215976Sjmallett} 160215976Sjmallett#else 161215976Sjmallett#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull) 162215976Sjmallett#endif 163215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164215976Sjmallettstatic inline uint64_t CVMX_SPXX_INT_MSK(unsigned long block_id) 165215976Sjmallett{ 166215976Sjmallett if (!( 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 169215976Sjmallett cvmx_warn("CVMX_SPXX_INT_MSK(%lu) is invalid on this chip\n", block_id); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull; 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_SPXX_INT_REG(unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 181215976Sjmallett cvmx_warn("CVMX_SPXX_INT_REG(%lu) is invalid on this chip\n", block_id); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull; 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallettstatic inline uint64_t CVMX_SPXX_INT_SYNC(unsigned long block_id) 189215976Sjmallett{ 190215976Sjmallett if (!( 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 192215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 193215976Sjmallett cvmx_warn("CVMX_SPXX_INT_SYNC(%lu) is invalid on this chip\n", block_id); 194215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull; 195215976Sjmallett} 196215976Sjmallett#else 197215976Sjmallett#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull) 198215976Sjmallett#endif 199215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200215976Sjmallettstatic inline uint64_t CVMX_SPXX_TPA_ACC(unsigned long block_id) 201215976Sjmallett{ 202215976Sjmallett if (!( 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 205215976Sjmallett cvmx_warn("CVMX_SPXX_TPA_ACC(%lu) is invalid on this chip\n", block_id); 206215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull; 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallettstatic inline uint64_t CVMX_SPXX_TPA_MAX(unsigned long block_id) 213215976Sjmallett{ 214215976Sjmallett if (!( 215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 217215976Sjmallett cvmx_warn("CVMX_SPXX_TPA_MAX(%lu) is invalid on this chip\n", block_id); 218215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull; 219215976Sjmallett} 220215976Sjmallett#else 221215976Sjmallett#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull) 222215976Sjmallett#endif 223215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 224215976Sjmallettstatic inline uint64_t CVMX_SPXX_TPA_SEL(unsigned long block_id) 225215976Sjmallett{ 226215976Sjmallett if (!( 227215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 229215976Sjmallett cvmx_warn("CVMX_SPXX_TPA_SEL(%lu) is invalid on this chip\n", block_id); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_SPXX_TRN4_CTL(unsigned long block_id) 237215976Sjmallett{ 238215976Sjmallett if (!( 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 241215976Sjmallett cvmx_warn("CVMX_SPXX_TRN4_CTL(%lu) is invalid on this chip\n", block_id); 242215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull; 243215976Sjmallett} 244215976Sjmallett#else 245215976Sjmallett#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull) 246215976Sjmallett#endif 247215976Sjmallett 248215976Sjmallett/** 249215976Sjmallett * cvmx_spx#_bckprs_cnt 250215976Sjmallett */ 251232812Sjmallettunion cvmx_spxx_bckprs_cnt { 252215976Sjmallett uint64_t u64; 253232812Sjmallett struct cvmx_spxx_bckprs_cnt_s { 254232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 255215976Sjmallett uint64_t reserved_32_63 : 32; 256215976Sjmallett uint64_t cnt : 32; /**< Counts the number of core clock cycles in which 257215976Sjmallett the SPI-4.2 receiver receives data once the TPA 258215976Sjmallett for a particular port has been deasserted. The 259215976Sjmallett desired port to watch can be selected with the 260215976Sjmallett SPX_TPA_SEL[PRTSEL] field. CNT can be cleared by 261215976Sjmallett writing all 1s to it. */ 262215976Sjmallett#else 263215976Sjmallett uint64_t cnt : 32; 264215976Sjmallett uint64_t reserved_32_63 : 32; 265215976Sjmallett#endif 266215976Sjmallett } s; 267215976Sjmallett struct cvmx_spxx_bckprs_cnt_s cn38xx; 268215976Sjmallett struct cvmx_spxx_bckprs_cnt_s cn38xxp2; 269215976Sjmallett struct cvmx_spxx_bckprs_cnt_s cn58xx; 270215976Sjmallett struct cvmx_spxx_bckprs_cnt_s cn58xxp1; 271215976Sjmallett}; 272215976Sjmalletttypedef union cvmx_spxx_bckprs_cnt cvmx_spxx_bckprs_cnt_t; 273215976Sjmallett 274215976Sjmallett/** 275215976Sjmallett * cvmx_spx#_bist_stat 276215976Sjmallett * 277215976Sjmallett * Notes: 278215976Sjmallett * Bist results encoding 279215976Sjmallett * - 0: good (or bist in progress/never run) 280215976Sjmallett * - 1: bad 281215976Sjmallett */ 282232812Sjmallettunion cvmx_spxx_bist_stat { 283215976Sjmallett uint64_t u64; 284232812Sjmallett struct cvmx_spxx_bist_stat_s { 285232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 286215976Sjmallett uint64_t reserved_3_63 : 61; 287215976Sjmallett uint64_t stat2 : 1; /**< Bist Results/No Repair (Tx calendar table) 288215976Sjmallett (spx.stx.cal.calendar) */ 289215976Sjmallett uint64_t stat1 : 1; /**< Bist Results/No Repair (Rx calendar table) 290215976Sjmallett (spx.srx.spi4.cal.calendar) */ 291215976Sjmallett uint64_t stat0 : 1; /**< Bist Results/No Repair (Spi4 receive datapath FIFO) 292215976Sjmallett (spx.srx.spi4.dat.dpr) */ 293215976Sjmallett#else 294215976Sjmallett uint64_t stat0 : 1; 295215976Sjmallett uint64_t stat1 : 1; 296215976Sjmallett uint64_t stat2 : 1; 297215976Sjmallett uint64_t reserved_3_63 : 61; 298215976Sjmallett#endif 299215976Sjmallett } s; 300215976Sjmallett struct cvmx_spxx_bist_stat_s cn38xx; 301215976Sjmallett struct cvmx_spxx_bist_stat_s cn38xxp2; 302215976Sjmallett struct cvmx_spxx_bist_stat_s cn58xx; 303215976Sjmallett struct cvmx_spxx_bist_stat_s cn58xxp1; 304215976Sjmallett}; 305215976Sjmalletttypedef union cvmx_spxx_bist_stat cvmx_spxx_bist_stat_t; 306215976Sjmallett 307215976Sjmallett/** 308215976Sjmallett * cvmx_spx#_clk_ctl 309215976Sjmallett * 310215976Sjmallett * Notes: 311215976Sjmallett * * SRXDLCK 312215976Sjmallett * When asserted, this bit locks the Spi4 receive DLLs. This bit also 313215976Sjmallett * acts as the Spi4 receiver reset and must be asserted before the 314215976Sjmallett * training sequences are used to initialize the interface. This bit 315215976Sjmallett * only applies to the receiver interface. 316215976Sjmallett * 317215976Sjmallett * * RCVTRN 318215976Sjmallett * Once the SRXDLCK bit is asserted and the DLLs have locked and the 319215976Sjmallett * system has been programmed, software should assert this bit in order 320215976Sjmallett * to start looking for valid training sequence and synchronize the 321215976Sjmallett * interface. This bit only applies to the receiver interface. 322215976Sjmallett * 323215976Sjmallett * * DRPTRN 324215976Sjmallett * The Spi4 receiver can either convert training packets into NOPs or 325215976Sjmallett * drop them entirely. Dropping ticks allows the interface to deskew 326215976Sjmallett * periodically if the dclk and eclk ratios are close. This bit only 327215976Sjmallett * applies to the receiver interface. 328215976Sjmallett * 329215976Sjmallett * * SNDTRN 330215976Sjmallett * When software sets this bit, it indicates that the Spi4 transmit 331215976Sjmallett * interface has been setup and has seen the calendare status. Once the 332215976Sjmallett * transmitter begins sending training data, the receiving device is free 333215976Sjmallett * to start traversing the calendar table to synch the link. 334215976Sjmallett * 335215976Sjmallett * * STATRCV 336215976Sjmallett * This bit determines which status clock edge to sample the status 337215976Sjmallett * channel in Spi4 mode. Since the status channel is in the opposite 338215976Sjmallett * direction to the datapath, the STATRCV actually effects the 339215976Sjmallett * transmitter/TX block. 340215976Sjmallett * 341215976Sjmallett * * STATDRV 342215976Sjmallett * This bit determines which status clock edge to drive the status 343215976Sjmallett * channel in Spi4 mode. Since the status channel is in the opposite 344215976Sjmallett * direction to the datapath, the STATDRV actually effects the 345215976Sjmallett * receiver/RX block. 346215976Sjmallett * 347215976Sjmallett * * RUNBIST 348215976Sjmallett * RUNBIST will beginning BIST/BISR in all the SPX compilied memories. 349215976Sjmallett * These memories are... 350215976Sjmallett * 351215976Sjmallett * * spx.srx.spi4.dat.dpr // FIFO Spi4 to IMX 352215976Sjmallett * * spx.stx.cal.calendar // Spi4 TX calendar table 353215976Sjmallett * * spx.srx.spi4.cal.calendar // Spi4 RX calendar table 354215976Sjmallett * 355215976Sjmallett * RUNBIST must never be asserted when the interface is enabled. 356215976Sjmallett * Furthmore, setting RUNBIST at any other time is destructive and can 357215976Sjmallett * cause data and configuration corruption. The entire interface must be 358215976Sjmallett * reconfigured when this bit is set. 359215976Sjmallett * 360215976Sjmallett * * CLKDLY 361215976Sjmallett * CLKDLY should be kept at its reset value during normal operation. This 362215976Sjmallett * register controls the SPI4.2 static clock positioning which normally only is 363215976Sjmallett * set to the non-reset value in quarter clocking schemes. In this mode, the 364215976Sjmallett * delay window is not large enough for slow clock freq, therefore clock and 365215976Sjmallett * data must be statically positioned with CSRs. By changing the clock position 366215976Sjmallett * relative to the data bits, we give the system a wider window. 367215976Sjmallett * 368215976Sjmallett * * SEETRN 369215976Sjmallett * In systems in which no training data is sent to N2 or N2 cannot 370215976Sjmallett * correctly sample the training data, software may pulse this bit by 371215976Sjmallett * writing a '1' followed by a '0' in order to correctly set the 372215976Sjmallett * receivers state. The receive data bus should be idle at this time 373215976Sjmallett * (only NOPs on the bus). If N2 cannot see at least on training 374215976Sjmallett * sequence, the data bus will not send any data to the core. The 375215976Sjmallett * interface will hang. 376215976Sjmallett */ 377232812Sjmallettunion cvmx_spxx_clk_ctl { 378215976Sjmallett uint64_t u64; 379232812Sjmallett struct cvmx_spxx_clk_ctl_s { 380232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 381215976Sjmallett uint64_t reserved_17_63 : 47; 382215976Sjmallett uint64_t seetrn : 1; /**< Force the Spi4 receive into seeing a traing 383215976Sjmallett sequence */ 384215976Sjmallett uint64_t reserved_12_15 : 4; 385215976Sjmallett uint64_t clkdly : 5; /**< Set the spx__clkdly lines to this value to 386215976Sjmallett control the delay on the incoming dclk 387215976Sjmallett (spx__clkdly) */ 388215976Sjmallett uint64_t runbist : 1; /**< Write this bit to begin BIST testing in SPX */ 389215976Sjmallett uint64_t statdrv : 1; /**< Spi4 status channel drive mode 390215976Sjmallett - 1: Drive STAT on posedge of SCLK 391215976Sjmallett - 0: Drive STAT on negedge of SCLK */ 392215976Sjmallett uint64_t statrcv : 1; /**< Spi4 status channel sample mode 393215976Sjmallett - 1: Sample STAT on posedge of SCLK 394215976Sjmallett - 0: Sample STAT on negedge of SCLK */ 395215976Sjmallett uint64_t sndtrn : 1; /**< Start sending training patterns on the Spi4 396215976Sjmallett Tx Interface */ 397215976Sjmallett uint64_t drptrn : 1; /**< Drop blocks of training packets */ 398215976Sjmallett uint64_t rcvtrn : 1; /**< Write this bit once the DLL is locked to sync 399215976Sjmallett on the training seqeunce */ 400215976Sjmallett uint64_t srxdlck : 1; /**< Write this bit to lock the Spi4 receive DLL */ 401215976Sjmallett#else 402215976Sjmallett uint64_t srxdlck : 1; 403215976Sjmallett uint64_t rcvtrn : 1; 404215976Sjmallett uint64_t drptrn : 1; 405215976Sjmallett uint64_t sndtrn : 1; 406215976Sjmallett uint64_t statrcv : 1; 407215976Sjmallett uint64_t statdrv : 1; 408215976Sjmallett uint64_t runbist : 1; 409215976Sjmallett uint64_t clkdly : 5; 410215976Sjmallett uint64_t reserved_12_15 : 4; 411215976Sjmallett uint64_t seetrn : 1; 412215976Sjmallett uint64_t reserved_17_63 : 47; 413215976Sjmallett#endif 414215976Sjmallett } s; 415215976Sjmallett struct cvmx_spxx_clk_ctl_s cn38xx; 416215976Sjmallett struct cvmx_spxx_clk_ctl_s cn38xxp2; 417215976Sjmallett struct cvmx_spxx_clk_ctl_s cn58xx; 418215976Sjmallett struct cvmx_spxx_clk_ctl_s cn58xxp1; 419215976Sjmallett}; 420215976Sjmalletttypedef union cvmx_spxx_clk_ctl cvmx_spxx_clk_ctl_t; 421215976Sjmallett 422215976Sjmallett/** 423215976Sjmallett * cvmx_spx#_clk_stat 424215976Sjmallett */ 425232812Sjmallettunion cvmx_spxx_clk_stat { 426215976Sjmallett uint64_t u64; 427232812Sjmallett struct cvmx_spxx_clk_stat_s { 428232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 429215976Sjmallett uint64_t reserved_11_63 : 53; 430215976Sjmallett uint64_t stxcal : 1; /**< The transistion from Sync to Calendar on status 431215976Sjmallett channel */ 432215976Sjmallett uint64_t reserved_9_9 : 1; 433215976Sjmallett uint64_t srxtrn : 1; /**< Saw a good data training sequence */ 434215976Sjmallett uint64_t s4clk1 : 1; /**< Saw '1' on Spi4 transmit status forward clk input */ 435215976Sjmallett uint64_t s4clk0 : 1; /**< Saw '0' on Spi4 transmit status forward clk input */ 436215976Sjmallett uint64_t d4clk1 : 1; /**< Saw '1' on Spi4 receive data forward clk input */ 437215976Sjmallett uint64_t d4clk0 : 1; /**< Saw '0' on Spi4 receive data forward clk input */ 438215976Sjmallett uint64_t reserved_0_3 : 4; 439215976Sjmallett#else 440215976Sjmallett uint64_t reserved_0_3 : 4; 441215976Sjmallett uint64_t d4clk0 : 1; 442215976Sjmallett uint64_t d4clk1 : 1; 443215976Sjmallett uint64_t s4clk0 : 1; 444215976Sjmallett uint64_t s4clk1 : 1; 445215976Sjmallett uint64_t srxtrn : 1; 446215976Sjmallett uint64_t reserved_9_9 : 1; 447215976Sjmallett uint64_t stxcal : 1; 448215976Sjmallett uint64_t reserved_11_63 : 53; 449215976Sjmallett#endif 450215976Sjmallett } s; 451215976Sjmallett struct cvmx_spxx_clk_stat_s cn38xx; 452215976Sjmallett struct cvmx_spxx_clk_stat_s cn38xxp2; 453215976Sjmallett struct cvmx_spxx_clk_stat_s cn58xx; 454215976Sjmallett struct cvmx_spxx_clk_stat_s cn58xxp1; 455215976Sjmallett}; 456215976Sjmalletttypedef union cvmx_spxx_clk_stat cvmx_spxx_clk_stat_t; 457215976Sjmallett 458215976Sjmallett/** 459215976Sjmallett * cvmx_spx#_dbg_deskew_ctl 460215976Sjmallett * 461215976Sjmallett * Notes: 462215976Sjmallett * These bits are meant as a backdoor to control Spi4 per-bit deskew. See 463215976Sjmallett * that Spec for more details. 464215976Sjmallett * 465215976Sjmallett * The basic idea is to allow software to disable the auto-deskew widgets 466215976Sjmallett * and make any adjustments by hand. These steps should only be taken 467215976Sjmallett * once the RCVTRN bit is set and before any real traffic is sent on the 468215976Sjmallett * Spi4 bus. Great care should be taken when messing with these bits as 469215976Sjmallett * improper programmings can cause catestrophic or intermitent problems. 470215976Sjmallett * 471215976Sjmallett * The params we have to test are the MUX tap selects and the XCV delay 472215976Sjmallett * tap selects. 473215976Sjmallett * 474215976Sjmallett * For the muxes, we can set each tap to a random value and then read 475215976Sjmallett * back the taps. To write... 476215976Sjmallett * 477215976Sjmallett * SPXX_DBG_DESKEW_CTL[BITSEL] = bit to set 478215976Sjmallett * SPXX_DBG_DESKEW_CTL[OFFSET] = mux tap value (2-bits) 479215976Sjmallett * SPXX_DBG_DESKEW_CTL[MUX] = go bit 480215976Sjmallett * 481215976Sjmallett * Notice this can all happen with a single CSR write. To read, first 482215976Sjmallett * set the bit you to look at with the SPXX_DBG_DESKEW_CTL[BITSEL], then 483215976Sjmallett * simply read SPXX_DBG_DESKEW_STATE[MUXSEL]... 484215976Sjmallett * 485215976Sjmallett * SPXX_DBG_DESKEW_CTL[BITSEL] = bit to set 486215976Sjmallett * SPXX_DBG_DESKEW_STATE[MUXSEL] = 2-bit value 487215976Sjmallett * 488215976Sjmallett * For the xcv delay taps, the CSR controls increment and decrement the 489215976Sjmallett * 5-bit count value in the XCV. This is a saturating counter, so it 490215976Sjmallett * will not wrap when decrementing below zero or incrementing above 31. 491215976Sjmallett * 492215976Sjmallett * To write... 493215976Sjmallett * 494215976Sjmallett * SPXX_DBG_DESKEW_CTL[BITSEL] = bit to set 495215976Sjmallett * SPXX_DBG_DESKEW_CTL[OFFSET] = tap value increment or decrement amount (5-bits) 496215976Sjmallett * SPXX_DBG_DESKEW_CTL[INC|DEC] = go bit 497215976Sjmallett * 498215976Sjmallett * These values are copied in SPX, so that they can be read back by 499215976Sjmallett * software by a similar mechanism to the MUX selects... 500215976Sjmallett * 501215976Sjmallett * SPXX_DBG_DESKEW_CTL[BITSEL] = bit to set 502215976Sjmallett * SPXX_DBG_DESKEW_STATE[OFFSET] = 5-bit value 503215976Sjmallett * 504215976Sjmallett * In addition, there is a reset bit that sets all the state back to the 505215976Sjmallett * default/starting value of 0x10. 506215976Sjmallett * 507215976Sjmallett * SPXX_DBG_DESKEW_CTL[CLRDLY] = 1 508215976Sjmallett * 509215976Sjmallett * SINGLE STEP TRAINING MODE (WILMA) 510215976Sjmallett * Debug feature that will enable the user to single-step the debug 511215976Sjmallett * logic to watch initial movement and trends by putting the training 512215976Sjmallett * machine in single step mode. 513215976Sjmallett * 514215976Sjmallett * * SPX*_DBG_DESKEW_CTL[SSTEP] 515215976Sjmallett * This will put the training control logic into single step mode. We 516215976Sjmallett * will not deskew in this scenario and will require the TX device to 517215976Sjmallett * send continuous training sequences. 518215976Sjmallett * 519215976Sjmallett * It is required that SRX*_COM_CTL[INF_EN] be clear so that suspect 520215976Sjmallett * data does not flow into the chip. 521215976Sjmallett * 522215976Sjmallett * Deasserting SPX*_DBG_DESKEW_CTL[SSTEP] will attempt to deskew as per 523215976Sjmallett * the normal definition. Single step mode is for debug only. Special 524215976Sjmallett * care must be given to correctly deskew the interface if normal 525215976Sjmallett * operation is desired. 526215976Sjmallett * 527215976Sjmallett * * SPX*_DBG_DESKEW_CTL[SSTEP_GO] 528215976Sjmallett * Each write of '1' to SSTEP_GO will go through a single training 529215976Sjmallett * iteration and will perform... 530215976Sjmallett * 531215976Sjmallett * - DLL update, if SPX*_DBG_DESKEW_CTL[DLLDIS] is clear 532215976Sjmallett * - coarse update, if SPX*_TRN4_CTL[MUX_EN] is set 533215976Sjmallett * - single fine update, if SPX*_TRN4_CTL[MACRO_EN] is set and an edge 534215976Sjmallett * was detected after walked +/- SPX*_TRN4_CTL[MAXDIST] taps. 535215976Sjmallett * 536215976Sjmallett * Writes to this register have no effect if the interface is not in 537215976Sjmallett * SSTEP mode (SPX*_DBG_DESKEW_CTL[SSTEP]). 538215976Sjmallett * 539215976Sjmallett * The WILMA mode will be cleared at the final state transition, so 540215976Sjmallett * that software can set SPX*_DBG_DESKEW_CTL[SSTEP] and 541215976Sjmallett * SPX*_DBG_DESKEW_CTL[SSTEP_GO] before setting SPX*_CLK_CTL[RCVTRN] 542215976Sjmallett * and the machine will go through the initial iteration and stop - 543215976Sjmallett * waiting for another SPX*_DBG_DESKEW_CTL[SSTEP_GO] or an interface 544215976Sjmallett * enable. 545215976Sjmallett * 546215976Sjmallett * * SPX*_DBG_DESKEW_CTL[FALL8] 547215976Sjmallett * Determines how many pattern matches are required during training 548215976Sjmallett * operations to fallout of training and begin processing the normal data 549215976Sjmallett * stream. The default value is 10 pattern matches. The pattern that is 550215976Sjmallett * used is dependent on the SPX*_DBG_DESKEW_CTL[FALLNOP] CSR which 551215976Sjmallett * determines between non-training packets (the default) and NOPs. 552215976Sjmallett * 553215976Sjmallett * * SPX*_DBG_DESKEW_CTL[FALLNOP] 554215976Sjmallett * Determines the pattern that is required during training operations to 555215976Sjmallett * fallout of training and begin processing the normal data stream. The 556215976Sjmallett * default value is to match against non-training data. Setting this 557215976Sjmallett * bit, changes the behavior to watch for NOPs packet instead. 558215976Sjmallett * 559215976Sjmallett * This bit should not be changed dynamically while the link is 560215976Sjmallett * operational. 561215976Sjmallett */ 562232812Sjmallettunion cvmx_spxx_dbg_deskew_ctl { 563215976Sjmallett uint64_t u64; 564232812Sjmallett struct cvmx_spxx_dbg_deskew_ctl_s { 565232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 566215976Sjmallett uint64_t reserved_30_63 : 34; 567215976Sjmallett uint64_t fallnop : 1; /**< Training fallout on NOP matches instead of 568215976Sjmallett non-training matches. 569215976Sjmallett (spx_csr__spi4_fallout_nop) */ 570215976Sjmallett uint64_t fall8 : 1; /**< Training fallout at 8 pattern matches instead of 10 571215976Sjmallett (spx_csr__spi4_fallout_8_match) */ 572215976Sjmallett uint64_t reserved_26_27 : 2; 573215976Sjmallett uint64_t sstep_go : 1; /**< Single Step Training Sequence 574215976Sjmallett (spx_csr__spi4_single_step_go) */ 575215976Sjmallett uint64_t sstep : 1; /**< Single Step Training Mode 576215976Sjmallett (spx_csr__spi4_single_step_mode) */ 577215976Sjmallett uint64_t reserved_22_23 : 2; 578215976Sjmallett uint64_t clrdly : 1; /**< Resets the offset control in the XCV 579215976Sjmallett (spx_csr__spi4_dll_clr_dly) */ 580215976Sjmallett uint64_t dec : 1; /**< Decrement the offset by OFFSET for the Spi4 581215976Sjmallett bit selected by BITSEL 582215976Sjmallett (spx_csr__spi4_dbg_trn_dec) */ 583215976Sjmallett uint64_t inc : 1; /**< Increment the offset by OFFSET for the Spi4 584215976Sjmallett bit selected by BITSEL 585215976Sjmallett (spx_csr__spi4_dbg_trn_inc) */ 586215976Sjmallett uint64_t mux : 1; /**< Set the mux select tap for the Spi4 bit 587215976Sjmallett selected by BITSEL 588215976Sjmallett (spx_csr__spi4_dbg_trn_mux) */ 589215976Sjmallett uint64_t offset : 5; /**< Adds or subtracts (Based on INC or DEC) the 590215976Sjmallett offset to Spi4 bit BITSEL. 591215976Sjmallett (spx_csr__spi4_dbg_trn_offset) */ 592215976Sjmallett uint64_t bitsel : 5; /**< Select the Spi4 CTL or DAT bit 593215976Sjmallett 15-0 : Spi4 DAT[15:0] 594215976Sjmallett 16 : Spi4 CTL 595215976Sjmallett - 31-17: Invalid 596215976Sjmallett (spx_csr__spi4_dbg_trn_bitsel) */ 597215976Sjmallett uint64_t offdly : 6; /**< Set the spx__offset lines to this value when 598215976Sjmallett not in macro sequence 599215976Sjmallett (spx_csr__spi4_mac_offdly) */ 600215976Sjmallett uint64_t dllfrc : 1; /**< Force the Spi4 RX DLL to update 601215976Sjmallett (spx_csr__spi4_dll_force) */ 602215976Sjmallett uint64_t dlldis : 1; /**< Disable sending the update signal to the Spi4 603215976Sjmallett RX DLL when set 604215976Sjmallett (spx_csr__spi4_dll_trn_en) */ 605215976Sjmallett#else 606215976Sjmallett uint64_t dlldis : 1; 607215976Sjmallett uint64_t dllfrc : 1; 608215976Sjmallett uint64_t offdly : 6; 609215976Sjmallett uint64_t bitsel : 5; 610215976Sjmallett uint64_t offset : 5; 611215976Sjmallett uint64_t mux : 1; 612215976Sjmallett uint64_t inc : 1; 613215976Sjmallett uint64_t dec : 1; 614215976Sjmallett uint64_t clrdly : 1; 615215976Sjmallett uint64_t reserved_22_23 : 2; 616215976Sjmallett uint64_t sstep : 1; 617215976Sjmallett uint64_t sstep_go : 1; 618215976Sjmallett uint64_t reserved_26_27 : 2; 619215976Sjmallett uint64_t fall8 : 1; 620215976Sjmallett uint64_t fallnop : 1; 621215976Sjmallett uint64_t reserved_30_63 : 34; 622215976Sjmallett#endif 623215976Sjmallett } s; 624215976Sjmallett struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; 625215976Sjmallett struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; 626215976Sjmallett struct cvmx_spxx_dbg_deskew_ctl_s cn58xx; 627215976Sjmallett struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1; 628215976Sjmallett}; 629215976Sjmalletttypedef union cvmx_spxx_dbg_deskew_ctl cvmx_spxx_dbg_deskew_ctl_t; 630215976Sjmallett 631215976Sjmallett/** 632215976Sjmallett * cvmx_spx#_dbg_deskew_state 633215976Sjmallett * 634215976Sjmallett * Notes: 635215976Sjmallett * These bits are meant as a backdoor to control Spi4 per-bit deskew. See 636215976Sjmallett * that Spec for more details. 637215976Sjmallett */ 638232812Sjmallettunion cvmx_spxx_dbg_deskew_state { 639215976Sjmallett uint64_t u64; 640232812Sjmallett struct cvmx_spxx_dbg_deskew_state_s { 641232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 642215976Sjmallett uint64_t reserved_9_63 : 55; 643215976Sjmallett uint64_t testres : 1; /**< Training Test Mode Result 644215976Sjmallett (srx_spi4__test_mode_result) */ 645215976Sjmallett uint64_t unxterm : 1; /**< Unexpected training terminiation 646215976Sjmallett (srx_spi4__top_unxexp_trn_term) */ 647215976Sjmallett uint64_t muxsel : 2; /**< The mux select value of the bit selected by 648215976Sjmallett SPX_DBG_DESKEW_CTL[BITSEL] 649215976Sjmallett (srx_spi4__trn_mux_sel) */ 650215976Sjmallett uint64_t offset : 5; /**< The counter value of the bit selected by 651215976Sjmallett SPX_DBG_DESKEW_CTL[BITSEL] 652215976Sjmallett (srx_spi4__xcv_tap_select) */ 653215976Sjmallett#else 654215976Sjmallett uint64_t offset : 5; 655215976Sjmallett uint64_t muxsel : 2; 656215976Sjmallett uint64_t unxterm : 1; 657215976Sjmallett uint64_t testres : 1; 658215976Sjmallett uint64_t reserved_9_63 : 55; 659215976Sjmallett#endif 660215976Sjmallett } s; 661215976Sjmallett struct cvmx_spxx_dbg_deskew_state_s cn38xx; 662215976Sjmallett struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; 663215976Sjmallett struct cvmx_spxx_dbg_deskew_state_s cn58xx; 664215976Sjmallett struct cvmx_spxx_dbg_deskew_state_s cn58xxp1; 665215976Sjmallett}; 666215976Sjmalletttypedef union cvmx_spxx_dbg_deskew_state cvmx_spxx_dbg_deskew_state_t; 667215976Sjmallett 668215976Sjmallett/** 669215976Sjmallett * cvmx_spx#_drv_ctl 670215976Sjmallett * 671215976Sjmallett * Notes: 672215976Sjmallett * These bits all come from Duke - he will provide documentation and 673215976Sjmallett * explanation. I'll just butcher it. 674215976Sjmallett */ 675232812Sjmallettunion cvmx_spxx_drv_ctl { 676215976Sjmallett uint64_t u64; 677232812Sjmallett struct cvmx_spxx_drv_ctl_s { 678232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 679215976Sjmallett uint64_t reserved_0_63 : 64; 680215976Sjmallett#else 681215976Sjmallett uint64_t reserved_0_63 : 64; 682215976Sjmallett#endif 683215976Sjmallett } s; 684232812Sjmallett struct cvmx_spxx_drv_ctl_cn38xx { 685232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 686215976Sjmallett uint64_t reserved_16_63 : 48; 687215976Sjmallett uint64_t stx4ncmp : 4; /**< Duke (spx__spi4_tx_nctl_comp) */ 688215976Sjmallett uint64_t stx4pcmp : 4; /**< Duke (spx__spi4_tx_pctl_comp) */ 689215976Sjmallett uint64_t srx4cmp : 8; /**< Duke (spx__spi4_rx_rctl_comp) */ 690215976Sjmallett#else 691215976Sjmallett uint64_t srx4cmp : 8; 692215976Sjmallett uint64_t stx4pcmp : 4; 693215976Sjmallett uint64_t stx4ncmp : 4; 694215976Sjmallett uint64_t reserved_16_63 : 48; 695215976Sjmallett#endif 696215976Sjmallett } cn38xx; 697215976Sjmallett struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; 698232812Sjmallett struct cvmx_spxx_drv_ctl_cn58xx { 699232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 700215976Sjmallett uint64_t reserved_24_63 : 40; 701232812Sjmallett uint64_t stx4ncmp : 4; /**< Not used in CN58XX (spx__spi4_tx_nctl_comp) */ 702232812Sjmallett uint64_t stx4pcmp : 4; /**< Not used in CN58XX (spx__spi4_tx_pctl_comp) */ 703215976Sjmallett uint64_t reserved_10_15 : 6; 704232812Sjmallett uint64_t srx4cmp : 10; /**< Suresh (spx__spi4_rx_rctl_comp) 705232812Sjmallett Can be used to bypass the RX termination resistor 706232812Sjmallett value. We have an on-chip RX termination resistor 707232812Sjmallett compensation control block, which adjusts the 708232812Sjmallett resistor value to a nominal 100 ohms. This 709232812Sjmallett register can be used to bypass this automatically 710232812Sjmallett computed value. */ 711215976Sjmallett#else 712215976Sjmallett uint64_t srx4cmp : 10; 713215976Sjmallett uint64_t reserved_10_15 : 6; 714215976Sjmallett uint64_t stx4pcmp : 4; 715215976Sjmallett uint64_t stx4ncmp : 4; 716215976Sjmallett uint64_t reserved_24_63 : 40; 717215976Sjmallett#endif 718215976Sjmallett } cn58xx; 719215976Sjmallett struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; 720215976Sjmallett}; 721215976Sjmalletttypedef union cvmx_spxx_drv_ctl cvmx_spxx_drv_ctl_t; 722215976Sjmallett 723215976Sjmallett/** 724215976Sjmallett * cvmx_spx#_err_ctl 725215976Sjmallett * 726215976Sjmallett * SPX_ERR_CTL - Spi error control register 727215976Sjmallett * 728215976Sjmallett * 729215976Sjmallett * Notes: 730215976Sjmallett * * DIPPAY, DIPCLS, PRTNXA 731215976Sjmallett * These bits control whether or not the packet's ERR bit is set when any of 732215976Sjmallett * the these error is detected. If the corresponding error's bit is clear, 733215976Sjmallett * the packet ERR will be set. If the error bit is set, the SPX will simply 734215976Sjmallett * pass through the ERR bit without modifying it in anyway - the error bit 735215976Sjmallett * may or may not have been set by the transmitter device. 736215976Sjmallett */ 737232812Sjmallettunion cvmx_spxx_err_ctl { 738215976Sjmallett uint64_t u64; 739232812Sjmallett struct cvmx_spxx_err_ctl_s { 740232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 741215976Sjmallett uint64_t reserved_9_63 : 55; 742215976Sjmallett uint64_t prtnxa : 1; /**< Spi4 - set the ERR bit on packets in which the 743215976Sjmallett port is out-of-range */ 744215976Sjmallett uint64_t dipcls : 1; /**< Spi4 DIPERR on closing control words cause the 745215976Sjmallett ERR bit to be set */ 746215976Sjmallett uint64_t dippay : 1; /**< Spi4 DIPERR on payload control words cause the 747215976Sjmallett ERR bit to be set */ 748215976Sjmallett uint64_t reserved_4_5 : 2; 749215976Sjmallett uint64_t errcnt : 4; /**< Number of Dip4 errors before bringing down the 750215976Sjmallett interface */ 751215976Sjmallett#else 752215976Sjmallett uint64_t errcnt : 4; 753215976Sjmallett uint64_t reserved_4_5 : 2; 754215976Sjmallett uint64_t dippay : 1; 755215976Sjmallett uint64_t dipcls : 1; 756215976Sjmallett uint64_t prtnxa : 1; 757215976Sjmallett uint64_t reserved_9_63 : 55; 758215976Sjmallett#endif 759215976Sjmallett } s; 760215976Sjmallett struct cvmx_spxx_err_ctl_s cn38xx; 761215976Sjmallett struct cvmx_spxx_err_ctl_s cn38xxp2; 762215976Sjmallett struct cvmx_spxx_err_ctl_s cn58xx; 763215976Sjmallett struct cvmx_spxx_err_ctl_s cn58xxp1; 764215976Sjmallett}; 765215976Sjmalletttypedef union cvmx_spxx_err_ctl cvmx_spxx_err_ctl_t; 766215976Sjmallett 767215976Sjmallett/** 768215976Sjmallett * cvmx_spx#_int_dat 769215976Sjmallett * 770215976Sjmallett * SPX_INT_DAT - Interrupt Data Register 771215976Sjmallett * 772215976Sjmallett * 773215976Sjmallett * Notes: 774215976Sjmallett * Note: The SPX_INT_DAT[MUL] bit is set when multiple errors have been 775215976Sjmallett * detected that would set any of the data fields: PRT, RSVOP, and CALBNK. 776215976Sjmallett * 777215976Sjmallett * The following errors will cause MUL to assert for PRT conflicts. 778215976Sjmallett * - ABNORM 779215976Sjmallett * - APERR 780215976Sjmallett * - DPERR 781215976Sjmallett * 782215976Sjmallett * The following errors will cause MUL to assert for RSVOP conflicts. 783215976Sjmallett * - RSVERR 784215976Sjmallett * 785215976Sjmallett * The following errors will cause MUL to assert for CALBNK conflicts. 786215976Sjmallett * - CALERR 787215976Sjmallett * 788215976Sjmallett * The following errors will cause MUL to assert if multiple interrupts are 789215976Sjmallett * asserted. 790215976Sjmallett * - TPAOVR 791215976Sjmallett * 792215976Sjmallett * The MUL bit will be cleared once all outstanding errors have been 793215976Sjmallett * cleared by software (not just MUL errors - all errors). 794215976Sjmallett */ 795232812Sjmallettunion cvmx_spxx_int_dat { 796215976Sjmallett uint64_t u64; 797232812Sjmallett struct cvmx_spxx_int_dat_s { 798232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 799215976Sjmallett uint64_t reserved_32_63 : 32; 800215976Sjmallett uint64_t mul : 1; /**< Multiple errors have occured */ 801215976Sjmallett uint64_t reserved_14_30 : 17; 802215976Sjmallett uint64_t calbnk : 2; /**< Spi4 Calendar table parity error bank */ 803215976Sjmallett uint64_t rsvop : 4; /**< Spi4 reserved control word */ 804215976Sjmallett uint64_t prt : 8; /**< Port associated with error */ 805215976Sjmallett#else 806215976Sjmallett uint64_t prt : 8; 807215976Sjmallett uint64_t rsvop : 4; 808215976Sjmallett uint64_t calbnk : 2; 809215976Sjmallett uint64_t reserved_14_30 : 17; 810215976Sjmallett uint64_t mul : 1; 811215976Sjmallett uint64_t reserved_32_63 : 32; 812215976Sjmallett#endif 813215976Sjmallett } s; 814215976Sjmallett struct cvmx_spxx_int_dat_s cn38xx; 815215976Sjmallett struct cvmx_spxx_int_dat_s cn38xxp2; 816215976Sjmallett struct cvmx_spxx_int_dat_s cn58xx; 817215976Sjmallett struct cvmx_spxx_int_dat_s cn58xxp1; 818215976Sjmallett}; 819215976Sjmalletttypedef union cvmx_spxx_int_dat cvmx_spxx_int_dat_t; 820215976Sjmallett 821215976Sjmallett/** 822215976Sjmallett * cvmx_spx#_int_msk 823215976Sjmallett * 824215976Sjmallett * SPX_INT_MSK - Interrupt Mask Register 825215976Sjmallett * 826215976Sjmallett */ 827232812Sjmallettunion cvmx_spxx_int_msk { 828215976Sjmallett uint64_t u64; 829232812Sjmallett struct cvmx_spxx_int_msk_s { 830232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 831215976Sjmallett uint64_t reserved_12_63 : 52; 832215976Sjmallett uint64_t calerr : 1; /**< Spi4 Calendar table parity error */ 833215976Sjmallett uint64_t syncerr : 1; /**< Consecutive Spi4 DIP4 errors have exceeded 834215976Sjmallett SPX_ERR_CTL[ERRCNT] */ 835215976Sjmallett uint64_t diperr : 1; /**< Spi4 DIP4 error */ 836215976Sjmallett uint64_t tpaovr : 1; /**< Selected port has hit TPA overflow */ 837215976Sjmallett uint64_t rsverr : 1; /**< Spi4 reserved control word detected */ 838215976Sjmallett uint64_t drwnng : 1; /**< Spi4 receive FIFO drowning/overflow */ 839215976Sjmallett uint64_t clserr : 1; /**< Spi4 packet closed on non-16B alignment without EOP */ 840215976Sjmallett uint64_t spiovr : 1; /**< Spi async FIFO overflow (Spi3 or Spi4) */ 841215976Sjmallett uint64_t reserved_2_3 : 2; 842215976Sjmallett uint64_t abnorm : 1; /**< Abnormal packet termination (ERR bit) */ 843215976Sjmallett uint64_t prtnxa : 1; /**< Port out of range */ 844215976Sjmallett#else 845215976Sjmallett uint64_t prtnxa : 1; 846215976Sjmallett uint64_t abnorm : 1; 847215976Sjmallett uint64_t reserved_2_3 : 2; 848215976Sjmallett uint64_t spiovr : 1; 849215976Sjmallett uint64_t clserr : 1; 850215976Sjmallett uint64_t drwnng : 1; 851215976Sjmallett uint64_t rsverr : 1; 852215976Sjmallett uint64_t tpaovr : 1; 853215976Sjmallett uint64_t diperr : 1; 854215976Sjmallett uint64_t syncerr : 1; 855215976Sjmallett uint64_t calerr : 1; 856215976Sjmallett uint64_t reserved_12_63 : 52; 857215976Sjmallett#endif 858215976Sjmallett } s; 859215976Sjmallett struct cvmx_spxx_int_msk_s cn38xx; 860215976Sjmallett struct cvmx_spxx_int_msk_s cn38xxp2; 861215976Sjmallett struct cvmx_spxx_int_msk_s cn58xx; 862215976Sjmallett struct cvmx_spxx_int_msk_s cn58xxp1; 863215976Sjmallett}; 864215976Sjmalletttypedef union cvmx_spxx_int_msk cvmx_spxx_int_msk_t; 865215976Sjmallett 866215976Sjmallett/** 867215976Sjmallett * cvmx_spx#_int_reg 868215976Sjmallett * 869215976Sjmallett * SPX_INT_REG - Interrupt Register 870215976Sjmallett * 871215976Sjmallett * 872215976Sjmallett * Notes: 873215976Sjmallett * * PRTNXA 874215976Sjmallett * This error indicates that the port on the Spi bus was not a valid port 875215976Sjmallett * for the system. Spi4 accesses occur on payload control bit-times. The 876215976Sjmallett * SRX can be configured with the exact number of ports available (by 877215976Sjmallett * SRX_COM_CTL[PRTS] register). Any Spi access to anthing outside the range 878215976Sjmallett * of 0 .. (SRX_COM_CTL[PRTS] - 1) is considered an error. The offending 879215976Sjmallett * port is logged in SPX_INT_DAT[PRT] if there are no pending interrupts in 880215976Sjmallett * SPX_INT_REG that require SPX_INT_DAT[PRT]. 881215976Sjmallett * 882215976Sjmallett * SRX will not drop the packet with the bogus port address. Instead, the 883215976Sjmallett * port will be mapped into the supported port range. The remapped address 884215976Sjmallett * in simply... 885215976Sjmallett * 886215976Sjmallett * Address = [ interfaceId, ADR[3:0] ] 887215976Sjmallett * 888215976Sjmallett * If the SPX detects that a PRTNXA error has occured, the packet will 889215976Sjmallett * have its ERR bit set (or'ed in with the ERR bit from the transmitter) 890215976Sjmallett * if the SPX_ERR_CTL[PRTNXA] bit is clear. 891215976Sjmallett * 892215976Sjmallett * In Spi4 mode, SPX will generate an interrupt for every 8B data burst 893215976Sjmallett * associated with the invalid address. The SPX_INT_DAT[MUL] bit will never 894215976Sjmallett * be set. 895215976Sjmallett * 896215976Sjmallett * * ABNORM 897215976Sjmallett * This bit simply indicates that a given packet had abnormal terminiation. 898215976Sjmallett * In Spi4 mode, this means that packet completed with an EOPS[1:0] code of 899215976Sjmallett * 2'b01. This error can also be thought of as the application specific 900215976Sjmallett * error (as mentioned in the Spi4 spec). The offending port is logged in 901215976Sjmallett * SPX_INT_DAT[PRT] if there are no pending interrupts in SPX_INT_REG that 902215976Sjmallett * require SPX_INT_DAT[PRT]. 903215976Sjmallett * 904215976Sjmallett * The ABNORM error is only raised when the ERR bit that comes from the 905215976Sjmallett * Spi interface is set. It will never assert if any internal condition 906215976Sjmallett * causes the ERR bit to assert (e.g. PRTNXA or DPERR). 907215976Sjmallett * 908215976Sjmallett * * SPIOVR 909215976Sjmallett * This error indicates that the FIFOs that manage the async crossing from 910215976Sjmallett * the Spi clocks to the core clock domains have overflowed. This is a 911215976Sjmallett * fatal error and can cause much data/control corruption since ticks will 912215976Sjmallett * be dropped and reordered. This is purely a function of clock ratios and 913215976Sjmallett * correct system ratios should make this an impossible condition. 914215976Sjmallett * 915215976Sjmallett * * CLSERR 916215976Sjmallett * This is a Spi4 error that indicates that a given data transfer burst 917215976Sjmallett * that did not terminate with an EOP, did not end with the 16B alignment 918215976Sjmallett * as per the Spi4 spec. The offending port cannot be logged since the 919215976Sjmallett * block does not know the streamm terminated until the port switches. 920215976Sjmallett * At that time, that packet has already been pushed down the pipe. 921215976Sjmallett * 922215976Sjmallett * The CLSERR bit does not actually check the Spi4 burst - just how data 923215976Sjmallett * is accumulated for the downstream logic. Bursts that are separted by 924215976Sjmallett * idles or training will still be merged into accumulated transfers and 925215976Sjmallett * will not fire the CLSERR condition. The checker is really checking 926215976Sjmallett * non-8B aligned, non-EOP data ticks that are sent downstream. These 927215976Sjmallett * ticks are what will really mess up the core. 928215976Sjmallett * 929215976Sjmallett * This is an expensive fix, so we'll probably let it ride. We never 930215976Sjmallett * claim to check Spi4 protocol anyway. 931215976Sjmallett * 932215976Sjmallett * * DRWNNG 933215976Sjmallett * This error indicates that the Spi4 FIFO that services the GMX has 934215976Sjmallett * overflowed. Like the SPIOVR error condition, correct system ratios 935215976Sjmallett * should make this an impossible condition. 936215976Sjmallett * 937215976Sjmallett * * RSVERR 938215976Sjmallett * This Spi4 error indicates that the Spi4 receiver has seen a reserve 939215976Sjmallett * control packet. A reserve control packet is an invalid combiniation 940215976Sjmallett * of bits on DAT[15:12]. Basically this is DAT[15] == 1'b0 and DAT[12] 941215976Sjmallett * == 1'b1 (an SOP without a payload command). The RSVERR indicates an 942215976Sjmallett * error has occured and SPX_INT_DAT[RSVOP] holds the first reserved 943215976Sjmallett * opcode and will be set if there are no pending interrupts in 944215976Sjmallett * SPX_INT_REG that require SPX_INT_DAT[RSVOP]. 945215976Sjmallett * 946215976Sjmallett * * TPAOVR 947215976Sjmallett * This bit indicates that the TPA Watcher has flagged an event. See the 948215976Sjmallett * TPA Watcher for a more detailed discussion. 949215976Sjmallett * 950215976Sjmallett * * DIPERR 951215976Sjmallett * This bit indicates that the Spi4 receiver has encountered a DIP4 952215976Sjmallett * miscompare on the datapath. A DIPERR can occur in an IDLE or a 953215976Sjmallett * control word that frames a data burst. If the DIPERR occurs on a 954215976Sjmallett * framing word there are three cases. 955215976Sjmallett * 956215976Sjmallett * 1) DIPERR occurs at the end of a data burst. The previous packet is 957215976Sjmallett * marked with the ERR bit to be processed later if 958215976Sjmallett * SPX_ERR_CTL[DIPCLS] is clear. 959215976Sjmallett * 2) DIPERR occurs on a payload word. The subsequent packet is marked 960215976Sjmallett * with the ERR bit to be processed later if SPX_ERR_CTL[DIPPAY] is 961215976Sjmallett * clear. 962215976Sjmallett * 3) DIPERR occurs on a control word that closes on packet and is a 963215976Sjmallett * payload for another packet. In this case, both packets will have 964215976Sjmallett * their ERR bit marked depending on the respective values of 965215976Sjmallett * SPX_ERR_CTL[DIPCLS] and SPX_ERR_CTL[DIPPAY] as discussed above. 966215976Sjmallett * 967215976Sjmallett * * SYNCERR 968215976Sjmallett * This bit indicates that the Spi4 receiver has encountered 969215976Sjmallett * SPX_ERR_CTL[ERRCNT] consecutive Spi4 DIP4 errors and the interface 970215976Sjmallett * should be synched. 971215976Sjmallett * 972215976Sjmallett * * CALERR 973215976Sjmallett * This bit indicates that the Spi4 calendar table encountered a parity 974215976Sjmallett * error. This error bit is associated with the calendar table on the RX 975215976Sjmallett * interface - the interface that receives the Spi databus. Parity errors 976215976Sjmallett * can occur during normal operation when the calendar table is constantly 977215976Sjmallett * being read for the port information, or during initialization time, when 978215976Sjmallett * the user has access. Since the calendar table is split into two banks, 979215976Sjmallett * SPX_INT_DAT[CALBNK] indicates which banks have taken a parity error. 980215976Sjmallett * CALBNK[1] indicates the error occured in the upper bank, while CALBNK[0] 981215976Sjmallett * indicates that the error occured in the lower bank. SPX_INT_DAT[CALBNK] 982215976Sjmallett * will be set if there are no pending interrupts in SPX_INT_REG that 983215976Sjmallett * require SPX_INT_DAT[CALBNK]. 984215976Sjmallett * 985215976Sjmallett * * SPF 986215976Sjmallett * This bit indicates that a Spi fatal error has occurred. A fatal error 987215976Sjmallett * is defined as any error condition for which the corresponding 988215976Sjmallett * SPX_INT_SYNC bit is set. Therefore, conservative systems can halt the 989215976Sjmallett * interface on any error condition although this is not strictly 990215976Sjmallett * necessary. Some error are much more fatal in nature than others. 991215976Sjmallett * 992215976Sjmallett * PRTNXA, SPIOVR, CLSERR, DRWNNG, DIPERR, CALERR, and SYNCERR are examples 993215976Sjmallett * of fatal error for different reasons - usually because multiple port 994215976Sjmallett * streams could be effected. ABNORM, RSVERR, and TPAOVR are conditions 995215976Sjmallett * that are contained to a single packet which allows the interface to drop 996215976Sjmallett * a single packet and remain up and stable. 997215976Sjmallett */ 998232812Sjmallettunion cvmx_spxx_int_reg { 999215976Sjmallett uint64_t u64; 1000232812Sjmallett struct cvmx_spxx_int_reg_s { 1001232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1002215976Sjmallett uint64_t reserved_32_63 : 32; 1003215976Sjmallett uint64_t spf : 1; /**< Spi interface down */ 1004215976Sjmallett uint64_t reserved_12_30 : 19; 1005215976Sjmallett uint64_t calerr : 1; /**< Spi4 Calendar table parity error */ 1006215976Sjmallett uint64_t syncerr : 1; /**< Consecutive Spi4 DIP4 errors have exceeded 1007215976Sjmallett SPX_ERR_CTL[ERRCNT] */ 1008215976Sjmallett uint64_t diperr : 1; /**< Spi4 DIP4 error */ 1009215976Sjmallett uint64_t tpaovr : 1; /**< Selected port has hit TPA overflow */ 1010215976Sjmallett uint64_t rsverr : 1; /**< Spi4 reserved control word detected */ 1011215976Sjmallett uint64_t drwnng : 1; /**< Spi4 receive FIFO drowning/overflow */ 1012215976Sjmallett uint64_t clserr : 1; /**< Spi4 packet closed on non-16B alignment without EOP */ 1013215976Sjmallett uint64_t spiovr : 1; /**< Spi async FIFO overflow */ 1014215976Sjmallett uint64_t reserved_2_3 : 2; 1015215976Sjmallett uint64_t abnorm : 1; /**< Abnormal packet termination (ERR bit) */ 1016215976Sjmallett uint64_t prtnxa : 1; /**< Port out of range */ 1017215976Sjmallett#else 1018215976Sjmallett uint64_t prtnxa : 1; 1019215976Sjmallett uint64_t abnorm : 1; 1020215976Sjmallett uint64_t reserved_2_3 : 2; 1021215976Sjmallett uint64_t spiovr : 1; 1022215976Sjmallett uint64_t clserr : 1; 1023215976Sjmallett uint64_t drwnng : 1; 1024215976Sjmallett uint64_t rsverr : 1; 1025215976Sjmallett uint64_t tpaovr : 1; 1026215976Sjmallett uint64_t diperr : 1; 1027215976Sjmallett uint64_t syncerr : 1; 1028215976Sjmallett uint64_t calerr : 1; 1029215976Sjmallett uint64_t reserved_12_30 : 19; 1030215976Sjmallett uint64_t spf : 1; 1031215976Sjmallett uint64_t reserved_32_63 : 32; 1032215976Sjmallett#endif 1033215976Sjmallett } s; 1034215976Sjmallett struct cvmx_spxx_int_reg_s cn38xx; 1035215976Sjmallett struct cvmx_spxx_int_reg_s cn38xxp2; 1036215976Sjmallett struct cvmx_spxx_int_reg_s cn58xx; 1037215976Sjmallett struct cvmx_spxx_int_reg_s cn58xxp1; 1038215976Sjmallett}; 1039215976Sjmalletttypedef union cvmx_spxx_int_reg cvmx_spxx_int_reg_t; 1040215976Sjmallett 1041215976Sjmallett/** 1042215976Sjmallett * cvmx_spx#_int_sync 1043215976Sjmallett * 1044215976Sjmallett * SPX_INT_SYNC - Interrupt Sync Register 1045215976Sjmallett * 1046215976Sjmallett * 1047215976Sjmallett * Notes: 1048215976Sjmallett * This mask set indicates which exception condition should cause the 1049215976Sjmallett * SPX_INT_REG[SPF] bit to assert 1050215976Sjmallett * 1051215976Sjmallett * It is recommended that software set the PRTNXA, SPIOVR, CLSERR, DRWNNG, 1052215976Sjmallett * DIPERR, CALERR, and SYNCERR errors as synchronization events. Software is 1053215976Sjmallett * free to synchronize the bus on other conditions, but this is the minimum 1054215976Sjmallett * recommended set. 1055215976Sjmallett */ 1056232812Sjmallettunion cvmx_spxx_int_sync { 1057215976Sjmallett uint64_t u64; 1058232812Sjmallett struct cvmx_spxx_int_sync_s { 1059232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1060215976Sjmallett uint64_t reserved_12_63 : 52; 1061215976Sjmallett uint64_t calerr : 1; /**< Spi4 Calendar table parity error */ 1062215976Sjmallett uint64_t syncerr : 1; /**< Consecutive Spi4 DIP4 errors have exceeded 1063215976Sjmallett SPX_ERR_CTL[ERRCNT] */ 1064215976Sjmallett uint64_t diperr : 1; /**< Spi4 DIP4 error */ 1065215976Sjmallett uint64_t tpaovr : 1; /**< Selected port has hit TPA overflow */ 1066215976Sjmallett uint64_t rsverr : 1; /**< Spi4 reserved control word detected */ 1067215976Sjmallett uint64_t drwnng : 1; /**< Spi4 receive FIFO drowning/overflow */ 1068215976Sjmallett uint64_t clserr : 1; /**< Spi4 packet closed on non-16B alignment without EOP */ 1069215976Sjmallett uint64_t spiovr : 1; /**< Spi async FIFO overflow (Spi3 or Spi4) */ 1070215976Sjmallett uint64_t reserved_2_3 : 2; 1071215976Sjmallett uint64_t abnorm : 1; /**< Abnormal packet termination (ERR bit) */ 1072215976Sjmallett uint64_t prtnxa : 1; /**< Port out of range */ 1073215976Sjmallett#else 1074215976Sjmallett uint64_t prtnxa : 1; 1075215976Sjmallett uint64_t abnorm : 1; 1076215976Sjmallett uint64_t reserved_2_3 : 2; 1077215976Sjmallett uint64_t spiovr : 1; 1078215976Sjmallett uint64_t clserr : 1; 1079215976Sjmallett uint64_t drwnng : 1; 1080215976Sjmallett uint64_t rsverr : 1; 1081215976Sjmallett uint64_t tpaovr : 1; 1082215976Sjmallett uint64_t diperr : 1; 1083215976Sjmallett uint64_t syncerr : 1; 1084215976Sjmallett uint64_t calerr : 1; 1085215976Sjmallett uint64_t reserved_12_63 : 52; 1086215976Sjmallett#endif 1087215976Sjmallett } s; 1088215976Sjmallett struct cvmx_spxx_int_sync_s cn38xx; 1089215976Sjmallett struct cvmx_spxx_int_sync_s cn38xxp2; 1090215976Sjmallett struct cvmx_spxx_int_sync_s cn58xx; 1091215976Sjmallett struct cvmx_spxx_int_sync_s cn58xxp1; 1092215976Sjmallett}; 1093215976Sjmalletttypedef union cvmx_spxx_int_sync cvmx_spxx_int_sync_t; 1094215976Sjmallett 1095215976Sjmallett/** 1096215976Sjmallett * cvmx_spx#_tpa_acc 1097215976Sjmallett * 1098215976Sjmallett * SPX_TPA_ACC - TPA watcher byte accumulator 1099215976Sjmallett * 1100215976Sjmallett * 1101215976Sjmallett * Notes: 1102215976Sjmallett * This field allows the user to access the TPA watcher accumulator counter. 1103215976Sjmallett * This register reflects the number of bytes sent to IMX once the port 1104215976Sjmallett * specified by SPX_TPA_SEL[PRTSEL] has lost its TPA. The SPX_INT_REG[TPAOVR] 1105215976Sjmallett * bit is asserted when CNT >= SPX_TPA_MAX[MAX]. The CNT will continue to 1106215976Sjmallett * increment until the TPA for the port is asserted. At that point the CNT 1107215976Sjmallett * value is frozen until software clears the interrupt bit. 1108215976Sjmallett */ 1109232812Sjmallettunion cvmx_spxx_tpa_acc { 1110215976Sjmallett uint64_t u64; 1111232812Sjmallett struct cvmx_spxx_tpa_acc_s { 1112232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1113215976Sjmallett uint64_t reserved_32_63 : 32; 1114215976Sjmallett uint64_t cnt : 32; /**< TPA watcher accumulate count */ 1115215976Sjmallett#else 1116215976Sjmallett uint64_t cnt : 32; 1117215976Sjmallett uint64_t reserved_32_63 : 32; 1118215976Sjmallett#endif 1119215976Sjmallett } s; 1120215976Sjmallett struct cvmx_spxx_tpa_acc_s cn38xx; 1121215976Sjmallett struct cvmx_spxx_tpa_acc_s cn38xxp2; 1122215976Sjmallett struct cvmx_spxx_tpa_acc_s cn58xx; 1123215976Sjmallett struct cvmx_spxx_tpa_acc_s cn58xxp1; 1124215976Sjmallett}; 1125215976Sjmalletttypedef union cvmx_spxx_tpa_acc cvmx_spxx_tpa_acc_t; 1126215976Sjmallett 1127215976Sjmallett/** 1128215976Sjmallett * cvmx_spx#_tpa_max 1129215976Sjmallett * 1130215976Sjmallett * SPX_TPA_MAX - TPA watcher assertion threshold 1131215976Sjmallett * 1132215976Sjmallett * 1133215976Sjmallett * Notes: 1134215976Sjmallett * The TPA watcher has the ability to notify the system with an interrupt when 1135215976Sjmallett * too much data has been received on loss of TPA. The user sets the 1136215976Sjmallett * SPX_TPA_MAX[MAX] register and when the watcher has accumulated that many 1137215976Sjmallett * ticks, then the interrupt is conditionally raised (based on interrupt mask 1138215976Sjmallett * bits). This feature will be disabled if the programmed count is zero. 1139215976Sjmallett */ 1140232812Sjmallettunion cvmx_spxx_tpa_max { 1141215976Sjmallett uint64_t u64; 1142232812Sjmallett struct cvmx_spxx_tpa_max_s { 1143232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1144215976Sjmallett uint64_t reserved_32_63 : 32; 1145215976Sjmallett uint64_t max : 32; /**< TPA watcher TPA threshold */ 1146215976Sjmallett#else 1147215976Sjmallett uint64_t max : 32; 1148215976Sjmallett uint64_t reserved_32_63 : 32; 1149215976Sjmallett#endif 1150215976Sjmallett } s; 1151215976Sjmallett struct cvmx_spxx_tpa_max_s cn38xx; 1152215976Sjmallett struct cvmx_spxx_tpa_max_s cn38xxp2; 1153215976Sjmallett struct cvmx_spxx_tpa_max_s cn58xx; 1154215976Sjmallett struct cvmx_spxx_tpa_max_s cn58xxp1; 1155215976Sjmallett}; 1156215976Sjmalletttypedef union cvmx_spxx_tpa_max cvmx_spxx_tpa_max_t; 1157215976Sjmallett 1158215976Sjmallett/** 1159215976Sjmallett * cvmx_spx#_tpa_sel 1160215976Sjmallett * 1161215976Sjmallett * SPX_TPA_SEL - TPA watcher port selector 1162215976Sjmallett * 1163215976Sjmallett * 1164215976Sjmallett * Notes: 1165215976Sjmallett * The TPA Watcher is primarily a debug vehicle used to help initial bringup 1166215976Sjmallett * of a system. The TPA watcher counts bytes that roll in from the Spi 1167215976Sjmallett * interface. The user programs the Spi port to watch using 1168215976Sjmallett * SPX_TPA_SEL[PRTSEL]. Once the TPA is deasserted for that port, the watcher 1169215976Sjmallett * begins to count the data ticks that have been delivered to the inbound 1170215976Sjmallett * datapath (and eventually to the IOB). The result is that we can derive 1171215976Sjmallett * turn-around times of the other device by watching how much data was sent 1172215976Sjmallett * after a loss of TPA through the SPX_TPA_ACC[CNT] register. An optional 1173215976Sjmallett * interrupt may be raised as well. See SPX_TPA_MAX for further information. 1174215976Sjmallett * 1175215976Sjmallett * TPA's can be deasserted for a number of reasons... 1176215976Sjmallett * 1177215976Sjmallett * 1) IPD indicates backpressure 1178215976Sjmallett * 2) The GMX inbound FIFO is filling up and should BP 1179215976Sjmallett * 3) User has out an override on the TPA wires 1180215976Sjmallett */ 1181232812Sjmallettunion cvmx_spxx_tpa_sel { 1182215976Sjmallett uint64_t u64; 1183232812Sjmallett struct cvmx_spxx_tpa_sel_s { 1184232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1185215976Sjmallett uint64_t reserved_4_63 : 60; 1186215976Sjmallett uint64_t prtsel : 4; /**< TPA watcher port select */ 1187215976Sjmallett#else 1188215976Sjmallett uint64_t prtsel : 4; 1189215976Sjmallett uint64_t reserved_4_63 : 60; 1190215976Sjmallett#endif 1191215976Sjmallett } s; 1192215976Sjmallett struct cvmx_spxx_tpa_sel_s cn38xx; 1193215976Sjmallett struct cvmx_spxx_tpa_sel_s cn38xxp2; 1194215976Sjmallett struct cvmx_spxx_tpa_sel_s cn58xx; 1195215976Sjmallett struct cvmx_spxx_tpa_sel_s cn58xxp1; 1196215976Sjmallett}; 1197215976Sjmalletttypedef union cvmx_spxx_tpa_sel cvmx_spxx_tpa_sel_t; 1198215976Sjmallett 1199215976Sjmallett/** 1200215976Sjmallett * cvmx_spx#_trn4_ctl 1201215976Sjmallett * 1202215976Sjmallett * Notes: 1203215976Sjmallett * These bits are controls for the Spi4 RX bit deskew logic. See that Spec 1204215976Sjmallett * for further details. 1205215976Sjmallett * 1206215976Sjmallett * * BOOT_BIT 1207215976Sjmallett * On the initial training synchronization sequence, the hardware has the 1208215976Sjmallett * BOOT_BIT set which means that it will continueously perform macro 1209215976Sjmallett * operations. Once the BOOT_BIT is cleared, the macro machine will finish 1210215976Sjmallett * the macro operation is working on and then return to the idle state. 1211215976Sjmallett * Subsequent training sequences will only go through a single macro 1212215976Sjmallett * operation in order to do slight deskews. 1213215976Sjmallett * 1214215976Sjmallett * * JITTER 1215215976Sjmallett * Minimum value is 1. This parameter must be set for Spi4 mode using 1216215976Sjmallett * auto-bit deskew. Regardless of the original intent, this field must be 1217215976Sjmallett * set non-zero for deskew to function correctly. 1218215976Sjmallett * 1219215976Sjmallett * The thought is the JITTER range is no longer required since the macro 1220215976Sjmallett * machine was enhanced to understand about edge direction. Originally 1221215976Sjmallett * these bits were intended to compensate for clock jitter. 1222215976Sjmallett * 1223215976Sjmallett * dly: this is the intrinsic delay of each delay element 1224215976Sjmallett * tap currently, it is 70ps-110ps. 1225215976Sjmallett * jitter: amount of jitter we expect in the system (~200ps) 1226215976Sjmallett * j: number of taps to account for jitter 1227215976Sjmallett * 1228215976Sjmallett * j = ((jitter / dly) + 1) 1229215976Sjmallett * 1230215976Sjmallett * * TRNTEST 1231215976Sjmallett * This mode is used to test systems to make sure that the bit deskew 1232215976Sjmallett * parameters have been correctly setup. After configuration, software can 1233215976Sjmallett * set the TRNTEST mode bit. This should be done before SRX_COM_CTL[ST_EN] 1234215976Sjmallett * is set such that we can be sure that the TX device is simply sending 1235215976Sjmallett * continuous training patterns. 1236215976Sjmallett * 1237215976Sjmallett * The test mode samples every incoming bit-time and makes sure that it is 1238215976Sjmallett * either a training control or a training data packet. If any other data 1239215976Sjmallett * is observed, then SPX_DBG_DESKEW_STATE[TESTRES] will assert signaling a 1240215976Sjmallett * test failure. 1241215976Sjmallett * 1242215976Sjmallett * Software must clear TRNTEST before training is terminated. 1243215976Sjmallett * 1244215976Sjmallett * * Example Spi4 RX init flow... 1245215976Sjmallett * 1246215976Sjmallett * 1) set the CLKDLY lines (SPXX_CLK_CTL[CLKDLY]) 1247215976Sjmallett * - these bits must be set before the DLL can successfully lock 1248215976Sjmallett * 1249215976Sjmallett * 2) set the SRXDLCK (SPXX_CLK_CTL[SRXDLCK]) 1250215976Sjmallett * - this is the DLL lock bit which also acts as a block reset 1251215976Sjmallett * 1252215976Sjmallett * 3) wait for the DLLs lock 1253215976Sjmallett * 1254215976Sjmallett * 4) set any desired fields in SPXX_DBG_DESKEW_CTL 1255215976Sjmallett * - This register has only one field that most users will care about. 1256215976Sjmallett * When set, DLLDIS will disable sending update pulses to the Spi4 RX 1257215976Sjmallett * DLLs. This pulse allows the DLL to adjust to clock variations over 1258215976Sjmallett * time. In general, it is desired behavior. 1259215976Sjmallett * 1260215976Sjmallett * 5) set fields in SPXX_TRN4_CTL 1261215976Sjmallett * - These fields deal with the MUX training sequence 1262215976Sjmallett * * MUX_EN 1263215976Sjmallett * This is the enable bit for the mux select. The MUX select will 1264215976Sjmallett * run in the training sequence between the DLL and the Macro 1265215976Sjmallett * sequence when enabled. Once the MUX selects are selected, the 1266215976Sjmallett * entire macro sequence must be rerun. The expectation is that 1267215976Sjmallett * this is only run at boot time and this is bit cleared at/around 1268215976Sjmallett * step \#8. 1269215976Sjmallett * - These fields deal with the Macro training sequence 1270215976Sjmallett * * MACRO_EN 1271215976Sjmallett * This is the enable bit for the macro sequence. Macro sequences 1272215976Sjmallett * will run after the DLL and MUX training sequences. Each macro 1273215976Sjmallett * sequence can move the offset by one value. 1274215976Sjmallett * * MAXDIST 1275215976Sjmallett * This is how far we will search for an edge. Example... 1276215976Sjmallett * 1277215976Sjmallett * dly: this is the intrinsic delay of each delay element 1278215976Sjmallett * tap currently, it is 70ps-110ps. 1279215976Sjmallett * U: bit time period in time units. 1280215976Sjmallett * 1281215976Sjmallett * MAXDIST = MIN(16, ((bit_time / 2) / dly) 1282215976Sjmallett * 1283215976Sjmallett * Each MAXDIST iteration consists of an edge detect in the early 1284215976Sjmallett * and late (+/-) directions in an attempt to center the data. This 1285215976Sjmallett * requires two training transistions, the control/data and 1286215976Sjmallett * data/control transistions which comprise a training sequence. 1287215976Sjmallett * Therefore, the number of training sequences required for a single 1288215976Sjmallett * macro operation is simply MAXDIST. 1289215976Sjmallett * 1290215976Sjmallett * 6) set the RCVTRN go bit (SPXX_CLK_CTL[RCVTRN]) 1291215976Sjmallett * - this bit synchs on the first valid complete training cycle and 1292215976Sjmallett * starts to process the training packets 1293215976Sjmallett * 1294215976Sjmallett * 6b) This is where software could manually set the controls as opposed to 1295215976Sjmallett * letting the hardware do it. See the SPXX_DBG_DESKEW_CTL register 1296215976Sjmallett * description for more detail. 1297215976Sjmallett * 1298215976Sjmallett * 7) the TX device must continue to send training packets for the initial 1299215976Sjmallett * time period. 1300215976Sjmallett * - this can be determined by... 1301215976Sjmallett * 1302215976Sjmallett * DLL: one training sequence for the DLL adjustment (regardless of enable/disable) 1303215976Sjmallett * MUX: one training sequence for the Flop MUX taps (regardless of enable/disable) 1304215976Sjmallett * INIT_SEQUENCES: max number of taps that we must move 1305215976Sjmallett * 1306215976Sjmallett * INIT_SEQUENCES = MIN(16, ((bit_time / 2) / dly)) 1307215976Sjmallett * 1308215976Sjmallett * INIT_TRN = DLL + MUX + ROUNDUP((INIT_SEQUENCES * (MAXDIST + 2))) 1309215976Sjmallett * 1310215976Sjmallett * 1311215976Sjmallett * - software can either wait a fixed amount of time based on the clock 1312215976Sjmallett * frequencies or poll the SPXX_CLK_STAT[SRXTRN] register. Each 1313215976Sjmallett * assertion of SRXTRN means that at least one training sequence has 1314215976Sjmallett * been received. Software can poll, clear, and repeat on this bit to 1315215976Sjmallett * eventually count all required transistions. 1316215976Sjmallett * 1317215976Sjmallett * int cnt = 0; 1318215976Sjmallett * while (cnt < INIT_TRN) [ 1319215976Sjmallett * if (SPXX_CLK_STAT[SRXTRN]) [ 1320215976Sjmallett * cnt++; 1321215976Sjmallett * SPXX_CLK_STAT[SRXTRN] = 0; 1322215976Sjmallett * ] 1323215976Sjmallett * ] 1324215976Sjmallett * 1325215976Sjmallett * - subsequent training sequences will normally move the taps only 1326215976Sjmallett * one position, so the ALPHA equation becomes... 1327215976Sjmallett * 1328215976Sjmallett * MAC = (MAXDIST == 0) ? 1 : ROUNDUP((1 * (MAXDIST + 2))) + 1 1329215976Sjmallett * 1330215976Sjmallett * ALPHA = DLL + MUX + MAC 1331215976Sjmallett * 1332215976Sjmallett * ergo, MAXDIST simplifies to... 1333215976Sjmallett * 1334215976Sjmallett * ALPHA = (MAXDIST == 0) ? 3 : MAXDIST + 5 1335215976Sjmallett * 1336215976Sjmallett * DLL and MUX and MAC will always require at least a training sequence 1337215976Sjmallett * each - even if disabled. If the macro sequence is enabled, an 1338215976Sjmallett * additional training sequenece at the end is necessary. The extra 1339215976Sjmallett * sequence allows for all training state to be cleared before resuming 1340215976Sjmallett * normal operation. 1341215976Sjmallett * 1342215976Sjmallett * 8) after the recevier gets enough training sequences in order to achieve 1343215976Sjmallett * deskew lock, set SPXX_TRN4_CTL[CLR_BOOT] 1344215976Sjmallett * - this disables the continuous macro sequences and puts into into one 1345215976Sjmallett * macro sequnence per training operation 1346215976Sjmallett * - optionally, the machine can choose to fall out of training if 1347215976Sjmallett * enough NOPs follow the training operation (require at least 32 NOPs 1348215976Sjmallett * to follow the training sequence). 1349215976Sjmallett * 1350215976Sjmallett * There must be at least MAXDIST + 3 training sequences after the 1351215976Sjmallett * SPXX_TRN4_CTL[CLR_BOOT] is set or sufficient NOPs from the TX device. 1352215976Sjmallett * 1353215976Sjmallett * 9) the TX device continues to send training sequences until the RX 1354215976Sjmallett * device sends a calendar transistion. This is controlled by 1355215976Sjmallett * SRXX_COM_CTL[ST_EN]. Other restrictions require other Spi parameters 1356215976Sjmallett * (e.g. the calendar table) to be setup before this bit can be enabled. 1357215976Sjmallett * Once the entire interface is properly programmed, software writes 1358215976Sjmallett * SRXX_COM_CTL[INF_EN]. At this point, the Spi4 packets will begin to 1359215976Sjmallett * be sent into the N2K core and processed by the chip. 1360215976Sjmallett */ 1361232812Sjmallettunion cvmx_spxx_trn4_ctl { 1362215976Sjmallett uint64_t u64; 1363232812Sjmallett struct cvmx_spxx_trn4_ctl_s { 1364232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1365215976Sjmallett uint64_t reserved_13_63 : 51; 1366215976Sjmallett uint64_t trntest : 1; /**< Training Test Mode 1367215976Sjmallett This bit is only for initial bringup 1368215976Sjmallett (spx_csr__spi4_trn_test_mode) */ 1369215976Sjmallett uint64_t jitter : 3; /**< Accounts for jitter when the macro sequence is 1370215976Sjmallett locking. The value is how many consecutive 1371215976Sjmallett transititions before declaring en edge. Minimum 1372215976Sjmallett value is 1. This parameter must be set for Spi4 1373215976Sjmallett mode using auto-bit deskew. 1374215976Sjmallett (spx_csr__spi4_mac_jitter) */ 1375215976Sjmallett uint64_t clr_boot : 1; /**< Clear the macro boot sequence mode bit 1376215976Sjmallett (spx_csr__spi4_mac_clr_boot) */ 1377215976Sjmallett uint64_t set_boot : 1; /**< Enable the macro boot sequence mode bit 1378215976Sjmallett (spx_csr__spi4_mac_set_boot) */ 1379215976Sjmallett uint64_t maxdist : 5; /**< This field defines how far from center the 1380215976Sjmallett deskew logic will search in a single macro 1381215976Sjmallett sequence (spx_csr__spi4_mac_iters) */ 1382215976Sjmallett uint64_t macro_en : 1; /**< Allow the macro sequence to center the sample 1383215976Sjmallett point in the data window through hardware 1384215976Sjmallett (spx_csr__spi4_mac_trn_en) */ 1385215976Sjmallett uint64_t mux_en : 1; /**< Enable the hardware machine that selects the 1386215976Sjmallett proper coarse FLOP selects 1387215976Sjmallett (spx_csr__spi4_mux_trn_en) */ 1388215976Sjmallett#else 1389215976Sjmallett uint64_t mux_en : 1; 1390215976Sjmallett uint64_t macro_en : 1; 1391215976Sjmallett uint64_t maxdist : 5; 1392215976Sjmallett uint64_t set_boot : 1; 1393215976Sjmallett uint64_t clr_boot : 1; 1394215976Sjmallett uint64_t jitter : 3; 1395215976Sjmallett uint64_t trntest : 1; 1396215976Sjmallett uint64_t reserved_13_63 : 51; 1397215976Sjmallett#endif 1398215976Sjmallett } s; 1399215976Sjmallett struct cvmx_spxx_trn4_ctl_s cn38xx; 1400215976Sjmallett struct cvmx_spxx_trn4_ctl_s cn38xxp2; 1401215976Sjmallett struct cvmx_spxx_trn4_ctl_s cn58xx; 1402215976Sjmallett struct cvmx_spxx_trn4_ctl_s cn58xxp1; 1403215976Sjmallett}; 1404215976Sjmalletttypedef union cvmx_spxx_trn4_ctl cvmx_spxx_trn4_ctl_t; 1405215976Sjmallett 1406215976Sjmallett#endif 1407