cvmx-raid.h revision 210284
1210284Sjmallett/***********************license start*************** 2210284Sjmallett * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3210284Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6210284Sjmallett * Redistribution and use in source and binary forms, with or without 7210284Sjmallett * modification, are permitted provided that the following conditions are 8210284Sjmallett * met: 9210284Sjmallett * 10210284Sjmallett * * Redistributions of source code must retain the above copyright 11210284Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13210284Sjmallett * * Redistributions in binary form must reproduce the above 14210284Sjmallett * copyright notice, this list of conditions and the following 15210284Sjmallett * disclaimer in the documentation and/or other materials provided 16210284Sjmallett * with the distribution. 17210284Sjmallett * 18210284Sjmallett * * Neither the name of Cavium Networks nor the names of 19210284Sjmallett * its contributors may be used to endorse or promote products 20210284Sjmallett * derived from this software without specific prior written 21210284Sjmallett * permission. 22210284Sjmallett * 23210284Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24210284Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25210284Sjmallett * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26210284Sjmallett * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27210284Sjmallett * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28210284Sjmallett * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29210284Sjmallett * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30210284Sjmallett * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31210284Sjmallett * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32210284Sjmallett * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33210284Sjmallett * 34210284Sjmallett * 35210284Sjmallett * For any questions regarding licensing please contact marketing@caviumnetworks.com 36210284Sjmallett * 37210284Sjmallett ***********************license end**************************************/ 38210284Sjmallett 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett/** 45210284Sjmallett * @file 46210284Sjmallett * 47210284Sjmallett * Interface to RAID block. This is not available on all chips. 48210284Sjmallett * 49210284Sjmallett * <hr>$Revision: 41586 $<hr> 50210284Sjmallett */ 51210284Sjmallett 52210284Sjmallett#ifndef __CVMX_RAID_H__ 53210284Sjmallett#define __CVMX_RAID_H__ 54210284Sjmallett 55210284Sjmallett#ifdef __cplusplus 56210284Sjmallettextern "C" { 57210284Sjmallett#endif 58210284Sjmallett 59210284Sjmallett/** 60210284Sjmallett * This structure defines the type of command words the RAID block 61210284Sjmallett * will accept. 62210284Sjmallett */ 63210284Sjmalletttypedef union 64210284Sjmallett{ 65210284Sjmallett uint64_t u64; 66210284Sjmallett struct 67210284Sjmallett { 68210284Sjmallett uint64_t reserved_37_63 : 27; /**< Must be zero */ 69210284Sjmallett uint64_t q_cmp : 1; /**< Indicates whether the Q pipe is in normal mode (CWORD[Q_CMP]=0) or in non-zero 70210284Sjmallett byte detect mode (CWORD[Q_CMP]=1). 71210284Sjmallett In non-zero byte detect mode, the Q OWORD[PTR] result is the non-zero detect 72210284Sjmallett result, which indicates the position of the first non-zero byte in the pipe result bytes. 73210284Sjmallett CWORD[Q_CMP] must not be set when CWORD[QOUT]=0, and must not be set 74210284Sjmallett when CWORD[Q_XOR] is set. */ 75210284Sjmallett uint64_t p_cmp : 1; /**< Indicates whether the P pipe is in normal mode (CWORD[P_CMP]=0) or in non-zero 76210284Sjmallett byte detect mode (CWORD[P_CMP]=1). 77210284Sjmallett In non-zero byte detect mode, the P OWORD[PTR] result is the non-zero detect 78210284Sjmallett result, which indicates the position of the first non-zero byte in the pipe result bytes. 79210284Sjmallett CWORD[P_CMP] must not be set when CWORD[POUT]=0, and must not be set 80210284Sjmallett when CWORD[P_XOR] is set. */ 81210284Sjmallett uint64_t q_xor : 1; /**< Indicates whether the Q output buffer bytes are the normal Q pipe result or the 82210284Sjmallett normal Q pipe result exclusive-OR'ed with the P pipe result. 83210284Sjmallett When CWORD[Q_XOR]=0 (and CWORD[Q_CMP]=0), the Q output buffer bytes are 84210284Sjmallett the normal Q pipe result, which does not include the P pipe result in any way. 85210284Sjmallett When CWORD[Q_XOR]=1, the Q output buffer bytes are the normal Q pipe result 86210284Sjmallett exclusive-OR'ed with the P pipe result, as if the P pipe result were another Q IWORD 87210284Sjmallett for the Q pipe with QMULT=1. 88210284Sjmallett CWORD[Q_XOR] must not be set unless both CWORD[POUT,QOUT] are set, and 89210284Sjmallett must not be set when CWORD[Q_CMP] is set. */ 90210284Sjmallett uint64_t p_xor : 1; /**< Indicates whether the P output buffer bytes are the normal P pipe result or the 91210284Sjmallett normal P pipe result exclusive-OR'ed with the Q pipe result. 92210284Sjmallett When CWORD[P_XOR]=0 (and CWORD[P_CMP]=0), the P output buffer bytes are 93210284Sjmallett the normal P pipe result, which does not include the Q pipe result in any way. 94210284Sjmallett When CWORD[P_XOR]=1, the P output buffer bytes are the normal P pipe result 95210284Sjmallett exclusive-OR'ed with the Q pipe result, as if the Q pipe result were another P 96210284Sjmallett IWORD for the P pipe. 97210284Sjmallett CWORD[P_XOR] must not be set unless both CWORD[POUT,QOUT] are set, and 98210284Sjmallett must not be set when CWORD[P_CMP] is set. */ 99210284Sjmallett uint64_t wqe : 1; /**< Indicates whether RAD submits a work queue entry or writes an L2/DRAM byte to 100210284Sjmallett zero after completing the instruction. 101210284Sjmallett When CWORD[WQE] is set and RESP[PTR]!=0, RAD adds the work queue entry 102210284Sjmallett indicated by RESP[PTR] to the selected POW input queue after completing the 103210284Sjmallett instruction. 104210284Sjmallett When CWORD[WQE] is clear and RESP[PTR]!=0, RAD writes the L2/DRAM byte 105210284Sjmallett indicated by RESP[PTR] to zero after completing the instruction. */ 106210284Sjmallett uint64_t qout : 1; /**< Indicates whether the Q pipe is used by this instruction. 107210284Sjmallett If CWORD[QOUT] is set, IWORD[QEN] must be set for at least one IWORD. 108210284Sjmallett At least one of CWORD[QOUT,POUT] must be set. */ 109210284Sjmallett uint64_t pout : 1; /**< Indicates whether the P pipe is used by this instruction. 110210284Sjmallett If CWORD[POUT] is set, IWORD[PEN] must be set for at least one IWORD. 111210284Sjmallett At least one of CWORD[QOUT,POUT] must be set. */ 112210284Sjmallett uint64_t iword : 6; /**< Indicates the number of input buffers used. 113210284Sjmallett 1 <= CWORD[IWORD] <= 32. */ 114210284Sjmallett uint64_t size : 24; /**< Indicates the size in bytes of all input buffers. When CWORD[Q_CMP,P_CMP]=0, 115210284Sjmallett also indicates the size of the Q/P output buffers. 116210284Sjmallett CWORD[SIZE] must be a multiple of 8B (i.e. <2:0> must be zero). */ 117210284Sjmallett } cword; 118210284Sjmallett struct 119210284Sjmallett { 120210284Sjmallett uint64_t reserved_58_63 : 6; /**< Must be zero */ 121210284Sjmallett uint64_t fw : 1; /**< When set, indicates that RAD can modify any byte in any (128B) cache line touched 122210284Sjmallett by L2/DRAM addresses OWORD[PTR] through OWORD[PTR]+CWORD[SIZE]�1. 123210284Sjmallett Setting OWORD[FW] can improve hardware performance, as some DRAM loads can 124210284Sjmallett be avoided on L2 cache misses. The Q OWORD[FW] must not be set when 125210284Sjmallett CWORD[Q_CMP] is set, and the P OWORD[FW] must not be set when 126210284Sjmallett CWORD[P_CMP] is set. */ 127210284Sjmallett uint64_t nc : 1; /**< When set, indicates that RAD should not allocate L2 cache space for the P/Q data on 128210284Sjmallett L2 cache misses. 129210284Sjmallett OWORD[NC] should typically be clear, though setting OWORD[NC] can improve 130210284Sjmallett performance in some circumstances, as the L2 cache will not be polluted by P/Q data. 131210284Sjmallett The Q OWORD[NC] must not be set when CWORD[Q_CMP] is set, and the P 132210284Sjmallett OWORD[NC] must not be set when CWORD[P_CMP] is set. */ 133210284Sjmallett uint64_t reserved_40_55 : 16; /**< Must be zero */ 134210284Sjmallett uint64_t addr : 40; /**< When CWORD[P_CMP,Q_CMP]=0, OWORD[PTR] indicates the starting address of 135210284Sjmallett the L2/DRAM buffer that will receive the P/Q data. In the non-compare mode, the 136210284Sjmallett output buffer receives all of the output buffer bytes. 137210284Sjmallett When CWORD[P_CMP,Q_CMP]=1, the corresponding P/Q pipe is in compare mode, 138210284Sjmallett and the only output of the pipe is the non-zero detect result. In this case, 139210284Sjmallett OWORD[PTR] indicates the 8-byte location of the non-zero detect result. */ 140210284Sjmallett } oword; 141210284Sjmallett struct 142210284Sjmallett { 143210284Sjmallett uint64_t reserved_57_63 : 7; /**< Must be zero */ 144210284Sjmallett uint64_t nc : 1; /**< When set, indicates that RAD should not allocate L2 cache space for this input buffer 145210284Sjmallett data on L2 cache misses. 146210284Sjmallett Setting IWORD[NC] may improve performance in some circumstances, as the L2 147210284Sjmallett cache may not be polluted with input buffer data. */ 148210284Sjmallett uint64_t reserved_50_55 : 6; /**< Must be zero */ 149210284Sjmallett uint64_t qen : 1; /**< Indicates that this input buffer data should participate in the Q pipe result. 150210284Sjmallett The Q pipe hardware multiplies each participating input byte by IWORD[QMULT] 151210284Sjmallett before accumulating them by exclusive-OR'ing. 152210284Sjmallett IWORD[QEN] must not be set when CWORD[QOUT] is not set. 153210284Sjmallett If CWORD[QOUT] is set, IWORD[QEN] must be set for at least one IWORD. */ 154210284Sjmallett uint64_t pen : 1; /**< Indicates that this input buffer data should participate in the P pipe result. 155210284Sjmallett The P pipe hardware accumulates each participating input byte by bit-wise 156210284Sjmallett exclusive-OR'ing it. 157210284Sjmallett IWORD[PEN] must not be set when CWORD[POUT] is not set. 158210284Sjmallett If CWORD[POUT] is set, IWORD[PEN] must be set for at least one IWORD. */ 159210284Sjmallett uint64_t qmult : 8; /**< The Q pipe multiplier for the input buffer. Section 26.1 above describes the GF(28) 160210284Sjmallett multiplication algorithm. 161210284Sjmallett IWORD[QMULT] must be zero when IWORD[QEN] is not set. 162210284Sjmallett IWORD[QMULT] must not be zero when IWORD[QEN] is set. 163210284Sjmallett When IWORD[QMULT] is 1, the multiplication simplifies to the identity function, 164210284Sjmallett and the Q pipe performs the same XOR function as the P pipe. */ 165210284Sjmallett uint64_t addr : 40; /**< The starting address of the input buffer in L2/DRAM. 166210284Sjmallett IWORD[PTR] must be naturally-aligned on an 8 byte boundary (i.e. <2:0> must be 167210284Sjmallett zero). */ 168210284Sjmallett } iword; 169210284Sjmallett} cvmx_raid_word_t; 170210284Sjmallett 171210284Sjmallett/** 172210284Sjmallett * Initialize the RAID block 173210284Sjmallett * 174210284Sjmallett * @param polynomial Coefficients for the RAID polynomial 175210284Sjmallett * 176210284Sjmallett * @return Zero on success, negative on failure 177210284Sjmallett */ 178210284Sjmallettint cvmx_raid_initialize(cvmx_rad_reg_polynomial_t polynomial); 179210284Sjmallett 180210284Sjmallett/** 181210284Sjmallett * Shutdown the RAID block. RAID must be idle when 182210284Sjmallett * this function is called. 183210284Sjmallett * 184210284Sjmallett * @return Zero on success, negative on failure 185210284Sjmallett */ 186210284Sjmallettint cvmx_raid_shutdown(void); 187210284Sjmallett 188210284Sjmallett/** 189210284Sjmallett * Submit a command to the RAID block 190210284Sjmallett * 191210284Sjmallett * @param num_words Number of command words to submit 192210284Sjmallett * @param words Command words 193210284Sjmallett * 194210284Sjmallett * @return Zero on success, negative on failure 195210284Sjmallett */ 196210284Sjmallettint cvmx_raid_submit(int num_words, cvmx_raid_word_t words[]); 197210284Sjmallett 198210284Sjmallett#ifdef __cplusplus 199210284Sjmallett} 200210284Sjmallett#endif 201210284Sjmallett 202210284Sjmallett#endif // __CVMX_CMD_QUEUE_H__ 203