cvmx-pcieepx-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pcieepx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pcieepx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCIEEPX_TYPEDEFS_H__ 53#define __CVMX_PCIEEPX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 61 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 62 cvmx_warn("CVMX_PCIEEPX_CFG000(%lu) is invalid on this chip\n", block_id); 63 return 0x0000000000000000ull; 64} 65#else 66#define CVMX_PCIEEPX_CFG000(block_id) (0x0000000000000000ull) 67#endif 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69static inline uint64_t CVMX_PCIEEPX_CFG001(unsigned long block_id) 70{ 71 if (!( 72 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 73 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 74 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 75 cvmx_warn("CVMX_PCIEEPX_CFG001(%lu) is invalid on this chip\n", block_id); 76 return 0x0000000000000004ull; 77} 78#else 79#define CVMX_PCIEEPX_CFG001(block_id) (0x0000000000000004ull) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82static inline uint64_t CVMX_PCIEEPX_CFG002(unsigned long block_id) 83{ 84 if (!( 85 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 86 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 87 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 88 cvmx_warn("CVMX_PCIEEPX_CFG002(%lu) is invalid on this chip\n", block_id); 89 return 0x0000000000000008ull; 90} 91#else 92#define CVMX_PCIEEPX_CFG002(block_id) (0x0000000000000008ull) 93#endif 94#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95static inline uint64_t CVMX_PCIEEPX_CFG003(unsigned long block_id) 96{ 97 if (!( 98 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 99 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 100 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 101 cvmx_warn("CVMX_PCIEEPX_CFG003(%lu) is invalid on this chip\n", block_id); 102 return 0x000000000000000Cull; 103} 104#else 105#define CVMX_PCIEEPX_CFG003(block_id) (0x000000000000000Cull) 106#endif 107#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108static inline uint64_t CVMX_PCIEEPX_CFG004(unsigned long block_id) 109{ 110 if (!( 111 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 112 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 113 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 114 cvmx_warn("CVMX_PCIEEPX_CFG004(%lu) is invalid on this chip\n", block_id); 115 return 0x0000000000000010ull; 116} 117#else 118#define CVMX_PCIEEPX_CFG004(block_id) (0x0000000000000010ull) 119#endif 120#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121static inline uint64_t CVMX_PCIEEPX_CFG004_MASK(unsigned long block_id) 122{ 123 if (!( 124 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 125 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 126 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 127 cvmx_warn("CVMX_PCIEEPX_CFG004_MASK(%lu) is invalid on this chip\n", block_id); 128 return 0x0000000080000010ull; 129} 130#else 131#define CVMX_PCIEEPX_CFG004_MASK(block_id) (0x0000000080000010ull) 132#endif 133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134static inline uint64_t CVMX_PCIEEPX_CFG005(unsigned long block_id) 135{ 136 if (!( 137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 139 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 140 cvmx_warn("CVMX_PCIEEPX_CFG005(%lu) is invalid on this chip\n", block_id); 141 return 0x0000000000000014ull; 142} 143#else 144#define CVMX_PCIEEPX_CFG005(block_id) (0x0000000000000014ull) 145#endif 146#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147static inline uint64_t CVMX_PCIEEPX_CFG005_MASK(unsigned long block_id) 148{ 149 if (!( 150 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 151 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 152 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 153 cvmx_warn("CVMX_PCIEEPX_CFG005_MASK(%lu) is invalid on this chip\n", block_id); 154 return 0x0000000080000014ull; 155} 156#else 157#define CVMX_PCIEEPX_CFG005_MASK(block_id) (0x0000000080000014ull) 158#endif 159#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160static inline uint64_t CVMX_PCIEEPX_CFG006(unsigned long block_id) 161{ 162 if (!( 163 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 164 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 165 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 166 cvmx_warn("CVMX_PCIEEPX_CFG006(%lu) is invalid on this chip\n", block_id); 167 return 0x0000000000000018ull; 168} 169#else 170#define CVMX_PCIEEPX_CFG006(block_id) (0x0000000000000018ull) 171#endif 172#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173static inline uint64_t CVMX_PCIEEPX_CFG006_MASK(unsigned long block_id) 174{ 175 if (!( 176 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 177 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 178 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 179 cvmx_warn("CVMX_PCIEEPX_CFG006_MASK(%lu) is invalid on this chip\n", block_id); 180 return 0x0000000080000018ull; 181} 182#else 183#define CVMX_PCIEEPX_CFG006_MASK(block_id) (0x0000000080000018ull) 184#endif 185#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186static inline uint64_t CVMX_PCIEEPX_CFG007(unsigned long block_id) 187{ 188 if (!( 189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 192 cvmx_warn("CVMX_PCIEEPX_CFG007(%lu) is invalid on this chip\n", block_id); 193 return 0x000000000000001Cull; 194} 195#else 196#define CVMX_PCIEEPX_CFG007(block_id) (0x000000000000001Cull) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_PCIEEPX_CFG007_MASK(unsigned long block_id) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 203 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 204 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 205 cvmx_warn("CVMX_PCIEEPX_CFG007_MASK(%lu) is invalid on this chip\n", block_id); 206 return 0x000000008000001Cull; 207} 208#else 209#define CVMX_PCIEEPX_CFG007_MASK(block_id) (0x000000008000001Cull) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_PCIEEPX_CFG008(unsigned long block_id) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 216 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 217 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 218 cvmx_warn("CVMX_PCIEEPX_CFG008(%lu) is invalid on this chip\n", block_id); 219 return 0x0000000000000020ull; 220} 221#else 222#define CVMX_PCIEEPX_CFG008(block_id) (0x0000000000000020ull) 223#endif 224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225static inline uint64_t CVMX_PCIEEPX_CFG008_MASK(unsigned long block_id) 226{ 227 if (!( 228 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 229 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 230 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 231 cvmx_warn("CVMX_PCIEEPX_CFG008_MASK(%lu) is invalid on this chip\n", block_id); 232 return 0x0000000080000020ull; 233} 234#else 235#define CVMX_PCIEEPX_CFG008_MASK(block_id) (0x0000000080000020ull) 236#endif 237#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 238static inline uint64_t CVMX_PCIEEPX_CFG009(unsigned long block_id) 239{ 240 if (!( 241 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 242 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 244 cvmx_warn("CVMX_PCIEEPX_CFG009(%lu) is invalid on this chip\n", block_id); 245 return 0x0000000000000024ull; 246} 247#else 248#define CVMX_PCIEEPX_CFG009(block_id) (0x0000000000000024ull) 249#endif 250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251static inline uint64_t CVMX_PCIEEPX_CFG009_MASK(unsigned long block_id) 252{ 253 if (!( 254 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 255 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 256 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 257 cvmx_warn("CVMX_PCIEEPX_CFG009_MASK(%lu) is invalid on this chip\n", block_id); 258 return 0x0000000080000024ull; 259} 260#else 261#define CVMX_PCIEEPX_CFG009_MASK(block_id) (0x0000000080000024ull) 262#endif 263#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264static inline uint64_t CVMX_PCIEEPX_CFG010(unsigned long block_id) 265{ 266 if (!( 267 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 268 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 269 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 270 cvmx_warn("CVMX_PCIEEPX_CFG010(%lu) is invalid on this chip\n", block_id); 271 return 0x0000000000000028ull; 272} 273#else 274#define CVMX_PCIEEPX_CFG010(block_id) (0x0000000000000028ull) 275#endif 276#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277static inline uint64_t CVMX_PCIEEPX_CFG011(unsigned long block_id) 278{ 279 if (!( 280 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 281 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 282 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 283 cvmx_warn("CVMX_PCIEEPX_CFG011(%lu) is invalid on this chip\n", block_id); 284 return 0x000000000000002Cull; 285} 286#else 287#define CVMX_PCIEEPX_CFG011(block_id) (0x000000000000002Cull) 288#endif 289#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 290static inline uint64_t CVMX_PCIEEPX_CFG012(unsigned long block_id) 291{ 292 if (!( 293 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 294 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 295 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 296 cvmx_warn("CVMX_PCIEEPX_CFG012(%lu) is invalid on this chip\n", block_id); 297 return 0x0000000000000030ull; 298} 299#else 300#define CVMX_PCIEEPX_CFG012(block_id) (0x0000000000000030ull) 301#endif 302#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 303static inline uint64_t CVMX_PCIEEPX_CFG012_MASK(unsigned long block_id) 304{ 305 if (!( 306 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 307 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 308 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 309 cvmx_warn("CVMX_PCIEEPX_CFG012_MASK(%lu) is invalid on this chip\n", block_id); 310 return 0x0000000080000030ull; 311} 312#else 313#define CVMX_PCIEEPX_CFG012_MASK(block_id) (0x0000000080000030ull) 314#endif 315#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 316static inline uint64_t CVMX_PCIEEPX_CFG013(unsigned long block_id) 317{ 318 if (!( 319 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 320 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 321 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 322 cvmx_warn("CVMX_PCIEEPX_CFG013(%lu) is invalid on this chip\n", block_id); 323 return 0x0000000000000034ull; 324} 325#else 326#define CVMX_PCIEEPX_CFG013(block_id) (0x0000000000000034ull) 327#endif 328#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329static inline uint64_t CVMX_PCIEEPX_CFG015(unsigned long block_id) 330{ 331 if (!( 332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 335 cvmx_warn("CVMX_PCIEEPX_CFG015(%lu) is invalid on this chip\n", block_id); 336 return 0x000000000000003Cull; 337} 338#else 339#define CVMX_PCIEEPX_CFG015(block_id) (0x000000000000003Cull) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342static inline uint64_t CVMX_PCIEEPX_CFG016(unsigned long block_id) 343{ 344 if (!( 345 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 346 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 347 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 348 cvmx_warn("CVMX_PCIEEPX_CFG016(%lu) is invalid on this chip\n", block_id); 349 return 0x0000000000000040ull; 350} 351#else 352#define CVMX_PCIEEPX_CFG016(block_id) (0x0000000000000040ull) 353#endif 354#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355static inline uint64_t CVMX_PCIEEPX_CFG017(unsigned long block_id) 356{ 357 if (!( 358 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 359 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 360 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 361 cvmx_warn("CVMX_PCIEEPX_CFG017(%lu) is invalid on this chip\n", block_id); 362 return 0x0000000000000044ull; 363} 364#else 365#define CVMX_PCIEEPX_CFG017(block_id) (0x0000000000000044ull) 366#endif 367#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368static inline uint64_t CVMX_PCIEEPX_CFG020(unsigned long block_id) 369{ 370 if (!( 371 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 372 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 373 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 374 cvmx_warn("CVMX_PCIEEPX_CFG020(%lu) is invalid on this chip\n", block_id); 375 return 0x0000000000000050ull; 376} 377#else 378#define CVMX_PCIEEPX_CFG020(block_id) (0x0000000000000050ull) 379#endif 380#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 381static inline uint64_t CVMX_PCIEEPX_CFG021(unsigned long block_id) 382{ 383 if (!( 384 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 385 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 386 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 387 cvmx_warn("CVMX_PCIEEPX_CFG021(%lu) is invalid on this chip\n", block_id); 388 return 0x0000000000000054ull; 389} 390#else 391#define CVMX_PCIEEPX_CFG021(block_id) (0x0000000000000054ull) 392#endif 393#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 394static inline uint64_t CVMX_PCIEEPX_CFG022(unsigned long block_id) 395{ 396 if (!( 397 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 398 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 399 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 400 cvmx_warn("CVMX_PCIEEPX_CFG022(%lu) is invalid on this chip\n", block_id); 401 return 0x0000000000000058ull; 402} 403#else 404#define CVMX_PCIEEPX_CFG022(block_id) (0x0000000000000058ull) 405#endif 406#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 407static inline uint64_t CVMX_PCIEEPX_CFG023(unsigned long block_id) 408{ 409 if (!( 410 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 411 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 412 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 413 cvmx_warn("CVMX_PCIEEPX_CFG023(%lu) is invalid on this chip\n", block_id); 414 return 0x000000000000005Cull; 415} 416#else 417#define CVMX_PCIEEPX_CFG023(block_id) (0x000000000000005Cull) 418#endif 419#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 420static inline uint64_t CVMX_PCIEEPX_CFG028(unsigned long block_id) 421{ 422 if (!( 423 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 424 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 425 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 426 cvmx_warn("CVMX_PCIEEPX_CFG028(%lu) is invalid on this chip\n", block_id); 427 return 0x0000000000000070ull; 428} 429#else 430#define CVMX_PCIEEPX_CFG028(block_id) (0x0000000000000070ull) 431#endif 432#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 433static inline uint64_t CVMX_PCIEEPX_CFG029(unsigned long block_id) 434{ 435 if (!( 436 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 437 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 438 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 439 cvmx_warn("CVMX_PCIEEPX_CFG029(%lu) is invalid on this chip\n", block_id); 440 return 0x0000000000000074ull; 441} 442#else 443#define CVMX_PCIEEPX_CFG029(block_id) (0x0000000000000074ull) 444#endif 445#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446static inline uint64_t CVMX_PCIEEPX_CFG030(unsigned long block_id) 447{ 448 if (!( 449 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 450 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 451 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 452 cvmx_warn("CVMX_PCIEEPX_CFG030(%lu) is invalid on this chip\n", block_id); 453 return 0x0000000000000078ull; 454} 455#else 456#define CVMX_PCIEEPX_CFG030(block_id) (0x0000000000000078ull) 457#endif 458#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 459static inline uint64_t CVMX_PCIEEPX_CFG031(unsigned long block_id) 460{ 461 if (!( 462 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 463 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 464 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 465 cvmx_warn("CVMX_PCIEEPX_CFG031(%lu) is invalid on this chip\n", block_id); 466 return 0x000000000000007Cull; 467} 468#else 469#define CVMX_PCIEEPX_CFG031(block_id) (0x000000000000007Cull) 470#endif 471#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 472static inline uint64_t CVMX_PCIEEPX_CFG032(unsigned long block_id) 473{ 474 if (!( 475 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 476 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 477 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 478 cvmx_warn("CVMX_PCIEEPX_CFG032(%lu) is invalid on this chip\n", block_id); 479 return 0x0000000000000080ull; 480} 481#else 482#define CVMX_PCIEEPX_CFG032(block_id) (0x0000000000000080ull) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485static inline uint64_t CVMX_PCIEEPX_CFG033(unsigned long block_id) 486{ 487 if (!( 488 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 489 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 490 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 491 cvmx_warn("CVMX_PCIEEPX_CFG033(%lu) is invalid on this chip\n", block_id); 492 return 0x0000000000000084ull; 493} 494#else 495#define CVMX_PCIEEPX_CFG033(block_id) (0x0000000000000084ull) 496#endif 497#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498static inline uint64_t CVMX_PCIEEPX_CFG034(unsigned long block_id) 499{ 500 if (!( 501 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 502 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 503 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 504 cvmx_warn("CVMX_PCIEEPX_CFG034(%lu) is invalid on this chip\n", block_id); 505 return 0x0000000000000088ull; 506} 507#else 508#define CVMX_PCIEEPX_CFG034(block_id) (0x0000000000000088ull) 509#endif 510#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 511static inline uint64_t CVMX_PCIEEPX_CFG037(unsigned long block_id) 512{ 513 if (!( 514 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 515 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 516 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 517 cvmx_warn("CVMX_PCIEEPX_CFG037(%lu) is invalid on this chip\n", block_id); 518 return 0x0000000000000094ull; 519} 520#else 521#define CVMX_PCIEEPX_CFG037(block_id) (0x0000000000000094ull) 522#endif 523#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 524static inline uint64_t CVMX_PCIEEPX_CFG038(unsigned long block_id) 525{ 526 if (!( 527 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 528 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 529 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 530 cvmx_warn("CVMX_PCIEEPX_CFG038(%lu) is invalid on this chip\n", block_id); 531 return 0x0000000000000098ull; 532} 533#else 534#define CVMX_PCIEEPX_CFG038(block_id) (0x0000000000000098ull) 535#endif 536#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 537static inline uint64_t CVMX_PCIEEPX_CFG039(unsigned long block_id) 538{ 539 if (!( 540 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 541 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 542 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 543 cvmx_warn("CVMX_PCIEEPX_CFG039(%lu) is invalid on this chip\n", block_id); 544 return 0x000000000000009Cull; 545} 546#else 547#define CVMX_PCIEEPX_CFG039(block_id) (0x000000000000009Cull) 548#endif 549#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 550static inline uint64_t CVMX_PCIEEPX_CFG040(unsigned long block_id) 551{ 552 if (!( 553 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 554 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 555 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 556 cvmx_warn("CVMX_PCIEEPX_CFG040(%lu) is invalid on this chip\n", block_id); 557 return 0x00000000000000A0ull; 558} 559#else 560#define CVMX_PCIEEPX_CFG040(block_id) (0x00000000000000A0ull) 561#endif 562#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 563static inline uint64_t CVMX_PCIEEPX_CFG041(unsigned long block_id) 564{ 565 if (!( 566 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 567 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 568 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 569 cvmx_warn("CVMX_PCIEEPX_CFG041(%lu) is invalid on this chip\n", block_id); 570 return 0x00000000000000A4ull; 571} 572#else 573#define CVMX_PCIEEPX_CFG041(block_id) (0x00000000000000A4ull) 574#endif 575#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 576static inline uint64_t CVMX_PCIEEPX_CFG042(unsigned long block_id) 577{ 578 if (!( 579 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 580 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 581 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 582 cvmx_warn("CVMX_PCIEEPX_CFG042(%lu) is invalid on this chip\n", block_id); 583 return 0x00000000000000A8ull; 584} 585#else 586#define CVMX_PCIEEPX_CFG042(block_id) (0x00000000000000A8ull) 587#endif 588#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 589static inline uint64_t CVMX_PCIEEPX_CFG064(unsigned long block_id) 590{ 591 if (!( 592 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 593 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 594 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 595 cvmx_warn("CVMX_PCIEEPX_CFG064(%lu) is invalid on this chip\n", block_id); 596 return 0x0000000000000100ull; 597} 598#else 599#define CVMX_PCIEEPX_CFG064(block_id) (0x0000000000000100ull) 600#endif 601#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 602static inline uint64_t CVMX_PCIEEPX_CFG065(unsigned long block_id) 603{ 604 if (!( 605 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 606 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 607 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 608 cvmx_warn("CVMX_PCIEEPX_CFG065(%lu) is invalid on this chip\n", block_id); 609 return 0x0000000000000104ull; 610} 611#else 612#define CVMX_PCIEEPX_CFG065(block_id) (0x0000000000000104ull) 613#endif 614#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 615static inline uint64_t CVMX_PCIEEPX_CFG066(unsigned long block_id) 616{ 617 if (!( 618 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 619 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 620 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 621 cvmx_warn("CVMX_PCIEEPX_CFG066(%lu) is invalid on this chip\n", block_id); 622 return 0x0000000000000108ull; 623} 624#else 625#define CVMX_PCIEEPX_CFG066(block_id) (0x0000000000000108ull) 626#endif 627#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628static inline uint64_t CVMX_PCIEEPX_CFG067(unsigned long block_id) 629{ 630 if (!( 631 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 632 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 633 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 634 cvmx_warn("CVMX_PCIEEPX_CFG067(%lu) is invalid on this chip\n", block_id); 635 return 0x000000000000010Cull; 636} 637#else 638#define CVMX_PCIEEPX_CFG067(block_id) (0x000000000000010Cull) 639#endif 640#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 641static inline uint64_t CVMX_PCIEEPX_CFG068(unsigned long block_id) 642{ 643 if (!( 644 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 645 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 646 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 647 cvmx_warn("CVMX_PCIEEPX_CFG068(%lu) is invalid on this chip\n", block_id); 648 return 0x0000000000000110ull; 649} 650#else 651#define CVMX_PCIEEPX_CFG068(block_id) (0x0000000000000110ull) 652#endif 653#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 654static inline uint64_t CVMX_PCIEEPX_CFG069(unsigned long block_id) 655{ 656 if (!( 657 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 658 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 659 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 660 cvmx_warn("CVMX_PCIEEPX_CFG069(%lu) is invalid on this chip\n", block_id); 661 return 0x0000000000000114ull; 662} 663#else 664#define CVMX_PCIEEPX_CFG069(block_id) (0x0000000000000114ull) 665#endif 666#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 667static inline uint64_t CVMX_PCIEEPX_CFG070(unsigned long block_id) 668{ 669 if (!( 670 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 671 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 672 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 673 cvmx_warn("CVMX_PCIEEPX_CFG070(%lu) is invalid on this chip\n", block_id); 674 return 0x0000000000000118ull; 675} 676#else 677#define CVMX_PCIEEPX_CFG070(block_id) (0x0000000000000118ull) 678#endif 679#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 680static inline uint64_t CVMX_PCIEEPX_CFG071(unsigned long block_id) 681{ 682 if (!( 683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 685 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 686 cvmx_warn("CVMX_PCIEEPX_CFG071(%lu) is invalid on this chip\n", block_id); 687 return 0x000000000000011Cull; 688} 689#else 690#define CVMX_PCIEEPX_CFG071(block_id) (0x000000000000011Cull) 691#endif 692#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 693static inline uint64_t CVMX_PCIEEPX_CFG072(unsigned long block_id) 694{ 695 if (!( 696 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 697 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 698 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 699 cvmx_warn("CVMX_PCIEEPX_CFG072(%lu) is invalid on this chip\n", block_id); 700 return 0x0000000000000120ull; 701} 702#else 703#define CVMX_PCIEEPX_CFG072(block_id) (0x0000000000000120ull) 704#endif 705#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 706static inline uint64_t CVMX_PCIEEPX_CFG073(unsigned long block_id) 707{ 708 if (!( 709 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 710 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 711 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 712 cvmx_warn("CVMX_PCIEEPX_CFG073(%lu) is invalid on this chip\n", block_id); 713 return 0x0000000000000124ull; 714} 715#else 716#define CVMX_PCIEEPX_CFG073(block_id) (0x0000000000000124ull) 717#endif 718#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 719static inline uint64_t CVMX_PCIEEPX_CFG074(unsigned long block_id) 720{ 721 if (!( 722 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 723 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 724 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 725 cvmx_warn("CVMX_PCIEEPX_CFG074(%lu) is invalid on this chip\n", block_id); 726 return 0x0000000000000128ull; 727} 728#else 729#define CVMX_PCIEEPX_CFG074(block_id) (0x0000000000000128ull) 730#endif 731#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 732static inline uint64_t CVMX_PCIEEPX_CFG448(unsigned long block_id) 733{ 734 if (!( 735 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 736 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 737 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 738 cvmx_warn("CVMX_PCIEEPX_CFG448(%lu) is invalid on this chip\n", block_id); 739 return 0x0000000000000700ull; 740} 741#else 742#define CVMX_PCIEEPX_CFG448(block_id) (0x0000000000000700ull) 743#endif 744#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 745static inline uint64_t CVMX_PCIEEPX_CFG449(unsigned long block_id) 746{ 747 if (!( 748 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 749 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 750 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 751 cvmx_warn("CVMX_PCIEEPX_CFG449(%lu) is invalid on this chip\n", block_id); 752 return 0x0000000000000704ull; 753} 754#else 755#define CVMX_PCIEEPX_CFG449(block_id) (0x0000000000000704ull) 756#endif 757#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 758static inline uint64_t CVMX_PCIEEPX_CFG450(unsigned long block_id) 759{ 760 if (!( 761 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 762 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 763 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 764 cvmx_warn("CVMX_PCIEEPX_CFG450(%lu) is invalid on this chip\n", block_id); 765 return 0x0000000000000708ull; 766} 767#else 768#define CVMX_PCIEEPX_CFG450(block_id) (0x0000000000000708ull) 769#endif 770#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771static inline uint64_t CVMX_PCIEEPX_CFG451(unsigned long block_id) 772{ 773 if (!( 774 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 775 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 776 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 777 cvmx_warn("CVMX_PCIEEPX_CFG451(%lu) is invalid on this chip\n", block_id); 778 return 0x000000000000070Cull; 779} 780#else 781#define CVMX_PCIEEPX_CFG451(block_id) (0x000000000000070Cull) 782#endif 783#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 784static inline uint64_t CVMX_PCIEEPX_CFG452(unsigned long block_id) 785{ 786 if (!( 787 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 788 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 789 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 790 cvmx_warn("CVMX_PCIEEPX_CFG452(%lu) is invalid on this chip\n", block_id); 791 return 0x0000000000000710ull; 792} 793#else 794#define CVMX_PCIEEPX_CFG452(block_id) (0x0000000000000710ull) 795#endif 796#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 797static inline uint64_t CVMX_PCIEEPX_CFG453(unsigned long block_id) 798{ 799 if (!( 800 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 801 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 802 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 803 cvmx_warn("CVMX_PCIEEPX_CFG453(%lu) is invalid on this chip\n", block_id); 804 return 0x0000000000000714ull; 805} 806#else 807#define CVMX_PCIEEPX_CFG453(block_id) (0x0000000000000714ull) 808#endif 809#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 810static inline uint64_t CVMX_PCIEEPX_CFG454(unsigned long block_id) 811{ 812 if (!( 813 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 814 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 815 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 816 cvmx_warn("CVMX_PCIEEPX_CFG454(%lu) is invalid on this chip\n", block_id); 817 return 0x0000000000000718ull; 818} 819#else 820#define CVMX_PCIEEPX_CFG454(block_id) (0x0000000000000718ull) 821#endif 822#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 823static inline uint64_t CVMX_PCIEEPX_CFG455(unsigned long block_id) 824{ 825 if (!( 826 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 827 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 828 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 829 cvmx_warn("CVMX_PCIEEPX_CFG455(%lu) is invalid on this chip\n", block_id); 830 return 0x000000000000071Cull; 831} 832#else 833#define CVMX_PCIEEPX_CFG455(block_id) (0x000000000000071Cull) 834#endif 835#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 836static inline uint64_t CVMX_PCIEEPX_CFG456(unsigned long block_id) 837{ 838 if (!( 839 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 840 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 841 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 842 cvmx_warn("CVMX_PCIEEPX_CFG456(%lu) is invalid on this chip\n", block_id); 843 return 0x0000000000000720ull; 844} 845#else 846#define CVMX_PCIEEPX_CFG456(block_id) (0x0000000000000720ull) 847#endif 848#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 849static inline uint64_t CVMX_PCIEEPX_CFG458(unsigned long block_id) 850{ 851 if (!( 852 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 853 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 854 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 855 cvmx_warn("CVMX_PCIEEPX_CFG458(%lu) is invalid on this chip\n", block_id); 856 return 0x0000000000000728ull; 857} 858#else 859#define CVMX_PCIEEPX_CFG458(block_id) (0x0000000000000728ull) 860#endif 861#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 862static inline uint64_t CVMX_PCIEEPX_CFG459(unsigned long block_id) 863{ 864 if (!( 865 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 866 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 867 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 868 cvmx_warn("CVMX_PCIEEPX_CFG459(%lu) is invalid on this chip\n", block_id); 869 return 0x000000000000072Cull; 870} 871#else 872#define CVMX_PCIEEPX_CFG459(block_id) (0x000000000000072Cull) 873#endif 874#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 875static inline uint64_t CVMX_PCIEEPX_CFG460(unsigned long block_id) 876{ 877 if (!( 878 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 879 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 880 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 881 cvmx_warn("CVMX_PCIEEPX_CFG460(%lu) is invalid on this chip\n", block_id); 882 return 0x0000000000000730ull; 883} 884#else 885#define CVMX_PCIEEPX_CFG460(block_id) (0x0000000000000730ull) 886#endif 887#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 888static inline uint64_t CVMX_PCIEEPX_CFG461(unsigned long block_id) 889{ 890 if (!( 891 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 892 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 893 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 894 cvmx_warn("CVMX_PCIEEPX_CFG461(%lu) is invalid on this chip\n", block_id); 895 return 0x0000000000000734ull; 896} 897#else 898#define CVMX_PCIEEPX_CFG461(block_id) (0x0000000000000734ull) 899#endif 900#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 901static inline uint64_t CVMX_PCIEEPX_CFG462(unsigned long block_id) 902{ 903 if (!( 904 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 905 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 906 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 907 cvmx_warn("CVMX_PCIEEPX_CFG462(%lu) is invalid on this chip\n", block_id); 908 return 0x0000000000000738ull; 909} 910#else 911#define CVMX_PCIEEPX_CFG462(block_id) (0x0000000000000738ull) 912#endif 913#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 914static inline uint64_t CVMX_PCIEEPX_CFG463(unsigned long block_id) 915{ 916 if (!( 917 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 918 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 919 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 920 cvmx_warn("CVMX_PCIEEPX_CFG463(%lu) is invalid on this chip\n", block_id); 921 return 0x000000000000073Cull; 922} 923#else 924#define CVMX_PCIEEPX_CFG463(block_id) (0x000000000000073Cull) 925#endif 926#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 927static inline uint64_t CVMX_PCIEEPX_CFG464(unsigned long block_id) 928{ 929 if (!( 930 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 931 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 932 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 933 cvmx_warn("CVMX_PCIEEPX_CFG464(%lu) is invalid on this chip\n", block_id); 934 return 0x0000000000000740ull; 935} 936#else 937#define CVMX_PCIEEPX_CFG464(block_id) (0x0000000000000740ull) 938#endif 939#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 940static inline uint64_t CVMX_PCIEEPX_CFG465(unsigned long block_id) 941{ 942 if (!( 943 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 944 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 945 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 946 cvmx_warn("CVMX_PCIEEPX_CFG465(%lu) is invalid on this chip\n", block_id); 947 return 0x0000000000000744ull; 948} 949#else 950#define CVMX_PCIEEPX_CFG465(block_id) (0x0000000000000744ull) 951#endif 952#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 953static inline uint64_t CVMX_PCIEEPX_CFG466(unsigned long block_id) 954{ 955 if (!( 956 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 957 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 958 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 959 cvmx_warn("CVMX_PCIEEPX_CFG466(%lu) is invalid on this chip\n", block_id); 960 return 0x0000000000000748ull; 961} 962#else 963#define CVMX_PCIEEPX_CFG466(block_id) (0x0000000000000748ull) 964#endif 965#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 966static inline uint64_t CVMX_PCIEEPX_CFG467(unsigned long block_id) 967{ 968 if (!( 969 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 970 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 971 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 972 cvmx_warn("CVMX_PCIEEPX_CFG467(%lu) is invalid on this chip\n", block_id); 973 return 0x000000000000074Cull; 974} 975#else 976#define CVMX_PCIEEPX_CFG467(block_id) (0x000000000000074Cull) 977#endif 978#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 979static inline uint64_t CVMX_PCIEEPX_CFG468(unsigned long block_id) 980{ 981 if (!( 982 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 983 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 984 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 985 cvmx_warn("CVMX_PCIEEPX_CFG468(%lu) is invalid on this chip\n", block_id); 986 return 0x0000000000000750ull; 987} 988#else 989#define CVMX_PCIEEPX_CFG468(block_id) (0x0000000000000750ull) 990#endif 991#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 992static inline uint64_t CVMX_PCIEEPX_CFG490(unsigned long block_id) 993{ 994 if (!( 995 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 996 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 997 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 998 cvmx_warn("CVMX_PCIEEPX_CFG490(%lu) is invalid on this chip\n", block_id); 999 return 0x00000000000007A8ull; 1000} 1001#else 1002#define CVMX_PCIEEPX_CFG490(block_id) (0x00000000000007A8ull) 1003#endif 1004#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1005static inline uint64_t CVMX_PCIEEPX_CFG491(unsigned long block_id) 1006{ 1007 if (!( 1008 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1009 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1010 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1011 cvmx_warn("CVMX_PCIEEPX_CFG491(%lu) is invalid on this chip\n", block_id); 1012 return 0x00000000000007ACull; 1013} 1014#else 1015#define CVMX_PCIEEPX_CFG491(block_id) (0x00000000000007ACull) 1016#endif 1017#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1018static inline uint64_t CVMX_PCIEEPX_CFG492(unsigned long block_id) 1019{ 1020 if (!( 1021 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1022 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1023 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1024 cvmx_warn("CVMX_PCIEEPX_CFG492(%lu) is invalid on this chip\n", block_id); 1025 return 0x00000000000007B0ull; 1026} 1027#else 1028#define CVMX_PCIEEPX_CFG492(block_id) (0x00000000000007B0ull) 1029#endif 1030#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1031static inline uint64_t CVMX_PCIEEPX_CFG515(unsigned long block_id) 1032{ 1033 if (!( 1034 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1035 cvmx_warn("CVMX_PCIEEPX_CFG515(%lu) is invalid on this chip\n", block_id); 1036 return 0x000000000000080Cull; 1037} 1038#else 1039#define CVMX_PCIEEPX_CFG515(block_id) (0x000000000000080Cull) 1040#endif 1041#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1042static inline uint64_t CVMX_PCIEEPX_CFG516(unsigned long block_id) 1043{ 1044 if (!( 1045 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1046 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1047 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1048 cvmx_warn("CVMX_PCIEEPX_CFG516(%lu) is invalid on this chip\n", block_id); 1049 return 0x0000000000000810ull; 1050} 1051#else 1052#define CVMX_PCIEEPX_CFG516(block_id) (0x0000000000000810ull) 1053#endif 1054#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1055static inline uint64_t CVMX_PCIEEPX_CFG517(unsigned long block_id) 1056{ 1057 if (!( 1058 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1059 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1060 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1061 cvmx_warn("CVMX_PCIEEPX_CFG517(%lu) is invalid on this chip\n", block_id); 1062 return 0x0000000000000814ull; 1063} 1064#else 1065#define CVMX_PCIEEPX_CFG517(block_id) (0x0000000000000814ull) 1066#endif 1067 1068/** 1069 * cvmx_pcieep#_cfg000 1070 * 1071 * PCIE_CFG000 = First 32-bits of PCIE type 0 config space (Device ID and Vendor ID Register) 1072 * 1073 */ 1074union cvmx_pcieepx_cfg000 1075{ 1076 uint32_t u32; 1077 struct cvmx_pcieepx_cfg000_s 1078 { 1079#if __BYTE_ORDER == __BIG_ENDIAN 1080 uint32_t devid : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR 1081 However, the application must not change this field. 1082 For EEPROM loads also see VENDID of this register. */ 1083 uint32_t vendid : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR 1084 However, the application must not change this field. 1085 During and EPROM Load is a value of 0xFFFF is loaded to this 1086 field and a value of 0xFFFF is loaded to the DEVID field of 1087 this register, the value will not be loaded, EEPROM load will 1088 stop, and the FastLinkEnable bit will be set in the 1089 PCIE_CFG452 register. */ 1090#else 1091 uint32_t vendid : 16; 1092 uint32_t devid : 16; 1093#endif 1094 } s; 1095 struct cvmx_pcieepx_cfg000_s cn52xx; 1096 struct cvmx_pcieepx_cfg000_s cn52xxp1; 1097 struct cvmx_pcieepx_cfg000_s cn56xx; 1098 struct cvmx_pcieepx_cfg000_s cn56xxp1; 1099 struct cvmx_pcieepx_cfg000_s cn63xx; 1100 struct cvmx_pcieepx_cfg000_s cn63xxp1; 1101}; 1102typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t; 1103 1104/** 1105 * cvmx_pcieep#_cfg001 1106 * 1107 * PCIE_CFG001 = Second 32-bits of PCIE type 0 config space (Command/Status Register) 1108 * 1109 */ 1110union cvmx_pcieepx_cfg001 1111{ 1112 uint32_t u32; 1113 struct cvmx_pcieepx_cfg001_s 1114 { 1115#if __BYTE_ORDER == __BIG_ENDIAN 1116 uint32_t dpe : 1; /**< Detected Parity Error */ 1117 uint32_t sse : 1; /**< Signaled System Error */ 1118 uint32_t rma : 1; /**< Received Master Abort */ 1119 uint32_t rta : 1; /**< Received Target Abort */ 1120 uint32_t sta : 1; /**< Signaled Target Abort */ 1121 uint32_t devt : 2; /**< DEVSEL Timing 1122 Not applicable for PCI Express. Hardwired to 0. */ 1123 uint32_t mdpe : 1; /**< Master Data Parity Error */ 1124 uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1125 Not applicable for PCI Express. Hardwired to 0. */ 1126 uint32_t reserved_22_22 : 1; 1127 uint32_t m66 : 1; /**< 66 MHz Capable 1128 Not applicable for PCI Express. Hardwired to 0. */ 1129 uint32_t cl : 1; /**< Capabilities List 1130 Indicates presence of an extended capability item. 1131 Hardwired to 1. */ 1132 uint32_t i_stat : 1; /**< INTx Status */ 1133 uint32_t reserved_11_18 : 8; 1134 uint32_t i_dis : 1; /**< INTx Assertion Disable */ 1135 uint32_t fbbe : 1; /**< Fast Back-to-Back Enable 1136 Not applicable for PCI Express. Must be hardwired to 0. */ 1137 uint32_t see : 1; /**< SERR# Enable */ 1138 uint32_t ids_wcc : 1; /**< IDSEL Stepping/Wait Cycle Control 1139 Not applicable for PCI Express. Must be hardwired to 0 */ 1140 uint32_t per : 1; /**< Parity Error Response */ 1141 uint32_t vps : 1; /**< VGA Palette Snoop 1142 Not applicable for PCI Express. Must be hardwired to 0. */ 1143 uint32_t mwice : 1; /**< Memory Write and Invalidate 1144 Not applicable for PCI Express. Must be hardwired to 0. */ 1145 uint32_t scse : 1; /**< Special Cycle Enable 1146 Not applicable for PCI Express. Must be hardwired to 0. */ 1147 uint32_t me : 1; /**< Bus Master Enable */ 1148 uint32_t msae : 1; /**< Memory Space Enable */ 1149 uint32_t isae : 1; /**< I/O Space Enable */ 1150#else 1151 uint32_t isae : 1; 1152 uint32_t msae : 1; 1153 uint32_t me : 1; 1154 uint32_t scse : 1; 1155 uint32_t mwice : 1; 1156 uint32_t vps : 1; 1157 uint32_t per : 1; 1158 uint32_t ids_wcc : 1; 1159 uint32_t see : 1; 1160 uint32_t fbbe : 1; 1161 uint32_t i_dis : 1; 1162 uint32_t reserved_11_18 : 8; 1163 uint32_t i_stat : 1; 1164 uint32_t cl : 1; 1165 uint32_t m66 : 1; 1166 uint32_t reserved_22_22 : 1; 1167 uint32_t fbb : 1; 1168 uint32_t mdpe : 1; 1169 uint32_t devt : 2; 1170 uint32_t sta : 1; 1171 uint32_t rta : 1; 1172 uint32_t rma : 1; 1173 uint32_t sse : 1; 1174 uint32_t dpe : 1; 1175#endif 1176 } s; 1177 struct cvmx_pcieepx_cfg001_s cn52xx; 1178 struct cvmx_pcieepx_cfg001_s cn52xxp1; 1179 struct cvmx_pcieepx_cfg001_s cn56xx; 1180 struct cvmx_pcieepx_cfg001_s cn56xxp1; 1181 struct cvmx_pcieepx_cfg001_s cn63xx; 1182 struct cvmx_pcieepx_cfg001_s cn63xxp1; 1183}; 1184typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t; 1185 1186/** 1187 * cvmx_pcieep#_cfg002 1188 * 1189 * PCIE_CFG002 = Third 32-bits of PCIE type 0 config space (Revision ID/Class Code Register) 1190 * 1191 */ 1192union cvmx_pcieepx_cfg002 1193{ 1194 uint32_t u32; 1195 struct cvmx_pcieepx_cfg002_s 1196 { 1197#if __BYTE_ORDER == __BIG_ENDIAN 1198 uint32_t bcc : 8; /**< Base Class Code, writable through PEM(0..1)_CFG_WR 1199 However, the application must not change this field. */ 1200 uint32_t sc : 8; /**< Subclass Code, writable through PEM(0..1)_CFG_WR 1201 However, the application must not change this field. */ 1202 uint32_t pi : 8; /**< Programming Interface, writable through PEM(0..1)_CFG_WR 1203 However, the application must not change this field. */ 1204 uint32_t rid : 8; /**< Revision ID, writable through PEM(0..1)_CFG_WR 1205 However, the application must not change this field. */ 1206#else 1207 uint32_t rid : 8; 1208 uint32_t pi : 8; 1209 uint32_t sc : 8; 1210 uint32_t bcc : 8; 1211#endif 1212 } s; 1213 struct cvmx_pcieepx_cfg002_s cn52xx; 1214 struct cvmx_pcieepx_cfg002_s cn52xxp1; 1215 struct cvmx_pcieepx_cfg002_s cn56xx; 1216 struct cvmx_pcieepx_cfg002_s cn56xxp1; 1217 struct cvmx_pcieepx_cfg002_s cn63xx; 1218 struct cvmx_pcieepx_cfg002_s cn63xxp1; 1219}; 1220typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t; 1221 1222/** 1223 * cvmx_pcieep#_cfg003 1224 * 1225 * PCIE_CFG003 = Fourth 32-bits of PCIE type 0 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register) 1226 * 1227 */ 1228union cvmx_pcieepx_cfg003 1229{ 1230 uint32_t u32; 1231 struct cvmx_pcieepx_cfg003_s 1232 { 1233#if __BYTE_ORDER == __BIG_ENDIAN 1234 uint32_t bist : 8; /**< The BIST register functions are not supported. 1235 All 8 bits of the BIST register are hardwired to 0. */ 1236 uint32_t mfd : 1; /**< Multi Function Device 1237 The Multi Function Device bit is writable through PEM(0..1)_CFG_WR. 1238 However, this is a single function device. Therefore, the 1239 application must not write a 1 to this bit. */ 1240 uint32_t chf : 7; /**< Configuration Header Format 1241 Hardwired to 0 for type 0. */ 1242 uint32_t lt : 8; /**< Master Latency Timer 1243 Not applicable for PCI Express, hardwired to 0. */ 1244 uint32_t cls : 8; /**< Cache Line Size 1245 The Cache Line Size register is RW for legacy compatibility 1246 purposes and is not applicable to PCI Express device 1247 functionality. 1248 Writing to the Cache Line Size register does not impact 1249 functionality. */ 1250#else 1251 uint32_t cls : 8; 1252 uint32_t lt : 8; 1253 uint32_t chf : 7; 1254 uint32_t mfd : 1; 1255 uint32_t bist : 8; 1256#endif 1257 } s; 1258 struct cvmx_pcieepx_cfg003_s cn52xx; 1259 struct cvmx_pcieepx_cfg003_s cn52xxp1; 1260 struct cvmx_pcieepx_cfg003_s cn56xx; 1261 struct cvmx_pcieepx_cfg003_s cn56xxp1; 1262 struct cvmx_pcieepx_cfg003_s cn63xx; 1263 struct cvmx_pcieepx_cfg003_s cn63xxp1; 1264}; 1265typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t; 1266 1267/** 1268 * cvmx_pcieep#_cfg004 1269 * 1270 * PCIE_CFG004 = Fifth 32-bits of PCIE type 0 config space (Base Address Register 0 - Low) 1271 * 1272 */ 1273union cvmx_pcieepx_cfg004 1274{ 1275 uint32_t u32; 1276 struct cvmx_pcieepx_cfg004_s 1277 { 1278#if __BYTE_ORDER == __BIG_ENDIAN 1279 uint32_t lbab : 18; /**< Lower bits of the BAR 0 base address */ 1280 uint32_t reserved_4_13 : 10; 1281 uint32_t pf : 1; /**< Prefetchable 1282 This field is writable through PEM(0..1)_CFG_WR. 1283 However, the application must not change this field. */ 1284 uint32_t typ : 2; /**< BAR type 1285 o 00 = 32-bit BAR 1286 o 10 = 64-bit BAR 1287 This field is writable through PEM(0..1)_CFG_WR. 1288 However, the application must not change this field. */ 1289 uint32_t mspc : 1; /**< Memory Space Indicator 1290 o 0 = BAR 0 is a memory BAR 1291 o 1 = BAR 0 is an I/O BAR 1292 This field is writable through PEM(0..1)_CFG_WR. 1293 However, the application must not change this field. */ 1294#else 1295 uint32_t mspc : 1; 1296 uint32_t typ : 2; 1297 uint32_t pf : 1; 1298 uint32_t reserved_4_13 : 10; 1299 uint32_t lbab : 18; 1300#endif 1301 } s; 1302 struct cvmx_pcieepx_cfg004_s cn52xx; 1303 struct cvmx_pcieepx_cfg004_s cn52xxp1; 1304 struct cvmx_pcieepx_cfg004_s cn56xx; 1305 struct cvmx_pcieepx_cfg004_s cn56xxp1; 1306 struct cvmx_pcieepx_cfg004_s cn63xx; 1307 struct cvmx_pcieepx_cfg004_s cn63xxp1; 1308}; 1309typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t; 1310 1311/** 1312 * cvmx_pcieep#_cfg004_mask 1313 * 1314 * PCIE_CFG004_MASK (BAR Mask 0 - Low) 1315 * The BAR 0 Mask register is invisible to host software and not readable from the application. 1316 * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR. 1317 */ 1318union cvmx_pcieepx_cfg004_mask 1319{ 1320 uint32_t u32; 1321 struct cvmx_pcieepx_cfg004_mask_s 1322 { 1323#if __BYTE_ORDER == __BIG_ENDIAN 1324 uint32_t lmask : 31; /**< Bar Mask Low */ 1325 uint32_t enb : 1; /**< Bar Enable 1326 o 0: BAR 0 is disabled 1327 o 1: BAR 0 is enabled 1328 Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1329 register rather than as a mask bit because bit 0 of a BAR is 1330 always masked from writing by host software. Bit 0 must be 1331 written prior to writing the other mask bits. */ 1332#else 1333 uint32_t enb : 1; 1334 uint32_t lmask : 31; 1335#endif 1336 } s; 1337 struct cvmx_pcieepx_cfg004_mask_s cn52xx; 1338 struct cvmx_pcieepx_cfg004_mask_s cn52xxp1; 1339 struct cvmx_pcieepx_cfg004_mask_s cn56xx; 1340 struct cvmx_pcieepx_cfg004_mask_s cn56xxp1; 1341 struct cvmx_pcieepx_cfg004_mask_s cn63xx; 1342 struct cvmx_pcieepx_cfg004_mask_s cn63xxp1; 1343}; 1344typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t; 1345 1346/** 1347 * cvmx_pcieep#_cfg005 1348 * 1349 * PCIE_CFG005 = Sixth 32-bits of PCIE type 0 config space (Base Address Register 0 - High) 1350 * 1351 */ 1352union cvmx_pcieepx_cfg005 1353{ 1354 uint32_t u32; 1355 struct cvmx_pcieepx_cfg005_s 1356 { 1357#if __BYTE_ORDER == __BIG_ENDIAN 1358 uint32_t ubab : 32; /**< Contains the upper 32 bits of the BAR 0 base address. */ 1359#else 1360 uint32_t ubab : 32; 1361#endif 1362 } s; 1363 struct cvmx_pcieepx_cfg005_s cn52xx; 1364 struct cvmx_pcieepx_cfg005_s cn52xxp1; 1365 struct cvmx_pcieepx_cfg005_s cn56xx; 1366 struct cvmx_pcieepx_cfg005_s cn56xxp1; 1367 struct cvmx_pcieepx_cfg005_s cn63xx; 1368 struct cvmx_pcieepx_cfg005_s cn63xxp1; 1369}; 1370typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t; 1371 1372/** 1373 * cvmx_pcieep#_cfg005_mask 1374 * 1375 * PCIE_CFG005_MASK = (BAR Mask 0 - High) 1376 * The BAR 0 Mask register is invisible to host software and not readable from the application. 1377 * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR. 1378 */ 1379union cvmx_pcieepx_cfg005_mask 1380{ 1381 uint32_t u32; 1382 struct cvmx_pcieepx_cfg005_mask_s 1383 { 1384#if __BYTE_ORDER == __BIG_ENDIAN 1385 uint32_t umask : 32; /**< Bar Mask High */ 1386#else 1387 uint32_t umask : 32; 1388#endif 1389 } s; 1390 struct cvmx_pcieepx_cfg005_mask_s cn52xx; 1391 struct cvmx_pcieepx_cfg005_mask_s cn52xxp1; 1392 struct cvmx_pcieepx_cfg005_mask_s cn56xx; 1393 struct cvmx_pcieepx_cfg005_mask_s cn56xxp1; 1394 struct cvmx_pcieepx_cfg005_mask_s cn63xx; 1395 struct cvmx_pcieepx_cfg005_mask_s cn63xxp1; 1396}; 1397typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t; 1398 1399/** 1400 * cvmx_pcieep#_cfg006 1401 * 1402 * PCIE_CFG006 = Seventh 32-bits of PCIE type 0 config space (Base Address Register 1 - Low) 1403 * 1404 */ 1405union cvmx_pcieepx_cfg006 1406{ 1407 uint32_t u32; 1408 struct cvmx_pcieepx_cfg006_s 1409 { 1410#if __BYTE_ORDER == __BIG_ENDIAN 1411 uint32_t lbab : 6; /**< Lower bits of the BAR 1 base address */ 1412 uint32_t reserved_4_25 : 22; 1413 uint32_t pf : 1; /**< Prefetchable 1414 This field is writable through PEM(0..1)_CFG_WR. 1415 However, the application must not change this field. */ 1416 uint32_t typ : 2; /**< BAR type 1417 o 00 = 32-bit BAR 1418 o 10 = 64-bit BAR 1419 This field is writable through PEM(0..1)_CFG_WR. 1420 However, the application must not change this field. */ 1421 uint32_t mspc : 1; /**< Memory Space Indicator 1422 o 0 = BAR 0 is a memory BAR 1423 o 1 = BAR 0 is an I/O BAR 1424 This field is writable through PEM(0..1)_CFG_WR. 1425 However, the application must not change this field. */ 1426#else 1427 uint32_t mspc : 1; 1428 uint32_t typ : 2; 1429 uint32_t pf : 1; 1430 uint32_t reserved_4_25 : 22; 1431 uint32_t lbab : 6; 1432#endif 1433 } s; 1434 struct cvmx_pcieepx_cfg006_s cn52xx; 1435 struct cvmx_pcieepx_cfg006_s cn52xxp1; 1436 struct cvmx_pcieepx_cfg006_s cn56xx; 1437 struct cvmx_pcieepx_cfg006_s cn56xxp1; 1438 struct cvmx_pcieepx_cfg006_s cn63xx; 1439 struct cvmx_pcieepx_cfg006_s cn63xxp1; 1440}; 1441typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t; 1442 1443/** 1444 * cvmx_pcieep#_cfg006_mask 1445 * 1446 * PCIE_CFG006_MASK (BAR Mask 1 - Low) 1447 * The BAR 1 Mask register is invisible to host software and not readable from the application. 1448 * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR. 1449 */ 1450union cvmx_pcieepx_cfg006_mask 1451{ 1452 uint32_t u32; 1453 struct cvmx_pcieepx_cfg006_mask_s 1454 { 1455#if __BYTE_ORDER == __BIG_ENDIAN 1456 uint32_t lmask : 31; /**< Bar Mask Low */ 1457 uint32_t enb : 1; /**< Bar Enable 1458 o 0: BAR 1 is disabled 1459 o 1: BAR 1 is enabled 1460 Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1461 register rather than as a mask bit because bit 0 of a BAR is 1462 always masked from writing by host software. Bit 0 must be 1463 written prior to writing the other mask bits. */ 1464#else 1465 uint32_t enb : 1; 1466 uint32_t lmask : 31; 1467#endif 1468 } s; 1469 struct cvmx_pcieepx_cfg006_mask_s cn52xx; 1470 struct cvmx_pcieepx_cfg006_mask_s cn52xxp1; 1471 struct cvmx_pcieepx_cfg006_mask_s cn56xx; 1472 struct cvmx_pcieepx_cfg006_mask_s cn56xxp1; 1473 struct cvmx_pcieepx_cfg006_mask_s cn63xx; 1474 struct cvmx_pcieepx_cfg006_mask_s cn63xxp1; 1475}; 1476typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t; 1477 1478/** 1479 * cvmx_pcieep#_cfg007 1480 * 1481 * PCIE_CFG007 = Eighth 32-bits of PCIE type 0 config space (Base Address Register 1 - High) 1482 * 1483 */ 1484union cvmx_pcieepx_cfg007 1485{ 1486 uint32_t u32; 1487 struct cvmx_pcieepx_cfg007_s 1488 { 1489#if __BYTE_ORDER == __BIG_ENDIAN 1490 uint32_t ubab : 32; /**< Contains the upper 32 bits of the BAR 1 base address. */ 1491#else 1492 uint32_t ubab : 32; 1493#endif 1494 } s; 1495 struct cvmx_pcieepx_cfg007_s cn52xx; 1496 struct cvmx_pcieepx_cfg007_s cn52xxp1; 1497 struct cvmx_pcieepx_cfg007_s cn56xx; 1498 struct cvmx_pcieepx_cfg007_s cn56xxp1; 1499 struct cvmx_pcieepx_cfg007_s cn63xx; 1500 struct cvmx_pcieepx_cfg007_s cn63xxp1; 1501}; 1502typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t; 1503 1504/** 1505 * cvmx_pcieep#_cfg007_mask 1506 * 1507 * PCIE_CFG007_MASK (BAR Mask 1 - High) 1508 * The BAR 1 Mask register is invisible to host software and not readable from the application. 1509 * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR. 1510 */ 1511union cvmx_pcieepx_cfg007_mask 1512{ 1513 uint32_t u32; 1514 struct cvmx_pcieepx_cfg007_mask_s 1515 { 1516#if __BYTE_ORDER == __BIG_ENDIAN 1517 uint32_t umask : 32; /**< Bar Mask High */ 1518#else 1519 uint32_t umask : 32; 1520#endif 1521 } s; 1522 struct cvmx_pcieepx_cfg007_mask_s cn52xx; 1523 struct cvmx_pcieepx_cfg007_mask_s cn52xxp1; 1524 struct cvmx_pcieepx_cfg007_mask_s cn56xx; 1525 struct cvmx_pcieepx_cfg007_mask_s cn56xxp1; 1526 struct cvmx_pcieepx_cfg007_mask_s cn63xx; 1527 struct cvmx_pcieepx_cfg007_mask_s cn63xxp1; 1528}; 1529typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t; 1530 1531/** 1532 * cvmx_pcieep#_cfg008 1533 * 1534 * PCIE_CFG008 = Ninth 32-bits of PCIE type 0 config space (Base Address Register 2 - Low) 1535 * 1536 */ 1537union cvmx_pcieepx_cfg008 1538{ 1539 uint32_t u32; 1540 struct cvmx_pcieepx_cfg008_s 1541 { 1542#if __BYTE_ORDER == __BIG_ENDIAN 1543 uint32_t reserved_4_31 : 28; 1544 uint32_t pf : 1; /**< Prefetchable 1545 This field is writable through PEM(0..1)_CFG_WR. 1546 However, the application must not change this field. */ 1547 uint32_t typ : 2; /**< BAR type 1548 o 00 = 32-bit BAR 1549 o 10 = 64-bit BAR 1550 This field is writable through PEM(0..1)_CFG_WR. 1551 However, the application must not change this field. */ 1552 uint32_t mspc : 1; /**< Memory Space Indicator 1553 o 0 = BAR 0 is a memory BAR 1554 o 1 = BAR 0 is an I/O BAR 1555 This field is writable through PEM(0..1)_CFG_WR. 1556 However, the application must not change this field. */ 1557#else 1558 uint32_t mspc : 1; 1559 uint32_t typ : 2; 1560 uint32_t pf : 1; 1561 uint32_t reserved_4_31 : 28; 1562#endif 1563 } s; 1564 struct cvmx_pcieepx_cfg008_s cn52xx; 1565 struct cvmx_pcieepx_cfg008_s cn52xxp1; 1566 struct cvmx_pcieepx_cfg008_s cn56xx; 1567 struct cvmx_pcieepx_cfg008_s cn56xxp1; 1568 struct cvmx_pcieepx_cfg008_s cn63xx; 1569 struct cvmx_pcieepx_cfg008_s cn63xxp1; 1570}; 1571typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t; 1572 1573/** 1574 * cvmx_pcieep#_cfg008_mask 1575 * 1576 * PCIE_CFG008_MASK (BAR Mask 2 - Low) 1577 * The BAR 2 Mask register is invisible to host software and not readable from the application. 1578 * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR. 1579 */ 1580union cvmx_pcieepx_cfg008_mask 1581{ 1582 uint32_t u32; 1583 struct cvmx_pcieepx_cfg008_mask_s 1584 { 1585#if __BYTE_ORDER == __BIG_ENDIAN 1586 uint32_t lmask : 31; /**< Bar Mask Low */ 1587 uint32_t enb : 1; /**< Bar Enable 1588 o 0: BAR 2 is disabled 1589 o 1: BAR 2 is enabled 1590 Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1591 register rather than as a mask bit because bit 0 of a BAR is 1592 always masked from writing by host software. Bit 0 must be 1593 written prior to writing the other mask bits. */ 1594#else 1595 uint32_t enb : 1; 1596 uint32_t lmask : 31; 1597#endif 1598 } s; 1599 struct cvmx_pcieepx_cfg008_mask_s cn52xx; 1600 struct cvmx_pcieepx_cfg008_mask_s cn52xxp1; 1601 struct cvmx_pcieepx_cfg008_mask_s cn56xx; 1602 struct cvmx_pcieepx_cfg008_mask_s cn56xxp1; 1603 struct cvmx_pcieepx_cfg008_mask_s cn63xx; 1604 struct cvmx_pcieepx_cfg008_mask_s cn63xxp1; 1605}; 1606typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t; 1607 1608/** 1609 * cvmx_pcieep#_cfg009 1610 * 1611 * PCIE_CFG009 = Tenth 32-bits of PCIE type 0 config space (Base Address Register 2 - High) 1612 * 1613 */ 1614union cvmx_pcieepx_cfg009 1615{ 1616 uint32_t u32; 1617 struct cvmx_pcieepx_cfg009_s 1618 { 1619#if __BYTE_ORDER == __BIG_ENDIAN 1620 uint32_t reserved_0_31 : 32; 1621#else 1622 uint32_t reserved_0_31 : 32; 1623#endif 1624 } s; 1625 struct cvmx_pcieepx_cfg009_cn52xx 1626 { 1627#if __BYTE_ORDER == __BIG_ENDIAN 1628 uint32_t ubab : 25; /**< Contains the upper 32 bits of the BAR 2 base address. */ 1629 uint32_t reserved_0_6 : 7; 1630#else 1631 uint32_t reserved_0_6 : 7; 1632 uint32_t ubab : 25; 1633#endif 1634 } cn52xx; 1635 struct cvmx_pcieepx_cfg009_cn52xx cn52xxp1; 1636 struct cvmx_pcieepx_cfg009_cn52xx cn56xx; 1637 struct cvmx_pcieepx_cfg009_cn52xx cn56xxp1; 1638 struct cvmx_pcieepx_cfg009_cn63xx 1639 { 1640#if __BYTE_ORDER == __BIG_ENDIAN 1641 uint32_t ubab : 23; /**< Contains the upper 32 bits of the BAR 2 base address. */ 1642 uint32_t reserved_0_8 : 9; 1643#else 1644 uint32_t reserved_0_8 : 9; 1645 uint32_t ubab : 23; 1646#endif 1647 } cn63xx; 1648 struct cvmx_pcieepx_cfg009_cn63xx cn63xxp1; 1649}; 1650typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t; 1651 1652/** 1653 * cvmx_pcieep#_cfg009_mask 1654 * 1655 * PCIE_CFG009_MASK (BAR Mask 2 - High) 1656 * The BAR 2 Mask register is invisible to host software and not readable from the application. 1657 * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR. 1658 */ 1659union cvmx_pcieepx_cfg009_mask 1660{ 1661 uint32_t u32; 1662 struct cvmx_pcieepx_cfg009_mask_s 1663 { 1664#if __BYTE_ORDER == __BIG_ENDIAN 1665 uint32_t umask : 32; /**< Bar Mask High */ 1666#else 1667 uint32_t umask : 32; 1668#endif 1669 } s; 1670 struct cvmx_pcieepx_cfg009_mask_s cn52xx; 1671 struct cvmx_pcieepx_cfg009_mask_s cn52xxp1; 1672 struct cvmx_pcieepx_cfg009_mask_s cn56xx; 1673 struct cvmx_pcieepx_cfg009_mask_s cn56xxp1; 1674 struct cvmx_pcieepx_cfg009_mask_s cn63xx; 1675 struct cvmx_pcieepx_cfg009_mask_s cn63xxp1; 1676}; 1677typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t; 1678 1679/** 1680 * cvmx_pcieep#_cfg010 1681 * 1682 * PCIE_CFG010 = Eleventh 32-bits of PCIE type 0 config space (CardBus CIS Pointer Register) 1683 * 1684 */ 1685union cvmx_pcieepx_cfg010 1686{ 1687 uint32_t u32; 1688 struct cvmx_pcieepx_cfg010_s 1689 { 1690#if __BYTE_ORDER == __BIG_ENDIAN 1691 uint32_t cisp : 32; /**< CardBus CIS Pointer 1692 Optional, writable through PEM(0..1)_CFG_WR. */ 1693#else 1694 uint32_t cisp : 32; 1695#endif 1696 } s; 1697 struct cvmx_pcieepx_cfg010_s cn52xx; 1698 struct cvmx_pcieepx_cfg010_s cn52xxp1; 1699 struct cvmx_pcieepx_cfg010_s cn56xx; 1700 struct cvmx_pcieepx_cfg010_s cn56xxp1; 1701 struct cvmx_pcieepx_cfg010_s cn63xx; 1702 struct cvmx_pcieepx_cfg010_s cn63xxp1; 1703}; 1704typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t; 1705 1706/** 1707 * cvmx_pcieep#_cfg011 1708 * 1709 * PCIE_CFG011 = Twelfth 32-bits of PCIE type 0 config space (Subsystem ID and Subsystem Vendor ID Register) 1710 * 1711 */ 1712union cvmx_pcieepx_cfg011 1713{ 1714 uint32_t u32; 1715 struct cvmx_pcieepx_cfg011_s 1716 { 1717#if __BYTE_ORDER == __BIG_ENDIAN 1718 uint32_t ssid : 16; /**< Subsystem ID 1719 Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR. However, the application must not change this field. */ 1720 uint32_t ssvid : 16; /**< Subsystem Vendor ID 1721 Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR. 1722 However, the application must not change this field. */ 1723#else 1724 uint32_t ssvid : 16; 1725 uint32_t ssid : 16; 1726#endif 1727 } s; 1728 struct cvmx_pcieepx_cfg011_s cn52xx; 1729 struct cvmx_pcieepx_cfg011_s cn52xxp1; 1730 struct cvmx_pcieepx_cfg011_s cn56xx; 1731 struct cvmx_pcieepx_cfg011_s cn56xxp1; 1732 struct cvmx_pcieepx_cfg011_s cn63xx; 1733 struct cvmx_pcieepx_cfg011_s cn63xxp1; 1734}; 1735typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t; 1736 1737/** 1738 * cvmx_pcieep#_cfg012 1739 * 1740 * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 0 config space (Expansion ROM Base Address Register) 1741 * 1742 */ 1743union cvmx_pcieepx_cfg012 1744{ 1745 uint32_t u32; 1746 struct cvmx_pcieepx_cfg012_s 1747 { 1748#if __BYTE_ORDER == __BIG_ENDIAN 1749 uint32_t eraddr : 16; /**< Expansion ROM Address */ 1750 uint32_t reserved_1_15 : 15; 1751 uint32_t er_en : 1; /**< Expansion ROM Enable */ 1752#else 1753 uint32_t er_en : 1; 1754 uint32_t reserved_1_15 : 15; 1755 uint32_t eraddr : 16; 1756#endif 1757 } s; 1758 struct cvmx_pcieepx_cfg012_s cn52xx; 1759 struct cvmx_pcieepx_cfg012_s cn52xxp1; 1760 struct cvmx_pcieepx_cfg012_s cn56xx; 1761 struct cvmx_pcieepx_cfg012_s cn56xxp1; 1762 struct cvmx_pcieepx_cfg012_s cn63xx; 1763 struct cvmx_pcieepx_cfg012_s cn63xxp1; 1764}; 1765typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t; 1766 1767/** 1768 * cvmx_pcieep#_cfg012_mask 1769 * 1770 * PCIE_CFG012_MASK (Exapansion ROM BAR Mask) 1771 * The ROM Mask register is invisible to host software and not readable from the application. 1772 * The ROM Mask register is only writable through PEM(0..1)_CFG_WR. 1773 */ 1774union cvmx_pcieepx_cfg012_mask 1775{ 1776 uint32_t u32; 1777 struct cvmx_pcieepx_cfg012_mask_s 1778 { 1779#if __BYTE_ORDER == __BIG_ENDIAN 1780 uint32_t mask : 31; /**< Bar Mask Low NS */ 1781 uint32_t enb : 1; /**< Bar Enable NS 1782 o 0: BAR ROM is disabled 1783 o 1: BAR ROM is enabled 1784 Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1785 register rather than as a mask bit because bit 0 of a BAR is 1786 always masked from writing by host software. Bit 0 must be 1787 written prior to writing the other mask bits. */ 1788#else 1789 uint32_t enb : 1; 1790 uint32_t mask : 31; 1791#endif 1792 } s; 1793 struct cvmx_pcieepx_cfg012_mask_s cn52xx; 1794 struct cvmx_pcieepx_cfg012_mask_s cn52xxp1; 1795 struct cvmx_pcieepx_cfg012_mask_s cn56xx; 1796 struct cvmx_pcieepx_cfg012_mask_s cn56xxp1; 1797 struct cvmx_pcieepx_cfg012_mask_s cn63xx; 1798 struct cvmx_pcieepx_cfg012_mask_s cn63xxp1; 1799}; 1800typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t; 1801 1802/** 1803 * cvmx_pcieep#_cfg013 1804 * 1805 * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 0 config space (Capability Pointer Register) 1806 * 1807 */ 1808union cvmx_pcieepx_cfg013 1809{ 1810 uint32_t u32; 1811 struct cvmx_pcieepx_cfg013_s 1812 { 1813#if __BYTE_ORDER == __BIG_ENDIAN 1814 uint32_t reserved_8_31 : 24; 1815 uint32_t cp : 8; /**< First Capability Pointer. 1816 Points to Power Management Capability structure by 1817 default, writable through PEM(0..1)_CFG_WR. 1818 However, the application must not change this field. */ 1819#else 1820 uint32_t cp : 8; 1821 uint32_t reserved_8_31 : 24; 1822#endif 1823 } s; 1824 struct cvmx_pcieepx_cfg013_s cn52xx; 1825 struct cvmx_pcieepx_cfg013_s cn52xxp1; 1826 struct cvmx_pcieepx_cfg013_s cn56xx; 1827 struct cvmx_pcieepx_cfg013_s cn56xxp1; 1828 struct cvmx_pcieepx_cfg013_s cn63xx; 1829 struct cvmx_pcieepx_cfg013_s cn63xxp1; 1830}; 1831typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t; 1832 1833/** 1834 * cvmx_pcieep#_cfg015 1835 * 1836 * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 0 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register) 1837 * 1838 */ 1839union cvmx_pcieepx_cfg015 1840{ 1841 uint32_t u32; 1842 struct cvmx_pcieepx_cfg015_s 1843 { 1844#if __BYTE_ORDER == __BIG_ENDIAN 1845 uint32_t ml : 8; /**< Maximum Latency (Hardwired to 0) */ 1846 uint32_t mg : 8; /**< Minimum Grant (Hardwired to 0) */ 1847 uint32_t inta : 8; /**< Interrupt Pin 1848 Identifies the legacy interrupt Message that the device 1849 (or device function) uses. 1850 The Interrupt Pin register is writable through PEM(0..1)_CFG_WR. 1851 In a single-function configuration, only INTA is used. 1852 Therefore, the application must not change this field. */ 1853 uint32_t il : 8; /**< Interrupt Line */ 1854#else 1855 uint32_t il : 8; 1856 uint32_t inta : 8; 1857 uint32_t mg : 8; 1858 uint32_t ml : 8; 1859#endif 1860 } s; 1861 struct cvmx_pcieepx_cfg015_s cn52xx; 1862 struct cvmx_pcieepx_cfg015_s cn52xxp1; 1863 struct cvmx_pcieepx_cfg015_s cn56xx; 1864 struct cvmx_pcieepx_cfg015_s cn56xxp1; 1865 struct cvmx_pcieepx_cfg015_s cn63xx; 1866 struct cvmx_pcieepx_cfg015_s cn63xxp1; 1867}; 1868typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t; 1869 1870/** 1871 * cvmx_pcieep#_cfg016 1872 * 1873 * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 0 config space 1874 * (Power Management Capability ID/ 1875 * Power Management Next Item Pointer/ 1876 * Power Management Capabilities Register) 1877 */ 1878union cvmx_pcieepx_cfg016 1879{ 1880 uint32_t u32; 1881 struct cvmx_pcieepx_cfg016_s 1882 { 1883#if __BYTE_ORDER == __BIG_ENDIAN 1884 uint32_t pmes : 5; /**< PME_Support 1885 o Bit 11: If set, PME Messages can be generated from D0 1886 o Bit 12: If set, PME Messages can be generated from D1 1887 o Bit 13: If set, PME Messages can be generated from D2 1888 o Bit 14: If set, PME Messages can be generated from D3hot 1889 o Bit 15: If set, PME Messages can be generated from D3cold 1890 The PME_Support field is writable through PEM(0..1)_CFG_WR. 1891 However, the application must not change this field. */ 1892 uint32_t d2s : 1; /**< D2 Support, writable through PEM(0..1)_CFG_WR 1893 However, the application must not change this field. */ 1894 uint32_t d1s : 1; /**< D1 Support, writable through PEM(0..1)_CFG_WR 1895 However, the application must not change this field. */ 1896 uint32_t auxc : 3; /**< AUX Current, writable through PEM(0..1)_CFG_WR 1897 However, the application must not change this field. */ 1898 uint32_t dsi : 1; /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR 1899 However, the application must not change this field. */ 1900 uint32_t reserved_20_20 : 1; 1901 uint32_t pme_clock : 1; /**< PME Clock, hardwired to 0 */ 1902 uint32_t pmsv : 3; /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR 1903 However, the application must not change this field. */ 1904 uint32_t ncp : 8; /**< Next Capability Pointer 1905 Points to the MSI capabilities by default, writable 1906 through PEM(0..1)_CFG_WR. 1907 However, the application must not change this field. */ 1908 uint32_t pmcid : 8; /**< Power Management Capability ID */ 1909#else 1910 uint32_t pmcid : 8; 1911 uint32_t ncp : 8; 1912 uint32_t pmsv : 3; 1913 uint32_t pme_clock : 1; 1914 uint32_t reserved_20_20 : 1; 1915 uint32_t dsi : 1; 1916 uint32_t auxc : 3; 1917 uint32_t d1s : 1; 1918 uint32_t d2s : 1; 1919 uint32_t pmes : 5; 1920#endif 1921 } s; 1922 struct cvmx_pcieepx_cfg016_s cn52xx; 1923 struct cvmx_pcieepx_cfg016_s cn52xxp1; 1924 struct cvmx_pcieepx_cfg016_s cn56xx; 1925 struct cvmx_pcieepx_cfg016_s cn56xxp1; 1926 struct cvmx_pcieepx_cfg016_s cn63xx; 1927 struct cvmx_pcieepx_cfg016_s cn63xxp1; 1928}; 1929typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t; 1930 1931/** 1932 * cvmx_pcieep#_cfg017 1933 * 1934 * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 0 config space (Power Management Control and Status Register) 1935 * 1936 */ 1937union cvmx_pcieepx_cfg017 1938{ 1939 uint32_t u32; 1940 struct cvmx_pcieepx_cfg017_s 1941 { 1942#if __BYTE_ORDER == __BIG_ENDIAN 1943 uint32_t pmdia : 8; /**< Data register for additional information (not supported) */ 1944 uint32_t bpccee : 1; /**< Bus Power/Clock Control Enable, hardwired to 0 */ 1945 uint32_t bd3h : 1; /**< B2/B3 Support, hardwired to 0 */ 1946 uint32_t reserved_16_21 : 6; 1947 uint32_t pmess : 1; /**< PME Status 1948 Indicates if a previously enabled PME event occurred or not. */ 1949 uint32_t pmedsia : 2; /**< Data Scale (not supported) */ 1950 uint32_t pmds : 4; /**< Data Select (not supported) */ 1951 uint32_t pmeens : 1; /**< PME Enable 1952 A value of 1 indicates that the device is enabled to 1953 generate PME. */ 1954 uint32_t reserved_4_7 : 4; 1955 uint32_t nsr : 1; /**< No Soft Reset, writable through PEM(0..1)_CFG_WR 1956 However, the application must not change this field. */ 1957 uint32_t reserved_2_2 : 1; 1958 uint32_t ps : 2; /**< Power State 1959 Controls the device power state: 1960 o 00b: D0 1961 o 01b: D1 1962 o 10b: D2 1963 o 11b: D3 1964 The written value is ignored if the specific state is 1965 not supported. */ 1966#else 1967 uint32_t ps : 2; 1968 uint32_t reserved_2_2 : 1; 1969 uint32_t nsr : 1; 1970 uint32_t reserved_4_7 : 4; 1971 uint32_t pmeens : 1; 1972 uint32_t pmds : 4; 1973 uint32_t pmedsia : 2; 1974 uint32_t pmess : 1; 1975 uint32_t reserved_16_21 : 6; 1976 uint32_t bd3h : 1; 1977 uint32_t bpccee : 1; 1978 uint32_t pmdia : 8; 1979#endif 1980 } s; 1981 struct cvmx_pcieepx_cfg017_s cn52xx; 1982 struct cvmx_pcieepx_cfg017_s cn52xxp1; 1983 struct cvmx_pcieepx_cfg017_s cn56xx; 1984 struct cvmx_pcieepx_cfg017_s cn56xxp1; 1985 struct cvmx_pcieepx_cfg017_s cn63xx; 1986 struct cvmx_pcieepx_cfg017_s cn63xxp1; 1987}; 1988typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t; 1989 1990/** 1991 * cvmx_pcieep#_cfg020 1992 * 1993 * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 0 config space 1994 * (MSI Capability ID/ 1995 * MSI Next Item Pointer/ 1996 * MSI Control Register) 1997 */ 1998union cvmx_pcieepx_cfg020 1999{ 2000 uint32_t u32; 2001 struct cvmx_pcieepx_cfg020_s 2002 { 2003#if __BYTE_ORDER == __BIG_ENDIAN 2004 uint32_t reserved_24_31 : 8; 2005 uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR 2006 However, the application must not change this field. */ 2007 uint32_t mme : 3; /**< Multiple Message Enabled 2008 Indicates that multiple Message mode is enabled by system 2009 software. The number of Messages enabled must be less than 2010 or equal to the Multiple Message Capable value. */ 2011 uint32_t mmc : 3; /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR 2012 However, the application must not change this field. */ 2013 uint32_t msien : 1; /**< MSI Enabled 2014 When set, INTx must be disabled. */ 2015 uint32_t ncp : 8; /**< Next Capability Pointer 2016 Points to PCI Express Capabilities by default, 2017 writable through PEM(0..1)_CFG_WR. 2018 However, the application must not change this field. */ 2019 uint32_t msicid : 8; /**< MSI Capability ID */ 2020#else 2021 uint32_t msicid : 8; 2022 uint32_t ncp : 8; 2023 uint32_t msien : 1; 2024 uint32_t mmc : 3; 2025 uint32_t mme : 3; 2026 uint32_t m64 : 1; 2027 uint32_t reserved_24_31 : 8; 2028#endif 2029 } s; 2030 struct cvmx_pcieepx_cfg020_s cn52xx; 2031 struct cvmx_pcieepx_cfg020_s cn52xxp1; 2032 struct cvmx_pcieepx_cfg020_s cn56xx; 2033 struct cvmx_pcieepx_cfg020_s cn56xxp1; 2034 struct cvmx_pcieepx_cfg020_s cn63xx; 2035 struct cvmx_pcieepx_cfg020_s cn63xxp1; 2036}; 2037typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t; 2038 2039/** 2040 * cvmx_pcieep#_cfg021 2041 * 2042 * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 0 config space (MSI Lower 32 Bits Address Register) 2043 * 2044 */ 2045union cvmx_pcieepx_cfg021 2046{ 2047 uint32_t u32; 2048 struct cvmx_pcieepx_cfg021_s 2049 { 2050#if __BYTE_ORDER == __BIG_ENDIAN 2051 uint32_t lmsi : 30; /**< Lower 32-bit Address */ 2052 uint32_t reserved_0_1 : 2; 2053#else 2054 uint32_t reserved_0_1 : 2; 2055 uint32_t lmsi : 30; 2056#endif 2057 } s; 2058 struct cvmx_pcieepx_cfg021_s cn52xx; 2059 struct cvmx_pcieepx_cfg021_s cn52xxp1; 2060 struct cvmx_pcieepx_cfg021_s cn56xx; 2061 struct cvmx_pcieepx_cfg021_s cn56xxp1; 2062 struct cvmx_pcieepx_cfg021_s cn63xx; 2063 struct cvmx_pcieepx_cfg021_s cn63xxp1; 2064}; 2065typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t; 2066 2067/** 2068 * cvmx_pcieep#_cfg022 2069 * 2070 * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 0 config space (MSI Upper 32 bits Address Register) 2071 * 2072 */ 2073union cvmx_pcieepx_cfg022 2074{ 2075 uint32_t u32; 2076 struct cvmx_pcieepx_cfg022_s 2077 { 2078#if __BYTE_ORDER == __BIG_ENDIAN 2079 uint32_t umsi : 32; /**< Upper 32-bit Address */ 2080#else 2081 uint32_t umsi : 32; 2082#endif 2083 } s; 2084 struct cvmx_pcieepx_cfg022_s cn52xx; 2085 struct cvmx_pcieepx_cfg022_s cn52xxp1; 2086 struct cvmx_pcieepx_cfg022_s cn56xx; 2087 struct cvmx_pcieepx_cfg022_s cn56xxp1; 2088 struct cvmx_pcieepx_cfg022_s cn63xx; 2089 struct cvmx_pcieepx_cfg022_s cn63xxp1; 2090}; 2091typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t; 2092 2093/** 2094 * cvmx_pcieep#_cfg023 2095 * 2096 * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 0 config space (MSI Data Register) 2097 * 2098 */ 2099union cvmx_pcieepx_cfg023 2100{ 2101 uint32_t u32; 2102 struct cvmx_pcieepx_cfg023_s 2103 { 2104#if __BYTE_ORDER == __BIG_ENDIAN 2105 uint32_t reserved_16_31 : 16; 2106 uint32_t msimd : 16; /**< MSI Data 2107 Pattern assigned by system software, bits [4:0] are Or-ed with 2108 MSI_VECTOR to generate 32 MSI Messages per function. */ 2109#else 2110 uint32_t msimd : 16; 2111 uint32_t reserved_16_31 : 16; 2112#endif 2113 } s; 2114 struct cvmx_pcieepx_cfg023_s cn52xx; 2115 struct cvmx_pcieepx_cfg023_s cn52xxp1; 2116 struct cvmx_pcieepx_cfg023_s cn56xx; 2117 struct cvmx_pcieepx_cfg023_s cn56xxp1; 2118 struct cvmx_pcieepx_cfg023_s cn63xx; 2119 struct cvmx_pcieepx_cfg023_s cn63xxp1; 2120}; 2121typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t; 2122 2123/** 2124 * cvmx_pcieep#_cfg028 2125 * 2126 * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 0 config space 2127 * (PCI Express Capabilities List Register/ 2128 * PCI Express Capabilities Register) 2129 */ 2130union cvmx_pcieepx_cfg028 2131{ 2132 uint32_t u32; 2133 struct cvmx_pcieepx_cfg028_s 2134 { 2135#if __BYTE_ORDER == __BIG_ENDIAN 2136 uint32_t reserved_30_31 : 2; 2137 uint32_t imn : 5; /**< Interrupt Message Number 2138 Updated by hardware, writable through PEM(0..1)_CFG_WR. 2139 However, the application must not change this field. */ 2140 uint32_t si : 1; /**< Slot Implemented 2141 This bit is writable through PEM(0..1)_CFG_WR. 2142 However, it must be 0 for 2143 an Endpoint device. Therefore, the application must not write a 2144 1 to this bit. */ 2145 uint32_t dpt : 4; /**< Device Port Type */ 2146 uint32_t pciecv : 4; /**< PCI Express Capability Version */ 2147 uint32_t ncp : 8; /**< Next Capability Pointer 2148 Writable through PEM(0..1)_CFG_WR. 2149 However, the application must not change this field. */ 2150 uint32_t pcieid : 8; /**< PCIE Capability ID */ 2151#else 2152 uint32_t pcieid : 8; 2153 uint32_t ncp : 8; 2154 uint32_t pciecv : 4; 2155 uint32_t dpt : 4; 2156 uint32_t si : 1; 2157 uint32_t imn : 5; 2158 uint32_t reserved_30_31 : 2; 2159#endif 2160 } s; 2161 struct cvmx_pcieepx_cfg028_s cn52xx; 2162 struct cvmx_pcieepx_cfg028_s cn52xxp1; 2163 struct cvmx_pcieepx_cfg028_s cn56xx; 2164 struct cvmx_pcieepx_cfg028_s cn56xxp1; 2165 struct cvmx_pcieepx_cfg028_s cn63xx; 2166 struct cvmx_pcieepx_cfg028_s cn63xxp1; 2167}; 2168typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t; 2169 2170/** 2171 * cvmx_pcieep#_cfg029 2172 * 2173 * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 0 config space (Device Capabilities Register) 2174 * 2175 */ 2176union cvmx_pcieepx_cfg029 2177{ 2178 uint32_t u32; 2179 struct cvmx_pcieepx_cfg029_s 2180 { 2181#if __BYTE_ORDER == __BIG_ENDIAN 2182 uint32_t reserved_28_31 : 4; 2183 uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2184 From Message from RC, upstream port only. */ 2185 uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2186 From Message from RC, upstream port only. */ 2187 uint32_t reserved_16_17 : 2; 2188 uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2189 However, the application must not change this field. */ 2190 uint32_t reserved_12_14 : 3; 2191 uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2192 However, the application must not change this field. */ 2193 uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2194 However, the application must not change this field. */ 2195 uint32_t etfs : 1; /**< Extended Tag Field Supported 2196 This bit is writable through PEM(0..1)_CFG_WR. 2197 However, the application 2198 must not write a 1 to this bit. */ 2199 uint32_t pfs : 2; /**< Phantom Function Supported 2200 This field is writable through PEM(0..1)_CFG_WR. 2201 However, Phantom 2202 Function is not supported. Therefore, the application must not 2203 write any value other than 0x0 to this field. */ 2204 uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2205 However, the application must not change this field. */ 2206#else 2207 uint32_t mpss : 3; 2208 uint32_t pfs : 2; 2209 uint32_t etfs : 1; 2210 uint32_t el0al : 3; 2211 uint32_t el1al : 3; 2212 uint32_t reserved_12_14 : 3; 2213 uint32_t rber : 1; 2214 uint32_t reserved_16_17 : 2; 2215 uint32_t csplv : 8; 2216 uint32_t cspls : 2; 2217 uint32_t reserved_28_31 : 4; 2218#endif 2219 } s; 2220 struct cvmx_pcieepx_cfg029_s cn52xx; 2221 struct cvmx_pcieepx_cfg029_s cn52xxp1; 2222 struct cvmx_pcieepx_cfg029_s cn56xx; 2223 struct cvmx_pcieepx_cfg029_s cn56xxp1; 2224 struct cvmx_pcieepx_cfg029_s cn63xx; 2225 struct cvmx_pcieepx_cfg029_s cn63xxp1; 2226}; 2227typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t; 2228 2229/** 2230 * cvmx_pcieep#_cfg030 2231 * 2232 * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 0 config space 2233 * (Device Control Register/Device Status Register) 2234 */ 2235union cvmx_pcieepx_cfg030 2236{ 2237 uint32_t u32; 2238 struct cvmx_pcieepx_cfg030_s 2239 { 2240#if __BYTE_ORDER == __BIG_ENDIAN 2241 uint32_t reserved_22_31 : 10; 2242 uint32_t tp : 1; /**< Transaction Pending 2243 Set to 1 when Non-Posted Requests are not yet completed 2244 and clear when they are completed. */ 2245 uint32_t ap_d : 1; /**< Aux Power Detected 2246 Set to 1 if Aux power detected. */ 2247 uint32_t ur_d : 1; /**< Unsupported Request Detected 2248 Errors are logged in this register regardless of whether 2249 error reporting is enabled in the Device Control register. 2250 UR_D occurs when we receive something we don't support. 2251 Unsupported requests are Nonfatal errors, so UR_D should 2252 cause NFE_D. Receiving a vendor defined message should 2253 cause an unsupported request. */ 2254 uint32_t fe_d : 1; /**< Fatal Error Detected 2255 Errors are logged in this register regardless of whether 2256 error reporting is enabled in the Device Control register. 2257 FE_D is set if receive any of the errors in PCIE_CFG066 that 2258 has a severity set to Fatal. Malformed TLP's generally fit 2259 into this category. */ 2260 uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2261 Errors are logged in this register regardless of whether 2262 error reporting is enabled in the Device Control register. 2263 NFE_D is set if we receive any of the errors in PCIE_CFG066 2264 that has a severity set to Nonfatal and does NOT meet Advisory 2265 Nonfatal criteria , which 2266 most poisoned TLP's should be. */ 2267 uint32_t ce_d : 1; /**< Correctable Error Detected 2268 Errors are logged in this register regardless of whether 2269 error reporting is enabled in the Device Control register. 2270 CE_D is set if we receive any of the errors in PCIE_CFG068 2271 for example a Replay Timer Timeout. Also, it can be set if 2272 we get any of the errors in PCIE_CFG066 that has a severity 2273 set to Nonfatal and meets the Advisory Nonfatal criteria, 2274 which most ECRC errors 2275 should be. */ 2276 uint32_t reserved_15_15 : 1; 2277 uint32_t mrrs : 3; /**< Max Read Request Size 2278 0 = 128B 2279 1 = 256B 2280 2 = 512B 2281 3 = 1024B 2282 4 = 2048B 2283 5 = 4096B 2284 Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and 2285 also must be set properly. 2286 SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must 2287 not exceed the desired max read request size. */ 2288 uint32_t ns_en : 1; /**< Enable No Snoop */ 2289 uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2290 uint32_t pf_en : 1; /**< Phantom Function Enable 2291 This bit should never be set - OCTEON requests never use 2292 phantom functions. */ 2293 uint32_t etf_en : 1; /**< Extended Tag Field Enable 2294 This bit should never be set - OCTEON requests never use 2295 extended tags. */ 2296 uint32_t mps : 3; /**< Max Payload Size 2297 Legal values: 2298 0 = 128B 2299 1 = 256B 2300 Larger sizes not supported by OCTEON. 2301 Note: DPI_SLI_PRT#_CFG[MPS] must be set to the same 2302 value for proper functionality. */ 2303 uint32_t ro_en : 1; /**< Enable Relaxed Ordering */ 2304 uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2305 uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2306 uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2307 uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2308#else 2309 uint32_t ce_en : 1; 2310 uint32_t nfe_en : 1; 2311 uint32_t fe_en : 1; 2312 uint32_t ur_en : 1; 2313 uint32_t ro_en : 1; 2314 uint32_t mps : 3; 2315 uint32_t etf_en : 1; 2316 uint32_t pf_en : 1; 2317 uint32_t ap_en : 1; 2318 uint32_t ns_en : 1; 2319 uint32_t mrrs : 3; 2320 uint32_t reserved_15_15 : 1; 2321 uint32_t ce_d : 1; 2322 uint32_t nfe_d : 1; 2323 uint32_t fe_d : 1; 2324 uint32_t ur_d : 1; 2325 uint32_t ap_d : 1; 2326 uint32_t tp : 1; 2327 uint32_t reserved_22_31 : 10; 2328#endif 2329 } s; 2330 struct cvmx_pcieepx_cfg030_s cn52xx; 2331 struct cvmx_pcieepx_cfg030_s cn52xxp1; 2332 struct cvmx_pcieepx_cfg030_s cn56xx; 2333 struct cvmx_pcieepx_cfg030_s cn56xxp1; 2334 struct cvmx_pcieepx_cfg030_s cn63xx; 2335 struct cvmx_pcieepx_cfg030_s cn63xxp1; 2336}; 2337typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t; 2338 2339/** 2340 * cvmx_pcieep#_cfg031 2341 * 2342 * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 0 config space 2343 * (Link Capabilities Register) 2344 */ 2345union cvmx_pcieepx_cfg031 2346{ 2347 uint32_t u32; 2348 struct cvmx_pcieepx_cfg031_s 2349 { 2350#if __BYTE_ORDER == __BIG_ENDIAN 2351 uint32_t pnum : 8; /**< Port Number, writable through PEM(0..1)_CFG_WR 2352 However, the application must not change this field. */ 2353 uint32_t reserved_22_23 : 2; 2354 uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */ 2355 uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable */ 2356 uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2357 Not supported, hardwired to 0x0. */ 2358 uint32_t cpm : 1; /**< Clock Power Management 2359 The default value is the value you specify during hardware 2360 configuration, writable through PEM(0..1)_CFG_WR. 2361 However, the application must not change this field. */ 2362 uint32_t l1el : 3; /**< L1 Exit Latency 2363 The default value is the value you specify during hardware 2364 configuration, writable through PEM(0..1)_CFG_WR. 2365 However, the application must not change this field. */ 2366 uint32_t l0el : 3; /**< L0s Exit Latency 2367 The default value is the value you specify during hardware 2368 configuration, writable through PEM(0..1)_CFG_WR. 2369 However, the application must not change this field. */ 2370 uint32_t aslpms : 2; /**< Active State Link PM Support 2371 The default value is the value you specify during hardware 2372 configuration, writable through PEM(0..1)_CFG_WR. 2373 However, the application must not change this field. */ 2374 uint32_t mlw : 6; /**< Maximum Link Width 2375 The default value is the value you specify during hardware 2376 configuration (x1, x4, x8, or x16), writable through PEM(0..1)_CFG_WR. */ 2377 uint32_t mls : 4; /**< Maximum Link Speed 2378 The following values are accepted: 2379 0001b: 2.5 GHz supported 2380 0010b: 5.0 GHz and 2.5 GHz supported 2381 This field is writable through PEM(0..1)_CFG_WR. 2382 However, the application must not change this field. */ 2383#else 2384 uint32_t mls : 4; 2385 uint32_t mlw : 6; 2386 uint32_t aslpms : 2; 2387 uint32_t l0el : 3; 2388 uint32_t l1el : 3; 2389 uint32_t cpm : 1; 2390 uint32_t sderc : 1; 2391 uint32_t dllarc : 1; 2392 uint32_t lbnc : 1; 2393 uint32_t reserved_22_23 : 2; 2394 uint32_t pnum : 8; 2395#endif 2396 } s; 2397 struct cvmx_pcieepx_cfg031_s cn52xx; 2398 struct cvmx_pcieepx_cfg031_s cn52xxp1; 2399 struct cvmx_pcieepx_cfg031_s cn56xx; 2400 struct cvmx_pcieepx_cfg031_s cn56xxp1; 2401 struct cvmx_pcieepx_cfg031_s cn63xx; 2402 struct cvmx_pcieepx_cfg031_s cn63xxp1; 2403}; 2404typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t; 2405 2406/** 2407 * cvmx_pcieep#_cfg032 2408 * 2409 * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 0 config space 2410 * (Link Control Register/Link Status Register) 2411 */ 2412union cvmx_pcieepx_cfg032 2413{ 2414 uint32_t u32; 2415 struct cvmx_pcieepx_cfg032_s 2416 { 2417#if __BYTE_ORDER == __BIG_ENDIAN 2418 uint32_t reserved_30_31 : 2; 2419 uint32_t dlla : 1; /**< Data Link Layer Active 2420 Not applicable for an upstream Port or Endpoint device, 2421 hardwired to 0. */ 2422 uint32_t scc : 1; /**< Slot Clock Configuration 2423 Indicates that the component uses the same physical reference 2424 clock that the platform provides on the connector. 2425 Writable through PEM(0..1)_CFG_WR. 2426 However, the application must not change this field. */ 2427 uint32_t lt : 1; /**< Link Training 2428 Not applicable for an upstream Port or Endpoint device, 2429 hardwired to 0. */ 2430 uint32_t reserved_26_26 : 1; 2431 uint32_t nlw : 6; /**< Negotiated Link Width 2432 Set automatically by hardware after Link initialization. */ 2433 uint32_t ls : 4; /**< Link Speed 2434 The negotiated Link speed: 2.5 Gbps */ 2435 uint32_t reserved_10_15 : 6; 2436 uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 2437 (Not Supported) */ 2438 uint32_t ecpm : 1; /**< Enable Clock Power Management 2439 Hardwired to 0 if Clock Power Management is disabled in 2440 the Link Capabilities register. */ 2441 uint32_t es : 1; /**< Extended Synch */ 2442 uint32_t ccc : 1; /**< Common Clock Configuration */ 2443 uint32_t rl : 1; /**< Retrain Link 2444 Not applicable for an upstream Port or Endpoint device, 2445 hardwired to 0. */ 2446 uint32_t ld : 1; /**< Link Disable 2447 Not applicable for an upstream Port or Endpoint device, 2448 hardwired to 0. */ 2449 uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */ 2450 uint32_t reserved_2_2 : 1; 2451 uint32_t aslpc : 2; /**< Active State Link PM Control */ 2452#else 2453 uint32_t aslpc : 2; 2454 uint32_t reserved_2_2 : 1; 2455 uint32_t rcb : 1; 2456 uint32_t ld : 1; 2457 uint32_t rl : 1; 2458 uint32_t ccc : 1; 2459 uint32_t es : 1; 2460 uint32_t ecpm : 1; 2461 uint32_t hawd : 1; 2462 uint32_t reserved_10_15 : 6; 2463 uint32_t ls : 4; 2464 uint32_t nlw : 6; 2465 uint32_t reserved_26_26 : 1; 2466 uint32_t lt : 1; 2467 uint32_t scc : 1; 2468 uint32_t dlla : 1; 2469 uint32_t reserved_30_31 : 2; 2470#endif 2471 } s; 2472 struct cvmx_pcieepx_cfg032_s cn52xx; 2473 struct cvmx_pcieepx_cfg032_s cn52xxp1; 2474 struct cvmx_pcieepx_cfg032_s cn56xx; 2475 struct cvmx_pcieepx_cfg032_s cn56xxp1; 2476 struct cvmx_pcieepx_cfg032_s cn63xx; 2477 struct cvmx_pcieepx_cfg032_s cn63xxp1; 2478}; 2479typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t; 2480 2481/** 2482 * cvmx_pcieep#_cfg033 2483 * 2484 * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space 2485 * (Slot Capabilities Register) 2486 */ 2487union cvmx_pcieepx_cfg033 2488{ 2489 uint32_t u32; 2490 struct cvmx_pcieepx_cfg033_s 2491 { 2492#if __BYTE_ORDER == __BIG_ENDIAN 2493 uint32_t ps_num : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR 2494 However, the application must not change this field. */ 2495 uint32_t nccs : 1; /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR 2496 However, the application must not change this field. */ 2497 uint32_t emip : 1; /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR 2498 However, the application must not change this field. */ 2499 uint32_t sp_ls : 2; /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR 2500 However, the application must not change this field. */ 2501 uint32_t sp_lv : 8; /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR 2502 However, the application must not change this field. */ 2503 uint32_t hp_c : 1; /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR 2504 However, the application must not change this field. */ 2505 uint32_t hp_s : 1; /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR 2506 However, the application must not change this field. */ 2507 uint32_t pip : 1; /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR 2508 However, the application must not change this field. */ 2509 uint32_t aip : 1; /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR 2510 However, the application must not change this field. */ 2511 uint32_t mrlsp : 1; /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR 2512 However, the application must not change this field. */ 2513 uint32_t pcp : 1; /**< Power Controller Present, writable through PEM(0..1)_CFG_WR 2514 However, the application must not change this field. */ 2515 uint32_t abp : 1; /**< Attention Button Present, writable through PEM(0..1)_CFG_WR 2516 However, the application must not change this field. */ 2517#else 2518 uint32_t abp : 1; 2519 uint32_t pcp : 1; 2520 uint32_t mrlsp : 1; 2521 uint32_t aip : 1; 2522 uint32_t pip : 1; 2523 uint32_t hp_s : 1; 2524 uint32_t hp_c : 1; 2525 uint32_t sp_lv : 8; 2526 uint32_t sp_ls : 2; 2527 uint32_t emip : 1; 2528 uint32_t nccs : 1; 2529 uint32_t ps_num : 13; 2530#endif 2531 } s; 2532 struct cvmx_pcieepx_cfg033_s cn52xx; 2533 struct cvmx_pcieepx_cfg033_s cn52xxp1; 2534 struct cvmx_pcieepx_cfg033_s cn56xx; 2535 struct cvmx_pcieepx_cfg033_s cn56xxp1; 2536 struct cvmx_pcieepx_cfg033_s cn63xx; 2537 struct cvmx_pcieepx_cfg033_s cn63xxp1; 2538}; 2539typedef union cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg033_t; 2540 2541/** 2542 * cvmx_pcieep#_cfg034 2543 * 2544 * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space 2545 * (Slot Control Register/Slot Status Register) 2546 */ 2547union cvmx_pcieepx_cfg034 2548{ 2549 uint32_t u32; 2550 struct cvmx_pcieepx_cfg034_s 2551 { 2552#if __BYTE_ORDER == __BIG_ENDIAN 2553 uint32_t reserved_25_31 : 7; 2554 uint32_t dlls_c : 1; /**< Data Link Layer State Changed 2555 Not applicable for an upstream Port or Endpoint device, 2556 hardwired to 0. */ 2557 uint32_t emis : 1; /**< Electromechanical Interlock Status */ 2558 uint32_t pds : 1; /**< Presence Detect State */ 2559 uint32_t mrlss : 1; /**< MRL Sensor State */ 2560 uint32_t ccint_d : 1; /**< Command Completed */ 2561 uint32_t pd_c : 1; /**< Presence Detect Changed */ 2562 uint32_t mrls_c : 1; /**< MRL Sensor Changed */ 2563 uint32_t pf_d : 1; /**< Power Fault Detected */ 2564 uint32_t abp_d : 1; /**< Attention Button Pressed */ 2565 uint32_t reserved_13_15 : 3; 2566 uint32_t dlls_en : 1; /**< Data Link Layer State Changed Enable 2567 Not applicable for an upstream Port or Endpoint device, 2568 hardwired to 0. */ 2569 uint32_t emic : 1; /**< Electromechanical Interlock Control */ 2570 uint32_t pcc : 1; /**< Power Controller Control */ 2571 uint32_t pic : 2; /**< Power Indicator Control */ 2572 uint32_t aic : 2; /**< Attention Indicator Control */ 2573 uint32_t hpint_en : 1; /**< Hot-Plug Interrupt Enable */ 2574 uint32_t ccint_en : 1; /**< Command Completed Interrupt Enable */ 2575 uint32_t pd_en : 1; /**< Presence Detect Changed Enable */ 2576 uint32_t mrls_en : 1; /**< MRL Sensor Changed Enable */ 2577 uint32_t pf_en : 1; /**< Power Fault Detected Enable */ 2578 uint32_t abp_en : 1; /**< Attention Button Pressed Enable */ 2579#else 2580 uint32_t abp_en : 1; 2581 uint32_t pf_en : 1; 2582 uint32_t mrls_en : 1; 2583 uint32_t pd_en : 1; 2584 uint32_t ccint_en : 1; 2585 uint32_t hpint_en : 1; 2586 uint32_t aic : 2; 2587 uint32_t pic : 2; 2588 uint32_t pcc : 1; 2589 uint32_t emic : 1; 2590 uint32_t dlls_en : 1; 2591 uint32_t reserved_13_15 : 3; 2592 uint32_t abp_d : 1; 2593 uint32_t pf_d : 1; 2594 uint32_t mrls_c : 1; 2595 uint32_t pd_c : 1; 2596 uint32_t ccint_d : 1; 2597 uint32_t mrlss : 1; 2598 uint32_t pds : 1; 2599 uint32_t emis : 1; 2600 uint32_t dlls_c : 1; 2601 uint32_t reserved_25_31 : 7; 2602#endif 2603 } s; 2604 struct cvmx_pcieepx_cfg034_s cn52xx; 2605 struct cvmx_pcieepx_cfg034_s cn52xxp1; 2606 struct cvmx_pcieepx_cfg034_s cn56xx; 2607 struct cvmx_pcieepx_cfg034_s cn56xxp1; 2608 struct cvmx_pcieepx_cfg034_s cn63xx; 2609 struct cvmx_pcieepx_cfg034_s cn63xxp1; 2610}; 2611typedef union cvmx_pcieepx_cfg034 cvmx_pcieepx_cfg034_t; 2612 2613/** 2614 * cvmx_pcieep#_cfg037 2615 * 2616 * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 0 config space 2617 * (Device Capabilities 2 Register) 2618 */ 2619union cvmx_pcieepx_cfg037 2620{ 2621 uint32_t u32; 2622 struct cvmx_pcieepx_cfg037_s 2623 { 2624#if __BYTE_ORDER == __BIG_ENDIAN 2625 uint32_t reserved_5_31 : 27; 2626 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 2627 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported 2628 Value of 0 indicates that Completion Timeout Programming 2629 is not supported 2630 Completion timeout is 16.7ms. */ 2631#else 2632 uint32_t ctrs : 4; 2633 uint32_t ctds : 1; 2634 uint32_t reserved_5_31 : 27; 2635#endif 2636 } s; 2637 struct cvmx_pcieepx_cfg037_s cn52xx; 2638 struct cvmx_pcieepx_cfg037_s cn52xxp1; 2639 struct cvmx_pcieepx_cfg037_s cn56xx; 2640 struct cvmx_pcieepx_cfg037_s cn56xxp1; 2641 struct cvmx_pcieepx_cfg037_s cn63xx; 2642 struct cvmx_pcieepx_cfg037_s cn63xxp1; 2643}; 2644typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t; 2645 2646/** 2647 * cvmx_pcieep#_cfg038 2648 * 2649 * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 0 config space 2650 * (Device Control 2 Register/Device Status 2 Register) 2651 */ 2652union cvmx_pcieepx_cfg038 2653{ 2654 uint32_t u32; 2655 struct cvmx_pcieepx_cfg038_s 2656 { 2657#if __BYTE_ORDER == __BIG_ENDIAN 2658 uint32_t reserved_5_31 : 27; 2659 uint32_t ctd : 1; /**< Completion Timeout Disable */ 2660 uint32_t ctv : 4; /**< Completion Timeout Value 2661 Completion Timeout Programming is not supported 2662 Completion timeout is 16.7ms. */ 2663#else 2664 uint32_t ctv : 4; 2665 uint32_t ctd : 1; 2666 uint32_t reserved_5_31 : 27; 2667#endif 2668 } s; 2669 struct cvmx_pcieepx_cfg038_s cn52xx; 2670 struct cvmx_pcieepx_cfg038_s cn52xxp1; 2671 struct cvmx_pcieepx_cfg038_s cn56xx; 2672 struct cvmx_pcieepx_cfg038_s cn56xxp1; 2673 struct cvmx_pcieepx_cfg038_s cn63xx; 2674 struct cvmx_pcieepx_cfg038_s cn63xxp1; 2675}; 2676typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t; 2677 2678/** 2679 * cvmx_pcieep#_cfg039 2680 * 2681 * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 0 config space 2682 * (Link Capabilities 2 Register) 2683 */ 2684union cvmx_pcieepx_cfg039 2685{ 2686 uint32_t u32; 2687 struct cvmx_pcieepx_cfg039_s 2688 { 2689#if __BYTE_ORDER == __BIG_ENDIAN 2690 uint32_t reserved_0_31 : 32; 2691#else 2692 uint32_t reserved_0_31 : 32; 2693#endif 2694 } s; 2695 struct cvmx_pcieepx_cfg039_s cn52xx; 2696 struct cvmx_pcieepx_cfg039_s cn52xxp1; 2697 struct cvmx_pcieepx_cfg039_s cn56xx; 2698 struct cvmx_pcieepx_cfg039_s cn56xxp1; 2699 struct cvmx_pcieepx_cfg039_s cn63xx; 2700 struct cvmx_pcieepx_cfg039_s cn63xxp1; 2701}; 2702typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t; 2703 2704/** 2705 * cvmx_pcieep#_cfg040 2706 * 2707 * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 0 config space 2708 * (Link Control 2 Register/Link Status 2 Register) 2709 */ 2710union cvmx_pcieepx_cfg040 2711{ 2712 uint32_t u32; 2713 struct cvmx_pcieepx_cfg040_s 2714 { 2715#if __BYTE_ORDER == __BIG_ENDIAN 2716 uint32_t reserved_17_31 : 15; 2717 uint32_t cdl : 1; /**< Current De-emphasis Level 2718 When the Link is operating at 5 GT/s speed, this bit 2719 reflects the level of de-emphasis. Encodings: 2720 1b: -3.5 dB 2721 0b: -6 dB 2722 Note: The value in this bit is undefined when the Link is 2723 operating at 2.5 GT/s speed */ 2724 uint32_t reserved_13_15 : 3; 2725 uint32_t cde : 1; /**< Compliance De-emphasis 2726 This bit sets the de-emphasis level in Polling. Compliance 2727 state if the entry occurred due to the Tx Compliance 2728 Receive bit being 1b. Encodings: 2729 1b: -3.5 dB 2730 0b: -6 dB 2731 Note: When the Link is operating at 2.5 GT/s, the setting 2732 of this bit has no effect. */ 2733 uint32_t csos : 1; /**< Compliance SOS 2734 When set to 1b, the LTSSM is required to send SKP 2735 Ordered Sets periodically in between the (modified) 2736 compliance patterns. 2737 Note: When the Link is operating at 2.5 GT/s, the setting 2738 of this bit has no effect. */ 2739 uint32_t emc : 1; /**< Enter Modified Compliance 2740 When this bit is set to 1b, the device transmits a modified 2741 compliance pattern if the LTSSM enters Polling. 2742 Compliance state. */ 2743 uint32_t tm : 3; /**< Transmit Margin 2744 This field controls the value of the non-de-emphasized 2745 voltage level at the Transmitter pins: 2746 - 000: 800-1200 mV for full swing 400-600 mV for half-swing 2747 - 001-010: values must be monotonic with a non-zero slope 2748 - 011: 200-400 mV for full-swing and 100-200 mV for halfswing 2749 - 100-111: reserved 2750 This field is reset to 000b on entry to the LTSSM Polling. 2751 Compliance substate. 2752 When operating in 5.0 GT/s mode with full swing, the 2753 de-emphasis ratio must be maintained within +/- 1 dB 2754 from the specification-defined operational value 2755 either -3.5 or -6 dB). */ 2756 uint32_t sde : 1; /**< Selectable De-emphasis 2757 Not applicable for an upstream Port or Endpoint device. 2758 Hardwired to 0. */ 2759 uint32_t hasd : 1; /**< Hardware Autonomous Speed Disable 2760 When asserted, the 2761 application must disable hardware from changing the Link 2762 speed for device-specific reasons other than attempting to 2763 correct unreliable Link operation by reducing Link speed. 2764 Initial transition to the highest supported common link 2765 speed is not blocked by this signal. */ 2766 uint32_t ec : 1; /**< Enter Compliance 2767 Software is permitted to force a link to enter Compliance 2768 mode at the speed indicated in the Target Link Speed 2769 field by setting this bit to 1b in both components on a link 2770 and then initiating a hot reset on the link. */ 2771 uint32_t tls : 4; /**< Target Link Speed 2772 For Downstream ports, this field sets an upper limit on link 2773 operational speed by restricting the values advertised by 2774 the upstream component in its training sequences: 2775 - 0001: 2.5Gb/s Target Link Speed 2776 - 0010: 5Gb/s Target Link Speed 2777 All other encodings are reserved. 2778 If a value is written to this field that does not correspond to 2779 a speed included in the Supported Link Speeds field, the 2780 result is undefined. 2781 For both Upstream and Downstream ports, this field is 2782 used to set the target compliance mode speed when 2783 software is using the Enter Compliance bit to force a link 2784 into compliance mode. 2785 Out of reset this will have a value of 1 or 2 which is 2786 selected by qlmCfgx[1]. */ 2787#else 2788 uint32_t tls : 4; 2789 uint32_t ec : 1; 2790 uint32_t hasd : 1; 2791 uint32_t sde : 1; 2792 uint32_t tm : 3; 2793 uint32_t emc : 1; 2794 uint32_t csos : 1; 2795 uint32_t cde : 1; 2796 uint32_t reserved_13_15 : 3; 2797 uint32_t cdl : 1; 2798 uint32_t reserved_17_31 : 15; 2799#endif 2800 } s; 2801 struct cvmx_pcieepx_cfg040_cn52xx 2802 { 2803#if __BYTE_ORDER == __BIG_ENDIAN 2804 uint32_t reserved_0_31 : 32; 2805#else 2806 uint32_t reserved_0_31 : 32; 2807#endif 2808 } cn52xx; 2809 struct cvmx_pcieepx_cfg040_cn52xx cn52xxp1; 2810 struct cvmx_pcieepx_cfg040_cn52xx cn56xx; 2811 struct cvmx_pcieepx_cfg040_cn52xx cn56xxp1; 2812 struct cvmx_pcieepx_cfg040_s cn63xx; 2813 struct cvmx_pcieepx_cfg040_s cn63xxp1; 2814}; 2815typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t; 2816 2817/** 2818 * cvmx_pcieep#_cfg041 2819 * 2820 * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space 2821 * (Slot Capabilities 2 Register) 2822 */ 2823union cvmx_pcieepx_cfg041 2824{ 2825 uint32_t u32; 2826 struct cvmx_pcieepx_cfg041_s 2827 { 2828#if __BYTE_ORDER == __BIG_ENDIAN 2829 uint32_t reserved_0_31 : 32; 2830#else 2831 uint32_t reserved_0_31 : 32; 2832#endif 2833 } s; 2834 struct cvmx_pcieepx_cfg041_s cn52xx; 2835 struct cvmx_pcieepx_cfg041_s cn52xxp1; 2836 struct cvmx_pcieepx_cfg041_s cn56xx; 2837 struct cvmx_pcieepx_cfg041_s cn56xxp1; 2838 struct cvmx_pcieepx_cfg041_s cn63xx; 2839 struct cvmx_pcieepx_cfg041_s cn63xxp1; 2840}; 2841typedef union cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg041_t; 2842 2843/** 2844 * cvmx_pcieep#_cfg042 2845 * 2846 * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space 2847 * (Slot Control 2 Register/Slot Status 2 Register) 2848 */ 2849union cvmx_pcieepx_cfg042 2850{ 2851 uint32_t u32; 2852 struct cvmx_pcieepx_cfg042_s 2853 { 2854#if __BYTE_ORDER == __BIG_ENDIAN 2855 uint32_t reserved_0_31 : 32; 2856#else 2857 uint32_t reserved_0_31 : 32; 2858#endif 2859 } s; 2860 struct cvmx_pcieepx_cfg042_s cn52xx; 2861 struct cvmx_pcieepx_cfg042_s cn52xxp1; 2862 struct cvmx_pcieepx_cfg042_s cn56xx; 2863 struct cvmx_pcieepx_cfg042_s cn56xxp1; 2864 struct cvmx_pcieepx_cfg042_s cn63xx; 2865 struct cvmx_pcieepx_cfg042_s cn63xxp1; 2866}; 2867typedef union cvmx_pcieepx_cfg042 cvmx_pcieepx_cfg042_t; 2868 2869/** 2870 * cvmx_pcieep#_cfg064 2871 * 2872 * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 0 config space 2873 * (PCI Express Enhanced Capability Header) 2874 */ 2875union cvmx_pcieepx_cfg064 2876{ 2877 uint32_t u32; 2878 struct cvmx_pcieepx_cfg064_s 2879 { 2880#if __BYTE_ORDER == __BIG_ENDIAN 2881 uint32_t nco : 12; /**< Next Capability Offset */ 2882 uint32_t cv : 4; /**< Capability Version */ 2883 uint32_t pcieec : 16; /**< PCIE Express Extended Capability */ 2884#else 2885 uint32_t pcieec : 16; 2886 uint32_t cv : 4; 2887 uint32_t nco : 12; 2888#endif 2889 } s; 2890 struct cvmx_pcieepx_cfg064_s cn52xx; 2891 struct cvmx_pcieepx_cfg064_s cn52xxp1; 2892 struct cvmx_pcieepx_cfg064_s cn56xx; 2893 struct cvmx_pcieepx_cfg064_s cn56xxp1; 2894 struct cvmx_pcieepx_cfg064_s cn63xx; 2895 struct cvmx_pcieepx_cfg064_s cn63xxp1; 2896}; 2897typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t; 2898 2899/** 2900 * cvmx_pcieep#_cfg065 2901 * 2902 * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 0 config space 2903 * (Uncorrectable Error Status Register) 2904 */ 2905union cvmx_pcieepx_cfg065 2906{ 2907 uint32_t u32; 2908 struct cvmx_pcieepx_cfg065_s 2909 { 2910#if __BYTE_ORDER == __BIG_ENDIAN 2911 uint32_t reserved_21_31 : 11; 2912 uint32_t ures : 1; /**< Unsupported Request Error Status */ 2913 uint32_t ecrces : 1; /**< ECRC Error Status */ 2914 uint32_t mtlps : 1; /**< Malformed TLP Status */ 2915 uint32_t ros : 1; /**< Receiver Overflow Status */ 2916 uint32_t ucs : 1; /**< Unexpected Completion Status */ 2917 uint32_t cas : 1; /**< Completer Abort Status */ 2918 uint32_t cts : 1; /**< Completion Timeout Status */ 2919 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 2920 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 2921 uint32_t reserved_6_11 : 6; 2922 uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 2923 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 2924 uint32_t reserved_0_3 : 4; 2925#else 2926 uint32_t reserved_0_3 : 4; 2927 uint32_t dlpes : 1; 2928 uint32_t sdes : 1; 2929 uint32_t reserved_6_11 : 6; 2930 uint32_t ptlps : 1; 2931 uint32_t fcpes : 1; 2932 uint32_t cts : 1; 2933 uint32_t cas : 1; 2934 uint32_t ucs : 1; 2935 uint32_t ros : 1; 2936 uint32_t mtlps : 1; 2937 uint32_t ecrces : 1; 2938 uint32_t ures : 1; 2939 uint32_t reserved_21_31 : 11; 2940#endif 2941 } s; 2942 struct cvmx_pcieepx_cfg065_s cn52xx; 2943 struct cvmx_pcieepx_cfg065_s cn52xxp1; 2944 struct cvmx_pcieepx_cfg065_s cn56xx; 2945 struct cvmx_pcieepx_cfg065_s cn56xxp1; 2946 struct cvmx_pcieepx_cfg065_s cn63xx; 2947 struct cvmx_pcieepx_cfg065_s cn63xxp1; 2948}; 2949typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t; 2950 2951/** 2952 * cvmx_pcieep#_cfg066 2953 * 2954 * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 0 config space 2955 * (Uncorrectable Error Mask Register) 2956 */ 2957union cvmx_pcieepx_cfg066 2958{ 2959 uint32_t u32; 2960 struct cvmx_pcieepx_cfg066_s 2961 { 2962#if __BYTE_ORDER == __BIG_ENDIAN 2963 uint32_t reserved_21_31 : 11; 2964 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 2965 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 2966 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 2967 uint32_t rom : 1; /**< Receiver Overflow Mask */ 2968 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 2969 uint32_t cam : 1; /**< Completer Abort Mask */ 2970 uint32_t ctm : 1; /**< Completion Timeout Mask */ 2971 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 2972 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 2973 uint32_t reserved_6_11 : 6; 2974 uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 2975 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 2976 uint32_t reserved_0_3 : 4; 2977#else 2978 uint32_t reserved_0_3 : 4; 2979 uint32_t dlpem : 1; 2980 uint32_t sdem : 1; 2981 uint32_t reserved_6_11 : 6; 2982 uint32_t ptlpm : 1; 2983 uint32_t fcpem : 1; 2984 uint32_t ctm : 1; 2985 uint32_t cam : 1; 2986 uint32_t ucm : 1; 2987 uint32_t rom : 1; 2988 uint32_t mtlpm : 1; 2989 uint32_t ecrcem : 1; 2990 uint32_t urem : 1; 2991 uint32_t reserved_21_31 : 11; 2992#endif 2993 } s; 2994 struct cvmx_pcieepx_cfg066_s cn52xx; 2995 struct cvmx_pcieepx_cfg066_s cn52xxp1; 2996 struct cvmx_pcieepx_cfg066_s cn56xx; 2997 struct cvmx_pcieepx_cfg066_s cn56xxp1; 2998 struct cvmx_pcieepx_cfg066_s cn63xx; 2999 struct cvmx_pcieepx_cfg066_s cn63xxp1; 3000}; 3001typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t; 3002 3003/** 3004 * cvmx_pcieep#_cfg067 3005 * 3006 * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 0 config space 3007 * (Uncorrectable Error Severity Register) 3008 */ 3009union cvmx_pcieepx_cfg067 3010{ 3011 uint32_t u32; 3012 struct cvmx_pcieepx_cfg067_s 3013 { 3014#if __BYTE_ORDER == __BIG_ENDIAN 3015 uint32_t reserved_21_31 : 11; 3016 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 3017 uint32_t ecrces : 1; /**< ECRC Error Severity */ 3018 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 3019 uint32_t ros : 1; /**< Receiver Overflow Severity */ 3020 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 3021 uint32_t cas : 1; /**< Completer Abort Severity */ 3022 uint32_t cts : 1; /**< Completion Timeout Severity */ 3023 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 3024 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 3025 uint32_t reserved_6_11 : 6; 3026 uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 3027 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 3028 uint32_t reserved_0_3 : 4; 3029#else 3030 uint32_t reserved_0_3 : 4; 3031 uint32_t dlpes : 1; 3032 uint32_t sdes : 1; 3033 uint32_t reserved_6_11 : 6; 3034 uint32_t ptlps : 1; 3035 uint32_t fcpes : 1; 3036 uint32_t cts : 1; 3037 uint32_t cas : 1; 3038 uint32_t ucs : 1; 3039 uint32_t ros : 1; 3040 uint32_t mtlps : 1; 3041 uint32_t ecrces : 1; 3042 uint32_t ures : 1; 3043 uint32_t reserved_21_31 : 11; 3044#endif 3045 } s; 3046 struct cvmx_pcieepx_cfg067_s cn52xx; 3047 struct cvmx_pcieepx_cfg067_s cn52xxp1; 3048 struct cvmx_pcieepx_cfg067_s cn56xx; 3049 struct cvmx_pcieepx_cfg067_s cn56xxp1; 3050 struct cvmx_pcieepx_cfg067_s cn63xx; 3051 struct cvmx_pcieepx_cfg067_s cn63xxp1; 3052}; 3053typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t; 3054 3055/** 3056 * cvmx_pcieep#_cfg068 3057 * 3058 * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 0 config space 3059 * (Correctable Error Status Register) 3060 */ 3061union cvmx_pcieepx_cfg068 3062{ 3063 uint32_t u32; 3064 struct cvmx_pcieepx_cfg068_s 3065 { 3066#if __BYTE_ORDER == __BIG_ENDIAN 3067 uint32_t reserved_14_31 : 18; 3068 uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 3069 uint32_t rtts : 1; /**< Reply Timer Timeout Status */ 3070 uint32_t reserved_9_11 : 3; 3071 uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 3072 uint32_t bdllps : 1; /**< Bad DLLP Status */ 3073 uint32_t btlps : 1; /**< Bad TLP Status */ 3074 uint32_t reserved_1_5 : 5; 3075 uint32_t res : 1; /**< Receiver Error Status */ 3076#else 3077 uint32_t res : 1; 3078 uint32_t reserved_1_5 : 5; 3079 uint32_t btlps : 1; 3080 uint32_t bdllps : 1; 3081 uint32_t rnrs : 1; 3082 uint32_t reserved_9_11 : 3; 3083 uint32_t rtts : 1; 3084 uint32_t anfes : 1; 3085 uint32_t reserved_14_31 : 18; 3086#endif 3087 } s; 3088 struct cvmx_pcieepx_cfg068_s cn52xx; 3089 struct cvmx_pcieepx_cfg068_s cn52xxp1; 3090 struct cvmx_pcieepx_cfg068_s cn56xx; 3091 struct cvmx_pcieepx_cfg068_s cn56xxp1; 3092 struct cvmx_pcieepx_cfg068_s cn63xx; 3093 struct cvmx_pcieepx_cfg068_s cn63xxp1; 3094}; 3095typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t; 3096 3097/** 3098 * cvmx_pcieep#_cfg069 3099 * 3100 * PCIE_CFG069 = Seventieth 32-bits of PCIE type 0 config space 3101 * (Correctable Error Mask Register) 3102 */ 3103union cvmx_pcieepx_cfg069 3104{ 3105 uint32_t u32; 3106 struct cvmx_pcieepx_cfg069_s 3107 { 3108#if __BYTE_ORDER == __BIG_ENDIAN 3109 uint32_t reserved_14_31 : 18; 3110 uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 3111 uint32_t rttm : 1; /**< Reply Timer Timeout Mask */ 3112 uint32_t reserved_9_11 : 3; 3113 uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 3114 uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 3115 uint32_t btlpm : 1; /**< Bad TLP Mask */ 3116 uint32_t reserved_1_5 : 5; 3117 uint32_t rem : 1; /**< Receiver Error Mask */ 3118#else 3119 uint32_t rem : 1; 3120 uint32_t reserved_1_5 : 5; 3121 uint32_t btlpm : 1; 3122 uint32_t bdllpm : 1; 3123 uint32_t rnrm : 1; 3124 uint32_t reserved_9_11 : 3; 3125 uint32_t rttm : 1; 3126 uint32_t anfem : 1; 3127 uint32_t reserved_14_31 : 18; 3128#endif 3129 } s; 3130 struct cvmx_pcieepx_cfg069_s cn52xx; 3131 struct cvmx_pcieepx_cfg069_s cn52xxp1; 3132 struct cvmx_pcieepx_cfg069_s cn56xx; 3133 struct cvmx_pcieepx_cfg069_s cn56xxp1; 3134 struct cvmx_pcieepx_cfg069_s cn63xx; 3135 struct cvmx_pcieepx_cfg069_s cn63xxp1; 3136}; 3137typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t; 3138 3139/** 3140 * cvmx_pcieep#_cfg070 3141 * 3142 * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 0 config space 3143 * (Advanced Error Capabilities and Control Register) 3144 */ 3145union cvmx_pcieepx_cfg070 3146{ 3147 uint32_t u32; 3148 struct cvmx_pcieepx_cfg070_s 3149 { 3150#if __BYTE_ORDER == __BIG_ENDIAN 3151 uint32_t reserved_9_31 : 23; 3152 uint32_t ce : 1; /**< ECRC Check Enable */ 3153 uint32_t cc : 1; /**< ECRC Check Capable */ 3154 uint32_t ge : 1; /**< ECRC Generation Enable */ 3155 uint32_t gc : 1; /**< ECRC Generation Capability */ 3156 uint32_t fep : 5; /**< First Error Pointer */ 3157#else 3158 uint32_t fep : 5; 3159 uint32_t gc : 1; 3160 uint32_t ge : 1; 3161 uint32_t cc : 1; 3162 uint32_t ce : 1; 3163 uint32_t reserved_9_31 : 23; 3164#endif 3165 } s; 3166 struct cvmx_pcieepx_cfg070_s cn52xx; 3167 struct cvmx_pcieepx_cfg070_s cn52xxp1; 3168 struct cvmx_pcieepx_cfg070_s cn56xx; 3169 struct cvmx_pcieepx_cfg070_s cn56xxp1; 3170 struct cvmx_pcieepx_cfg070_s cn63xx; 3171 struct cvmx_pcieepx_cfg070_s cn63xxp1; 3172}; 3173typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t; 3174 3175/** 3176 * cvmx_pcieep#_cfg071 3177 * 3178 * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 0 config space 3179 * (Header Log Register 1) 3180 */ 3181union cvmx_pcieepx_cfg071 3182{ 3183 uint32_t u32; 3184 struct cvmx_pcieepx_cfg071_s 3185 { 3186#if __BYTE_ORDER == __BIG_ENDIAN 3187 uint32_t dword1 : 32; /**< Header Log Register (first DWORD) */ 3188#else 3189 uint32_t dword1 : 32; 3190#endif 3191 } s; 3192 struct cvmx_pcieepx_cfg071_s cn52xx; 3193 struct cvmx_pcieepx_cfg071_s cn52xxp1; 3194 struct cvmx_pcieepx_cfg071_s cn56xx; 3195 struct cvmx_pcieepx_cfg071_s cn56xxp1; 3196 struct cvmx_pcieepx_cfg071_s cn63xx; 3197 struct cvmx_pcieepx_cfg071_s cn63xxp1; 3198}; 3199typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t; 3200 3201/** 3202 * cvmx_pcieep#_cfg072 3203 * 3204 * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 0 config space 3205 * (Header Log Register 2) 3206 */ 3207union cvmx_pcieepx_cfg072 3208{ 3209 uint32_t u32; 3210 struct cvmx_pcieepx_cfg072_s 3211 { 3212#if __BYTE_ORDER == __BIG_ENDIAN 3213 uint32_t dword2 : 32; /**< Header Log Register (second DWORD) */ 3214#else 3215 uint32_t dword2 : 32; 3216#endif 3217 } s; 3218 struct cvmx_pcieepx_cfg072_s cn52xx; 3219 struct cvmx_pcieepx_cfg072_s cn52xxp1; 3220 struct cvmx_pcieepx_cfg072_s cn56xx; 3221 struct cvmx_pcieepx_cfg072_s cn56xxp1; 3222 struct cvmx_pcieepx_cfg072_s cn63xx; 3223 struct cvmx_pcieepx_cfg072_s cn63xxp1; 3224}; 3225typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t; 3226 3227/** 3228 * cvmx_pcieep#_cfg073 3229 * 3230 * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 0 config space 3231 * (Header Log Register 3) 3232 */ 3233union cvmx_pcieepx_cfg073 3234{ 3235 uint32_t u32; 3236 struct cvmx_pcieepx_cfg073_s 3237 { 3238#if __BYTE_ORDER == __BIG_ENDIAN 3239 uint32_t dword3 : 32; /**< Header Log Register (third DWORD) */ 3240#else 3241 uint32_t dword3 : 32; 3242#endif 3243 } s; 3244 struct cvmx_pcieepx_cfg073_s cn52xx; 3245 struct cvmx_pcieepx_cfg073_s cn52xxp1; 3246 struct cvmx_pcieepx_cfg073_s cn56xx; 3247 struct cvmx_pcieepx_cfg073_s cn56xxp1; 3248 struct cvmx_pcieepx_cfg073_s cn63xx; 3249 struct cvmx_pcieepx_cfg073_s cn63xxp1; 3250}; 3251typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t; 3252 3253/** 3254 * cvmx_pcieep#_cfg074 3255 * 3256 * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 0 config space 3257 * (Header Log Register 4) 3258 */ 3259union cvmx_pcieepx_cfg074 3260{ 3261 uint32_t u32; 3262 struct cvmx_pcieepx_cfg074_s 3263 { 3264#if __BYTE_ORDER == __BIG_ENDIAN 3265 uint32_t dword4 : 32; /**< Header Log Register (fourth DWORD) */ 3266#else 3267 uint32_t dword4 : 32; 3268#endif 3269 } s; 3270 struct cvmx_pcieepx_cfg074_s cn52xx; 3271 struct cvmx_pcieepx_cfg074_s cn52xxp1; 3272 struct cvmx_pcieepx_cfg074_s cn56xx; 3273 struct cvmx_pcieepx_cfg074_s cn56xxp1; 3274 struct cvmx_pcieepx_cfg074_s cn63xx; 3275 struct cvmx_pcieepx_cfg074_s cn63xxp1; 3276}; 3277typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t; 3278 3279/** 3280 * cvmx_pcieep#_cfg448 3281 * 3282 * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 0 config space 3283 * (Ack Latency Timer and Replay Timer Register) 3284 */ 3285union cvmx_pcieepx_cfg448 3286{ 3287 uint32_t u32; 3288 struct cvmx_pcieepx_cfg448_s 3289 { 3290#if __BYTE_ORDER == __BIG_ENDIAN 3291 uint32_t rtl : 16; /**< Replay Time Limit 3292 The replay timer expires when it reaches this limit. The PCI 3293 Express bus initiates a replay upon reception of a Nak or when 3294 the replay timer expires. 3295 The default is then updated based on the Negotiated Link Width 3296 and Max_Payload_Size. */ 3297 uint32_t rtltl : 16; /**< Round Trip Latency Time Limit 3298 The Ack/Nak latency timer expires when it reaches this limit. 3299 The default is then updated based on the Negotiated Link Width 3300 and Max_Payload_Size. */ 3301#else 3302 uint32_t rtltl : 16; 3303 uint32_t rtl : 16; 3304#endif 3305 } s; 3306 struct cvmx_pcieepx_cfg448_s cn52xx; 3307 struct cvmx_pcieepx_cfg448_s cn52xxp1; 3308 struct cvmx_pcieepx_cfg448_s cn56xx; 3309 struct cvmx_pcieepx_cfg448_s cn56xxp1; 3310 struct cvmx_pcieepx_cfg448_s cn63xx; 3311 struct cvmx_pcieepx_cfg448_s cn63xxp1; 3312}; 3313typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t; 3314 3315/** 3316 * cvmx_pcieep#_cfg449 3317 * 3318 * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 0 config space 3319 * (Other Message Register) 3320 */ 3321union cvmx_pcieepx_cfg449 3322{ 3323 uint32_t u32; 3324 struct cvmx_pcieepx_cfg449_s 3325 { 3326#if __BYTE_ORDER == __BIG_ENDIAN 3327 uint32_t omr : 32; /**< Other Message Register 3328 This register can be used for either of the following purposes: 3329 o To send a specific PCI Express Message, the application 3330 writes the payload of the Message into this register, then 3331 sets bit 0 of the Port Link Control Register to send the 3332 Message. 3333 o To store a corruption pattern for corrupting the LCRC on all 3334 TLPs, the application places a 32-bit corruption pattern into 3335 this register and enables this function by setting bit 25 of 3336 the Port Link Control Register. When enabled, the transmit 3337 LCRC result is XOR'd with this pattern before inserting 3338 it into the packet. */ 3339#else 3340 uint32_t omr : 32; 3341#endif 3342 } s; 3343 struct cvmx_pcieepx_cfg449_s cn52xx; 3344 struct cvmx_pcieepx_cfg449_s cn52xxp1; 3345 struct cvmx_pcieepx_cfg449_s cn56xx; 3346 struct cvmx_pcieepx_cfg449_s cn56xxp1; 3347 struct cvmx_pcieepx_cfg449_s cn63xx; 3348 struct cvmx_pcieepx_cfg449_s cn63xxp1; 3349}; 3350typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t; 3351 3352/** 3353 * cvmx_pcieep#_cfg450 3354 * 3355 * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 0 config space 3356 * (Port Force Link Register) 3357 */ 3358union cvmx_pcieepx_cfg450 3359{ 3360 uint32_t u32; 3361 struct cvmx_pcieepx_cfg450_s 3362 { 3363#if __BYTE_ORDER == __BIG_ENDIAN 3364 uint32_t lpec : 8; /**< Low Power Entrance Count 3365 The Power Management state will wait for this many clock cycles 3366 for the associated completion of a CfgWr to PCIE_CFG017 register 3367 Power State (PS) field register to go low-power. This register 3368 is intended for applications that do not let the PCI Express 3369 bus handle a completion for configuration request to the 3370 Power Management Control and Status (PCIE_CFG017) register. */ 3371 uint32_t reserved_22_23 : 2; 3372 uint32_t link_state : 6; /**< Link State 3373 The Link state that the PCI Express Bus will be forced to 3374 when bit 15 (Force Link) is set. 3375 State encoding: 3376 o DETECT_QUIET 00h 3377 o DETECT_ACT 01h 3378 o POLL_ACTIVE 02h 3379 o POLL_COMPLIANCE 03h 3380 o POLL_CONFIG 04h 3381 o PRE_DETECT_QUIET 05h 3382 o DETECT_WAIT 06h 3383 o CFG_LINKWD_START 07h 3384 o CFG_LINKWD_ACEPT 08h 3385 o CFG_LANENUM_WAIT 09h 3386 o CFG_LANENUM_ACEPT 0Ah 3387 o CFG_COMPLETE 0Bh 3388 o CFG_IDLE 0Ch 3389 o RCVRY_LOCK 0Dh 3390 o RCVRY_SPEED 0Eh 3391 o RCVRY_RCVRCFG 0Fh 3392 o RCVRY_IDLE 10h 3393 o L0 11h 3394 o L0S 12h 3395 o L123_SEND_EIDLE 13h 3396 o L1_IDLE 14h 3397 o L2_IDLE 15h 3398 o L2_WAKE 16h 3399 o DISABLED_ENTRY 17h 3400 o DISABLED_IDLE 18h 3401 o DISABLED 19h 3402 o LPBK_ENTRY 1Ah 3403 o LPBK_ACTIVE 1Bh 3404 o LPBK_EXIT 1Ch 3405 o LPBK_EXIT_TIMEOUT 1Dh 3406 o HOT_RESET_ENTRY 1Eh 3407 o HOT_RESET 1Fh */ 3408 uint32_t force_link : 1; /**< Force Link 3409 Forces the Link to the state specified by the Link State field. 3410 The Force Link pulse will trigger Link re-negotiation. 3411 * As the The Force Link is a pulse, writing a 1 to it does 3412 trigger the forced link state event, even thought reading it 3413 always returns a 0. */ 3414 uint32_t reserved_8_14 : 7; 3415 uint32_t link_num : 8; /**< Link Number 3416 Not used for Endpoint */ 3417#else 3418 uint32_t link_num : 8; 3419 uint32_t reserved_8_14 : 7; 3420 uint32_t force_link : 1; 3421 uint32_t link_state : 6; 3422 uint32_t reserved_22_23 : 2; 3423 uint32_t lpec : 8; 3424#endif 3425 } s; 3426 struct cvmx_pcieepx_cfg450_s cn52xx; 3427 struct cvmx_pcieepx_cfg450_s cn52xxp1; 3428 struct cvmx_pcieepx_cfg450_s cn56xx; 3429 struct cvmx_pcieepx_cfg450_s cn56xxp1; 3430 struct cvmx_pcieepx_cfg450_s cn63xx; 3431 struct cvmx_pcieepx_cfg450_s cn63xxp1; 3432}; 3433typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t; 3434 3435/** 3436 * cvmx_pcieep#_cfg451 3437 * 3438 * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 0 config space 3439 * (Ack Frequency Register) 3440 */ 3441union cvmx_pcieepx_cfg451 3442{ 3443 uint32_t u32; 3444 struct cvmx_pcieepx_cfg451_s 3445 { 3446#if __BYTE_ORDER == __BIG_ENDIAN 3447 uint32_t reserved_30_31 : 2; 3448 uint32_t l1el : 3; /**< L1 Entrance Latency 3449 Values correspond to: 3450 o 000: 1 ms 3451 o 001: 2 ms 3452 o 010: 4 ms 3453 o 011: 8 ms 3454 o 100: 16 ms 3455 o 101: 32 ms 3456 o 110 or 111: 64 ms */ 3457 uint32_t l0el : 3; /**< L0s Entrance Latency 3458 Values correspond to: 3459 o 000: 1 ms 3460 o 001: 2 ms 3461 o 010: 3 ms 3462 o 011: 4 ms 3463 o 100: 5 ms 3464 o 101: 6 ms 3465 o 110 or 111: 7 ms */ 3466 uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 3467 The number of Fast Training Sequence ordered sets to be 3468 transmitted when transitioning from L0s to L0. The maximum 3469 number of FTS ordered-sets that a component can request is 255. 3470 Note: A value of zero is not supported; a value of 3471 zero can cause the LTSSM to go into the recovery state 3472 when exiting from L0s. */ 3473 uint32_t n_fts : 8; /**< N_FTS 3474 The number of Fast Training Sequence ordered sets to be 3475 transmitted when transitioning from L0s to L0. The maximum 3476 number of FTS ordered-sets that a component can request is 255. 3477 Note: A value of zero is not supported; a value of 3478 zero can cause the LTSSM to go into the recovery state 3479 when exiting from L0s. */ 3480 uint32_t ack_freq : 8; /**< Ack Frequency 3481 The number of pending Ack's specified here (up to 255) before 3482 sending an Ack. */ 3483#else 3484 uint32_t ack_freq : 8; 3485 uint32_t n_fts : 8; 3486 uint32_t n_fts_cc : 8; 3487 uint32_t l0el : 3; 3488 uint32_t l1el : 3; 3489 uint32_t reserved_30_31 : 2; 3490#endif 3491 } s; 3492 struct cvmx_pcieepx_cfg451_s cn52xx; 3493 struct cvmx_pcieepx_cfg451_s cn52xxp1; 3494 struct cvmx_pcieepx_cfg451_s cn56xx; 3495 struct cvmx_pcieepx_cfg451_s cn56xxp1; 3496 struct cvmx_pcieepx_cfg451_s cn63xx; 3497 struct cvmx_pcieepx_cfg451_s cn63xxp1; 3498}; 3499typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t; 3500 3501/** 3502 * cvmx_pcieep#_cfg452 3503 * 3504 * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 0 config space 3505 * (Port Link Control Register) 3506 */ 3507union cvmx_pcieepx_cfg452 3508{ 3509 uint32_t u32; 3510 struct cvmx_pcieepx_cfg452_s 3511 { 3512#if __BYTE_ORDER == __BIG_ENDIAN 3513 uint32_t reserved_26_31 : 6; 3514 uint32_t eccrc : 1; /**< Enable Corrupted CRC 3515 Causes corrupt LCRC for TLPs when set, 3516 using the pattern contained in the Other Message register. 3517 This is a test feature, not to be used in normal operation. */ 3518 uint32_t reserved_22_24 : 3; 3519 uint32_t lme : 6; /**< Link Mode Enable 3520 o 000001: x1 3521 o 000011: x2 3522 o 000111: x4 3523 o 001111: x8 (not supported) 3524 o 011111: x16 (not supported) 3525 o 111111: x32 (not supported) 3526 This field indicates the MAXIMUM number of lanes supported 3527 by the PCIe port. The value can be set less than 0x7 3528 to limit the number of lanes the PCIe will attempt to use. 3529 If the value of 0x7 set by the HW is not desired, 3530 this field can be programmed to a smaller value (i.e. EEPROM) 3531 See also MLW. 3532 (Note: The value of this field does NOT indicate the number 3533 of lanes in use by the PCIe. LME sets the max number of lanes 3534 in the PCIe core that COULD be used. As per the PCIe specs, 3535 the PCIe core can negotiate a smaller link width, so all 3536 of x4, x2, and x1 are supported when LME=0x7, 3537 for example.) */ 3538 uint32_t reserved_8_15 : 8; 3539 uint32_t flm : 1; /**< Fast Link Mode 3540 Sets all internal timers to fast mode for simulation purposes. 3541 If during an eeprom load, the first word loaded is 0xffffffff, 3542 then the EEPROM load will be terminated and this bit will be set. */ 3543 uint32_t reserved_6_6 : 1; 3544 uint32_t dllle : 1; /**< DLL Link Enable 3545 Enables Link initialization. If DLL Link Enable = 0, the PCI 3546 Express bus does not transmit InitFC DLLPs and does not 3547 establish a Link. */ 3548 uint32_t reserved_4_4 : 1; 3549 uint32_t ra : 1; /**< Reset Assert 3550 Triggers a recovery and forces the LTSSM to the Hot Reset 3551 state (downstream port only). */ 3552 uint32_t le : 1; /**< Loopback Enable 3553 Initiate loopback mode as a master. On a 0->1 transition, 3554 the PCIe core sends TS ordered sets with the loopback bit set 3555 to cause the link partner to enter into loopback mode as a 3556 slave. Normal transmission is not possible when LE=1. To exit 3557 loopback mode, take the link through a reset sequence. */ 3558 uint32_t sd : 1; /**< Scramble Disable 3559 Turns off data scrambling. */ 3560 uint32_t omr : 1; /**< Other Message Request 3561 When software writes a `1' to this bit, the PCI Express bus 3562 transmits the Message contained in the Other Message register. */ 3563#else 3564 uint32_t omr : 1; 3565 uint32_t sd : 1; 3566 uint32_t le : 1; 3567 uint32_t ra : 1; 3568 uint32_t reserved_4_4 : 1; 3569 uint32_t dllle : 1; 3570 uint32_t reserved_6_6 : 1; 3571 uint32_t flm : 1; 3572 uint32_t reserved_8_15 : 8; 3573 uint32_t lme : 6; 3574 uint32_t reserved_22_24 : 3; 3575 uint32_t eccrc : 1; 3576 uint32_t reserved_26_31 : 6; 3577#endif 3578 } s; 3579 struct cvmx_pcieepx_cfg452_s cn52xx; 3580 struct cvmx_pcieepx_cfg452_s cn52xxp1; 3581 struct cvmx_pcieepx_cfg452_s cn56xx; 3582 struct cvmx_pcieepx_cfg452_s cn56xxp1; 3583 struct cvmx_pcieepx_cfg452_s cn63xx; 3584 struct cvmx_pcieepx_cfg452_s cn63xxp1; 3585}; 3586typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t; 3587 3588/** 3589 * cvmx_pcieep#_cfg453 3590 * 3591 * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 0 config space 3592 * (Lane Skew Register) 3593 */ 3594union cvmx_pcieepx_cfg453 3595{ 3596 uint32_t u32; 3597 struct cvmx_pcieepx_cfg453_s 3598 { 3599#if __BYTE_ORDER == __BIG_ENDIAN 3600 uint32_t dlld : 1; /**< Disable Lane-to-Lane Deskew 3601 Disables the internal Lane-to-Lane deskew logic. */ 3602 uint32_t reserved_26_30 : 5; 3603 uint32_t ack_nak : 1; /**< Ack/Nak Disable 3604 Prevents the PCI Express bus from sending Ack and Nak DLLPs. */ 3605 uint32_t fcd : 1; /**< Flow Control Disable 3606 Prevents the PCI Express bus from sending FC DLLPs. */ 3607 uint32_t ilst : 24; /**< Insert Lane Skew for Transmit 3608 Causes skew between lanes for test purposes. There are three 3609 bits per Lane. The value is in units of one symbol time. For 3610 example, the value 010b for a Lane forces a skew of two symbol 3611 times for that Lane. The maximum skew value for any Lane is 5 3612 symbol times. */ 3613#else 3614 uint32_t ilst : 24; 3615 uint32_t fcd : 1; 3616 uint32_t ack_nak : 1; 3617 uint32_t reserved_26_30 : 5; 3618 uint32_t dlld : 1; 3619#endif 3620 } s; 3621 struct cvmx_pcieepx_cfg453_s cn52xx; 3622 struct cvmx_pcieepx_cfg453_s cn52xxp1; 3623 struct cvmx_pcieepx_cfg453_s cn56xx; 3624 struct cvmx_pcieepx_cfg453_s cn56xxp1; 3625 struct cvmx_pcieepx_cfg453_s cn63xx; 3626 struct cvmx_pcieepx_cfg453_s cn63xxp1; 3627}; 3628typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t; 3629 3630/** 3631 * cvmx_pcieep#_cfg454 3632 * 3633 * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 0 config space 3634 * (Symbol Number Register) 3635 */ 3636union cvmx_pcieepx_cfg454 3637{ 3638 uint32_t u32; 3639 struct cvmx_pcieepx_cfg454_s 3640 { 3641#if __BYTE_ORDER == __BIG_ENDIAN 3642 uint32_t reserved_29_31 : 3; 3643 uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 3644 Increases the timer value for the Flow Control watchdog timer, 3645 in increments of 16 clock cycles. */ 3646 uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 3647 Increases the timer value for the Ack/Nak latency timer, in 3648 increments of 64 clock cycles. */ 3649 uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 3650 Increases the timer value for the replay timer, in increments 3651 of 64 clock cycles. */ 3652 uint32_t reserved_11_13 : 3; 3653 uint32_t nskps : 3; /**< Number of SKP Symbols */ 3654 uint32_t reserved_4_7 : 4; 3655 uint32_t ntss : 4; /**< Number of TS Symbols 3656 Sets the number of TS identifier symbols that are sent in TS1 3657 and TS2 ordered sets. */ 3658#else 3659 uint32_t ntss : 4; 3660 uint32_t reserved_4_7 : 4; 3661 uint32_t nskps : 3; 3662 uint32_t reserved_11_13 : 3; 3663 uint32_t tmrt : 5; 3664 uint32_t tmanlt : 5; 3665 uint32_t tmfcwt : 5; 3666 uint32_t reserved_29_31 : 3; 3667#endif 3668 } s; 3669 struct cvmx_pcieepx_cfg454_s cn52xx; 3670 struct cvmx_pcieepx_cfg454_s cn52xxp1; 3671 struct cvmx_pcieepx_cfg454_s cn56xx; 3672 struct cvmx_pcieepx_cfg454_s cn56xxp1; 3673 struct cvmx_pcieepx_cfg454_s cn63xx; 3674 struct cvmx_pcieepx_cfg454_s cn63xxp1; 3675}; 3676typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t; 3677 3678/** 3679 * cvmx_pcieep#_cfg455 3680 * 3681 * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 0 config space 3682 * (Symbol Timer Register/Filter Mask Register 1) 3683 */ 3684union cvmx_pcieepx_cfg455 3685{ 3686 uint32_t u32; 3687 struct cvmx_pcieepx_cfg455_s 3688 { 3689#if __BYTE_ORDER == __BIG_ENDIAN 3690 uint32_t m_cfg0_filt : 1; /**< Mask filtering of received Configuration Requests (RC mode only) */ 3691 uint32_t m_io_filt : 1; /**< Mask filtering of received I/O Requests (RC mode only) */ 3692 uint32_t msg_ctrl : 1; /**< Message Control 3693 The application must not change this field. */ 3694 uint32_t m_cpl_ecrc_filt : 1; /**< Mask ECRC error filtering for Completions */ 3695 uint32_t m_ecrc_filt : 1; /**< Mask ECRC error filtering */ 3696 uint32_t m_cpl_len_err : 1; /**< Mask Length mismatch error for received Completions */ 3697 uint32_t m_cpl_attr_err : 1; /**< Mask Attributes mismatch error for received Completions */ 3698 uint32_t m_cpl_tc_err : 1; /**< Mask Traffic Class mismatch error for received Completions */ 3699 uint32_t m_cpl_fun_err : 1; /**< Mask function mismatch error for received Completions */ 3700 uint32_t m_cpl_rid_err : 1; /**< Mask Requester ID mismatch error for received Completions */ 3701 uint32_t m_cpl_tag_err : 1; /**< Mask Tag error rules for received Completions */ 3702 uint32_t m_lk_filt : 1; /**< Mask Locked Request filtering */ 3703 uint32_t m_cfg1_filt : 1; /**< Mask Type 1 Configuration Request filtering */ 3704 uint32_t m_bar_match : 1; /**< Mask BAR match filtering */ 3705 uint32_t m_pois_filt : 1; /**< Mask poisoned TLP filtering */ 3706 uint32_t m_fun : 1; /**< Mask function */ 3707 uint32_t dfcwt : 1; /**< Disable FC Watchdog Timer */ 3708 uint32_t reserved_11_14 : 4; 3709 uint32_t skpiv : 11; /**< SKP Interval Value */ 3710#else 3711 uint32_t skpiv : 11; 3712 uint32_t reserved_11_14 : 4; 3713 uint32_t dfcwt : 1; 3714 uint32_t m_fun : 1; 3715 uint32_t m_pois_filt : 1; 3716 uint32_t m_bar_match : 1; 3717 uint32_t m_cfg1_filt : 1; 3718 uint32_t m_lk_filt : 1; 3719 uint32_t m_cpl_tag_err : 1; 3720 uint32_t m_cpl_rid_err : 1; 3721 uint32_t m_cpl_fun_err : 1; 3722 uint32_t m_cpl_tc_err : 1; 3723 uint32_t m_cpl_attr_err : 1; 3724 uint32_t m_cpl_len_err : 1; 3725 uint32_t m_ecrc_filt : 1; 3726 uint32_t m_cpl_ecrc_filt : 1; 3727 uint32_t msg_ctrl : 1; 3728 uint32_t m_io_filt : 1; 3729 uint32_t m_cfg0_filt : 1; 3730#endif 3731 } s; 3732 struct cvmx_pcieepx_cfg455_s cn52xx; 3733 struct cvmx_pcieepx_cfg455_s cn52xxp1; 3734 struct cvmx_pcieepx_cfg455_s cn56xx; 3735 struct cvmx_pcieepx_cfg455_s cn56xxp1; 3736 struct cvmx_pcieepx_cfg455_s cn63xx; 3737 struct cvmx_pcieepx_cfg455_s cn63xxp1; 3738}; 3739typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t; 3740 3741/** 3742 * cvmx_pcieep#_cfg456 3743 * 3744 * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 0 config space 3745 * (Filter Mask Register 2) 3746 */ 3747union cvmx_pcieepx_cfg456 3748{ 3749 uint32_t u32; 3750 struct cvmx_pcieepx_cfg456_s 3751 { 3752#if __BYTE_ORDER == __BIG_ENDIAN 3753 uint32_t reserved_2_31 : 30; 3754 uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 3755 uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 3756#else 3757 uint32_t m_vend0_drp : 1; 3758 uint32_t m_vend1_drp : 1; 3759 uint32_t reserved_2_31 : 30; 3760#endif 3761 } s; 3762 struct cvmx_pcieepx_cfg456_s cn52xx; 3763 struct cvmx_pcieepx_cfg456_s cn52xxp1; 3764 struct cvmx_pcieepx_cfg456_s cn56xx; 3765 struct cvmx_pcieepx_cfg456_s cn56xxp1; 3766 struct cvmx_pcieepx_cfg456_s cn63xx; 3767 struct cvmx_pcieepx_cfg456_s cn63xxp1; 3768}; 3769typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t; 3770 3771/** 3772 * cvmx_pcieep#_cfg458 3773 * 3774 * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 0 config space 3775 * (Debug Register 0) 3776 */ 3777union cvmx_pcieepx_cfg458 3778{ 3779 uint32_t u32; 3780 struct cvmx_pcieepx_cfg458_s 3781 { 3782#if __BYTE_ORDER == __BIG_ENDIAN 3783 uint32_t dbg_info_l32 : 32; /**< Debug Info Lower 32 Bits */ 3784#else 3785 uint32_t dbg_info_l32 : 32; 3786#endif 3787 } s; 3788 struct cvmx_pcieepx_cfg458_s cn52xx; 3789 struct cvmx_pcieepx_cfg458_s cn52xxp1; 3790 struct cvmx_pcieepx_cfg458_s cn56xx; 3791 struct cvmx_pcieepx_cfg458_s cn56xxp1; 3792 struct cvmx_pcieepx_cfg458_s cn63xx; 3793 struct cvmx_pcieepx_cfg458_s cn63xxp1; 3794}; 3795typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t; 3796 3797/** 3798 * cvmx_pcieep#_cfg459 3799 * 3800 * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 0 config space 3801 * (Debug Register 1) 3802 */ 3803union cvmx_pcieepx_cfg459 3804{ 3805 uint32_t u32; 3806 struct cvmx_pcieepx_cfg459_s 3807 { 3808#if __BYTE_ORDER == __BIG_ENDIAN 3809 uint32_t dbg_info_u32 : 32; /**< Debug Info Upper 32 Bits */ 3810#else 3811 uint32_t dbg_info_u32 : 32; 3812#endif 3813 } s; 3814 struct cvmx_pcieepx_cfg459_s cn52xx; 3815 struct cvmx_pcieepx_cfg459_s cn52xxp1; 3816 struct cvmx_pcieepx_cfg459_s cn56xx; 3817 struct cvmx_pcieepx_cfg459_s cn56xxp1; 3818 struct cvmx_pcieepx_cfg459_s cn63xx; 3819 struct cvmx_pcieepx_cfg459_s cn63xxp1; 3820}; 3821typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t; 3822 3823/** 3824 * cvmx_pcieep#_cfg460 3825 * 3826 * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 0 config space 3827 * (Transmit Posted FC Credit Status) 3828 */ 3829union cvmx_pcieepx_cfg460 3830{ 3831 uint32_t u32; 3832 struct cvmx_pcieepx_cfg460_s 3833 { 3834#if __BYTE_ORDER == __BIG_ENDIAN 3835 uint32_t reserved_20_31 : 12; 3836 uint32_t tphfcc : 8; /**< Transmit Posted Header FC Credits 3837 The Posted Header credits advertised by the receiver at the 3838 other end of the Link, updated with each UpdateFC DLLP. */ 3839 uint32_t tpdfcc : 12; /**< Transmit Posted Data FC Credits 3840 The Posted Data credits advertised by the receiver at the other 3841 end of the Link, updated with each UpdateFC DLLP. */ 3842#else 3843 uint32_t tpdfcc : 12; 3844 uint32_t tphfcc : 8; 3845 uint32_t reserved_20_31 : 12; 3846#endif 3847 } s; 3848 struct cvmx_pcieepx_cfg460_s cn52xx; 3849 struct cvmx_pcieepx_cfg460_s cn52xxp1; 3850 struct cvmx_pcieepx_cfg460_s cn56xx; 3851 struct cvmx_pcieepx_cfg460_s cn56xxp1; 3852 struct cvmx_pcieepx_cfg460_s cn63xx; 3853 struct cvmx_pcieepx_cfg460_s cn63xxp1; 3854}; 3855typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t; 3856 3857/** 3858 * cvmx_pcieep#_cfg461 3859 * 3860 * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 0 config space 3861 * (Transmit Non-Posted FC Credit Status) 3862 */ 3863union cvmx_pcieepx_cfg461 3864{ 3865 uint32_t u32; 3866 struct cvmx_pcieepx_cfg461_s 3867 { 3868#if __BYTE_ORDER == __BIG_ENDIAN 3869 uint32_t reserved_20_31 : 12; 3870 uint32_t tchfcc : 8; /**< Transmit Non-Posted Header FC Credits 3871 The Non-Posted Header credits advertised by the receiver at the 3872 other end of the Link, updated with each UpdateFC DLLP. */ 3873 uint32_t tcdfcc : 12; /**< Transmit Non-Posted Data FC Credits 3874 The Non-Posted Data credits advertised by the receiver at the 3875 other end of the Link, updated with each UpdateFC DLLP. */ 3876#else 3877 uint32_t tcdfcc : 12; 3878 uint32_t tchfcc : 8; 3879 uint32_t reserved_20_31 : 12; 3880#endif 3881 } s; 3882 struct cvmx_pcieepx_cfg461_s cn52xx; 3883 struct cvmx_pcieepx_cfg461_s cn52xxp1; 3884 struct cvmx_pcieepx_cfg461_s cn56xx; 3885 struct cvmx_pcieepx_cfg461_s cn56xxp1; 3886 struct cvmx_pcieepx_cfg461_s cn63xx; 3887 struct cvmx_pcieepx_cfg461_s cn63xxp1; 3888}; 3889typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t; 3890 3891/** 3892 * cvmx_pcieep#_cfg462 3893 * 3894 * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 0 config space 3895 * (Transmit Completion FC Credit Status ) 3896 */ 3897union cvmx_pcieepx_cfg462 3898{ 3899 uint32_t u32; 3900 struct cvmx_pcieepx_cfg462_s 3901 { 3902#if __BYTE_ORDER == __BIG_ENDIAN 3903 uint32_t reserved_20_31 : 12; 3904 uint32_t tchfcc : 8; /**< Transmit Completion Header FC Credits 3905 The Completion Header credits advertised by the receiver at the 3906 other end of the Link, updated with each UpdateFC DLLP. */ 3907 uint32_t tcdfcc : 12; /**< Transmit Completion Data FC Credits 3908 The Completion Data credits advertised by the receiver at the 3909 other end of the Link, updated with each UpdateFC DLLP. */ 3910#else 3911 uint32_t tcdfcc : 12; 3912 uint32_t tchfcc : 8; 3913 uint32_t reserved_20_31 : 12; 3914#endif 3915 } s; 3916 struct cvmx_pcieepx_cfg462_s cn52xx; 3917 struct cvmx_pcieepx_cfg462_s cn52xxp1; 3918 struct cvmx_pcieepx_cfg462_s cn56xx; 3919 struct cvmx_pcieepx_cfg462_s cn56xxp1; 3920 struct cvmx_pcieepx_cfg462_s cn63xx; 3921 struct cvmx_pcieepx_cfg462_s cn63xxp1; 3922}; 3923typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t; 3924 3925/** 3926 * cvmx_pcieep#_cfg463 3927 * 3928 * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 0 config space 3929 * (Queue Status) 3930 */ 3931union cvmx_pcieepx_cfg463 3932{ 3933 uint32_t u32; 3934 struct cvmx_pcieepx_cfg463_s 3935 { 3936#if __BYTE_ORDER == __BIG_ENDIAN 3937 uint32_t reserved_3_31 : 29; 3938 uint32_t rqne : 1; /**< Received Queue Not Empty 3939 Indicates there is data in one or more of the receive buffers. */ 3940 uint32_t trbne : 1; /**< Transmit Retry Buffer Not Empty 3941 Indicates that there is data in the transmit retry buffer. */ 3942 uint32_t rtlpfccnr : 1; /**< Received TLP FC Credits Not Returned 3943 Indicates that the PCI Express bus has sent a TLP but has not 3944 yet received an UpdateFC DLLP indicating that the credits for 3945 that TLP have been restored by the receiver at the other end of 3946 the Link. */ 3947#else 3948 uint32_t rtlpfccnr : 1; 3949 uint32_t trbne : 1; 3950 uint32_t rqne : 1; 3951 uint32_t reserved_3_31 : 29; 3952#endif 3953 } s; 3954 struct cvmx_pcieepx_cfg463_s cn52xx; 3955 struct cvmx_pcieepx_cfg463_s cn52xxp1; 3956 struct cvmx_pcieepx_cfg463_s cn56xx; 3957 struct cvmx_pcieepx_cfg463_s cn56xxp1; 3958 struct cvmx_pcieepx_cfg463_s cn63xx; 3959 struct cvmx_pcieepx_cfg463_s cn63xxp1; 3960}; 3961typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t; 3962 3963/** 3964 * cvmx_pcieep#_cfg464 3965 * 3966 * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 0 config space 3967 * (VC Transmit Arbitration Register 1) 3968 */ 3969union cvmx_pcieepx_cfg464 3970{ 3971 uint32_t u32; 3972 struct cvmx_pcieepx_cfg464_s 3973 { 3974#if __BYTE_ORDER == __BIG_ENDIAN 3975 uint32_t wrr_vc3 : 8; /**< WRR Weight for VC3 */ 3976 uint32_t wrr_vc2 : 8; /**< WRR Weight for VC2 */ 3977 uint32_t wrr_vc1 : 8; /**< WRR Weight for VC1 */ 3978 uint32_t wrr_vc0 : 8; /**< WRR Weight for VC0 */ 3979#else 3980 uint32_t wrr_vc0 : 8; 3981 uint32_t wrr_vc1 : 8; 3982 uint32_t wrr_vc2 : 8; 3983 uint32_t wrr_vc3 : 8; 3984#endif 3985 } s; 3986 struct cvmx_pcieepx_cfg464_s cn52xx; 3987 struct cvmx_pcieepx_cfg464_s cn52xxp1; 3988 struct cvmx_pcieepx_cfg464_s cn56xx; 3989 struct cvmx_pcieepx_cfg464_s cn56xxp1; 3990 struct cvmx_pcieepx_cfg464_s cn63xx; 3991 struct cvmx_pcieepx_cfg464_s cn63xxp1; 3992}; 3993typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t; 3994 3995/** 3996 * cvmx_pcieep#_cfg465 3997 * 3998 * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of PCIE type 0 config space 3999 * (VC Transmit Arbitration Register 2) 4000 */ 4001union cvmx_pcieepx_cfg465 4002{ 4003 uint32_t u32; 4004 struct cvmx_pcieepx_cfg465_s 4005 { 4006#if __BYTE_ORDER == __BIG_ENDIAN 4007 uint32_t wrr_vc7 : 8; /**< WRR Weight for VC7 */ 4008 uint32_t wrr_vc6 : 8; /**< WRR Weight for VC6 */ 4009 uint32_t wrr_vc5 : 8; /**< WRR Weight for VC5 */ 4010 uint32_t wrr_vc4 : 8; /**< WRR Weight for VC4 */ 4011#else 4012 uint32_t wrr_vc4 : 8; 4013 uint32_t wrr_vc5 : 8; 4014 uint32_t wrr_vc6 : 8; 4015 uint32_t wrr_vc7 : 8; 4016#endif 4017 } s; 4018 struct cvmx_pcieepx_cfg465_s cn52xx; 4019 struct cvmx_pcieepx_cfg465_s cn52xxp1; 4020 struct cvmx_pcieepx_cfg465_s cn56xx; 4021 struct cvmx_pcieepx_cfg465_s cn56xxp1; 4022 struct cvmx_pcieepx_cfg465_s cn63xx; 4023 struct cvmx_pcieepx_cfg465_s cn63xxp1; 4024}; 4025typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t; 4026 4027/** 4028 * cvmx_pcieep#_cfg466 4029 * 4030 * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 0 config space 4031 * (VC0 Posted Receive Queue Control) 4032 */ 4033union cvmx_pcieepx_cfg466 4034{ 4035 uint32_t u32; 4036 struct cvmx_pcieepx_cfg466_s 4037 { 4038#if __BYTE_ORDER == __BIG_ENDIAN 4039 uint32_t rx_queue_order : 1; /**< VC Ordering for Receive Queues 4040 Determines the VC ordering rule for the receive queues, used 4041 only in the segmented-buffer configuration, 4042 writable through PEM(0..1)_CFG_WR: 4043 o 1: Strict ordering, higher numbered VCs have higher priority 4044 o 0: Round robin 4045 However, the application must not change this field. */ 4046 uint32_t type_ordering : 1; /**< TLP Type Ordering for VC0 4047 Determines the TLP type ordering rule for VC0 receive queues, 4048 used only in the segmented-buffer configuration, writable 4049 through PEM(0..1)_CFG_WR: 4050 o 1: Ordering of received TLPs follows the rules in 4051 PCI Express Base Specification 4052 o 0: Strict ordering for received TLPs: Posted, then 4053 Completion, then Non-Posted 4054 However, the application must not change this field. */ 4055 uint32_t reserved_24_29 : 6; 4056 uint32_t queue_mode : 3; /**< VC0 Posted TLP Queue Mode 4057 The operating mode of the Posted receive queue for VC0, used 4058 only in the segmented-buffer configuration, writable through 4059 PEM(0..1)_CFG_WR. 4060 However, the application must not change this field. 4061 Only one bit can be set at a time: 4062 o Bit 23: Bypass 4063 o Bit 22: Cut-through 4064 o Bit 21: Store-and-forward */ 4065 uint32_t reserved_20_20 : 1; 4066 uint32_t header_credits : 8; /**< VC0 Posted Header Credits 4067 The number of initial Posted header credits for VC0, used for 4068 all receive queue buffer configurations. 4069 This field is writable through PEM(0..1)_CFG_WR. 4070 However, the application must not change this field. */ 4071 uint32_t data_credits : 12; /**< VC0 Posted Data Credits 4072 The number of initial Posted data credits for VC0, used for all 4073 receive queue buffer configurations. 4074 This field is writable through PEM(0..1)_CFG_WR. 4075 However, the application must not change this field. */ 4076#else 4077 uint32_t data_credits : 12; 4078 uint32_t header_credits : 8; 4079 uint32_t reserved_20_20 : 1; 4080 uint32_t queue_mode : 3; 4081 uint32_t reserved_24_29 : 6; 4082 uint32_t type_ordering : 1; 4083 uint32_t rx_queue_order : 1; 4084#endif 4085 } s; 4086 struct cvmx_pcieepx_cfg466_s cn52xx; 4087 struct cvmx_pcieepx_cfg466_s cn52xxp1; 4088 struct cvmx_pcieepx_cfg466_s cn56xx; 4089 struct cvmx_pcieepx_cfg466_s cn56xxp1; 4090 struct cvmx_pcieepx_cfg466_s cn63xx; 4091 struct cvmx_pcieepx_cfg466_s cn63xxp1; 4092}; 4093typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t; 4094 4095/** 4096 * cvmx_pcieep#_cfg467 4097 * 4098 * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 0 config space 4099 * (VC0 Non-Posted Receive Queue Control) 4100 */ 4101union cvmx_pcieepx_cfg467 4102{ 4103 uint32_t u32; 4104 struct cvmx_pcieepx_cfg467_s 4105 { 4106#if __BYTE_ORDER == __BIG_ENDIAN 4107 uint32_t reserved_24_31 : 8; 4108 uint32_t queue_mode : 3; /**< VC0 Non-Posted TLP Queue Mode 4109 The operating mode of the Non-Posted receive queue for VC0, 4110 used only in the segmented-buffer configuration, writable 4111 through PEM(0..1)_CFG_WR. 4112 Only one bit can be set at a time: 4113 o Bit 23: Bypass 4114 o Bit 22: Cut-through 4115 o Bit 21: Store-and-forward 4116 However, the application must not change this field. */ 4117 uint32_t reserved_20_20 : 1; 4118 uint32_t header_credits : 8; /**< VC0 Non-Posted Header Credits 4119 The number of initial Non-Posted header credits for VC0, used 4120 for all receive queue buffer configurations. 4121 This field is writable through PEM(0..1)_CFG_WR. 4122 However, the application must not change this field. */ 4123 uint32_t data_credits : 12; /**< VC0 Non-Posted Data Credits 4124 The number of initial Non-Posted data credits for VC0, used for 4125 all receive queue buffer configurations. 4126 This field is writable through PEM(0..1)_CFG_WR. 4127 However, the application must not change this field. */ 4128#else 4129 uint32_t data_credits : 12; 4130 uint32_t header_credits : 8; 4131 uint32_t reserved_20_20 : 1; 4132 uint32_t queue_mode : 3; 4133 uint32_t reserved_24_31 : 8; 4134#endif 4135 } s; 4136 struct cvmx_pcieepx_cfg467_s cn52xx; 4137 struct cvmx_pcieepx_cfg467_s cn52xxp1; 4138 struct cvmx_pcieepx_cfg467_s cn56xx; 4139 struct cvmx_pcieepx_cfg467_s cn56xxp1; 4140 struct cvmx_pcieepx_cfg467_s cn63xx; 4141 struct cvmx_pcieepx_cfg467_s cn63xxp1; 4142}; 4143typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t; 4144 4145/** 4146 * cvmx_pcieep#_cfg468 4147 * 4148 * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 0 config space 4149 * (VC0 Completion Receive Queue Control) 4150 */ 4151union cvmx_pcieepx_cfg468 4152{ 4153 uint32_t u32; 4154 struct cvmx_pcieepx_cfg468_s 4155 { 4156#if __BYTE_ORDER == __BIG_ENDIAN 4157 uint32_t reserved_24_31 : 8; 4158 uint32_t queue_mode : 3; /**< VC0 Completion TLP Queue Mode 4159 The operating mode of the Completion receive queue for VC0, 4160 used only in the segmented-buffer configuration, writable 4161 through PEM(0..1)_CFG_WR. 4162 Only one bit can be set at a time: 4163 o Bit 23: Bypass 4164 o Bit 22: Cut-through 4165 o Bit 21: Store-and-forward 4166 However, the application must not change this field. */ 4167 uint32_t reserved_20_20 : 1; 4168 uint32_t header_credits : 8; /**< VC0 Completion Header Credits 4169 The number of initial Completion header credits for VC0, used 4170 for all receive queue buffer configurations. 4171 This field is writable through PEM(0..1)_CFG_WR. 4172 However, the application must not change this field. */ 4173 uint32_t data_credits : 12; /**< VC0 Completion Data Credits 4174 The number of initial Completion data credits for VC0, used for 4175 all receive queue buffer configurations. 4176 This field is writable through PEM(0..1)_CFG_WR. 4177 However, the application must not change this field. */ 4178#else 4179 uint32_t data_credits : 12; 4180 uint32_t header_credits : 8; 4181 uint32_t reserved_20_20 : 1; 4182 uint32_t queue_mode : 3; 4183 uint32_t reserved_24_31 : 8; 4184#endif 4185 } s; 4186 struct cvmx_pcieepx_cfg468_s cn52xx; 4187 struct cvmx_pcieepx_cfg468_s cn52xxp1; 4188 struct cvmx_pcieepx_cfg468_s cn56xx; 4189 struct cvmx_pcieepx_cfg468_s cn56xxp1; 4190 struct cvmx_pcieepx_cfg468_s cn63xx; 4191 struct cvmx_pcieepx_cfg468_s cn63xxp1; 4192}; 4193typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t; 4194 4195/** 4196 * cvmx_pcieep#_cfg490 4197 * 4198 * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space 4199 * (VC0 Posted Buffer Depth) 4200 */ 4201union cvmx_pcieepx_cfg490 4202{ 4203 uint32_t u32; 4204 struct cvmx_pcieepx_cfg490_s 4205 { 4206#if __BYTE_ORDER == __BIG_ENDIAN 4207 uint32_t reserved_26_31 : 6; 4208 uint32_t header_depth : 10; /**< VC0 Posted Header Queue Depth 4209 Sets the number of entries in the Posted header queue for VC0 4210 when using the segmented-buffer configuration, writable through 4211 PEM(0..1)_CFG_WR. 4212 However, the application must not change this field. */ 4213 uint32_t reserved_14_15 : 2; 4214 uint32_t data_depth : 14; /**< VC0 Posted Data Queue Depth 4215 Sets the number of entries in the Posted data queue for VC0 4216 when using the segmented-buffer configuration, writable 4217 through PEM(0..1)_CFG_WR. 4218 However, the application must not change this field. */ 4219#else 4220 uint32_t data_depth : 14; 4221 uint32_t reserved_14_15 : 2; 4222 uint32_t header_depth : 10; 4223 uint32_t reserved_26_31 : 6; 4224#endif 4225 } s; 4226 struct cvmx_pcieepx_cfg490_s cn52xx; 4227 struct cvmx_pcieepx_cfg490_s cn52xxp1; 4228 struct cvmx_pcieepx_cfg490_s cn56xx; 4229 struct cvmx_pcieepx_cfg490_s cn56xxp1; 4230 struct cvmx_pcieepx_cfg490_s cn63xx; 4231 struct cvmx_pcieepx_cfg490_s cn63xxp1; 4232}; 4233typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t; 4234 4235/** 4236 * cvmx_pcieep#_cfg491 4237 * 4238 * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space 4239 * (VC0 Non-Posted Buffer Depth) 4240 */ 4241union cvmx_pcieepx_cfg491 4242{ 4243 uint32_t u32; 4244 struct cvmx_pcieepx_cfg491_s 4245 { 4246#if __BYTE_ORDER == __BIG_ENDIAN 4247 uint32_t reserved_26_31 : 6; 4248 uint32_t header_depth : 10; /**< VC0 Non-Posted Header Queue Depth 4249 Sets the number of entries in the Non-Posted header queue for 4250 VC0 when using the segmented-buffer configuration, writable 4251 through PEM(0..1)_CFG_WR. 4252 However, the application must not change this field. */ 4253 uint32_t reserved_14_15 : 2; 4254 uint32_t data_depth : 14; /**< VC0 Non-Posted Data Queue Depth 4255 Sets the number of entries in the Non-Posted data queue for VC0 4256 when using the segmented-buffer configuration, writable 4257 through PEM(0..1)_CFG_WR. 4258 However, the application must not change this field. */ 4259#else 4260 uint32_t data_depth : 14; 4261 uint32_t reserved_14_15 : 2; 4262 uint32_t header_depth : 10; 4263 uint32_t reserved_26_31 : 6; 4264#endif 4265 } s; 4266 struct cvmx_pcieepx_cfg491_s cn52xx; 4267 struct cvmx_pcieepx_cfg491_s cn52xxp1; 4268 struct cvmx_pcieepx_cfg491_s cn56xx; 4269 struct cvmx_pcieepx_cfg491_s cn56xxp1; 4270 struct cvmx_pcieepx_cfg491_s cn63xx; 4271 struct cvmx_pcieepx_cfg491_s cn63xxp1; 4272}; 4273typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t; 4274 4275/** 4276 * cvmx_pcieep#_cfg492 4277 * 4278 * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space 4279 * (VC0 Completion Buffer Depth) 4280 */ 4281union cvmx_pcieepx_cfg492 4282{ 4283 uint32_t u32; 4284 struct cvmx_pcieepx_cfg492_s 4285 { 4286#if __BYTE_ORDER == __BIG_ENDIAN 4287 uint32_t reserved_26_31 : 6; 4288 uint32_t header_depth : 10; /**< VC0 Completion Header Queue Depth 4289 Sets the number of entries in the Completion header queue for 4290 VC0 when using the segmented-buffer configuration, writable 4291 through PEM(0..1)_CFG_WR. 4292 However, the application must not change this field. */ 4293 uint32_t reserved_14_15 : 2; 4294 uint32_t data_depth : 14; /**< VC0 Completion Data Queue Depth 4295 Sets the number of entries in the Completion data queue for VC0 4296 when using the segmented-buffer configuration, writable 4297 through PEM(0..1)_CFG_WR. 4298 However, the application must not change this field. */ 4299#else 4300 uint32_t data_depth : 14; 4301 uint32_t reserved_14_15 : 2; 4302 uint32_t header_depth : 10; 4303 uint32_t reserved_26_31 : 6; 4304#endif 4305 } s; 4306 struct cvmx_pcieepx_cfg492_s cn52xx; 4307 struct cvmx_pcieepx_cfg492_s cn52xxp1; 4308 struct cvmx_pcieepx_cfg492_s cn56xx; 4309 struct cvmx_pcieepx_cfg492_s cn56xxp1; 4310 struct cvmx_pcieepx_cfg492_s cn63xx; 4311 struct cvmx_pcieepx_cfg492_s cn63xxp1; 4312}; 4313typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t; 4314 4315/** 4316 * cvmx_pcieep#_cfg515 4317 * 4318 * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 0 config space 4319 * (Port Logic Register (Gen2)) 4320 */ 4321union cvmx_pcieepx_cfg515 4322{ 4323 uint32_t u32; 4324 struct cvmx_pcieepx_cfg515_s 4325 { 4326#if __BYTE_ORDER == __BIG_ENDIAN 4327 uint32_t reserved_21_31 : 11; 4328 uint32_t s_d_e : 1; /**< SEL_DE_EMPHASIS 4329 Used to set the de-emphasis level for upstream ports. */ 4330 uint32_t ctcrb : 1; /**< Config Tx Compliance Receive Bit 4331 When set to 1, signals LTSSM to transmit TS ordered sets 4332 with the compliance receive bit assert (equal to 1). */ 4333 uint32_t cpyts : 1; /**< Config PHY Tx Swing 4334 Indicates the voltage level the PHY should drive. When set to 4335 1, indicates Full Swing. When set to 0, indicates Low Swing */ 4336 uint32_t dsc : 1; /**< Directed Speed Change 4337 Indicates to the LTSSM whether or not to initiate a speed 4338 change. */ 4339 uint32_t le : 9; /**< Lane Enable 4340 Indicates the number of lanes to check for exit from electrical 4341 idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2, 4342 etc. Used to limit the maximum link width to ignore broken 4343 lanes that detect a receiver, but will not exit electrical 4344 idle and 4345 would otherwise prevent a valid link from being configured. */ 4346 uint32_t n_fts : 8; /**< N_FTS 4347 Sets the Number of Fast Training Sequences (N_FTS) that 4348 the core advertises as its N_FTS during GEN2 Link training. 4349 This value is used to inform the Link partner about the PHYs 4350 ability to recover synchronization after a low power state. 4351 Note: Do not set N_FTS to zero; doing so can cause the 4352 LTSSM to go into the recovery state when exiting from 4353 L0s. */ 4354#else 4355 uint32_t n_fts : 8; 4356 uint32_t le : 9; 4357 uint32_t dsc : 1; 4358 uint32_t cpyts : 1; 4359 uint32_t ctcrb : 1; 4360 uint32_t s_d_e : 1; 4361 uint32_t reserved_21_31 : 11; 4362#endif 4363 } s; 4364 struct cvmx_pcieepx_cfg515_s cn63xx; 4365 struct cvmx_pcieepx_cfg515_s cn63xxp1; 4366}; 4367typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t; 4368 4369/** 4370 * cvmx_pcieep#_cfg516 4371 * 4372 * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 0 config space 4373 * (PHY Status Register) 4374 */ 4375union cvmx_pcieepx_cfg516 4376{ 4377 uint32_t u32; 4378 struct cvmx_pcieepx_cfg516_s 4379 { 4380#if __BYTE_ORDER == __BIG_ENDIAN 4381 uint32_t phy_stat : 32; /**< PHY Status */ 4382#else 4383 uint32_t phy_stat : 32; 4384#endif 4385 } s; 4386 struct cvmx_pcieepx_cfg516_s cn52xx; 4387 struct cvmx_pcieepx_cfg516_s cn52xxp1; 4388 struct cvmx_pcieepx_cfg516_s cn56xx; 4389 struct cvmx_pcieepx_cfg516_s cn56xxp1; 4390 struct cvmx_pcieepx_cfg516_s cn63xx; 4391 struct cvmx_pcieepx_cfg516_s cn63xxp1; 4392}; 4393typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t; 4394 4395/** 4396 * cvmx_pcieep#_cfg517 4397 * 4398 * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 0 config space 4399 * (PHY Control Register) 4400 */ 4401union cvmx_pcieepx_cfg517 4402{ 4403 uint32_t u32; 4404 struct cvmx_pcieepx_cfg517_s 4405 { 4406#if __BYTE_ORDER == __BIG_ENDIAN 4407 uint32_t phy_ctrl : 32; /**< PHY Control */ 4408#else 4409 uint32_t phy_ctrl : 32; 4410#endif 4411 } s; 4412 struct cvmx_pcieepx_cfg517_s cn52xx; 4413 struct cvmx_pcieepx_cfg517_s cn52xxp1; 4414 struct cvmx_pcieepx_cfg517_s cn56xx; 4415 struct cvmx_pcieepx_cfg517_s cn56xxp1; 4416 struct cvmx_pcieepx_cfg517_s cn63xx; 4417 struct cvmx_pcieepx_cfg517_s cn63xxp1; 4418}; 4419typedef union cvmx_pcieepx_cfg517 cvmx_pcieepx_cfg517_t; 4420 4421#endif 4422