1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pcieepx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pcieepx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PCIEEPX_DEFS_H__ 53232812Sjmallett#define __CVMX_PCIEEPX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 64232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 65232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 66215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG000(%lu) is invalid on this chip\n", block_id); 67215976Sjmallett return 0x0000000000000000ull; 68215976Sjmallett} 69215976Sjmallett#else 70215976Sjmallett#define CVMX_PCIEEPX_CFG000(block_id) (0x0000000000000000ull) 71215976Sjmallett#endif 72215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 73215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG001(unsigned long block_id) 74215976Sjmallett{ 75215976Sjmallett if (!( 76215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 77215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 78232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 79232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 80232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 81232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 82232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 83215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG001(%lu) is invalid on this chip\n", block_id); 84215976Sjmallett return 0x0000000000000004ull; 85215976Sjmallett} 86215976Sjmallett#else 87215976Sjmallett#define CVMX_PCIEEPX_CFG001(block_id) (0x0000000000000004ull) 88215976Sjmallett#endif 89215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 90215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG002(unsigned long block_id) 91215976Sjmallett{ 92215976Sjmallett if (!( 93215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 94215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 95232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 96232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 97232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 98232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 99232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 100215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG002(%lu) is invalid on this chip\n", block_id); 101215976Sjmallett return 0x0000000000000008ull; 102215976Sjmallett} 103215976Sjmallett#else 104215976Sjmallett#define CVMX_PCIEEPX_CFG002(block_id) (0x0000000000000008ull) 105215976Sjmallett#endif 106215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 107215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG003(unsigned long block_id) 108215976Sjmallett{ 109215976Sjmallett if (!( 110215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 111215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 112232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 113232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 114232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 115232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 116232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 117215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG003(%lu) is invalid on this chip\n", block_id); 118215976Sjmallett return 0x000000000000000Cull; 119215976Sjmallett} 120215976Sjmallett#else 121215976Sjmallett#define CVMX_PCIEEPX_CFG003(block_id) (0x000000000000000Cull) 122215976Sjmallett#endif 123215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG004(unsigned long block_id) 125215976Sjmallett{ 126215976Sjmallett if (!( 127215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 128215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 129232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 130232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 131232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 132232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 133232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 134215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG004(%lu) is invalid on this chip\n", block_id); 135215976Sjmallett return 0x0000000000000010ull; 136215976Sjmallett} 137215976Sjmallett#else 138215976Sjmallett#define CVMX_PCIEEPX_CFG004(block_id) (0x0000000000000010ull) 139215976Sjmallett#endif 140215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 141215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG004_MASK(unsigned long block_id) 142215976Sjmallett{ 143215976Sjmallett if (!( 144215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 145215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 146232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 147232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 148232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 149232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 150232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 151215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG004_MASK(%lu) is invalid on this chip\n", block_id); 152215976Sjmallett return 0x0000000080000010ull; 153215976Sjmallett} 154215976Sjmallett#else 155215976Sjmallett#define CVMX_PCIEEPX_CFG004_MASK(block_id) (0x0000000080000010ull) 156215976Sjmallett#endif 157215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 158215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG005(unsigned long block_id) 159215976Sjmallett{ 160215976Sjmallett if (!( 161215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 162215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 163232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 164232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 165232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 168215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG005(%lu) is invalid on this chip\n", block_id); 169215976Sjmallett return 0x0000000000000014ull; 170215976Sjmallett} 171215976Sjmallett#else 172215976Sjmallett#define CVMX_PCIEEPX_CFG005(block_id) (0x0000000000000014ull) 173215976Sjmallett#endif 174215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG005_MASK(unsigned long block_id) 176215976Sjmallett{ 177215976Sjmallett if (!( 178215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 180232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 181232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 182232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 183232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 184232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 185215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG005_MASK(%lu) is invalid on this chip\n", block_id); 186215976Sjmallett return 0x0000000080000014ull; 187215976Sjmallett} 188215976Sjmallett#else 189215976Sjmallett#define CVMX_PCIEEPX_CFG005_MASK(block_id) (0x0000000080000014ull) 190215976Sjmallett#endif 191215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG006(unsigned long block_id) 193215976Sjmallett{ 194215976Sjmallett if (!( 195215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 196215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 197232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 198232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 199232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 200232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 201232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 202215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG006(%lu) is invalid on this chip\n", block_id); 203215976Sjmallett return 0x0000000000000018ull; 204215976Sjmallett} 205215976Sjmallett#else 206215976Sjmallett#define CVMX_PCIEEPX_CFG006(block_id) (0x0000000000000018ull) 207215976Sjmallett#endif 208215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 209215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG006_MASK(unsigned long block_id) 210215976Sjmallett{ 211215976Sjmallett if (!( 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 214232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 215232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 216232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 217232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 218232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 219215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG006_MASK(%lu) is invalid on this chip\n", block_id); 220215976Sjmallett return 0x0000000080000018ull; 221215976Sjmallett} 222215976Sjmallett#else 223215976Sjmallett#define CVMX_PCIEEPX_CFG006_MASK(block_id) (0x0000000080000018ull) 224215976Sjmallett#endif 225215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 226215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG007(unsigned long block_id) 227215976Sjmallett{ 228215976Sjmallett if (!( 229215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 230215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 231232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 232232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 233232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 234232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 235232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 236215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG007(%lu) is invalid on this chip\n", block_id); 237215976Sjmallett return 0x000000000000001Cull; 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_PCIEEPX_CFG007(block_id) (0x000000000000001Cull) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG007_MASK(unsigned long block_id) 244215976Sjmallett{ 245215976Sjmallett if (!( 246215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 247215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 248232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 249232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 250232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 253215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG007_MASK(%lu) is invalid on this chip\n", block_id); 254215976Sjmallett return 0x000000008000001Cull; 255215976Sjmallett} 256215976Sjmallett#else 257215976Sjmallett#define CVMX_PCIEEPX_CFG007_MASK(block_id) (0x000000008000001Cull) 258215976Sjmallett#endif 259215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG008(unsigned long block_id) 261215976Sjmallett{ 262215976Sjmallett if (!( 263215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 264215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 265232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 266232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 267232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 268232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 270215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG008(%lu) is invalid on this chip\n", block_id); 271215976Sjmallett return 0x0000000000000020ull; 272215976Sjmallett} 273215976Sjmallett#else 274215976Sjmallett#define CVMX_PCIEEPX_CFG008(block_id) (0x0000000000000020ull) 275215976Sjmallett#endif 276215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG008_MASK(unsigned long block_id) 278215976Sjmallett{ 279215976Sjmallett if (!( 280215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 281215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 282232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 283232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 284232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 285232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 287215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG008_MASK(%lu) is invalid on this chip\n", block_id); 288215976Sjmallett return 0x0000000080000020ull; 289215976Sjmallett} 290215976Sjmallett#else 291215976Sjmallett#define CVMX_PCIEEPX_CFG008_MASK(block_id) (0x0000000080000020ull) 292215976Sjmallett#endif 293215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 294215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG009(unsigned long block_id) 295215976Sjmallett{ 296215976Sjmallett if (!( 297215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 298215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 300232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 301232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 302232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 303232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 304215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG009(%lu) is invalid on this chip\n", block_id); 305215976Sjmallett return 0x0000000000000024ull; 306215976Sjmallett} 307215976Sjmallett#else 308215976Sjmallett#define CVMX_PCIEEPX_CFG009(block_id) (0x0000000000000024ull) 309215976Sjmallett#endif 310215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG009_MASK(unsigned long block_id) 312215976Sjmallett{ 313215976Sjmallett if (!( 314215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 315215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 317232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 318232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 319232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 320232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 321215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG009_MASK(%lu) is invalid on this chip\n", block_id); 322215976Sjmallett return 0x0000000080000024ull; 323215976Sjmallett} 324215976Sjmallett#else 325215976Sjmallett#define CVMX_PCIEEPX_CFG009_MASK(block_id) (0x0000000080000024ull) 326215976Sjmallett#endif 327215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 328215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG010(unsigned long block_id) 329215976Sjmallett{ 330215976Sjmallett if (!( 331215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 333232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 334232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 336232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 337232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 338215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG010(%lu) is invalid on this chip\n", block_id); 339215976Sjmallett return 0x0000000000000028ull; 340215976Sjmallett} 341215976Sjmallett#else 342215976Sjmallett#define CVMX_PCIEEPX_CFG010(block_id) (0x0000000000000028ull) 343215976Sjmallett#endif 344215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 345215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG011(unsigned long block_id) 346215976Sjmallett{ 347215976Sjmallett if (!( 348215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 349215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 350232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 351232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 352232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 353232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 354232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 355215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG011(%lu) is invalid on this chip\n", block_id); 356215976Sjmallett return 0x000000000000002Cull; 357215976Sjmallett} 358215976Sjmallett#else 359215976Sjmallett#define CVMX_PCIEEPX_CFG011(block_id) (0x000000000000002Cull) 360215976Sjmallett#endif 361215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 362215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG012(unsigned long block_id) 363215976Sjmallett{ 364215976Sjmallett if (!( 365215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 366215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 367232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 368232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 369232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 370232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 371232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 372215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG012(%lu) is invalid on this chip\n", block_id); 373215976Sjmallett return 0x0000000000000030ull; 374215976Sjmallett} 375215976Sjmallett#else 376215976Sjmallett#define CVMX_PCIEEPX_CFG012(block_id) (0x0000000000000030ull) 377215976Sjmallett#endif 378215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG012_MASK(unsigned long block_id) 380215976Sjmallett{ 381215976Sjmallett if (!( 382215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 383215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 384232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 385232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 386232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 387232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 388232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 389215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG012_MASK(%lu) is invalid on this chip\n", block_id); 390215976Sjmallett return 0x0000000080000030ull; 391215976Sjmallett} 392215976Sjmallett#else 393215976Sjmallett#define CVMX_PCIEEPX_CFG012_MASK(block_id) (0x0000000080000030ull) 394215976Sjmallett#endif 395215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 396215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG013(unsigned long block_id) 397215976Sjmallett{ 398215976Sjmallett if (!( 399215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 400215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 401232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 402232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 403232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 404232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 405232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 406215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG013(%lu) is invalid on this chip\n", block_id); 407215976Sjmallett return 0x0000000000000034ull; 408215976Sjmallett} 409215976Sjmallett#else 410215976Sjmallett#define CVMX_PCIEEPX_CFG013(block_id) (0x0000000000000034ull) 411215976Sjmallett#endif 412215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 413215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG015(unsigned long block_id) 414215976Sjmallett{ 415215976Sjmallett if (!( 416215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 417215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 418232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 419232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 420232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 421232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 422232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 423215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG015(%lu) is invalid on this chip\n", block_id); 424215976Sjmallett return 0x000000000000003Cull; 425215976Sjmallett} 426215976Sjmallett#else 427215976Sjmallett#define CVMX_PCIEEPX_CFG015(block_id) (0x000000000000003Cull) 428215976Sjmallett#endif 429215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG016(unsigned long block_id) 431215976Sjmallett{ 432215976Sjmallett if (!( 433215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 434215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 435232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 436232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 437232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 438232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 439232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 440215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG016(%lu) is invalid on this chip\n", block_id); 441215976Sjmallett return 0x0000000000000040ull; 442215976Sjmallett} 443215976Sjmallett#else 444215976Sjmallett#define CVMX_PCIEEPX_CFG016(block_id) (0x0000000000000040ull) 445215976Sjmallett#endif 446215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 447215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG017(unsigned long block_id) 448215976Sjmallett{ 449215976Sjmallett if (!( 450215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 451215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 452232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 453232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 454232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 455232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 456232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 457215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG017(%lu) is invalid on this chip\n", block_id); 458215976Sjmallett return 0x0000000000000044ull; 459215976Sjmallett} 460215976Sjmallett#else 461215976Sjmallett#define CVMX_PCIEEPX_CFG017(block_id) (0x0000000000000044ull) 462215976Sjmallett#endif 463215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 464215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG020(unsigned long block_id) 465215976Sjmallett{ 466215976Sjmallett if (!( 467215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 468215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 469232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 470232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 471232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 472232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 473232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 474215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG020(%lu) is invalid on this chip\n", block_id); 475215976Sjmallett return 0x0000000000000050ull; 476215976Sjmallett} 477215976Sjmallett#else 478215976Sjmallett#define CVMX_PCIEEPX_CFG020(block_id) (0x0000000000000050ull) 479215976Sjmallett#endif 480215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 481215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG021(unsigned long block_id) 482215976Sjmallett{ 483215976Sjmallett if (!( 484215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 485215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 486232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 487232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 488232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 489232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 490232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 491215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG021(%lu) is invalid on this chip\n", block_id); 492215976Sjmallett return 0x0000000000000054ull; 493215976Sjmallett} 494215976Sjmallett#else 495215976Sjmallett#define CVMX_PCIEEPX_CFG021(block_id) (0x0000000000000054ull) 496215976Sjmallett#endif 497215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG022(unsigned long block_id) 499215976Sjmallett{ 500215976Sjmallett if (!( 501215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 502215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 503232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 504232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 505232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 506232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 507232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 508215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG022(%lu) is invalid on this chip\n", block_id); 509215976Sjmallett return 0x0000000000000058ull; 510215976Sjmallett} 511215976Sjmallett#else 512215976Sjmallett#define CVMX_PCIEEPX_CFG022(block_id) (0x0000000000000058ull) 513215976Sjmallett#endif 514215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 515215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG023(unsigned long block_id) 516215976Sjmallett{ 517215976Sjmallett if (!( 518215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 519215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 520232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 521232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 522232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 523232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 524232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 525215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG023(%lu) is invalid on this chip\n", block_id); 526215976Sjmallett return 0x000000000000005Cull; 527215976Sjmallett} 528215976Sjmallett#else 529215976Sjmallett#define CVMX_PCIEEPX_CFG023(block_id) (0x000000000000005Cull) 530215976Sjmallett#endif 531215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 532215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG028(unsigned long block_id) 533215976Sjmallett{ 534215976Sjmallett if (!( 535215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 536215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 537232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 538232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 539232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 540232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 541232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 542215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG028(%lu) is invalid on this chip\n", block_id); 543215976Sjmallett return 0x0000000000000070ull; 544215976Sjmallett} 545215976Sjmallett#else 546215976Sjmallett#define CVMX_PCIEEPX_CFG028(block_id) (0x0000000000000070ull) 547215976Sjmallett#endif 548215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 549215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG029(unsigned long block_id) 550215976Sjmallett{ 551215976Sjmallett if (!( 552215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 553215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 554232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 555232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 556232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 557232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 558232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 559215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG029(%lu) is invalid on this chip\n", block_id); 560215976Sjmallett return 0x0000000000000074ull; 561215976Sjmallett} 562215976Sjmallett#else 563215976Sjmallett#define CVMX_PCIEEPX_CFG029(block_id) (0x0000000000000074ull) 564215976Sjmallett#endif 565215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG030(unsigned long block_id) 567215976Sjmallett{ 568215976Sjmallett if (!( 569215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 570215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 571232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 572232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 573232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 574232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 575232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 576215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG030(%lu) is invalid on this chip\n", block_id); 577215976Sjmallett return 0x0000000000000078ull; 578215976Sjmallett} 579215976Sjmallett#else 580215976Sjmallett#define CVMX_PCIEEPX_CFG030(block_id) (0x0000000000000078ull) 581215976Sjmallett#endif 582215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 583215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG031(unsigned long block_id) 584215976Sjmallett{ 585215976Sjmallett if (!( 586215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 587215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 588232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 589232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 590232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 591232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 592232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 593215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG031(%lu) is invalid on this chip\n", block_id); 594215976Sjmallett return 0x000000000000007Cull; 595215976Sjmallett} 596215976Sjmallett#else 597215976Sjmallett#define CVMX_PCIEEPX_CFG031(block_id) (0x000000000000007Cull) 598215976Sjmallett#endif 599215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 600215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG032(unsigned long block_id) 601215976Sjmallett{ 602215976Sjmallett if (!( 603215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 604215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 605232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 606232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 607232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 608232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 609232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 610215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG032(%lu) is invalid on this chip\n", block_id); 611215976Sjmallett return 0x0000000000000080ull; 612215976Sjmallett} 613215976Sjmallett#else 614215976Sjmallett#define CVMX_PCIEEPX_CFG032(block_id) (0x0000000000000080ull) 615215976Sjmallett#endif 616215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG033(unsigned long block_id) 618215976Sjmallett{ 619215976Sjmallett if (!( 620215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 621215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 622215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 623215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG033(%lu) is invalid on this chip\n", block_id); 624215976Sjmallett return 0x0000000000000084ull; 625215976Sjmallett} 626215976Sjmallett#else 627215976Sjmallett#define CVMX_PCIEEPX_CFG033(block_id) (0x0000000000000084ull) 628215976Sjmallett#endif 629215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 630215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG034(unsigned long block_id) 631215976Sjmallett{ 632215976Sjmallett if (!( 633215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 634215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 635215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 636215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG034(%lu) is invalid on this chip\n", block_id); 637215976Sjmallett return 0x0000000000000088ull; 638215976Sjmallett} 639215976Sjmallett#else 640215976Sjmallett#define CVMX_PCIEEPX_CFG034(block_id) (0x0000000000000088ull) 641215976Sjmallett#endif 642215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 643215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG037(unsigned long block_id) 644215976Sjmallett{ 645215976Sjmallett if (!( 646215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 647215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 648232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 649232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 650232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 651232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 652232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 653215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG037(%lu) is invalid on this chip\n", block_id); 654215976Sjmallett return 0x0000000000000094ull; 655215976Sjmallett} 656215976Sjmallett#else 657215976Sjmallett#define CVMX_PCIEEPX_CFG037(block_id) (0x0000000000000094ull) 658215976Sjmallett#endif 659215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 660215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG038(unsigned long block_id) 661215976Sjmallett{ 662215976Sjmallett if (!( 663215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 664215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 665232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 666232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 667232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 668232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 669232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 670215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG038(%lu) is invalid on this chip\n", block_id); 671215976Sjmallett return 0x0000000000000098ull; 672215976Sjmallett} 673215976Sjmallett#else 674215976Sjmallett#define CVMX_PCIEEPX_CFG038(block_id) (0x0000000000000098ull) 675215976Sjmallett#endif 676215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 677215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG039(unsigned long block_id) 678215976Sjmallett{ 679215976Sjmallett if (!( 680215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 681215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 682232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 683232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 684232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 685232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 686232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 687215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG039(%lu) is invalid on this chip\n", block_id); 688215976Sjmallett return 0x000000000000009Cull; 689215976Sjmallett} 690215976Sjmallett#else 691215976Sjmallett#define CVMX_PCIEEPX_CFG039(block_id) (0x000000000000009Cull) 692215976Sjmallett#endif 693215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG040(unsigned long block_id) 695215976Sjmallett{ 696215976Sjmallett if (!( 697215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 698215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 699232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 700232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 701232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 702232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 703232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 704215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG040(%lu) is invalid on this chip\n", block_id); 705215976Sjmallett return 0x00000000000000A0ull; 706215976Sjmallett} 707215976Sjmallett#else 708215976Sjmallett#define CVMX_PCIEEPX_CFG040(block_id) (0x00000000000000A0ull) 709215976Sjmallett#endif 710215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 711215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG041(unsigned long block_id) 712215976Sjmallett{ 713215976Sjmallett if (!( 714215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 715215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 716215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 717215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG041(%lu) is invalid on this chip\n", block_id); 718215976Sjmallett return 0x00000000000000A4ull; 719215976Sjmallett} 720215976Sjmallett#else 721215976Sjmallett#define CVMX_PCIEEPX_CFG041(block_id) (0x00000000000000A4ull) 722215976Sjmallett#endif 723215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 724215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG042(unsigned long block_id) 725215976Sjmallett{ 726215976Sjmallett if (!( 727215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 728215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 729215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 730215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG042(%lu) is invalid on this chip\n", block_id); 731215976Sjmallett return 0x00000000000000A8ull; 732215976Sjmallett} 733215976Sjmallett#else 734215976Sjmallett#define CVMX_PCIEEPX_CFG042(block_id) (0x00000000000000A8ull) 735215976Sjmallett#endif 736215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 737215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG064(unsigned long block_id) 738215976Sjmallett{ 739215976Sjmallett if (!( 740215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 741215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 742232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 743232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 744232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 745232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 746232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 747215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG064(%lu) is invalid on this chip\n", block_id); 748215976Sjmallett return 0x0000000000000100ull; 749215976Sjmallett} 750215976Sjmallett#else 751215976Sjmallett#define CVMX_PCIEEPX_CFG064(block_id) (0x0000000000000100ull) 752215976Sjmallett#endif 753215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 754215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG065(unsigned long block_id) 755215976Sjmallett{ 756215976Sjmallett if (!( 757215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 758215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 759232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 760232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 761232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 762232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 763232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 764215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG065(%lu) is invalid on this chip\n", block_id); 765215976Sjmallett return 0x0000000000000104ull; 766215976Sjmallett} 767215976Sjmallett#else 768215976Sjmallett#define CVMX_PCIEEPX_CFG065(block_id) (0x0000000000000104ull) 769215976Sjmallett#endif 770215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG066(unsigned long block_id) 772215976Sjmallett{ 773215976Sjmallett if (!( 774215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 775215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 776232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 777232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 778232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 779232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 780232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 781215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG066(%lu) is invalid on this chip\n", block_id); 782215976Sjmallett return 0x0000000000000108ull; 783215976Sjmallett} 784215976Sjmallett#else 785215976Sjmallett#define CVMX_PCIEEPX_CFG066(block_id) (0x0000000000000108ull) 786215976Sjmallett#endif 787215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 788215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG067(unsigned long block_id) 789215976Sjmallett{ 790215976Sjmallett if (!( 791215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 792215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 793232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 794232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 795232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 796232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 797232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 798215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG067(%lu) is invalid on this chip\n", block_id); 799215976Sjmallett return 0x000000000000010Cull; 800215976Sjmallett} 801215976Sjmallett#else 802215976Sjmallett#define CVMX_PCIEEPX_CFG067(block_id) (0x000000000000010Cull) 803215976Sjmallett#endif 804215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 805215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG068(unsigned long block_id) 806215976Sjmallett{ 807215976Sjmallett if (!( 808215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 809215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 810232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 811232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 812232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 813232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 814232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 815215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG068(%lu) is invalid on this chip\n", block_id); 816215976Sjmallett return 0x0000000000000110ull; 817215976Sjmallett} 818215976Sjmallett#else 819215976Sjmallett#define CVMX_PCIEEPX_CFG068(block_id) (0x0000000000000110ull) 820215976Sjmallett#endif 821215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 822215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG069(unsigned long block_id) 823215976Sjmallett{ 824215976Sjmallett if (!( 825215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 826215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 827232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 828232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 829232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 830232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 831232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 832215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG069(%lu) is invalid on this chip\n", block_id); 833215976Sjmallett return 0x0000000000000114ull; 834215976Sjmallett} 835215976Sjmallett#else 836215976Sjmallett#define CVMX_PCIEEPX_CFG069(block_id) (0x0000000000000114ull) 837215976Sjmallett#endif 838215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 839215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG070(unsigned long block_id) 840215976Sjmallett{ 841215976Sjmallett if (!( 842215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 843215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 844232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 845232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 846232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 847232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 848232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 849215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG070(%lu) is invalid on this chip\n", block_id); 850215976Sjmallett return 0x0000000000000118ull; 851215976Sjmallett} 852215976Sjmallett#else 853215976Sjmallett#define CVMX_PCIEEPX_CFG070(block_id) (0x0000000000000118ull) 854215976Sjmallett#endif 855215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 856215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG071(unsigned long block_id) 857215976Sjmallett{ 858215976Sjmallett if (!( 859215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 860215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 861232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 862232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 863232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 864232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 865232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 866215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG071(%lu) is invalid on this chip\n", block_id); 867215976Sjmallett return 0x000000000000011Cull; 868215976Sjmallett} 869215976Sjmallett#else 870215976Sjmallett#define CVMX_PCIEEPX_CFG071(block_id) (0x000000000000011Cull) 871215976Sjmallett#endif 872215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 873215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG072(unsigned long block_id) 874215976Sjmallett{ 875215976Sjmallett if (!( 876215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 877215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 878232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 879232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 880232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 881232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 882232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 883215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG072(%lu) is invalid on this chip\n", block_id); 884215976Sjmallett return 0x0000000000000120ull; 885215976Sjmallett} 886215976Sjmallett#else 887215976Sjmallett#define CVMX_PCIEEPX_CFG072(block_id) (0x0000000000000120ull) 888215976Sjmallett#endif 889215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 890215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG073(unsigned long block_id) 891215976Sjmallett{ 892215976Sjmallett if (!( 893215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 894215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 895232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 896232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 897232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 898232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 899232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 900215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG073(%lu) is invalid on this chip\n", block_id); 901215976Sjmallett return 0x0000000000000124ull; 902215976Sjmallett} 903215976Sjmallett#else 904215976Sjmallett#define CVMX_PCIEEPX_CFG073(block_id) (0x0000000000000124ull) 905215976Sjmallett#endif 906215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 907215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG074(unsigned long block_id) 908215976Sjmallett{ 909215976Sjmallett if (!( 910215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 911215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 912232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 913232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 914232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 915232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 916232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 917215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG074(%lu) is invalid on this chip\n", block_id); 918215976Sjmallett return 0x0000000000000128ull; 919215976Sjmallett} 920215976Sjmallett#else 921215976Sjmallett#define CVMX_PCIEEPX_CFG074(block_id) (0x0000000000000128ull) 922215976Sjmallett#endif 923215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 924215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG448(unsigned long block_id) 925215976Sjmallett{ 926215976Sjmallett if (!( 927215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 928215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 929232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 930232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 931232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 932232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 933232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 934215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG448(%lu) is invalid on this chip\n", block_id); 935215976Sjmallett return 0x0000000000000700ull; 936215976Sjmallett} 937215976Sjmallett#else 938215976Sjmallett#define CVMX_PCIEEPX_CFG448(block_id) (0x0000000000000700ull) 939215976Sjmallett#endif 940215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 941215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG449(unsigned long block_id) 942215976Sjmallett{ 943215976Sjmallett if (!( 944215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 945215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 946232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 947232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 948232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 949232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 950232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 951215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG449(%lu) is invalid on this chip\n", block_id); 952215976Sjmallett return 0x0000000000000704ull; 953215976Sjmallett} 954215976Sjmallett#else 955215976Sjmallett#define CVMX_PCIEEPX_CFG449(block_id) (0x0000000000000704ull) 956215976Sjmallett#endif 957215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 958215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG450(unsigned long block_id) 959215976Sjmallett{ 960215976Sjmallett if (!( 961215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 962215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 963232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 964232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 965232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 966232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 967232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 968215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG450(%lu) is invalid on this chip\n", block_id); 969215976Sjmallett return 0x0000000000000708ull; 970215976Sjmallett} 971215976Sjmallett#else 972215976Sjmallett#define CVMX_PCIEEPX_CFG450(block_id) (0x0000000000000708ull) 973215976Sjmallett#endif 974215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 975215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG451(unsigned long block_id) 976215976Sjmallett{ 977215976Sjmallett if (!( 978215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 979215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 980232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 981232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 982232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 983232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 984232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 985215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG451(%lu) is invalid on this chip\n", block_id); 986215976Sjmallett return 0x000000000000070Cull; 987215976Sjmallett} 988215976Sjmallett#else 989215976Sjmallett#define CVMX_PCIEEPX_CFG451(block_id) (0x000000000000070Cull) 990215976Sjmallett#endif 991215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 992215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG452(unsigned long block_id) 993215976Sjmallett{ 994215976Sjmallett if (!( 995215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 996215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 997232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 998232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 999232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1000232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1001232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1002215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG452(%lu) is invalid on this chip\n", block_id); 1003215976Sjmallett return 0x0000000000000710ull; 1004215976Sjmallett} 1005215976Sjmallett#else 1006215976Sjmallett#define CVMX_PCIEEPX_CFG452(block_id) (0x0000000000000710ull) 1007215976Sjmallett#endif 1008215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1009215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG453(unsigned long block_id) 1010215976Sjmallett{ 1011215976Sjmallett if (!( 1012215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1013215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1014232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1015232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1016232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1017232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1018232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1019215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG453(%lu) is invalid on this chip\n", block_id); 1020215976Sjmallett return 0x0000000000000714ull; 1021215976Sjmallett} 1022215976Sjmallett#else 1023215976Sjmallett#define CVMX_PCIEEPX_CFG453(block_id) (0x0000000000000714ull) 1024215976Sjmallett#endif 1025215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1026215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG454(unsigned long block_id) 1027215976Sjmallett{ 1028215976Sjmallett if (!( 1029215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1030215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1031232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1032232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1033232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1034232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1035232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1036215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG454(%lu) is invalid on this chip\n", block_id); 1037215976Sjmallett return 0x0000000000000718ull; 1038215976Sjmallett} 1039215976Sjmallett#else 1040215976Sjmallett#define CVMX_PCIEEPX_CFG454(block_id) (0x0000000000000718ull) 1041215976Sjmallett#endif 1042215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1043215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG455(unsigned long block_id) 1044215976Sjmallett{ 1045215976Sjmallett if (!( 1046215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1047215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1048232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1049232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1050232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1051232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1052232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1053215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG455(%lu) is invalid on this chip\n", block_id); 1054215976Sjmallett return 0x000000000000071Cull; 1055215976Sjmallett} 1056215976Sjmallett#else 1057215976Sjmallett#define CVMX_PCIEEPX_CFG455(block_id) (0x000000000000071Cull) 1058215976Sjmallett#endif 1059215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1060215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG456(unsigned long block_id) 1061215976Sjmallett{ 1062215976Sjmallett if (!( 1063215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1064215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1065232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1066232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1067232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1068232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1069232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1070215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG456(%lu) is invalid on this chip\n", block_id); 1071215976Sjmallett return 0x0000000000000720ull; 1072215976Sjmallett} 1073215976Sjmallett#else 1074215976Sjmallett#define CVMX_PCIEEPX_CFG456(block_id) (0x0000000000000720ull) 1075215976Sjmallett#endif 1076215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1077215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG458(unsigned long block_id) 1078215976Sjmallett{ 1079215976Sjmallett if (!( 1080215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1081215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1082232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1083232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1084232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1085232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1086232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1087215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG458(%lu) is invalid on this chip\n", block_id); 1088215976Sjmallett return 0x0000000000000728ull; 1089215976Sjmallett} 1090215976Sjmallett#else 1091215976Sjmallett#define CVMX_PCIEEPX_CFG458(block_id) (0x0000000000000728ull) 1092215976Sjmallett#endif 1093215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1094215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG459(unsigned long block_id) 1095215976Sjmallett{ 1096215976Sjmallett if (!( 1097215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1098215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1099232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1100232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1101232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1102232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1103232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1104215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG459(%lu) is invalid on this chip\n", block_id); 1105215976Sjmallett return 0x000000000000072Cull; 1106215976Sjmallett} 1107215976Sjmallett#else 1108215976Sjmallett#define CVMX_PCIEEPX_CFG459(block_id) (0x000000000000072Cull) 1109215976Sjmallett#endif 1110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1111215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG460(unsigned long block_id) 1112215976Sjmallett{ 1113215976Sjmallett if (!( 1114215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1115215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1116232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1117232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1118232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1119232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1120232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1121215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG460(%lu) is invalid on this chip\n", block_id); 1122215976Sjmallett return 0x0000000000000730ull; 1123215976Sjmallett} 1124215976Sjmallett#else 1125215976Sjmallett#define CVMX_PCIEEPX_CFG460(block_id) (0x0000000000000730ull) 1126215976Sjmallett#endif 1127215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1128215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG461(unsigned long block_id) 1129215976Sjmallett{ 1130215976Sjmallett if (!( 1131215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1132215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1133232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1134232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1135232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1136232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1137232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1138215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG461(%lu) is invalid on this chip\n", block_id); 1139215976Sjmallett return 0x0000000000000734ull; 1140215976Sjmallett} 1141215976Sjmallett#else 1142215976Sjmallett#define CVMX_PCIEEPX_CFG461(block_id) (0x0000000000000734ull) 1143215976Sjmallett#endif 1144215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1145215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG462(unsigned long block_id) 1146215976Sjmallett{ 1147215976Sjmallett if (!( 1148215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1149215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1150232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1151232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1152232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1153232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1154232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1155215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG462(%lu) is invalid on this chip\n", block_id); 1156215976Sjmallett return 0x0000000000000738ull; 1157215976Sjmallett} 1158215976Sjmallett#else 1159215976Sjmallett#define CVMX_PCIEEPX_CFG462(block_id) (0x0000000000000738ull) 1160215976Sjmallett#endif 1161215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1162215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG463(unsigned long block_id) 1163215976Sjmallett{ 1164215976Sjmallett if (!( 1165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1166215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1169232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1170232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1171232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1172215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG463(%lu) is invalid on this chip\n", block_id); 1173215976Sjmallett return 0x000000000000073Cull; 1174215976Sjmallett} 1175215976Sjmallett#else 1176215976Sjmallett#define CVMX_PCIEEPX_CFG463(block_id) (0x000000000000073Cull) 1177215976Sjmallett#endif 1178215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1179215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG464(unsigned long block_id) 1180215976Sjmallett{ 1181215976Sjmallett if (!( 1182215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1183215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1184232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1185232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1186232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1187232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1188232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1189215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG464(%lu) is invalid on this chip\n", block_id); 1190215976Sjmallett return 0x0000000000000740ull; 1191215976Sjmallett} 1192215976Sjmallett#else 1193215976Sjmallett#define CVMX_PCIEEPX_CFG464(block_id) (0x0000000000000740ull) 1194215976Sjmallett#endif 1195215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1196215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG465(unsigned long block_id) 1197215976Sjmallett{ 1198215976Sjmallett if (!( 1199215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1200215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1201232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1202232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1203232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1204232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1205232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1206215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG465(%lu) is invalid on this chip\n", block_id); 1207215976Sjmallett return 0x0000000000000744ull; 1208215976Sjmallett} 1209215976Sjmallett#else 1210215976Sjmallett#define CVMX_PCIEEPX_CFG465(block_id) (0x0000000000000744ull) 1211215976Sjmallett#endif 1212215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1213215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG466(unsigned long block_id) 1214215976Sjmallett{ 1215215976Sjmallett if (!( 1216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1217215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1218232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1219232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1220232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1221232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1222232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1223215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG466(%lu) is invalid on this chip\n", block_id); 1224215976Sjmallett return 0x0000000000000748ull; 1225215976Sjmallett} 1226215976Sjmallett#else 1227215976Sjmallett#define CVMX_PCIEEPX_CFG466(block_id) (0x0000000000000748ull) 1228215976Sjmallett#endif 1229215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1230215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG467(unsigned long block_id) 1231215976Sjmallett{ 1232215976Sjmallett if (!( 1233215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1234215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1235232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1236232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1237232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1238232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1239232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1240215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG467(%lu) is invalid on this chip\n", block_id); 1241215976Sjmallett return 0x000000000000074Cull; 1242215976Sjmallett} 1243215976Sjmallett#else 1244215976Sjmallett#define CVMX_PCIEEPX_CFG467(block_id) (0x000000000000074Cull) 1245215976Sjmallett#endif 1246215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1247215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG468(unsigned long block_id) 1248215976Sjmallett{ 1249215976Sjmallett if (!( 1250215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1251215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1253232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1254232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1255232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1256232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1257215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG468(%lu) is invalid on this chip\n", block_id); 1258215976Sjmallett return 0x0000000000000750ull; 1259215976Sjmallett} 1260215976Sjmallett#else 1261215976Sjmallett#define CVMX_PCIEEPX_CFG468(block_id) (0x0000000000000750ull) 1262215976Sjmallett#endif 1263215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1264215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG490(unsigned long block_id) 1265215976Sjmallett{ 1266215976Sjmallett if (!( 1267215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1268215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1270232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1271232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1272232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1273232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1274215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG490(%lu) is invalid on this chip\n", block_id); 1275215976Sjmallett return 0x00000000000007A8ull; 1276215976Sjmallett} 1277215976Sjmallett#else 1278215976Sjmallett#define CVMX_PCIEEPX_CFG490(block_id) (0x00000000000007A8ull) 1279215976Sjmallett#endif 1280215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1281215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG491(unsigned long block_id) 1282215976Sjmallett{ 1283215976Sjmallett if (!( 1284215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1285215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1287232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1288232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1289232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1290232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1291215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG491(%lu) is invalid on this chip\n", block_id); 1292215976Sjmallett return 0x00000000000007ACull; 1293215976Sjmallett} 1294215976Sjmallett#else 1295215976Sjmallett#define CVMX_PCIEEPX_CFG491(block_id) (0x00000000000007ACull) 1296215976Sjmallett#endif 1297215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1298215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG492(unsigned long block_id) 1299215976Sjmallett{ 1300215976Sjmallett if (!( 1301215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1302215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1303232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1304232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1305232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1306232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1307232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1308215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG492(%lu) is invalid on this chip\n", block_id); 1309215976Sjmallett return 0x00000000000007B0ull; 1310215976Sjmallett} 1311215976Sjmallett#else 1312215976Sjmallett#define CVMX_PCIEEPX_CFG492(block_id) (0x00000000000007B0ull) 1313215976Sjmallett#endif 1314215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1315215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG515(unsigned long block_id) 1316215976Sjmallett{ 1317215976Sjmallett if (!( 1318232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1319232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1320232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1321232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1322232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1323215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG515(%lu) is invalid on this chip\n", block_id); 1324215976Sjmallett return 0x000000000000080Cull; 1325215976Sjmallett} 1326215976Sjmallett#else 1327215976Sjmallett#define CVMX_PCIEEPX_CFG515(block_id) (0x000000000000080Cull) 1328215976Sjmallett#endif 1329215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1330215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG516(unsigned long block_id) 1331215976Sjmallett{ 1332215976Sjmallett if (!( 1333215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1334215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1336232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1337232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1338232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1339232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1340215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG516(%lu) is invalid on this chip\n", block_id); 1341215976Sjmallett return 0x0000000000000810ull; 1342215976Sjmallett} 1343215976Sjmallett#else 1344215976Sjmallett#define CVMX_PCIEEPX_CFG516(block_id) (0x0000000000000810ull) 1345215976Sjmallett#endif 1346215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1347215976Sjmallettstatic inline uint64_t CVMX_PCIEEPX_CFG517(unsigned long block_id) 1348215976Sjmallett{ 1349215976Sjmallett if (!( 1350215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 1351215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 1352232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1353232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1354232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1355232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1356232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1357215976Sjmallett cvmx_warn("CVMX_PCIEEPX_CFG517(%lu) is invalid on this chip\n", block_id); 1358215976Sjmallett return 0x0000000000000814ull; 1359215976Sjmallett} 1360215976Sjmallett#else 1361215976Sjmallett#define CVMX_PCIEEPX_CFG517(block_id) (0x0000000000000814ull) 1362215976Sjmallett#endif 1363215976Sjmallett 1364215976Sjmallett/** 1365215976Sjmallett * cvmx_pcieep#_cfg000 1366215976Sjmallett * 1367215976Sjmallett * PCIE_CFG000 = First 32-bits of PCIE type 0 config space (Device ID and Vendor ID Register) 1368215976Sjmallett * 1369215976Sjmallett */ 1370232812Sjmallettunion cvmx_pcieepx_cfg000 { 1371215976Sjmallett uint32_t u32; 1372232812Sjmallett struct cvmx_pcieepx_cfg000_s { 1373232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1374215976Sjmallett uint32_t devid : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR 1375215976Sjmallett However, the application must not change this field. 1376215976Sjmallett For EEPROM loads also see VENDID of this register. */ 1377215976Sjmallett uint32_t vendid : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR 1378215976Sjmallett However, the application must not change this field. 1379215976Sjmallett During and EPROM Load is a value of 0xFFFF is loaded to this 1380215976Sjmallett field and a value of 0xFFFF is loaded to the DEVID field of 1381215976Sjmallett this register, the value will not be loaded, EEPROM load will 1382215976Sjmallett stop, and the FastLinkEnable bit will be set in the 1383215976Sjmallett PCIE_CFG452 register. */ 1384215976Sjmallett#else 1385215976Sjmallett uint32_t vendid : 16; 1386215976Sjmallett uint32_t devid : 16; 1387215976Sjmallett#endif 1388215976Sjmallett } s; 1389215976Sjmallett struct cvmx_pcieepx_cfg000_s cn52xx; 1390215976Sjmallett struct cvmx_pcieepx_cfg000_s cn52xxp1; 1391215976Sjmallett struct cvmx_pcieepx_cfg000_s cn56xx; 1392215976Sjmallett struct cvmx_pcieepx_cfg000_s cn56xxp1; 1393232812Sjmallett struct cvmx_pcieepx_cfg000_s cn61xx; 1394215976Sjmallett struct cvmx_pcieepx_cfg000_s cn63xx; 1395215976Sjmallett struct cvmx_pcieepx_cfg000_s cn63xxp1; 1396232812Sjmallett struct cvmx_pcieepx_cfg000_s cn66xx; 1397232812Sjmallett struct cvmx_pcieepx_cfg000_s cn68xx; 1398232812Sjmallett struct cvmx_pcieepx_cfg000_s cn68xxp1; 1399232812Sjmallett struct cvmx_pcieepx_cfg000_s cnf71xx; 1400215976Sjmallett}; 1401215976Sjmalletttypedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t; 1402215976Sjmallett 1403215976Sjmallett/** 1404215976Sjmallett * cvmx_pcieep#_cfg001 1405215976Sjmallett * 1406215976Sjmallett * PCIE_CFG001 = Second 32-bits of PCIE type 0 config space (Command/Status Register) 1407215976Sjmallett * 1408215976Sjmallett */ 1409232812Sjmallettunion cvmx_pcieepx_cfg001 { 1410215976Sjmallett uint32_t u32; 1411232812Sjmallett struct cvmx_pcieepx_cfg001_s { 1412232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1413215976Sjmallett uint32_t dpe : 1; /**< Detected Parity Error */ 1414215976Sjmallett uint32_t sse : 1; /**< Signaled System Error */ 1415215976Sjmallett uint32_t rma : 1; /**< Received Master Abort */ 1416215976Sjmallett uint32_t rta : 1; /**< Received Target Abort */ 1417215976Sjmallett uint32_t sta : 1; /**< Signaled Target Abort */ 1418215976Sjmallett uint32_t devt : 2; /**< DEVSEL Timing 1419215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1420215976Sjmallett uint32_t mdpe : 1; /**< Master Data Parity Error */ 1421215976Sjmallett uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1422215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1423215976Sjmallett uint32_t reserved_22_22 : 1; 1424215976Sjmallett uint32_t m66 : 1; /**< 66 MHz Capable 1425215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1426215976Sjmallett uint32_t cl : 1; /**< Capabilities List 1427215976Sjmallett Indicates presence of an extended capability item. 1428215976Sjmallett Hardwired to 1. */ 1429215976Sjmallett uint32_t i_stat : 1; /**< INTx Status */ 1430215976Sjmallett uint32_t reserved_11_18 : 8; 1431215976Sjmallett uint32_t i_dis : 1; /**< INTx Assertion Disable */ 1432215976Sjmallett uint32_t fbbe : 1; /**< Fast Back-to-Back Enable 1433215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1434215976Sjmallett uint32_t see : 1; /**< SERR# Enable */ 1435215976Sjmallett uint32_t ids_wcc : 1; /**< IDSEL Stepping/Wait Cycle Control 1436215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0 */ 1437215976Sjmallett uint32_t per : 1; /**< Parity Error Response */ 1438215976Sjmallett uint32_t vps : 1; /**< VGA Palette Snoop 1439215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1440215976Sjmallett uint32_t mwice : 1; /**< Memory Write and Invalidate 1441215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1442215976Sjmallett uint32_t scse : 1; /**< Special Cycle Enable 1443215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1444215976Sjmallett uint32_t me : 1; /**< Bus Master Enable */ 1445215976Sjmallett uint32_t msae : 1; /**< Memory Space Enable */ 1446215976Sjmallett uint32_t isae : 1; /**< I/O Space Enable */ 1447215976Sjmallett#else 1448215976Sjmallett uint32_t isae : 1; 1449215976Sjmallett uint32_t msae : 1; 1450215976Sjmallett uint32_t me : 1; 1451215976Sjmallett uint32_t scse : 1; 1452215976Sjmallett uint32_t mwice : 1; 1453215976Sjmallett uint32_t vps : 1; 1454215976Sjmallett uint32_t per : 1; 1455215976Sjmallett uint32_t ids_wcc : 1; 1456215976Sjmallett uint32_t see : 1; 1457215976Sjmallett uint32_t fbbe : 1; 1458215976Sjmallett uint32_t i_dis : 1; 1459215976Sjmallett uint32_t reserved_11_18 : 8; 1460215976Sjmallett uint32_t i_stat : 1; 1461215976Sjmallett uint32_t cl : 1; 1462215976Sjmallett uint32_t m66 : 1; 1463215976Sjmallett uint32_t reserved_22_22 : 1; 1464215976Sjmallett uint32_t fbb : 1; 1465215976Sjmallett uint32_t mdpe : 1; 1466215976Sjmallett uint32_t devt : 2; 1467215976Sjmallett uint32_t sta : 1; 1468215976Sjmallett uint32_t rta : 1; 1469215976Sjmallett uint32_t rma : 1; 1470215976Sjmallett uint32_t sse : 1; 1471215976Sjmallett uint32_t dpe : 1; 1472215976Sjmallett#endif 1473215976Sjmallett } s; 1474215976Sjmallett struct cvmx_pcieepx_cfg001_s cn52xx; 1475215976Sjmallett struct cvmx_pcieepx_cfg001_s cn52xxp1; 1476215976Sjmallett struct cvmx_pcieepx_cfg001_s cn56xx; 1477215976Sjmallett struct cvmx_pcieepx_cfg001_s cn56xxp1; 1478232812Sjmallett struct cvmx_pcieepx_cfg001_s cn61xx; 1479215976Sjmallett struct cvmx_pcieepx_cfg001_s cn63xx; 1480215976Sjmallett struct cvmx_pcieepx_cfg001_s cn63xxp1; 1481232812Sjmallett struct cvmx_pcieepx_cfg001_s cn66xx; 1482232812Sjmallett struct cvmx_pcieepx_cfg001_s cn68xx; 1483232812Sjmallett struct cvmx_pcieepx_cfg001_s cn68xxp1; 1484232812Sjmallett struct cvmx_pcieepx_cfg001_s cnf71xx; 1485215976Sjmallett}; 1486215976Sjmalletttypedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t; 1487215976Sjmallett 1488215976Sjmallett/** 1489215976Sjmallett * cvmx_pcieep#_cfg002 1490215976Sjmallett * 1491215976Sjmallett * PCIE_CFG002 = Third 32-bits of PCIE type 0 config space (Revision ID/Class Code Register) 1492215976Sjmallett * 1493215976Sjmallett */ 1494232812Sjmallettunion cvmx_pcieepx_cfg002 { 1495215976Sjmallett uint32_t u32; 1496232812Sjmallett struct cvmx_pcieepx_cfg002_s { 1497232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1498215976Sjmallett uint32_t bcc : 8; /**< Base Class Code, writable through PEM(0..1)_CFG_WR 1499215976Sjmallett However, the application must not change this field. */ 1500215976Sjmallett uint32_t sc : 8; /**< Subclass Code, writable through PEM(0..1)_CFG_WR 1501215976Sjmallett However, the application must not change this field. */ 1502215976Sjmallett uint32_t pi : 8; /**< Programming Interface, writable through PEM(0..1)_CFG_WR 1503215976Sjmallett However, the application must not change this field. */ 1504215976Sjmallett uint32_t rid : 8; /**< Revision ID, writable through PEM(0..1)_CFG_WR 1505215976Sjmallett However, the application must not change this field. */ 1506215976Sjmallett#else 1507215976Sjmallett uint32_t rid : 8; 1508215976Sjmallett uint32_t pi : 8; 1509215976Sjmallett uint32_t sc : 8; 1510215976Sjmallett uint32_t bcc : 8; 1511215976Sjmallett#endif 1512215976Sjmallett } s; 1513215976Sjmallett struct cvmx_pcieepx_cfg002_s cn52xx; 1514215976Sjmallett struct cvmx_pcieepx_cfg002_s cn52xxp1; 1515215976Sjmallett struct cvmx_pcieepx_cfg002_s cn56xx; 1516215976Sjmallett struct cvmx_pcieepx_cfg002_s cn56xxp1; 1517232812Sjmallett struct cvmx_pcieepx_cfg002_s cn61xx; 1518215976Sjmallett struct cvmx_pcieepx_cfg002_s cn63xx; 1519215976Sjmallett struct cvmx_pcieepx_cfg002_s cn63xxp1; 1520232812Sjmallett struct cvmx_pcieepx_cfg002_s cn66xx; 1521232812Sjmallett struct cvmx_pcieepx_cfg002_s cn68xx; 1522232812Sjmallett struct cvmx_pcieepx_cfg002_s cn68xxp1; 1523232812Sjmallett struct cvmx_pcieepx_cfg002_s cnf71xx; 1524215976Sjmallett}; 1525215976Sjmalletttypedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t; 1526215976Sjmallett 1527215976Sjmallett/** 1528215976Sjmallett * cvmx_pcieep#_cfg003 1529215976Sjmallett * 1530215976Sjmallett * PCIE_CFG003 = Fourth 32-bits of PCIE type 0 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register) 1531215976Sjmallett * 1532215976Sjmallett */ 1533232812Sjmallettunion cvmx_pcieepx_cfg003 { 1534215976Sjmallett uint32_t u32; 1535232812Sjmallett struct cvmx_pcieepx_cfg003_s { 1536232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1537215976Sjmallett uint32_t bist : 8; /**< The BIST register functions are not supported. 1538215976Sjmallett All 8 bits of the BIST register are hardwired to 0. */ 1539215976Sjmallett uint32_t mfd : 1; /**< Multi Function Device 1540215976Sjmallett The Multi Function Device bit is writable through PEM(0..1)_CFG_WR. 1541215976Sjmallett However, this is a single function device. Therefore, the 1542215976Sjmallett application must not write a 1 to this bit. */ 1543215976Sjmallett uint32_t chf : 7; /**< Configuration Header Format 1544215976Sjmallett Hardwired to 0 for type 0. */ 1545215976Sjmallett uint32_t lt : 8; /**< Master Latency Timer 1546215976Sjmallett Not applicable for PCI Express, hardwired to 0. */ 1547215976Sjmallett uint32_t cls : 8; /**< Cache Line Size 1548215976Sjmallett The Cache Line Size register is RW for legacy compatibility 1549215976Sjmallett purposes and is not applicable to PCI Express device 1550215976Sjmallett functionality. 1551215976Sjmallett Writing to the Cache Line Size register does not impact 1552215976Sjmallett functionality. */ 1553215976Sjmallett#else 1554215976Sjmallett uint32_t cls : 8; 1555215976Sjmallett uint32_t lt : 8; 1556215976Sjmallett uint32_t chf : 7; 1557215976Sjmallett uint32_t mfd : 1; 1558215976Sjmallett uint32_t bist : 8; 1559215976Sjmallett#endif 1560215976Sjmallett } s; 1561215976Sjmallett struct cvmx_pcieepx_cfg003_s cn52xx; 1562215976Sjmallett struct cvmx_pcieepx_cfg003_s cn52xxp1; 1563215976Sjmallett struct cvmx_pcieepx_cfg003_s cn56xx; 1564215976Sjmallett struct cvmx_pcieepx_cfg003_s cn56xxp1; 1565232812Sjmallett struct cvmx_pcieepx_cfg003_s cn61xx; 1566215976Sjmallett struct cvmx_pcieepx_cfg003_s cn63xx; 1567215976Sjmallett struct cvmx_pcieepx_cfg003_s cn63xxp1; 1568232812Sjmallett struct cvmx_pcieepx_cfg003_s cn66xx; 1569232812Sjmallett struct cvmx_pcieepx_cfg003_s cn68xx; 1570232812Sjmallett struct cvmx_pcieepx_cfg003_s cn68xxp1; 1571232812Sjmallett struct cvmx_pcieepx_cfg003_s cnf71xx; 1572215976Sjmallett}; 1573215976Sjmalletttypedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t; 1574215976Sjmallett 1575215976Sjmallett/** 1576215976Sjmallett * cvmx_pcieep#_cfg004 1577215976Sjmallett * 1578215976Sjmallett * PCIE_CFG004 = Fifth 32-bits of PCIE type 0 config space (Base Address Register 0 - Low) 1579215976Sjmallett * 1580215976Sjmallett */ 1581232812Sjmallettunion cvmx_pcieepx_cfg004 { 1582215976Sjmallett uint32_t u32; 1583232812Sjmallett struct cvmx_pcieepx_cfg004_s { 1584232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1585215976Sjmallett uint32_t lbab : 18; /**< Lower bits of the BAR 0 base address */ 1586215976Sjmallett uint32_t reserved_4_13 : 10; 1587215976Sjmallett uint32_t pf : 1; /**< Prefetchable 1588215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1589215976Sjmallett However, the application must not change this field. */ 1590215976Sjmallett uint32_t typ : 2; /**< BAR type 1591215976Sjmallett o 00 = 32-bit BAR 1592215976Sjmallett o 10 = 64-bit BAR 1593215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1594215976Sjmallett However, the application must not change this field. */ 1595215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator 1596215976Sjmallett o 0 = BAR 0 is a memory BAR 1597215976Sjmallett o 1 = BAR 0 is an I/O BAR 1598215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1599215976Sjmallett However, the application must not change this field. */ 1600215976Sjmallett#else 1601215976Sjmallett uint32_t mspc : 1; 1602215976Sjmallett uint32_t typ : 2; 1603215976Sjmallett uint32_t pf : 1; 1604215976Sjmallett uint32_t reserved_4_13 : 10; 1605215976Sjmallett uint32_t lbab : 18; 1606215976Sjmallett#endif 1607215976Sjmallett } s; 1608215976Sjmallett struct cvmx_pcieepx_cfg004_s cn52xx; 1609215976Sjmallett struct cvmx_pcieepx_cfg004_s cn52xxp1; 1610215976Sjmallett struct cvmx_pcieepx_cfg004_s cn56xx; 1611215976Sjmallett struct cvmx_pcieepx_cfg004_s cn56xxp1; 1612232812Sjmallett struct cvmx_pcieepx_cfg004_s cn61xx; 1613215976Sjmallett struct cvmx_pcieepx_cfg004_s cn63xx; 1614215976Sjmallett struct cvmx_pcieepx_cfg004_s cn63xxp1; 1615232812Sjmallett struct cvmx_pcieepx_cfg004_s cn66xx; 1616232812Sjmallett struct cvmx_pcieepx_cfg004_s cn68xx; 1617232812Sjmallett struct cvmx_pcieepx_cfg004_s cn68xxp1; 1618232812Sjmallett struct cvmx_pcieepx_cfg004_s cnf71xx; 1619215976Sjmallett}; 1620215976Sjmalletttypedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t; 1621215976Sjmallett 1622215976Sjmallett/** 1623215976Sjmallett * cvmx_pcieep#_cfg004_mask 1624215976Sjmallett * 1625215976Sjmallett * PCIE_CFG004_MASK (BAR Mask 0 - Low) 1626215976Sjmallett * The BAR 0 Mask register is invisible to host software and not readable from the application. 1627215976Sjmallett * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR. 1628215976Sjmallett */ 1629232812Sjmallettunion cvmx_pcieepx_cfg004_mask { 1630215976Sjmallett uint32_t u32; 1631232812Sjmallett struct cvmx_pcieepx_cfg004_mask_s { 1632232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1633215976Sjmallett uint32_t lmask : 31; /**< Bar Mask Low */ 1634215976Sjmallett uint32_t enb : 1; /**< Bar Enable 1635215976Sjmallett o 0: BAR 0 is disabled 1636215976Sjmallett o 1: BAR 0 is enabled 1637215976Sjmallett Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1638215976Sjmallett register rather than as a mask bit because bit 0 of a BAR is 1639215976Sjmallett always masked from writing by host software. Bit 0 must be 1640215976Sjmallett written prior to writing the other mask bits. */ 1641215976Sjmallett#else 1642215976Sjmallett uint32_t enb : 1; 1643215976Sjmallett uint32_t lmask : 31; 1644215976Sjmallett#endif 1645215976Sjmallett } s; 1646215976Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn52xx; 1647215976Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn52xxp1; 1648215976Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn56xx; 1649215976Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn56xxp1; 1650232812Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn61xx; 1651215976Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn63xx; 1652215976Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn63xxp1; 1653232812Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn66xx; 1654232812Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn68xx; 1655232812Sjmallett struct cvmx_pcieepx_cfg004_mask_s cn68xxp1; 1656232812Sjmallett struct cvmx_pcieepx_cfg004_mask_s cnf71xx; 1657215976Sjmallett}; 1658215976Sjmalletttypedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t; 1659215976Sjmallett 1660215976Sjmallett/** 1661215976Sjmallett * cvmx_pcieep#_cfg005 1662215976Sjmallett * 1663215976Sjmallett * PCIE_CFG005 = Sixth 32-bits of PCIE type 0 config space (Base Address Register 0 - High) 1664215976Sjmallett * 1665215976Sjmallett */ 1666232812Sjmallettunion cvmx_pcieepx_cfg005 { 1667215976Sjmallett uint32_t u32; 1668232812Sjmallett struct cvmx_pcieepx_cfg005_s { 1669232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1670215976Sjmallett uint32_t ubab : 32; /**< Contains the upper 32 bits of the BAR 0 base address. */ 1671215976Sjmallett#else 1672215976Sjmallett uint32_t ubab : 32; 1673215976Sjmallett#endif 1674215976Sjmallett } s; 1675215976Sjmallett struct cvmx_pcieepx_cfg005_s cn52xx; 1676215976Sjmallett struct cvmx_pcieepx_cfg005_s cn52xxp1; 1677215976Sjmallett struct cvmx_pcieepx_cfg005_s cn56xx; 1678215976Sjmallett struct cvmx_pcieepx_cfg005_s cn56xxp1; 1679232812Sjmallett struct cvmx_pcieepx_cfg005_s cn61xx; 1680215976Sjmallett struct cvmx_pcieepx_cfg005_s cn63xx; 1681215976Sjmallett struct cvmx_pcieepx_cfg005_s cn63xxp1; 1682232812Sjmallett struct cvmx_pcieepx_cfg005_s cn66xx; 1683232812Sjmallett struct cvmx_pcieepx_cfg005_s cn68xx; 1684232812Sjmallett struct cvmx_pcieepx_cfg005_s cn68xxp1; 1685232812Sjmallett struct cvmx_pcieepx_cfg005_s cnf71xx; 1686215976Sjmallett}; 1687215976Sjmalletttypedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t; 1688215976Sjmallett 1689215976Sjmallett/** 1690215976Sjmallett * cvmx_pcieep#_cfg005_mask 1691215976Sjmallett * 1692215976Sjmallett * PCIE_CFG005_MASK = (BAR Mask 0 - High) 1693215976Sjmallett * The BAR 0 Mask register is invisible to host software and not readable from the application. 1694215976Sjmallett * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR. 1695215976Sjmallett */ 1696232812Sjmallettunion cvmx_pcieepx_cfg005_mask { 1697215976Sjmallett uint32_t u32; 1698232812Sjmallett struct cvmx_pcieepx_cfg005_mask_s { 1699232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1700215976Sjmallett uint32_t umask : 32; /**< Bar Mask High */ 1701215976Sjmallett#else 1702215976Sjmallett uint32_t umask : 32; 1703215976Sjmallett#endif 1704215976Sjmallett } s; 1705215976Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn52xx; 1706215976Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn52xxp1; 1707215976Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn56xx; 1708215976Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn56xxp1; 1709232812Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn61xx; 1710215976Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn63xx; 1711215976Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn63xxp1; 1712232812Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn66xx; 1713232812Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn68xx; 1714232812Sjmallett struct cvmx_pcieepx_cfg005_mask_s cn68xxp1; 1715232812Sjmallett struct cvmx_pcieepx_cfg005_mask_s cnf71xx; 1716215976Sjmallett}; 1717215976Sjmalletttypedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t; 1718215976Sjmallett 1719215976Sjmallett/** 1720215976Sjmallett * cvmx_pcieep#_cfg006 1721215976Sjmallett * 1722215976Sjmallett * PCIE_CFG006 = Seventh 32-bits of PCIE type 0 config space (Base Address Register 1 - Low) 1723215976Sjmallett * 1724215976Sjmallett */ 1725232812Sjmallettunion cvmx_pcieepx_cfg006 { 1726215976Sjmallett uint32_t u32; 1727232812Sjmallett struct cvmx_pcieepx_cfg006_s { 1728232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1729215976Sjmallett uint32_t lbab : 6; /**< Lower bits of the BAR 1 base address */ 1730215976Sjmallett uint32_t reserved_4_25 : 22; 1731215976Sjmallett uint32_t pf : 1; /**< Prefetchable 1732215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1733215976Sjmallett However, the application must not change this field. */ 1734215976Sjmallett uint32_t typ : 2; /**< BAR type 1735215976Sjmallett o 00 = 32-bit BAR 1736215976Sjmallett o 10 = 64-bit BAR 1737215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1738215976Sjmallett However, the application must not change this field. */ 1739215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator 1740215976Sjmallett o 0 = BAR 0 is a memory BAR 1741215976Sjmallett o 1 = BAR 0 is an I/O BAR 1742215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1743215976Sjmallett However, the application must not change this field. */ 1744215976Sjmallett#else 1745215976Sjmallett uint32_t mspc : 1; 1746215976Sjmallett uint32_t typ : 2; 1747215976Sjmallett uint32_t pf : 1; 1748215976Sjmallett uint32_t reserved_4_25 : 22; 1749215976Sjmallett uint32_t lbab : 6; 1750215976Sjmallett#endif 1751215976Sjmallett } s; 1752215976Sjmallett struct cvmx_pcieepx_cfg006_s cn52xx; 1753215976Sjmallett struct cvmx_pcieepx_cfg006_s cn52xxp1; 1754215976Sjmallett struct cvmx_pcieepx_cfg006_s cn56xx; 1755215976Sjmallett struct cvmx_pcieepx_cfg006_s cn56xxp1; 1756232812Sjmallett struct cvmx_pcieepx_cfg006_s cn61xx; 1757215976Sjmallett struct cvmx_pcieepx_cfg006_s cn63xx; 1758215976Sjmallett struct cvmx_pcieepx_cfg006_s cn63xxp1; 1759232812Sjmallett struct cvmx_pcieepx_cfg006_s cn66xx; 1760232812Sjmallett struct cvmx_pcieepx_cfg006_s cn68xx; 1761232812Sjmallett struct cvmx_pcieepx_cfg006_s cn68xxp1; 1762232812Sjmallett struct cvmx_pcieepx_cfg006_s cnf71xx; 1763215976Sjmallett}; 1764215976Sjmalletttypedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t; 1765215976Sjmallett 1766215976Sjmallett/** 1767215976Sjmallett * cvmx_pcieep#_cfg006_mask 1768215976Sjmallett * 1769215976Sjmallett * PCIE_CFG006_MASK (BAR Mask 1 - Low) 1770215976Sjmallett * The BAR 1 Mask register is invisible to host software and not readable from the application. 1771215976Sjmallett * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR. 1772215976Sjmallett */ 1773232812Sjmallettunion cvmx_pcieepx_cfg006_mask { 1774215976Sjmallett uint32_t u32; 1775232812Sjmallett struct cvmx_pcieepx_cfg006_mask_s { 1776232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1777215976Sjmallett uint32_t lmask : 31; /**< Bar Mask Low */ 1778215976Sjmallett uint32_t enb : 1; /**< Bar Enable 1779215976Sjmallett o 0: BAR 1 is disabled 1780215976Sjmallett o 1: BAR 1 is enabled 1781215976Sjmallett Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1782215976Sjmallett register rather than as a mask bit because bit 0 of a BAR is 1783215976Sjmallett always masked from writing by host software. Bit 0 must be 1784215976Sjmallett written prior to writing the other mask bits. */ 1785215976Sjmallett#else 1786215976Sjmallett uint32_t enb : 1; 1787215976Sjmallett uint32_t lmask : 31; 1788215976Sjmallett#endif 1789215976Sjmallett } s; 1790215976Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn52xx; 1791215976Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn52xxp1; 1792215976Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn56xx; 1793215976Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn56xxp1; 1794232812Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn61xx; 1795215976Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn63xx; 1796215976Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn63xxp1; 1797232812Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn66xx; 1798232812Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn68xx; 1799232812Sjmallett struct cvmx_pcieepx_cfg006_mask_s cn68xxp1; 1800232812Sjmallett struct cvmx_pcieepx_cfg006_mask_s cnf71xx; 1801215976Sjmallett}; 1802215976Sjmalletttypedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t; 1803215976Sjmallett 1804215976Sjmallett/** 1805215976Sjmallett * cvmx_pcieep#_cfg007 1806215976Sjmallett * 1807215976Sjmallett * PCIE_CFG007 = Eighth 32-bits of PCIE type 0 config space (Base Address Register 1 - High) 1808215976Sjmallett * 1809215976Sjmallett */ 1810232812Sjmallettunion cvmx_pcieepx_cfg007 { 1811215976Sjmallett uint32_t u32; 1812232812Sjmallett struct cvmx_pcieepx_cfg007_s { 1813232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1814215976Sjmallett uint32_t ubab : 32; /**< Contains the upper 32 bits of the BAR 1 base address. */ 1815215976Sjmallett#else 1816215976Sjmallett uint32_t ubab : 32; 1817215976Sjmallett#endif 1818215976Sjmallett } s; 1819215976Sjmallett struct cvmx_pcieepx_cfg007_s cn52xx; 1820215976Sjmallett struct cvmx_pcieepx_cfg007_s cn52xxp1; 1821215976Sjmallett struct cvmx_pcieepx_cfg007_s cn56xx; 1822215976Sjmallett struct cvmx_pcieepx_cfg007_s cn56xxp1; 1823232812Sjmallett struct cvmx_pcieepx_cfg007_s cn61xx; 1824215976Sjmallett struct cvmx_pcieepx_cfg007_s cn63xx; 1825215976Sjmallett struct cvmx_pcieepx_cfg007_s cn63xxp1; 1826232812Sjmallett struct cvmx_pcieepx_cfg007_s cn66xx; 1827232812Sjmallett struct cvmx_pcieepx_cfg007_s cn68xx; 1828232812Sjmallett struct cvmx_pcieepx_cfg007_s cn68xxp1; 1829232812Sjmallett struct cvmx_pcieepx_cfg007_s cnf71xx; 1830215976Sjmallett}; 1831215976Sjmalletttypedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t; 1832215976Sjmallett 1833215976Sjmallett/** 1834215976Sjmallett * cvmx_pcieep#_cfg007_mask 1835215976Sjmallett * 1836215976Sjmallett * PCIE_CFG007_MASK (BAR Mask 1 - High) 1837215976Sjmallett * The BAR 1 Mask register is invisible to host software and not readable from the application. 1838215976Sjmallett * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR. 1839215976Sjmallett */ 1840232812Sjmallettunion cvmx_pcieepx_cfg007_mask { 1841215976Sjmallett uint32_t u32; 1842232812Sjmallett struct cvmx_pcieepx_cfg007_mask_s { 1843232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1844215976Sjmallett uint32_t umask : 32; /**< Bar Mask High */ 1845215976Sjmallett#else 1846215976Sjmallett uint32_t umask : 32; 1847215976Sjmallett#endif 1848215976Sjmallett } s; 1849215976Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn52xx; 1850215976Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn52xxp1; 1851215976Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn56xx; 1852215976Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn56xxp1; 1853232812Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn61xx; 1854215976Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn63xx; 1855215976Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn63xxp1; 1856232812Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn66xx; 1857232812Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn68xx; 1858232812Sjmallett struct cvmx_pcieepx_cfg007_mask_s cn68xxp1; 1859232812Sjmallett struct cvmx_pcieepx_cfg007_mask_s cnf71xx; 1860215976Sjmallett}; 1861215976Sjmalletttypedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t; 1862215976Sjmallett 1863215976Sjmallett/** 1864215976Sjmallett * cvmx_pcieep#_cfg008 1865215976Sjmallett * 1866215976Sjmallett * PCIE_CFG008 = Ninth 32-bits of PCIE type 0 config space (Base Address Register 2 - Low) 1867215976Sjmallett * 1868215976Sjmallett */ 1869232812Sjmallettunion cvmx_pcieepx_cfg008 { 1870215976Sjmallett uint32_t u32; 1871232812Sjmallett struct cvmx_pcieepx_cfg008_s { 1872232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1873215976Sjmallett uint32_t reserved_4_31 : 28; 1874215976Sjmallett uint32_t pf : 1; /**< Prefetchable 1875215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1876215976Sjmallett However, the application must not change this field. */ 1877215976Sjmallett uint32_t typ : 2; /**< BAR type 1878215976Sjmallett o 00 = 32-bit BAR 1879215976Sjmallett o 10 = 64-bit BAR 1880215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1881215976Sjmallett However, the application must not change this field. */ 1882215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator 1883215976Sjmallett o 0 = BAR 0 is a memory BAR 1884215976Sjmallett o 1 = BAR 0 is an I/O BAR 1885215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 1886215976Sjmallett However, the application must not change this field. */ 1887215976Sjmallett#else 1888215976Sjmallett uint32_t mspc : 1; 1889215976Sjmallett uint32_t typ : 2; 1890215976Sjmallett uint32_t pf : 1; 1891215976Sjmallett uint32_t reserved_4_31 : 28; 1892215976Sjmallett#endif 1893215976Sjmallett } s; 1894215976Sjmallett struct cvmx_pcieepx_cfg008_s cn52xx; 1895215976Sjmallett struct cvmx_pcieepx_cfg008_s cn52xxp1; 1896215976Sjmallett struct cvmx_pcieepx_cfg008_s cn56xx; 1897215976Sjmallett struct cvmx_pcieepx_cfg008_s cn56xxp1; 1898232812Sjmallett struct cvmx_pcieepx_cfg008_s cn61xx; 1899215976Sjmallett struct cvmx_pcieepx_cfg008_s cn63xx; 1900215976Sjmallett struct cvmx_pcieepx_cfg008_s cn63xxp1; 1901232812Sjmallett struct cvmx_pcieepx_cfg008_s cn66xx; 1902232812Sjmallett struct cvmx_pcieepx_cfg008_s cn68xx; 1903232812Sjmallett struct cvmx_pcieepx_cfg008_s cn68xxp1; 1904232812Sjmallett struct cvmx_pcieepx_cfg008_s cnf71xx; 1905215976Sjmallett}; 1906215976Sjmalletttypedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t; 1907215976Sjmallett 1908215976Sjmallett/** 1909215976Sjmallett * cvmx_pcieep#_cfg008_mask 1910215976Sjmallett * 1911215976Sjmallett * PCIE_CFG008_MASK (BAR Mask 2 - Low) 1912215976Sjmallett * The BAR 2 Mask register is invisible to host software and not readable from the application. 1913215976Sjmallett * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR. 1914215976Sjmallett */ 1915232812Sjmallettunion cvmx_pcieepx_cfg008_mask { 1916215976Sjmallett uint32_t u32; 1917232812Sjmallett struct cvmx_pcieepx_cfg008_mask_s { 1918232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1919215976Sjmallett uint32_t lmask : 31; /**< Bar Mask Low */ 1920215976Sjmallett uint32_t enb : 1; /**< Bar Enable 1921215976Sjmallett o 0: BAR 2 is disabled 1922215976Sjmallett o 1: BAR 2 is enabled 1923215976Sjmallett Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 1924215976Sjmallett register rather than as a mask bit because bit 0 of a BAR is 1925215976Sjmallett always masked from writing by host software. Bit 0 must be 1926215976Sjmallett written prior to writing the other mask bits. */ 1927215976Sjmallett#else 1928215976Sjmallett uint32_t enb : 1; 1929215976Sjmallett uint32_t lmask : 31; 1930215976Sjmallett#endif 1931215976Sjmallett } s; 1932215976Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn52xx; 1933215976Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn52xxp1; 1934215976Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn56xx; 1935215976Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn56xxp1; 1936232812Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn61xx; 1937215976Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn63xx; 1938215976Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn63xxp1; 1939232812Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn66xx; 1940232812Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn68xx; 1941232812Sjmallett struct cvmx_pcieepx_cfg008_mask_s cn68xxp1; 1942232812Sjmallett struct cvmx_pcieepx_cfg008_mask_s cnf71xx; 1943215976Sjmallett}; 1944215976Sjmalletttypedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t; 1945215976Sjmallett 1946215976Sjmallett/** 1947215976Sjmallett * cvmx_pcieep#_cfg009 1948215976Sjmallett * 1949215976Sjmallett * PCIE_CFG009 = Tenth 32-bits of PCIE type 0 config space (Base Address Register 2 - High) 1950215976Sjmallett * 1951215976Sjmallett */ 1952232812Sjmallettunion cvmx_pcieepx_cfg009 { 1953215976Sjmallett uint32_t u32; 1954232812Sjmallett struct cvmx_pcieepx_cfg009_s { 1955232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1956215976Sjmallett uint32_t reserved_0_31 : 32; 1957215976Sjmallett#else 1958215976Sjmallett uint32_t reserved_0_31 : 32; 1959215976Sjmallett#endif 1960215976Sjmallett } s; 1961232812Sjmallett struct cvmx_pcieepx_cfg009_cn52xx { 1962232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1963215976Sjmallett uint32_t ubab : 25; /**< Contains the upper 32 bits of the BAR 2 base address. */ 1964215976Sjmallett uint32_t reserved_0_6 : 7; 1965215976Sjmallett#else 1966215976Sjmallett uint32_t reserved_0_6 : 7; 1967215976Sjmallett uint32_t ubab : 25; 1968215976Sjmallett#endif 1969215976Sjmallett } cn52xx; 1970215976Sjmallett struct cvmx_pcieepx_cfg009_cn52xx cn52xxp1; 1971215976Sjmallett struct cvmx_pcieepx_cfg009_cn52xx cn56xx; 1972215976Sjmallett struct cvmx_pcieepx_cfg009_cn52xx cn56xxp1; 1973232812Sjmallett struct cvmx_pcieepx_cfg009_cn61xx { 1974232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1975215976Sjmallett uint32_t ubab : 23; /**< Contains the upper 32 bits of the BAR 2 base address. */ 1976215976Sjmallett uint32_t reserved_0_8 : 9; 1977215976Sjmallett#else 1978215976Sjmallett uint32_t reserved_0_8 : 9; 1979215976Sjmallett uint32_t ubab : 23; 1980215976Sjmallett#endif 1981232812Sjmallett } cn61xx; 1982232812Sjmallett struct cvmx_pcieepx_cfg009_cn61xx cn63xx; 1983232812Sjmallett struct cvmx_pcieepx_cfg009_cn61xx cn63xxp1; 1984232812Sjmallett struct cvmx_pcieepx_cfg009_cn61xx cn66xx; 1985232812Sjmallett struct cvmx_pcieepx_cfg009_cn61xx cn68xx; 1986232812Sjmallett struct cvmx_pcieepx_cfg009_cn61xx cn68xxp1; 1987232812Sjmallett struct cvmx_pcieepx_cfg009_cn61xx cnf71xx; 1988215976Sjmallett}; 1989215976Sjmalletttypedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t; 1990215976Sjmallett 1991215976Sjmallett/** 1992215976Sjmallett * cvmx_pcieep#_cfg009_mask 1993215976Sjmallett * 1994215976Sjmallett * PCIE_CFG009_MASK (BAR Mask 2 - High) 1995215976Sjmallett * The BAR 2 Mask register is invisible to host software and not readable from the application. 1996215976Sjmallett * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR. 1997215976Sjmallett */ 1998232812Sjmallettunion cvmx_pcieepx_cfg009_mask { 1999215976Sjmallett uint32_t u32; 2000232812Sjmallett struct cvmx_pcieepx_cfg009_mask_s { 2001232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2002215976Sjmallett uint32_t umask : 32; /**< Bar Mask High */ 2003215976Sjmallett#else 2004215976Sjmallett uint32_t umask : 32; 2005215976Sjmallett#endif 2006215976Sjmallett } s; 2007215976Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn52xx; 2008215976Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn52xxp1; 2009215976Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn56xx; 2010215976Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn56xxp1; 2011232812Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn61xx; 2012215976Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn63xx; 2013215976Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn63xxp1; 2014232812Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn66xx; 2015232812Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn68xx; 2016232812Sjmallett struct cvmx_pcieepx_cfg009_mask_s cn68xxp1; 2017232812Sjmallett struct cvmx_pcieepx_cfg009_mask_s cnf71xx; 2018215976Sjmallett}; 2019215976Sjmalletttypedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t; 2020215976Sjmallett 2021215976Sjmallett/** 2022215976Sjmallett * cvmx_pcieep#_cfg010 2023215976Sjmallett * 2024215976Sjmallett * PCIE_CFG010 = Eleventh 32-bits of PCIE type 0 config space (CardBus CIS Pointer Register) 2025215976Sjmallett * 2026215976Sjmallett */ 2027232812Sjmallettunion cvmx_pcieepx_cfg010 { 2028215976Sjmallett uint32_t u32; 2029232812Sjmallett struct cvmx_pcieepx_cfg010_s { 2030232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2031215976Sjmallett uint32_t cisp : 32; /**< CardBus CIS Pointer 2032215976Sjmallett Optional, writable through PEM(0..1)_CFG_WR. */ 2033215976Sjmallett#else 2034215976Sjmallett uint32_t cisp : 32; 2035215976Sjmallett#endif 2036215976Sjmallett } s; 2037215976Sjmallett struct cvmx_pcieepx_cfg010_s cn52xx; 2038215976Sjmallett struct cvmx_pcieepx_cfg010_s cn52xxp1; 2039215976Sjmallett struct cvmx_pcieepx_cfg010_s cn56xx; 2040215976Sjmallett struct cvmx_pcieepx_cfg010_s cn56xxp1; 2041232812Sjmallett struct cvmx_pcieepx_cfg010_s cn61xx; 2042215976Sjmallett struct cvmx_pcieepx_cfg010_s cn63xx; 2043215976Sjmallett struct cvmx_pcieepx_cfg010_s cn63xxp1; 2044232812Sjmallett struct cvmx_pcieepx_cfg010_s cn66xx; 2045232812Sjmallett struct cvmx_pcieepx_cfg010_s cn68xx; 2046232812Sjmallett struct cvmx_pcieepx_cfg010_s cn68xxp1; 2047232812Sjmallett struct cvmx_pcieepx_cfg010_s cnf71xx; 2048215976Sjmallett}; 2049215976Sjmalletttypedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t; 2050215976Sjmallett 2051215976Sjmallett/** 2052215976Sjmallett * cvmx_pcieep#_cfg011 2053215976Sjmallett * 2054215976Sjmallett * PCIE_CFG011 = Twelfth 32-bits of PCIE type 0 config space (Subsystem ID and Subsystem Vendor ID Register) 2055215976Sjmallett * 2056215976Sjmallett */ 2057232812Sjmallettunion cvmx_pcieepx_cfg011 { 2058215976Sjmallett uint32_t u32; 2059232812Sjmallett struct cvmx_pcieepx_cfg011_s { 2060232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2061215976Sjmallett uint32_t ssid : 16; /**< Subsystem ID 2062215976Sjmallett Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR. However, the application must not change this field. */ 2063215976Sjmallett uint32_t ssvid : 16; /**< Subsystem Vendor ID 2064215976Sjmallett Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR. 2065215976Sjmallett However, the application must not change this field. */ 2066215976Sjmallett#else 2067215976Sjmallett uint32_t ssvid : 16; 2068215976Sjmallett uint32_t ssid : 16; 2069215976Sjmallett#endif 2070215976Sjmallett } s; 2071215976Sjmallett struct cvmx_pcieepx_cfg011_s cn52xx; 2072215976Sjmallett struct cvmx_pcieepx_cfg011_s cn52xxp1; 2073215976Sjmallett struct cvmx_pcieepx_cfg011_s cn56xx; 2074215976Sjmallett struct cvmx_pcieepx_cfg011_s cn56xxp1; 2075232812Sjmallett struct cvmx_pcieepx_cfg011_s cn61xx; 2076215976Sjmallett struct cvmx_pcieepx_cfg011_s cn63xx; 2077215976Sjmallett struct cvmx_pcieepx_cfg011_s cn63xxp1; 2078232812Sjmallett struct cvmx_pcieepx_cfg011_s cn66xx; 2079232812Sjmallett struct cvmx_pcieepx_cfg011_s cn68xx; 2080232812Sjmallett struct cvmx_pcieepx_cfg011_s cn68xxp1; 2081232812Sjmallett struct cvmx_pcieepx_cfg011_s cnf71xx; 2082215976Sjmallett}; 2083215976Sjmalletttypedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t; 2084215976Sjmallett 2085215976Sjmallett/** 2086215976Sjmallett * cvmx_pcieep#_cfg012 2087215976Sjmallett * 2088215976Sjmallett * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 0 config space (Expansion ROM Base Address Register) 2089215976Sjmallett * 2090215976Sjmallett */ 2091232812Sjmallettunion cvmx_pcieepx_cfg012 { 2092215976Sjmallett uint32_t u32; 2093232812Sjmallett struct cvmx_pcieepx_cfg012_s { 2094232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2095215976Sjmallett uint32_t eraddr : 16; /**< Expansion ROM Address */ 2096215976Sjmallett uint32_t reserved_1_15 : 15; 2097215976Sjmallett uint32_t er_en : 1; /**< Expansion ROM Enable */ 2098215976Sjmallett#else 2099215976Sjmallett uint32_t er_en : 1; 2100215976Sjmallett uint32_t reserved_1_15 : 15; 2101215976Sjmallett uint32_t eraddr : 16; 2102215976Sjmallett#endif 2103215976Sjmallett } s; 2104215976Sjmallett struct cvmx_pcieepx_cfg012_s cn52xx; 2105215976Sjmallett struct cvmx_pcieepx_cfg012_s cn52xxp1; 2106215976Sjmallett struct cvmx_pcieepx_cfg012_s cn56xx; 2107215976Sjmallett struct cvmx_pcieepx_cfg012_s cn56xxp1; 2108232812Sjmallett struct cvmx_pcieepx_cfg012_s cn61xx; 2109215976Sjmallett struct cvmx_pcieepx_cfg012_s cn63xx; 2110215976Sjmallett struct cvmx_pcieepx_cfg012_s cn63xxp1; 2111232812Sjmallett struct cvmx_pcieepx_cfg012_s cn66xx; 2112232812Sjmallett struct cvmx_pcieepx_cfg012_s cn68xx; 2113232812Sjmallett struct cvmx_pcieepx_cfg012_s cn68xxp1; 2114232812Sjmallett struct cvmx_pcieepx_cfg012_s cnf71xx; 2115215976Sjmallett}; 2116215976Sjmalletttypedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t; 2117215976Sjmallett 2118215976Sjmallett/** 2119215976Sjmallett * cvmx_pcieep#_cfg012_mask 2120215976Sjmallett * 2121215976Sjmallett * PCIE_CFG012_MASK (Exapansion ROM BAR Mask) 2122215976Sjmallett * The ROM Mask register is invisible to host software and not readable from the application. 2123215976Sjmallett * The ROM Mask register is only writable through PEM(0..1)_CFG_WR. 2124215976Sjmallett */ 2125232812Sjmallettunion cvmx_pcieepx_cfg012_mask { 2126215976Sjmallett uint32_t u32; 2127232812Sjmallett struct cvmx_pcieepx_cfg012_mask_s { 2128232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2129215976Sjmallett uint32_t mask : 31; /**< Bar Mask Low NS */ 2130215976Sjmallett uint32_t enb : 1; /**< Bar Enable NS 2131215976Sjmallett o 0: BAR ROM is disabled 2132215976Sjmallett o 1: BAR ROM is enabled 2133215976Sjmallett Bit 0 is interpreted as BAR Enable when writing to the BAR Mask 2134215976Sjmallett register rather than as a mask bit because bit 0 of a BAR is 2135215976Sjmallett always masked from writing by host software. Bit 0 must be 2136215976Sjmallett written prior to writing the other mask bits. */ 2137215976Sjmallett#else 2138215976Sjmallett uint32_t enb : 1; 2139215976Sjmallett uint32_t mask : 31; 2140215976Sjmallett#endif 2141215976Sjmallett } s; 2142215976Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn52xx; 2143215976Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn52xxp1; 2144215976Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn56xx; 2145215976Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn56xxp1; 2146232812Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn61xx; 2147215976Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn63xx; 2148215976Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn63xxp1; 2149232812Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn66xx; 2150232812Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn68xx; 2151232812Sjmallett struct cvmx_pcieepx_cfg012_mask_s cn68xxp1; 2152232812Sjmallett struct cvmx_pcieepx_cfg012_mask_s cnf71xx; 2153215976Sjmallett}; 2154215976Sjmalletttypedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t; 2155215976Sjmallett 2156215976Sjmallett/** 2157215976Sjmallett * cvmx_pcieep#_cfg013 2158215976Sjmallett * 2159215976Sjmallett * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 0 config space (Capability Pointer Register) 2160215976Sjmallett * 2161215976Sjmallett */ 2162232812Sjmallettunion cvmx_pcieepx_cfg013 { 2163215976Sjmallett uint32_t u32; 2164232812Sjmallett struct cvmx_pcieepx_cfg013_s { 2165232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2166215976Sjmallett uint32_t reserved_8_31 : 24; 2167215976Sjmallett uint32_t cp : 8; /**< First Capability Pointer. 2168215976Sjmallett Points to Power Management Capability structure by 2169215976Sjmallett default, writable through PEM(0..1)_CFG_WR. 2170215976Sjmallett However, the application must not change this field. */ 2171215976Sjmallett#else 2172215976Sjmallett uint32_t cp : 8; 2173215976Sjmallett uint32_t reserved_8_31 : 24; 2174215976Sjmallett#endif 2175215976Sjmallett } s; 2176215976Sjmallett struct cvmx_pcieepx_cfg013_s cn52xx; 2177215976Sjmallett struct cvmx_pcieepx_cfg013_s cn52xxp1; 2178215976Sjmallett struct cvmx_pcieepx_cfg013_s cn56xx; 2179215976Sjmallett struct cvmx_pcieepx_cfg013_s cn56xxp1; 2180232812Sjmallett struct cvmx_pcieepx_cfg013_s cn61xx; 2181215976Sjmallett struct cvmx_pcieepx_cfg013_s cn63xx; 2182215976Sjmallett struct cvmx_pcieepx_cfg013_s cn63xxp1; 2183232812Sjmallett struct cvmx_pcieepx_cfg013_s cn66xx; 2184232812Sjmallett struct cvmx_pcieepx_cfg013_s cn68xx; 2185232812Sjmallett struct cvmx_pcieepx_cfg013_s cn68xxp1; 2186232812Sjmallett struct cvmx_pcieepx_cfg013_s cnf71xx; 2187215976Sjmallett}; 2188215976Sjmalletttypedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t; 2189215976Sjmallett 2190215976Sjmallett/** 2191215976Sjmallett * cvmx_pcieep#_cfg015 2192215976Sjmallett * 2193215976Sjmallett * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 0 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register) 2194215976Sjmallett * 2195215976Sjmallett */ 2196232812Sjmallettunion cvmx_pcieepx_cfg015 { 2197215976Sjmallett uint32_t u32; 2198232812Sjmallett struct cvmx_pcieepx_cfg015_s { 2199232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2200215976Sjmallett uint32_t ml : 8; /**< Maximum Latency (Hardwired to 0) */ 2201215976Sjmallett uint32_t mg : 8; /**< Minimum Grant (Hardwired to 0) */ 2202215976Sjmallett uint32_t inta : 8; /**< Interrupt Pin 2203215976Sjmallett Identifies the legacy interrupt Message that the device 2204215976Sjmallett (or device function) uses. 2205215976Sjmallett The Interrupt Pin register is writable through PEM(0..1)_CFG_WR. 2206215976Sjmallett In a single-function configuration, only INTA is used. 2207215976Sjmallett Therefore, the application must not change this field. */ 2208215976Sjmallett uint32_t il : 8; /**< Interrupt Line */ 2209215976Sjmallett#else 2210215976Sjmallett uint32_t il : 8; 2211215976Sjmallett uint32_t inta : 8; 2212215976Sjmallett uint32_t mg : 8; 2213215976Sjmallett uint32_t ml : 8; 2214215976Sjmallett#endif 2215215976Sjmallett } s; 2216215976Sjmallett struct cvmx_pcieepx_cfg015_s cn52xx; 2217215976Sjmallett struct cvmx_pcieepx_cfg015_s cn52xxp1; 2218215976Sjmallett struct cvmx_pcieepx_cfg015_s cn56xx; 2219215976Sjmallett struct cvmx_pcieepx_cfg015_s cn56xxp1; 2220232812Sjmallett struct cvmx_pcieepx_cfg015_s cn61xx; 2221215976Sjmallett struct cvmx_pcieepx_cfg015_s cn63xx; 2222215976Sjmallett struct cvmx_pcieepx_cfg015_s cn63xxp1; 2223232812Sjmallett struct cvmx_pcieepx_cfg015_s cn66xx; 2224232812Sjmallett struct cvmx_pcieepx_cfg015_s cn68xx; 2225232812Sjmallett struct cvmx_pcieepx_cfg015_s cn68xxp1; 2226232812Sjmallett struct cvmx_pcieepx_cfg015_s cnf71xx; 2227215976Sjmallett}; 2228215976Sjmalletttypedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t; 2229215976Sjmallett 2230215976Sjmallett/** 2231215976Sjmallett * cvmx_pcieep#_cfg016 2232215976Sjmallett * 2233215976Sjmallett * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 0 config space 2234215976Sjmallett * (Power Management Capability ID/ 2235215976Sjmallett * Power Management Next Item Pointer/ 2236215976Sjmallett * Power Management Capabilities Register) 2237215976Sjmallett */ 2238232812Sjmallettunion cvmx_pcieepx_cfg016 { 2239215976Sjmallett uint32_t u32; 2240232812Sjmallett struct cvmx_pcieepx_cfg016_s { 2241232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2242215976Sjmallett uint32_t pmes : 5; /**< PME_Support 2243215976Sjmallett o Bit 11: If set, PME Messages can be generated from D0 2244215976Sjmallett o Bit 12: If set, PME Messages can be generated from D1 2245215976Sjmallett o Bit 13: If set, PME Messages can be generated from D2 2246215976Sjmallett o Bit 14: If set, PME Messages can be generated from D3hot 2247215976Sjmallett o Bit 15: If set, PME Messages can be generated from D3cold 2248215976Sjmallett The PME_Support field is writable through PEM(0..1)_CFG_WR. 2249215976Sjmallett However, the application must not change this field. */ 2250215976Sjmallett uint32_t d2s : 1; /**< D2 Support, writable through PEM(0..1)_CFG_WR 2251215976Sjmallett However, the application must not change this field. */ 2252215976Sjmallett uint32_t d1s : 1; /**< D1 Support, writable through PEM(0..1)_CFG_WR 2253215976Sjmallett However, the application must not change this field. */ 2254215976Sjmallett uint32_t auxc : 3; /**< AUX Current, writable through PEM(0..1)_CFG_WR 2255215976Sjmallett However, the application must not change this field. */ 2256215976Sjmallett uint32_t dsi : 1; /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR 2257215976Sjmallett However, the application must not change this field. */ 2258215976Sjmallett uint32_t reserved_20_20 : 1; 2259215976Sjmallett uint32_t pme_clock : 1; /**< PME Clock, hardwired to 0 */ 2260215976Sjmallett uint32_t pmsv : 3; /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR 2261215976Sjmallett However, the application must not change this field. */ 2262215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 2263215976Sjmallett Points to the MSI capabilities by default, writable 2264215976Sjmallett through PEM(0..1)_CFG_WR. 2265215976Sjmallett However, the application must not change this field. */ 2266215976Sjmallett uint32_t pmcid : 8; /**< Power Management Capability ID */ 2267215976Sjmallett#else 2268215976Sjmallett uint32_t pmcid : 8; 2269215976Sjmallett uint32_t ncp : 8; 2270215976Sjmallett uint32_t pmsv : 3; 2271215976Sjmallett uint32_t pme_clock : 1; 2272215976Sjmallett uint32_t reserved_20_20 : 1; 2273215976Sjmallett uint32_t dsi : 1; 2274215976Sjmallett uint32_t auxc : 3; 2275215976Sjmallett uint32_t d1s : 1; 2276215976Sjmallett uint32_t d2s : 1; 2277215976Sjmallett uint32_t pmes : 5; 2278215976Sjmallett#endif 2279215976Sjmallett } s; 2280215976Sjmallett struct cvmx_pcieepx_cfg016_s cn52xx; 2281215976Sjmallett struct cvmx_pcieepx_cfg016_s cn52xxp1; 2282215976Sjmallett struct cvmx_pcieepx_cfg016_s cn56xx; 2283215976Sjmallett struct cvmx_pcieepx_cfg016_s cn56xxp1; 2284232812Sjmallett struct cvmx_pcieepx_cfg016_s cn61xx; 2285215976Sjmallett struct cvmx_pcieepx_cfg016_s cn63xx; 2286215976Sjmallett struct cvmx_pcieepx_cfg016_s cn63xxp1; 2287232812Sjmallett struct cvmx_pcieepx_cfg016_s cn66xx; 2288232812Sjmallett struct cvmx_pcieepx_cfg016_s cn68xx; 2289232812Sjmallett struct cvmx_pcieepx_cfg016_s cn68xxp1; 2290232812Sjmallett struct cvmx_pcieepx_cfg016_s cnf71xx; 2291215976Sjmallett}; 2292215976Sjmalletttypedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t; 2293215976Sjmallett 2294215976Sjmallett/** 2295215976Sjmallett * cvmx_pcieep#_cfg017 2296215976Sjmallett * 2297215976Sjmallett * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 0 config space (Power Management Control and Status Register) 2298215976Sjmallett * 2299215976Sjmallett */ 2300232812Sjmallettunion cvmx_pcieepx_cfg017 { 2301215976Sjmallett uint32_t u32; 2302232812Sjmallett struct cvmx_pcieepx_cfg017_s { 2303232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2304215976Sjmallett uint32_t pmdia : 8; /**< Data register for additional information (not supported) */ 2305215976Sjmallett uint32_t bpccee : 1; /**< Bus Power/Clock Control Enable, hardwired to 0 */ 2306215976Sjmallett uint32_t bd3h : 1; /**< B2/B3 Support, hardwired to 0 */ 2307215976Sjmallett uint32_t reserved_16_21 : 6; 2308215976Sjmallett uint32_t pmess : 1; /**< PME Status 2309215976Sjmallett Indicates if a previously enabled PME event occurred or not. */ 2310215976Sjmallett uint32_t pmedsia : 2; /**< Data Scale (not supported) */ 2311215976Sjmallett uint32_t pmds : 4; /**< Data Select (not supported) */ 2312215976Sjmallett uint32_t pmeens : 1; /**< PME Enable 2313215976Sjmallett A value of 1 indicates that the device is enabled to 2314215976Sjmallett generate PME. */ 2315215976Sjmallett uint32_t reserved_4_7 : 4; 2316215976Sjmallett uint32_t nsr : 1; /**< No Soft Reset, writable through PEM(0..1)_CFG_WR 2317215976Sjmallett However, the application must not change this field. */ 2318215976Sjmallett uint32_t reserved_2_2 : 1; 2319215976Sjmallett uint32_t ps : 2; /**< Power State 2320215976Sjmallett Controls the device power state: 2321215976Sjmallett o 00b: D0 2322215976Sjmallett o 01b: D1 2323215976Sjmallett o 10b: D2 2324215976Sjmallett o 11b: D3 2325215976Sjmallett The written value is ignored if the specific state is 2326215976Sjmallett not supported. */ 2327215976Sjmallett#else 2328215976Sjmallett uint32_t ps : 2; 2329215976Sjmallett uint32_t reserved_2_2 : 1; 2330215976Sjmallett uint32_t nsr : 1; 2331215976Sjmallett uint32_t reserved_4_7 : 4; 2332215976Sjmallett uint32_t pmeens : 1; 2333215976Sjmallett uint32_t pmds : 4; 2334215976Sjmallett uint32_t pmedsia : 2; 2335215976Sjmallett uint32_t pmess : 1; 2336215976Sjmallett uint32_t reserved_16_21 : 6; 2337215976Sjmallett uint32_t bd3h : 1; 2338215976Sjmallett uint32_t bpccee : 1; 2339215976Sjmallett uint32_t pmdia : 8; 2340215976Sjmallett#endif 2341215976Sjmallett } s; 2342215976Sjmallett struct cvmx_pcieepx_cfg017_s cn52xx; 2343215976Sjmallett struct cvmx_pcieepx_cfg017_s cn52xxp1; 2344215976Sjmallett struct cvmx_pcieepx_cfg017_s cn56xx; 2345215976Sjmallett struct cvmx_pcieepx_cfg017_s cn56xxp1; 2346232812Sjmallett struct cvmx_pcieepx_cfg017_s cn61xx; 2347215976Sjmallett struct cvmx_pcieepx_cfg017_s cn63xx; 2348215976Sjmallett struct cvmx_pcieepx_cfg017_s cn63xxp1; 2349232812Sjmallett struct cvmx_pcieepx_cfg017_s cn66xx; 2350232812Sjmallett struct cvmx_pcieepx_cfg017_s cn68xx; 2351232812Sjmallett struct cvmx_pcieepx_cfg017_s cn68xxp1; 2352232812Sjmallett struct cvmx_pcieepx_cfg017_s cnf71xx; 2353215976Sjmallett}; 2354215976Sjmalletttypedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t; 2355215976Sjmallett 2356215976Sjmallett/** 2357215976Sjmallett * cvmx_pcieep#_cfg020 2358215976Sjmallett * 2359215976Sjmallett * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 0 config space 2360215976Sjmallett * (MSI Capability ID/ 2361215976Sjmallett * MSI Next Item Pointer/ 2362215976Sjmallett * MSI Control Register) 2363215976Sjmallett */ 2364232812Sjmallettunion cvmx_pcieepx_cfg020 { 2365215976Sjmallett uint32_t u32; 2366232812Sjmallett struct cvmx_pcieepx_cfg020_s { 2367232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2368232812Sjmallett uint32_t reserved_25_31 : 7; 2369232812Sjmallett uint32_t pvm : 1; /**< Per-vector masking capable */ 2370215976Sjmallett uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR 2371215976Sjmallett However, the application must not change this field. */ 2372215976Sjmallett uint32_t mme : 3; /**< Multiple Message Enabled 2373215976Sjmallett Indicates that multiple Message mode is enabled by system 2374215976Sjmallett software. The number of Messages enabled must be less than 2375215976Sjmallett or equal to the Multiple Message Capable value. */ 2376215976Sjmallett uint32_t mmc : 3; /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR 2377215976Sjmallett However, the application must not change this field. */ 2378215976Sjmallett uint32_t msien : 1; /**< MSI Enabled 2379215976Sjmallett When set, INTx must be disabled. */ 2380215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 2381215976Sjmallett Points to PCI Express Capabilities by default, 2382215976Sjmallett writable through PEM(0..1)_CFG_WR. 2383215976Sjmallett However, the application must not change this field. */ 2384215976Sjmallett uint32_t msicid : 8; /**< MSI Capability ID */ 2385215976Sjmallett#else 2386215976Sjmallett uint32_t msicid : 8; 2387215976Sjmallett uint32_t ncp : 8; 2388215976Sjmallett uint32_t msien : 1; 2389215976Sjmallett uint32_t mmc : 3; 2390215976Sjmallett uint32_t mme : 3; 2391215976Sjmallett uint32_t m64 : 1; 2392232812Sjmallett uint32_t pvm : 1; 2393232812Sjmallett uint32_t reserved_25_31 : 7; 2394232812Sjmallett#endif 2395232812Sjmallett } s; 2396232812Sjmallett struct cvmx_pcieepx_cfg020_cn52xx { 2397232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2398215976Sjmallett uint32_t reserved_24_31 : 8; 2399232812Sjmallett uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PESC(0..1)_CFG_WR 2400232812Sjmallett However, the application must not change this field. */ 2401232812Sjmallett uint32_t mme : 3; /**< Multiple Message Enabled 2402232812Sjmallett Indicates that multiple Message mode is enabled by system 2403232812Sjmallett software. The number of Messages enabled must be less than 2404232812Sjmallett or equal to the Multiple Message Capable value. */ 2405232812Sjmallett uint32_t mmc : 3; /**< Multiple Message Capable, writable through PESC(0..1)_CFG_WR 2406232812Sjmallett However, the application must not change this field. */ 2407232812Sjmallett uint32_t msien : 1; /**< MSI Enabled 2408232812Sjmallett When set, INTx must be disabled. */ 2409232812Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 2410232812Sjmallett Points to PCI Express Capabilities by default, 2411232812Sjmallett writable through PESC(0..1)_CFG_WR. 2412232812Sjmallett However, the application must not change this field. */ 2413232812Sjmallett uint32_t msicid : 8; /**< MSI Capability ID */ 2414232812Sjmallett#else 2415232812Sjmallett uint32_t msicid : 8; 2416232812Sjmallett uint32_t ncp : 8; 2417232812Sjmallett uint32_t msien : 1; 2418232812Sjmallett uint32_t mmc : 3; 2419232812Sjmallett uint32_t mme : 3; 2420232812Sjmallett uint32_t m64 : 1; 2421232812Sjmallett uint32_t reserved_24_31 : 8; 2422215976Sjmallett#endif 2423232812Sjmallett } cn52xx; 2424232812Sjmallett struct cvmx_pcieepx_cfg020_cn52xx cn52xxp1; 2425232812Sjmallett struct cvmx_pcieepx_cfg020_cn52xx cn56xx; 2426232812Sjmallett struct cvmx_pcieepx_cfg020_cn52xx cn56xxp1; 2427232812Sjmallett struct cvmx_pcieepx_cfg020_s cn61xx; 2428232812Sjmallett struct cvmx_pcieepx_cfg020_cn52xx cn63xx; 2429232812Sjmallett struct cvmx_pcieepx_cfg020_cn52xx cn63xxp1; 2430232812Sjmallett struct cvmx_pcieepx_cfg020_s cn66xx; 2431232812Sjmallett struct cvmx_pcieepx_cfg020_s cn68xx; 2432232812Sjmallett struct cvmx_pcieepx_cfg020_s cn68xxp1; 2433232812Sjmallett struct cvmx_pcieepx_cfg020_s cnf71xx; 2434215976Sjmallett}; 2435215976Sjmalletttypedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t; 2436215976Sjmallett 2437215976Sjmallett/** 2438215976Sjmallett * cvmx_pcieep#_cfg021 2439215976Sjmallett * 2440215976Sjmallett * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 0 config space (MSI Lower 32 Bits Address Register) 2441215976Sjmallett * 2442215976Sjmallett */ 2443232812Sjmallettunion cvmx_pcieepx_cfg021 { 2444215976Sjmallett uint32_t u32; 2445232812Sjmallett struct cvmx_pcieepx_cfg021_s { 2446232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2447215976Sjmallett uint32_t lmsi : 30; /**< Lower 32-bit Address */ 2448215976Sjmallett uint32_t reserved_0_1 : 2; 2449215976Sjmallett#else 2450215976Sjmallett uint32_t reserved_0_1 : 2; 2451215976Sjmallett uint32_t lmsi : 30; 2452215976Sjmallett#endif 2453215976Sjmallett } s; 2454215976Sjmallett struct cvmx_pcieepx_cfg021_s cn52xx; 2455215976Sjmallett struct cvmx_pcieepx_cfg021_s cn52xxp1; 2456215976Sjmallett struct cvmx_pcieepx_cfg021_s cn56xx; 2457215976Sjmallett struct cvmx_pcieepx_cfg021_s cn56xxp1; 2458232812Sjmallett struct cvmx_pcieepx_cfg021_s cn61xx; 2459215976Sjmallett struct cvmx_pcieepx_cfg021_s cn63xx; 2460215976Sjmallett struct cvmx_pcieepx_cfg021_s cn63xxp1; 2461232812Sjmallett struct cvmx_pcieepx_cfg021_s cn66xx; 2462232812Sjmallett struct cvmx_pcieepx_cfg021_s cn68xx; 2463232812Sjmallett struct cvmx_pcieepx_cfg021_s cn68xxp1; 2464232812Sjmallett struct cvmx_pcieepx_cfg021_s cnf71xx; 2465215976Sjmallett}; 2466215976Sjmalletttypedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t; 2467215976Sjmallett 2468215976Sjmallett/** 2469215976Sjmallett * cvmx_pcieep#_cfg022 2470215976Sjmallett * 2471215976Sjmallett * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 0 config space (MSI Upper 32 bits Address Register) 2472215976Sjmallett * 2473215976Sjmallett */ 2474232812Sjmallettunion cvmx_pcieepx_cfg022 { 2475215976Sjmallett uint32_t u32; 2476232812Sjmallett struct cvmx_pcieepx_cfg022_s { 2477232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2478215976Sjmallett uint32_t umsi : 32; /**< Upper 32-bit Address */ 2479215976Sjmallett#else 2480215976Sjmallett uint32_t umsi : 32; 2481215976Sjmallett#endif 2482215976Sjmallett } s; 2483215976Sjmallett struct cvmx_pcieepx_cfg022_s cn52xx; 2484215976Sjmallett struct cvmx_pcieepx_cfg022_s cn52xxp1; 2485215976Sjmallett struct cvmx_pcieepx_cfg022_s cn56xx; 2486215976Sjmallett struct cvmx_pcieepx_cfg022_s cn56xxp1; 2487232812Sjmallett struct cvmx_pcieepx_cfg022_s cn61xx; 2488215976Sjmallett struct cvmx_pcieepx_cfg022_s cn63xx; 2489215976Sjmallett struct cvmx_pcieepx_cfg022_s cn63xxp1; 2490232812Sjmallett struct cvmx_pcieepx_cfg022_s cn66xx; 2491232812Sjmallett struct cvmx_pcieepx_cfg022_s cn68xx; 2492232812Sjmallett struct cvmx_pcieepx_cfg022_s cn68xxp1; 2493232812Sjmallett struct cvmx_pcieepx_cfg022_s cnf71xx; 2494215976Sjmallett}; 2495215976Sjmalletttypedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t; 2496215976Sjmallett 2497215976Sjmallett/** 2498215976Sjmallett * cvmx_pcieep#_cfg023 2499215976Sjmallett * 2500215976Sjmallett * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 0 config space (MSI Data Register) 2501215976Sjmallett * 2502215976Sjmallett */ 2503232812Sjmallettunion cvmx_pcieepx_cfg023 { 2504215976Sjmallett uint32_t u32; 2505232812Sjmallett struct cvmx_pcieepx_cfg023_s { 2506232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2507215976Sjmallett uint32_t reserved_16_31 : 16; 2508215976Sjmallett uint32_t msimd : 16; /**< MSI Data 2509215976Sjmallett Pattern assigned by system software, bits [4:0] are Or-ed with 2510215976Sjmallett MSI_VECTOR to generate 32 MSI Messages per function. */ 2511215976Sjmallett#else 2512215976Sjmallett uint32_t msimd : 16; 2513215976Sjmallett uint32_t reserved_16_31 : 16; 2514215976Sjmallett#endif 2515215976Sjmallett } s; 2516215976Sjmallett struct cvmx_pcieepx_cfg023_s cn52xx; 2517215976Sjmallett struct cvmx_pcieepx_cfg023_s cn52xxp1; 2518215976Sjmallett struct cvmx_pcieepx_cfg023_s cn56xx; 2519215976Sjmallett struct cvmx_pcieepx_cfg023_s cn56xxp1; 2520232812Sjmallett struct cvmx_pcieepx_cfg023_s cn61xx; 2521215976Sjmallett struct cvmx_pcieepx_cfg023_s cn63xx; 2522215976Sjmallett struct cvmx_pcieepx_cfg023_s cn63xxp1; 2523232812Sjmallett struct cvmx_pcieepx_cfg023_s cn66xx; 2524232812Sjmallett struct cvmx_pcieepx_cfg023_s cn68xx; 2525232812Sjmallett struct cvmx_pcieepx_cfg023_s cn68xxp1; 2526232812Sjmallett struct cvmx_pcieepx_cfg023_s cnf71xx; 2527215976Sjmallett}; 2528215976Sjmalletttypedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t; 2529215976Sjmallett 2530215976Sjmallett/** 2531215976Sjmallett * cvmx_pcieep#_cfg028 2532215976Sjmallett * 2533215976Sjmallett * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 0 config space 2534215976Sjmallett * (PCI Express Capabilities List Register/ 2535215976Sjmallett * PCI Express Capabilities Register) 2536215976Sjmallett */ 2537232812Sjmallettunion cvmx_pcieepx_cfg028 { 2538215976Sjmallett uint32_t u32; 2539232812Sjmallett struct cvmx_pcieepx_cfg028_s { 2540232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2541215976Sjmallett uint32_t reserved_30_31 : 2; 2542215976Sjmallett uint32_t imn : 5; /**< Interrupt Message Number 2543215976Sjmallett Updated by hardware, writable through PEM(0..1)_CFG_WR. 2544215976Sjmallett However, the application must not change this field. */ 2545215976Sjmallett uint32_t si : 1; /**< Slot Implemented 2546215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 2547215976Sjmallett However, it must be 0 for 2548215976Sjmallett an Endpoint device. Therefore, the application must not write a 2549215976Sjmallett 1 to this bit. */ 2550215976Sjmallett uint32_t dpt : 4; /**< Device Port Type */ 2551215976Sjmallett uint32_t pciecv : 4; /**< PCI Express Capability Version */ 2552215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 2553232812Sjmallett writable through PEM(0..1)_CFG_WR. 2554215976Sjmallett However, the application must not change this field. */ 2555215976Sjmallett uint32_t pcieid : 8; /**< PCIE Capability ID */ 2556215976Sjmallett#else 2557215976Sjmallett uint32_t pcieid : 8; 2558215976Sjmallett uint32_t ncp : 8; 2559215976Sjmallett uint32_t pciecv : 4; 2560215976Sjmallett uint32_t dpt : 4; 2561215976Sjmallett uint32_t si : 1; 2562215976Sjmallett uint32_t imn : 5; 2563215976Sjmallett uint32_t reserved_30_31 : 2; 2564215976Sjmallett#endif 2565215976Sjmallett } s; 2566215976Sjmallett struct cvmx_pcieepx_cfg028_s cn52xx; 2567215976Sjmallett struct cvmx_pcieepx_cfg028_s cn52xxp1; 2568215976Sjmallett struct cvmx_pcieepx_cfg028_s cn56xx; 2569215976Sjmallett struct cvmx_pcieepx_cfg028_s cn56xxp1; 2570232812Sjmallett struct cvmx_pcieepx_cfg028_s cn61xx; 2571215976Sjmallett struct cvmx_pcieepx_cfg028_s cn63xx; 2572215976Sjmallett struct cvmx_pcieepx_cfg028_s cn63xxp1; 2573232812Sjmallett struct cvmx_pcieepx_cfg028_s cn66xx; 2574232812Sjmallett struct cvmx_pcieepx_cfg028_s cn68xx; 2575232812Sjmallett struct cvmx_pcieepx_cfg028_s cn68xxp1; 2576232812Sjmallett struct cvmx_pcieepx_cfg028_s cnf71xx; 2577215976Sjmallett}; 2578215976Sjmalletttypedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t; 2579215976Sjmallett 2580215976Sjmallett/** 2581215976Sjmallett * cvmx_pcieep#_cfg029 2582215976Sjmallett * 2583215976Sjmallett * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 0 config space (Device Capabilities Register) 2584215976Sjmallett * 2585215976Sjmallett */ 2586232812Sjmallettunion cvmx_pcieepx_cfg029 { 2587215976Sjmallett uint32_t u32; 2588232812Sjmallett struct cvmx_pcieepx_cfg029_s { 2589232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2590215976Sjmallett uint32_t reserved_28_31 : 4; 2591215976Sjmallett uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2592215976Sjmallett From Message from RC, upstream port only. */ 2593215976Sjmallett uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2594215976Sjmallett From Message from RC, upstream port only. */ 2595215976Sjmallett uint32_t reserved_16_17 : 2; 2596215976Sjmallett uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2597215976Sjmallett However, the application must not change this field. */ 2598215976Sjmallett uint32_t reserved_12_14 : 3; 2599215976Sjmallett uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2600215976Sjmallett However, the application must not change this field. */ 2601215976Sjmallett uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2602215976Sjmallett However, the application must not change this field. */ 2603215976Sjmallett uint32_t etfs : 1; /**< Extended Tag Field Supported 2604215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 2605215976Sjmallett However, the application 2606215976Sjmallett must not write a 1 to this bit. */ 2607215976Sjmallett uint32_t pfs : 2; /**< Phantom Function Supported 2608215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 2609215976Sjmallett However, Phantom 2610215976Sjmallett Function is not supported. Therefore, the application must not 2611215976Sjmallett write any value other than 0x0 to this field. */ 2612215976Sjmallett uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2613215976Sjmallett However, the application must not change this field. */ 2614215976Sjmallett#else 2615215976Sjmallett uint32_t mpss : 3; 2616215976Sjmallett uint32_t pfs : 2; 2617215976Sjmallett uint32_t etfs : 1; 2618215976Sjmallett uint32_t el0al : 3; 2619215976Sjmallett uint32_t el1al : 3; 2620215976Sjmallett uint32_t reserved_12_14 : 3; 2621215976Sjmallett uint32_t rber : 1; 2622215976Sjmallett uint32_t reserved_16_17 : 2; 2623215976Sjmallett uint32_t csplv : 8; 2624215976Sjmallett uint32_t cspls : 2; 2625215976Sjmallett uint32_t reserved_28_31 : 4; 2626215976Sjmallett#endif 2627215976Sjmallett } s; 2628215976Sjmallett struct cvmx_pcieepx_cfg029_s cn52xx; 2629215976Sjmallett struct cvmx_pcieepx_cfg029_s cn52xxp1; 2630215976Sjmallett struct cvmx_pcieepx_cfg029_s cn56xx; 2631215976Sjmallett struct cvmx_pcieepx_cfg029_s cn56xxp1; 2632232812Sjmallett struct cvmx_pcieepx_cfg029_cn61xx { 2633232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2634232812Sjmallett uint32_t reserved_29_31 : 3; 2635232812Sjmallett uint32_t flr_cap : 1; /**< Function Level Reset Capable 2636232812Sjmallett not supported */ 2637232812Sjmallett uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2638232812Sjmallett From Message from RC, upstream port only. */ 2639232812Sjmallett uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2640232812Sjmallett From Message from RC, upstream port only. */ 2641232812Sjmallett uint32_t reserved_16_17 : 2; 2642232812Sjmallett uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2643232812Sjmallett However, the application must not change this field. */ 2644232812Sjmallett uint32_t reserved_12_14 : 3; 2645232812Sjmallett uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2646232812Sjmallett However, the application must not change this field. */ 2647232812Sjmallett uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2648232812Sjmallett However, the application must not change this field. */ 2649232812Sjmallett uint32_t etfs : 1; /**< Extended Tag Field Supported 2650232812Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 2651232812Sjmallett However, the application 2652232812Sjmallett must not write a 1 to this bit. */ 2653232812Sjmallett uint32_t pfs : 2; /**< Phantom Function Supported 2654232812Sjmallett This field is writable through PEM(0..1)_CFG_WR. 2655232812Sjmallett However, Phantom 2656232812Sjmallett Function is not supported. Therefore, the application must not 2657232812Sjmallett write any value other than 0x0 to this field. */ 2658232812Sjmallett uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2659232812Sjmallett However, the application must not change this field. */ 2660232812Sjmallett#else 2661232812Sjmallett uint32_t mpss : 3; 2662232812Sjmallett uint32_t pfs : 2; 2663232812Sjmallett uint32_t etfs : 1; 2664232812Sjmallett uint32_t el0al : 3; 2665232812Sjmallett uint32_t el1al : 3; 2666232812Sjmallett uint32_t reserved_12_14 : 3; 2667232812Sjmallett uint32_t rber : 1; 2668232812Sjmallett uint32_t reserved_16_17 : 2; 2669232812Sjmallett uint32_t csplv : 8; 2670232812Sjmallett uint32_t cspls : 2; 2671232812Sjmallett uint32_t flr_cap : 1; 2672232812Sjmallett uint32_t reserved_29_31 : 3; 2673232812Sjmallett#endif 2674232812Sjmallett } cn61xx; 2675215976Sjmallett struct cvmx_pcieepx_cfg029_s cn63xx; 2676215976Sjmallett struct cvmx_pcieepx_cfg029_s cn63xxp1; 2677232812Sjmallett struct cvmx_pcieepx_cfg029_cn66xx { 2678232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2679232812Sjmallett uint32_t reserved_29_31 : 3; 2680232812Sjmallett uint32_t flr : 1; /**< Function Level Reset Capability 2681232812Sjmallett When set, core support of SR-IOV */ 2682232812Sjmallett uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2683232812Sjmallett From Message from RC, upstream port only. */ 2684232812Sjmallett uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2685232812Sjmallett From Message from RC, upstream port only. */ 2686232812Sjmallett uint32_t reserved_16_17 : 2; 2687232812Sjmallett uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2688232812Sjmallett However, the application must not change this field. */ 2689232812Sjmallett uint32_t reserved_12_14 : 3; 2690232812Sjmallett uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2691232812Sjmallett However, the application must not change this field. */ 2692232812Sjmallett uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2693232812Sjmallett However, the application must not change this field. */ 2694232812Sjmallett uint32_t etfs : 1; /**< Extended Tag Field Supported 2695232812Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 2696232812Sjmallett However, the application 2697232812Sjmallett must not write a 1 to this bit. */ 2698232812Sjmallett uint32_t pfs : 2; /**< Phantom Function Supported 2699232812Sjmallett This field is writable through PEM(0..1)_CFG_WR. 2700232812Sjmallett However, Phantom 2701232812Sjmallett Function is not supported. Therefore, the application must not 2702232812Sjmallett write any value other than 0x0 to this field. */ 2703232812Sjmallett uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2704232812Sjmallett However, the application must not change this field. */ 2705232812Sjmallett#else 2706232812Sjmallett uint32_t mpss : 3; 2707232812Sjmallett uint32_t pfs : 2; 2708232812Sjmallett uint32_t etfs : 1; 2709232812Sjmallett uint32_t el0al : 3; 2710232812Sjmallett uint32_t el1al : 3; 2711232812Sjmallett uint32_t reserved_12_14 : 3; 2712232812Sjmallett uint32_t rber : 1; 2713232812Sjmallett uint32_t reserved_16_17 : 2; 2714232812Sjmallett uint32_t csplv : 8; 2715232812Sjmallett uint32_t cspls : 2; 2716232812Sjmallett uint32_t flr : 1; 2717232812Sjmallett uint32_t reserved_29_31 : 3; 2718232812Sjmallett#endif 2719232812Sjmallett } cn66xx; 2720232812Sjmallett struct cvmx_pcieepx_cfg029_cn66xx cn68xx; 2721232812Sjmallett struct cvmx_pcieepx_cfg029_cn66xx cn68xxp1; 2722232812Sjmallett struct cvmx_pcieepx_cfg029_cn61xx cnf71xx; 2723215976Sjmallett}; 2724215976Sjmalletttypedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t; 2725215976Sjmallett 2726215976Sjmallett/** 2727215976Sjmallett * cvmx_pcieep#_cfg030 2728215976Sjmallett * 2729215976Sjmallett * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 0 config space 2730215976Sjmallett * (Device Control Register/Device Status Register) 2731215976Sjmallett */ 2732232812Sjmallettunion cvmx_pcieepx_cfg030 { 2733215976Sjmallett uint32_t u32; 2734232812Sjmallett struct cvmx_pcieepx_cfg030_s { 2735232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2736215976Sjmallett uint32_t reserved_22_31 : 10; 2737215976Sjmallett uint32_t tp : 1; /**< Transaction Pending 2738215976Sjmallett Set to 1 when Non-Posted Requests are not yet completed 2739215976Sjmallett and clear when they are completed. */ 2740215976Sjmallett uint32_t ap_d : 1; /**< Aux Power Detected 2741215976Sjmallett Set to 1 if Aux power detected. */ 2742215976Sjmallett uint32_t ur_d : 1; /**< Unsupported Request Detected 2743215976Sjmallett Errors are logged in this register regardless of whether 2744215976Sjmallett error reporting is enabled in the Device Control register. 2745215976Sjmallett UR_D occurs when we receive something we don't support. 2746215976Sjmallett Unsupported requests are Nonfatal errors, so UR_D should 2747215976Sjmallett cause NFE_D. Receiving a vendor defined message should 2748215976Sjmallett cause an unsupported request. */ 2749215976Sjmallett uint32_t fe_d : 1; /**< Fatal Error Detected 2750215976Sjmallett Errors are logged in this register regardless of whether 2751215976Sjmallett error reporting is enabled in the Device Control register. 2752215976Sjmallett FE_D is set if receive any of the errors in PCIE_CFG066 that 2753215976Sjmallett has a severity set to Fatal. Malformed TLP's generally fit 2754215976Sjmallett into this category. */ 2755215976Sjmallett uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2756215976Sjmallett Errors are logged in this register regardless of whether 2757215976Sjmallett error reporting is enabled in the Device Control register. 2758215976Sjmallett NFE_D is set if we receive any of the errors in PCIE_CFG066 2759215976Sjmallett that has a severity set to Nonfatal and does NOT meet Advisory 2760215976Sjmallett Nonfatal criteria , which 2761215976Sjmallett most poisoned TLP's should be. */ 2762215976Sjmallett uint32_t ce_d : 1; /**< Correctable Error Detected 2763215976Sjmallett Errors are logged in this register regardless of whether 2764215976Sjmallett error reporting is enabled in the Device Control register. 2765215976Sjmallett CE_D is set if we receive any of the errors in PCIE_CFG068 2766215976Sjmallett for example a Replay Timer Timeout. Also, it can be set if 2767215976Sjmallett we get any of the errors in PCIE_CFG066 that has a severity 2768215976Sjmallett set to Nonfatal and meets the Advisory Nonfatal criteria, 2769215976Sjmallett which most ECRC errors 2770215976Sjmallett should be. */ 2771232812Sjmallett uint32_t i_flr : 1; /**< Initiate Function Level Reset 2772232812Sjmallett (Not Supported) */ 2773215976Sjmallett uint32_t mrrs : 3; /**< Max Read Request Size 2774215976Sjmallett 0 = 128B 2775215976Sjmallett 1 = 256B 2776215976Sjmallett 2 = 512B 2777215976Sjmallett 3 = 1024B 2778215976Sjmallett 4 = 2048B 2779215976Sjmallett 5 = 4096B 2780215976Sjmallett Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and 2781215976Sjmallett also must be set properly. 2782215976Sjmallett SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must 2783215976Sjmallett not exceed the desired max read request size. */ 2784215976Sjmallett uint32_t ns_en : 1; /**< Enable No Snoop */ 2785215976Sjmallett uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2786215976Sjmallett uint32_t pf_en : 1; /**< Phantom Function Enable 2787215976Sjmallett This bit should never be set - OCTEON requests never use 2788215976Sjmallett phantom functions. */ 2789215976Sjmallett uint32_t etf_en : 1; /**< Extended Tag Field Enable 2790215976Sjmallett This bit should never be set - OCTEON requests never use 2791215976Sjmallett extended tags. */ 2792215976Sjmallett uint32_t mps : 3; /**< Max Payload Size 2793215976Sjmallett Legal values: 2794215976Sjmallett 0 = 128B 2795215976Sjmallett 1 = 256B 2796215976Sjmallett Larger sizes not supported by OCTEON. 2797215976Sjmallett Note: DPI_SLI_PRT#_CFG[MPS] must be set to the same 2798215976Sjmallett value for proper functionality. */ 2799232812Sjmallett uint32_t ro_en : 1; /**< Enable Relaxed Ordering 2800232812Sjmallett This bit is not used. */ 2801232812Sjmallett uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2802232812Sjmallett uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2803232812Sjmallett uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2804232812Sjmallett uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2805232812Sjmallett#else 2806232812Sjmallett uint32_t ce_en : 1; 2807232812Sjmallett uint32_t nfe_en : 1; 2808232812Sjmallett uint32_t fe_en : 1; 2809232812Sjmallett uint32_t ur_en : 1; 2810232812Sjmallett uint32_t ro_en : 1; 2811232812Sjmallett uint32_t mps : 3; 2812232812Sjmallett uint32_t etf_en : 1; 2813232812Sjmallett uint32_t pf_en : 1; 2814232812Sjmallett uint32_t ap_en : 1; 2815232812Sjmallett uint32_t ns_en : 1; 2816232812Sjmallett uint32_t mrrs : 3; 2817232812Sjmallett uint32_t i_flr : 1; 2818232812Sjmallett uint32_t ce_d : 1; 2819232812Sjmallett uint32_t nfe_d : 1; 2820232812Sjmallett uint32_t fe_d : 1; 2821232812Sjmallett uint32_t ur_d : 1; 2822232812Sjmallett uint32_t ap_d : 1; 2823232812Sjmallett uint32_t tp : 1; 2824232812Sjmallett uint32_t reserved_22_31 : 10; 2825232812Sjmallett#endif 2826232812Sjmallett } s; 2827232812Sjmallett struct cvmx_pcieepx_cfg030_cn52xx { 2828232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2829232812Sjmallett uint32_t reserved_22_31 : 10; 2830232812Sjmallett uint32_t tp : 1; /**< Transaction Pending 2831232812Sjmallett Set to 1 when Non-Posted Requests are not yet completed 2832232812Sjmallett and clear when they are completed. */ 2833232812Sjmallett uint32_t ap_d : 1; /**< Aux Power Detected 2834232812Sjmallett Set to 1 if Aux power detected. */ 2835232812Sjmallett uint32_t ur_d : 1; /**< Unsupported Request Detected 2836232812Sjmallett Errors are logged in this register regardless of whether 2837232812Sjmallett error reporting is enabled in the Device Control register. 2838232812Sjmallett UR_D occurs when we receive something we don't support. 2839232812Sjmallett Unsupported requests are Nonfatal errors, so UR_D should 2840232812Sjmallett cause NFE_D. Receiving a vendor defined message should 2841232812Sjmallett cause an unsupported request. */ 2842232812Sjmallett uint32_t fe_d : 1; /**< Fatal Error Detected 2843232812Sjmallett Errors are logged in this register regardless of whether 2844232812Sjmallett error reporting is enabled in the Device Control register. 2845232812Sjmallett FE_D is set if receive any of the errors in PCIE_CFG066 that 2846232812Sjmallett has a severity set to Fatal. Malformed TLP's generally fit 2847232812Sjmallett into this category. */ 2848232812Sjmallett uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2849232812Sjmallett Errors are logged in this register regardless of whether 2850232812Sjmallett error reporting is enabled in the Device Control register. 2851232812Sjmallett NFE_D is set if we receive any of the errors in PCIE_CFG066 2852232812Sjmallett that has a severity set to Nonfatal and does NOT meet Advisory 2853232812Sjmallett Nonfatal criteria (PCIe 1.1 spec, Section 6.2.3.2.4), which 2854232812Sjmallett most poisoned TLP's should be. */ 2855232812Sjmallett uint32_t ce_d : 1; /**< Correctable Error Detected 2856232812Sjmallett Errors are logged in this register regardless of whether 2857232812Sjmallett error reporting is enabled in the Device Control register. 2858232812Sjmallett CE_D is set if we receive any of the errors in PCIE_CFG068 2859232812Sjmallett for example a Replay Timer Timeout. Also, it can be set if 2860232812Sjmallett we get any of the errors in PCIE_CFG066 that has a severity 2861232812Sjmallett set to Nonfatal and meets the Advisory Nonfatal criteria 2862232812Sjmallett (PCIe 1.1 spec, Section 6.2.3.2.4), which most ECRC errors 2863232812Sjmallett should be. */ 2864232812Sjmallett uint32_t reserved_15_15 : 1; 2865232812Sjmallett uint32_t mrrs : 3; /**< Max Read Request Size 2866232812Sjmallett 0 = 128B 2867232812Sjmallett 1 = 256B 2868232812Sjmallett 2 = 512B 2869232812Sjmallett 3 = 1024B 2870232812Sjmallett 4 = 2048B 2871232812Sjmallett 5 = 4096B 2872232812Sjmallett Note: NPEI_CTL_STATUS2[MRRS] also must be set properly. 2873232812Sjmallett NPEI_CTL_STATUS2[MRRS] must not exceed the 2874232812Sjmallett desired max read request size. */ 2875232812Sjmallett uint32_t ns_en : 1; /**< Enable No Snoop */ 2876232812Sjmallett uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2877232812Sjmallett uint32_t pf_en : 1; /**< Phantom Function Enable 2878232812Sjmallett This bit should never be set - OCTEON requests never use 2879232812Sjmallett phantom functions. */ 2880232812Sjmallett uint32_t etf_en : 1; /**< Extended Tag Field Enable 2881232812Sjmallett This bit should never be set - OCTEON requests never use 2882232812Sjmallett extended tags. */ 2883232812Sjmallett uint32_t mps : 3; /**< Max Payload Size 2884232812Sjmallett Legal values: 2885232812Sjmallett 0 = 128B 2886232812Sjmallett 1 = 256B 2887232812Sjmallett Larger sizes not supported by OCTEON. 2888232812Sjmallett Note: NPEI_CTL_STATUS2[MPS] must be set to the same 2889232812Sjmallett value for proper functionality. */ 2890215976Sjmallett uint32_t ro_en : 1; /**< Enable Relaxed Ordering */ 2891215976Sjmallett uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2892215976Sjmallett uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2893215976Sjmallett uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2894215976Sjmallett uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2895215976Sjmallett#else 2896215976Sjmallett uint32_t ce_en : 1; 2897215976Sjmallett uint32_t nfe_en : 1; 2898215976Sjmallett uint32_t fe_en : 1; 2899215976Sjmallett uint32_t ur_en : 1; 2900215976Sjmallett uint32_t ro_en : 1; 2901215976Sjmallett uint32_t mps : 3; 2902215976Sjmallett uint32_t etf_en : 1; 2903215976Sjmallett uint32_t pf_en : 1; 2904215976Sjmallett uint32_t ap_en : 1; 2905215976Sjmallett uint32_t ns_en : 1; 2906215976Sjmallett uint32_t mrrs : 3; 2907215976Sjmallett uint32_t reserved_15_15 : 1; 2908215976Sjmallett uint32_t ce_d : 1; 2909215976Sjmallett uint32_t nfe_d : 1; 2910215976Sjmallett uint32_t fe_d : 1; 2911215976Sjmallett uint32_t ur_d : 1; 2912215976Sjmallett uint32_t ap_d : 1; 2913215976Sjmallett uint32_t tp : 1; 2914215976Sjmallett uint32_t reserved_22_31 : 10; 2915215976Sjmallett#endif 2916232812Sjmallett } cn52xx; 2917232812Sjmallett struct cvmx_pcieepx_cfg030_cn52xx cn52xxp1; 2918232812Sjmallett struct cvmx_pcieepx_cfg030_cn52xx cn56xx; 2919232812Sjmallett struct cvmx_pcieepx_cfg030_cn52xx cn56xxp1; 2920232812Sjmallett struct cvmx_pcieepx_cfg030_s cn61xx; 2921232812Sjmallett struct cvmx_pcieepx_cfg030_cn52xx cn63xx; 2922232812Sjmallett struct cvmx_pcieepx_cfg030_cn52xx cn63xxp1; 2923232812Sjmallett struct cvmx_pcieepx_cfg030_s cn66xx; 2924232812Sjmallett struct cvmx_pcieepx_cfg030_s cn68xx; 2925232812Sjmallett struct cvmx_pcieepx_cfg030_s cn68xxp1; 2926232812Sjmallett struct cvmx_pcieepx_cfg030_s cnf71xx; 2927215976Sjmallett}; 2928215976Sjmalletttypedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t; 2929215976Sjmallett 2930215976Sjmallett/** 2931215976Sjmallett * cvmx_pcieep#_cfg031 2932215976Sjmallett * 2933215976Sjmallett * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 0 config space 2934215976Sjmallett * (Link Capabilities Register) 2935215976Sjmallett */ 2936232812Sjmallettunion cvmx_pcieepx_cfg031 { 2937215976Sjmallett uint32_t u32; 2938232812Sjmallett struct cvmx_pcieepx_cfg031_s { 2939232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2940232812Sjmallett uint32_t pnum : 8; /**< Port Number 2941232812Sjmallett writable through PEM(0..1)_CFG_WR, however the application 2942232812Sjmallett must not change this field. */ 2943232812Sjmallett uint32_t reserved_23_23 : 1; 2944232812Sjmallett uint32_t aspm : 1; /**< ASPM Optionality Compliance */ 2945232812Sjmallett uint32_t lbnc : 1; /**< Link Bandwidth Notification Capability 2946232812Sjmallett Set 0 for Endpoint devices. */ 2947215976Sjmallett uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable */ 2948215976Sjmallett uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2949215976Sjmallett Not supported, hardwired to 0x0. */ 2950215976Sjmallett uint32_t cpm : 1; /**< Clock Power Management 2951215976Sjmallett The default value is the value you specify during hardware 2952215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2953215976Sjmallett However, the application must not change this field. */ 2954215976Sjmallett uint32_t l1el : 3; /**< L1 Exit Latency 2955215976Sjmallett The default value is the value you specify during hardware 2956215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2957215976Sjmallett However, the application must not change this field. */ 2958215976Sjmallett uint32_t l0el : 3; /**< L0s Exit Latency 2959215976Sjmallett The default value is the value you specify during hardware 2960215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2961215976Sjmallett However, the application must not change this field. */ 2962215976Sjmallett uint32_t aslpms : 2; /**< Active State Link PM Support 2963215976Sjmallett The default value is the value you specify during hardware 2964215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2965215976Sjmallett However, the application must not change this field. */ 2966215976Sjmallett uint32_t mlw : 6; /**< Maximum Link Width 2967215976Sjmallett The default value is the value you specify during hardware 2968232812Sjmallett configuration (x1), writable through PEM(0..1)_CFG_WR 2969232812Sjmallett however wider cofigurations are not supported. */ 2970215976Sjmallett uint32_t mls : 4; /**< Maximum Link Speed 2971232812Sjmallett The reset value of this field is controlled by a value sent from 2972232812Sjmallett the lsb of the MIO_QLM#_SPD register. 2973232812Sjmallett qlm#_spd[1] RST_VALUE NOTE 2974232812Sjmallett 1 0001b 2.5 GHz supported 2975232812Sjmallett 0 0010b 5.0 GHz and 2.5 GHz supported 2976215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 2977215976Sjmallett However, the application must not change this field. */ 2978215976Sjmallett#else 2979215976Sjmallett uint32_t mls : 4; 2980215976Sjmallett uint32_t mlw : 6; 2981215976Sjmallett uint32_t aslpms : 2; 2982215976Sjmallett uint32_t l0el : 3; 2983215976Sjmallett uint32_t l1el : 3; 2984215976Sjmallett uint32_t cpm : 1; 2985215976Sjmallett uint32_t sderc : 1; 2986215976Sjmallett uint32_t dllarc : 1; 2987215976Sjmallett uint32_t lbnc : 1; 2988232812Sjmallett uint32_t aspm : 1; 2989232812Sjmallett uint32_t reserved_23_23 : 1; 2990232812Sjmallett uint32_t pnum : 8; 2991232812Sjmallett#endif 2992232812Sjmallett } s; 2993232812Sjmallett struct cvmx_pcieepx_cfg031_cn52xx { 2994232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2995232812Sjmallett uint32_t pnum : 8; /**< Port Number, writable through PESC(0..1)_CFG_WR 2996232812Sjmallett However, the application must not change this field. */ 2997215976Sjmallett uint32_t reserved_22_23 : 2; 2998232812Sjmallett uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */ 2999232812Sjmallett uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable */ 3000232812Sjmallett uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 3001232812Sjmallett Not supported, hardwired to 0x0. */ 3002232812Sjmallett uint32_t cpm : 1; /**< Clock Power Management 3003232812Sjmallett The default value is the value you specify during hardware 3004232812Sjmallett configuration, writable through PESC(0..1)_CFG_WR. 3005232812Sjmallett However, the application must not change this field. */ 3006232812Sjmallett uint32_t l1el : 3; /**< L1 Exit Latency 3007232812Sjmallett The default value is the value you specify during hardware 3008232812Sjmallett configuration, writable through PESC(0..1)_CFG_WR. 3009232812Sjmallett However, the application must not change this field. */ 3010232812Sjmallett uint32_t l0el : 3; /**< L0s Exit Latency 3011232812Sjmallett The default value is the value you specify during hardware 3012232812Sjmallett configuration, writable through PESC(0..1)_CFG_WR. 3013232812Sjmallett However, the application must not change this field. */ 3014232812Sjmallett uint32_t aslpms : 2; /**< Active State Link PM Support 3015232812Sjmallett The default value is the value you specify during hardware 3016232812Sjmallett configuration, writable through PESC(0..1)_CFG_WR. 3017232812Sjmallett However, the application must not change this field. */ 3018232812Sjmallett uint32_t mlw : 6; /**< Maximum Link Width 3019232812Sjmallett The default value is the value you specify during hardware 3020232812Sjmallett configuration (x1, x2, x4, x8, or x16), writable through PESC(0..1)_CFG_WR. 3021232812Sjmallett This value will be set to 0x4 or 0x2 depending on the max 3022232812Sjmallett number of lanes (QLM_CFG == 0 set to 0x2 else 0x4). */ 3023232812Sjmallett uint32_t mls : 4; /**< Maximum Link Speed 3024232812Sjmallett Default value is 0x1 for 2.5 Gbps Link. 3025232812Sjmallett This field is writable through PESC(0..1)_CFG_WR. 3026232812Sjmallett However, 0x1 is the 3027232812Sjmallett only supported value. Therefore, the application must not write 3028232812Sjmallett any value other than 0x1 to this field. */ 3029232812Sjmallett#else 3030232812Sjmallett uint32_t mls : 4; 3031232812Sjmallett uint32_t mlw : 6; 3032232812Sjmallett uint32_t aslpms : 2; 3033232812Sjmallett uint32_t l0el : 3; 3034232812Sjmallett uint32_t l1el : 3; 3035232812Sjmallett uint32_t cpm : 1; 3036232812Sjmallett uint32_t sderc : 1; 3037232812Sjmallett uint32_t dllarc : 1; 3038232812Sjmallett uint32_t lbnc : 1; 3039232812Sjmallett uint32_t reserved_22_23 : 2; 3040215976Sjmallett uint32_t pnum : 8; 3041215976Sjmallett#endif 3042232812Sjmallett } cn52xx; 3043232812Sjmallett struct cvmx_pcieepx_cfg031_cn52xx cn52xxp1; 3044232812Sjmallett struct cvmx_pcieepx_cfg031_cn52xx cn56xx; 3045232812Sjmallett struct cvmx_pcieepx_cfg031_cn52xx cn56xxp1; 3046232812Sjmallett struct cvmx_pcieepx_cfg031_s cn61xx; 3047232812Sjmallett struct cvmx_pcieepx_cfg031_cn52xx cn63xx; 3048232812Sjmallett struct cvmx_pcieepx_cfg031_cn52xx cn63xxp1; 3049232812Sjmallett struct cvmx_pcieepx_cfg031_s cn66xx; 3050232812Sjmallett struct cvmx_pcieepx_cfg031_s cn68xx; 3051232812Sjmallett struct cvmx_pcieepx_cfg031_cn52xx cn68xxp1; 3052232812Sjmallett struct cvmx_pcieepx_cfg031_s cnf71xx; 3053215976Sjmallett}; 3054215976Sjmalletttypedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t; 3055215976Sjmallett 3056215976Sjmallett/** 3057215976Sjmallett * cvmx_pcieep#_cfg032 3058215976Sjmallett * 3059215976Sjmallett * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 0 config space 3060215976Sjmallett * (Link Control Register/Link Status Register) 3061215976Sjmallett */ 3062232812Sjmallettunion cvmx_pcieepx_cfg032 { 3063215976Sjmallett uint32_t u32; 3064232812Sjmallett struct cvmx_pcieepx_cfg032_s { 3065232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3066232812Sjmallett uint32_t lab : 1; /**< Link Autonomous Bandwidth Status */ 3067232812Sjmallett uint32_t lbm : 1; /**< Link Bandwidth Management Status */ 3068215976Sjmallett uint32_t dlla : 1; /**< Data Link Layer Active 3069215976Sjmallett Not applicable for an upstream Port or Endpoint device, 3070215976Sjmallett hardwired to 0. */ 3071215976Sjmallett uint32_t scc : 1; /**< Slot Clock Configuration 3072215976Sjmallett Indicates that the component uses the same physical reference 3073215976Sjmallett clock that the platform provides on the connector. 3074215976Sjmallett Writable through PEM(0..1)_CFG_WR. 3075215976Sjmallett However, the application must not change this field. */ 3076215976Sjmallett uint32_t lt : 1; /**< Link Training 3077215976Sjmallett Not applicable for an upstream Port or Endpoint device, 3078215976Sjmallett hardwired to 0. */ 3079215976Sjmallett uint32_t reserved_26_26 : 1; 3080215976Sjmallett uint32_t nlw : 6; /**< Negotiated Link Width 3081232812Sjmallett Set automatically by hardware after Link initialization. 3082232812Sjmallett Value is undefined when link is not up. */ 3083232812Sjmallett uint32_t ls : 4; /**< Link Speed 3084232812Sjmallett 1 == The negotiated Link speed: 2.5 Gbps 3085232812Sjmallett 2 == The negotiated Link speed: 5.0 Gbps 3086232812Sjmallett 4 == The negotiated Link speed: 8.0 Gbps (Not Supported) */ 3087232812Sjmallett uint32_t reserved_12_15 : 4; 3088232812Sjmallett uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable 3089232812Sjmallett This bit is not applicable and is reserved for endpoints */ 3090232812Sjmallett uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable 3091232812Sjmallett This bit is not applicable and is reserved for endpoints */ 3092232812Sjmallett uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 3093232812Sjmallett (Not Supported) */ 3094232812Sjmallett uint32_t ecpm : 1; /**< Enable Clock Power Management 3095232812Sjmallett Hardwired to 0 if Clock Power Management is disabled in 3096232812Sjmallett the Link Capabilities register. */ 3097232812Sjmallett uint32_t es : 1; /**< Extended Synch */ 3098232812Sjmallett uint32_t ccc : 1; /**< Common Clock Configuration */ 3099232812Sjmallett uint32_t rl : 1; /**< Retrain Link 3100232812Sjmallett Not applicable for an upstream Port or Endpoint device, 3101232812Sjmallett hardwired to 0. */ 3102232812Sjmallett uint32_t ld : 1; /**< Link Disable 3103232812Sjmallett Not applicable for an upstream Port or Endpoint device, 3104232812Sjmallett hardwired to 0. */ 3105232812Sjmallett uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */ 3106232812Sjmallett uint32_t reserved_2_2 : 1; 3107232812Sjmallett uint32_t aslpc : 2; /**< Active State Link PM Control */ 3108232812Sjmallett#else 3109232812Sjmallett uint32_t aslpc : 2; 3110232812Sjmallett uint32_t reserved_2_2 : 1; 3111232812Sjmallett uint32_t rcb : 1; 3112232812Sjmallett uint32_t ld : 1; 3113232812Sjmallett uint32_t rl : 1; 3114232812Sjmallett uint32_t ccc : 1; 3115232812Sjmallett uint32_t es : 1; 3116232812Sjmallett uint32_t ecpm : 1; 3117232812Sjmallett uint32_t hawd : 1; 3118232812Sjmallett uint32_t lbm_int_enb : 1; 3119232812Sjmallett uint32_t lab_int_enb : 1; 3120232812Sjmallett uint32_t reserved_12_15 : 4; 3121232812Sjmallett uint32_t ls : 4; 3122232812Sjmallett uint32_t nlw : 6; 3123232812Sjmallett uint32_t reserved_26_26 : 1; 3124232812Sjmallett uint32_t lt : 1; 3125232812Sjmallett uint32_t scc : 1; 3126232812Sjmallett uint32_t dlla : 1; 3127232812Sjmallett uint32_t lbm : 1; 3128232812Sjmallett uint32_t lab : 1; 3129232812Sjmallett#endif 3130232812Sjmallett } s; 3131232812Sjmallett struct cvmx_pcieepx_cfg032_cn52xx { 3132232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3133232812Sjmallett uint32_t reserved_30_31 : 2; 3134232812Sjmallett uint32_t dlla : 1; /**< Data Link Layer Active 3135232812Sjmallett Not applicable for an upstream Port or Endpoint device, 3136232812Sjmallett hardwired to 0. */ 3137232812Sjmallett uint32_t scc : 1; /**< Slot Clock Configuration 3138232812Sjmallett Indicates that the component uses the same physical reference 3139232812Sjmallett clock that the platform provides on the connector. 3140232812Sjmallett Writable through PESC(0..1)_CFG_WR. 3141232812Sjmallett However, the application must not change this field. */ 3142232812Sjmallett uint32_t lt : 1; /**< Link Training 3143232812Sjmallett Not applicable for an upstream Port or Endpoint device, 3144232812Sjmallett hardwired to 0. */ 3145232812Sjmallett uint32_t reserved_26_26 : 1; 3146232812Sjmallett uint32_t nlw : 6; /**< Negotiated Link Width 3147215976Sjmallett Set automatically by hardware after Link initialization. */ 3148215976Sjmallett uint32_t ls : 4; /**< Link Speed 3149215976Sjmallett The negotiated Link speed: 2.5 Gbps */ 3150215976Sjmallett uint32_t reserved_10_15 : 6; 3151215976Sjmallett uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 3152215976Sjmallett (Not Supported) */ 3153215976Sjmallett uint32_t ecpm : 1; /**< Enable Clock Power Management 3154215976Sjmallett Hardwired to 0 if Clock Power Management is disabled in 3155215976Sjmallett the Link Capabilities register. */ 3156215976Sjmallett uint32_t es : 1; /**< Extended Synch */ 3157215976Sjmallett uint32_t ccc : 1; /**< Common Clock Configuration */ 3158215976Sjmallett uint32_t rl : 1; /**< Retrain Link 3159215976Sjmallett Not applicable for an upstream Port or Endpoint device, 3160215976Sjmallett hardwired to 0. */ 3161215976Sjmallett uint32_t ld : 1; /**< Link Disable 3162215976Sjmallett Not applicable for an upstream Port or Endpoint device, 3163215976Sjmallett hardwired to 0. */ 3164215976Sjmallett uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */ 3165215976Sjmallett uint32_t reserved_2_2 : 1; 3166215976Sjmallett uint32_t aslpc : 2; /**< Active State Link PM Control */ 3167215976Sjmallett#else 3168215976Sjmallett uint32_t aslpc : 2; 3169215976Sjmallett uint32_t reserved_2_2 : 1; 3170215976Sjmallett uint32_t rcb : 1; 3171215976Sjmallett uint32_t ld : 1; 3172215976Sjmallett uint32_t rl : 1; 3173215976Sjmallett uint32_t ccc : 1; 3174215976Sjmallett uint32_t es : 1; 3175215976Sjmallett uint32_t ecpm : 1; 3176215976Sjmallett uint32_t hawd : 1; 3177215976Sjmallett uint32_t reserved_10_15 : 6; 3178215976Sjmallett uint32_t ls : 4; 3179215976Sjmallett uint32_t nlw : 6; 3180215976Sjmallett uint32_t reserved_26_26 : 1; 3181215976Sjmallett uint32_t lt : 1; 3182215976Sjmallett uint32_t scc : 1; 3183215976Sjmallett uint32_t dlla : 1; 3184215976Sjmallett uint32_t reserved_30_31 : 2; 3185215976Sjmallett#endif 3186232812Sjmallett } cn52xx; 3187232812Sjmallett struct cvmx_pcieepx_cfg032_cn52xx cn52xxp1; 3188232812Sjmallett struct cvmx_pcieepx_cfg032_cn52xx cn56xx; 3189232812Sjmallett struct cvmx_pcieepx_cfg032_cn52xx cn56xxp1; 3190232812Sjmallett struct cvmx_pcieepx_cfg032_s cn61xx; 3191232812Sjmallett struct cvmx_pcieepx_cfg032_cn52xx cn63xx; 3192232812Sjmallett struct cvmx_pcieepx_cfg032_cn52xx cn63xxp1; 3193232812Sjmallett struct cvmx_pcieepx_cfg032_s cn66xx; 3194232812Sjmallett struct cvmx_pcieepx_cfg032_s cn68xx; 3195232812Sjmallett struct cvmx_pcieepx_cfg032_cn68xxp1 { 3196232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3197232812Sjmallett uint32_t reserved_30_31 : 2; 3198232812Sjmallett uint32_t dlla : 1; /**< Data Link Layer Active 3199232812Sjmallett Not applicable for an upstream Port or Endpoint device, 3200232812Sjmallett hardwired to 0. */ 3201232812Sjmallett uint32_t scc : 1; /**< Slot Clock Configuration 3202232812Sjmallett Indicates that the component uses the same physical reference 3203232812Sjmallett clock that the platform provides on the connector. 3204232812Sjmallett Writable through PEM(0..1)_CFG_WR. 3205232812Sjmallett However, the application must not change this field. */ 3206232812Sjmallett uint32_t lt : 1; /**< Link Training 3207232812Sjmallett Not applicable for an upstream Port or Endpoint device, 3208232812Sjmallett hardwired to 0. */ 3209232812Sjmallett uint32_t reserved_26_26 : 1; 3210232812Sjmallett uint32_t nlw : 6; /**< Negotiated Link Width 3211232812Sjmallett Set automatically by hardware after Link initialization. */ 3212232812Sjmallett uint32_t ls : 4; /**< Link Speed 3213232812Sjmallett 1 == The negotiated Link speed: 2.5 Gbps 3214232812Sjmallett 2 == The negotiated Link speed: 5.0 Gbps 3215232812Sjmallett 4 == The negotiated Link speed: 8.0 Gbps (Not Supported) */ 3216232812Sjmallett uint32_t reserved_12_15 : 4; 3217232812Sjmallett uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable 3218232812Sjmallett This bit is not applicable and is reserved for endpoints */ 3219232812Sjmallett uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable 3220232812Sjmallett This bit is not applicable and is reserved for endpoints */ 3221232812Sjmallett uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 3222232812Sjmallett (Not Supported) */ 3223232812Sjmallett uint32_t ecpm : 1; /**< Enable Clock Power Management 3224232812Sjmallett Hardwired to 0 if Clock Power Management is disabled in 3225232812Sjmallett the Link Capabilities register. */ 3226232812Sjmallett uint32_t es : 1; /**< Extended Synch */ 3227232812Sjmallett uint32_t ccc : 1; /**< Common Clock Configuration */ 3228232812Sjmallett uint32_t rl : 1; /**< Retrain Link 3229232812Sjmallett Not applicable for an upstream Port or Endpoint device, 3230232812Sjmallett hardwired to 0. */ 3231232812Sjmallett uint32_t ld : 1; /**< Link Disable 3232232812Sjmallett Not applicable for an upstream Port or Endpoint device, 3233232812Sjmallett hardwired to 0. */ 3234232812Sjmallett uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */ 3235232812Sjmallett uint32_t reserved_2_2 : 1; 3236232812Sjmallett uint32_t aslpc : 2; /**< Active State Link PM Control */ 3237232812Sjmallett#else 3238232812Sjmallett uint32_t aslpc : 2; 3239232812Sjmallett uint32_t reserved_2_2 : 1; 3240232812Sjmallett uint32_t rcb : 1; 3241232812Sjmallett uint32_t ld : 1; 3242232812Sjmallett uint32_t rl : 1; 3243232812Sjmallett uint32_t ccc : 1; 3244232812Sjmallett uint32_t es : 1; 3245232812Sjmallett uint32_t ecpm : 1; 3246232812Sjmallett uint32_t hawd : 1; 3247232812Sjmallett uint32_t lbm_int_enb : 1; 3248232812Sjmallett uint32_t lab_int_enb : 1; 3249232812Sjmallett uint32_t reserved_12_15 : 4; 3250232812Sjmallett uint32_t ls : 4; 3251232812Sjmallett uint32_t nlw : 6; 3252232812Sjmallett uint32_t reserved_26_26 : 1; 3253232812Sjmallett uint32_t lt : 1; 3254232812Sjmallett uint32_t scc : 1; 3255232812Sjmallett uint32_t dlla : 1; 3256232812Sjmallett uint32_t reserved_30_31 : 2; 3257232812Sjmallett#endif 3258232812Sjmallett } cn68xxp1; 3259232812Sjmallett struct cvmx_pcieepx_cfg032_s cnf71xx; 3260215976Sjmallett}; 3261215976Sjmalletttypedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t; 3262215976Sjmallett 3263215976Sjmallett/** 3264215976Sjmallett * cvmx_pcieep#_cfg033 3265215976Sjmallett * 3266215976Sjmallett * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space 3267215976Sjmallett * (Slot Capabilities Register) 3268215976Sjmallett */ 3269232812Sjmallettunion cvmx_pcieepx_cfg033 { 3270215976Sjmallett uint32_t u32; 3271232812Sjmallett struct cvmx_pcieepx_cfg033_s { 3272232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3273215976Sjmallett uint32_t ps_num : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR 3274215976Sjmallett However, the application must not change this field. */ 3275215976Sjmallett uint32_t nccs : 1; /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR 3276215976Sjmallett However, the application must not change this field. */ 3277215976Sjmallett uint32_t emip : 1; /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR 3278215976Sjmallett However, the application must not change this field. */ 3279215976Sjmallett uint32_t sp_ls : 2; /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR 3280215976Sjmallett However, the application must not change this field. */ 3281215976Sjmallett uint32_t sp_lv : 8; /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR 3282215976Sjmallett However, the application must not change this field. */ 3283215976Sjmallett uint32_t hp_c : 1; /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR 3284215976Sjmallett However, the application must not change this field. */ 3285215976Sjmallett uint32_t hp_s : 1; /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR 3286215976Sjmallett However, the application must not change this field. */ 3287215976Sjmallett uint32_t pip : 1; /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR 3288215976Sjmallett However, the application must not change this field. */ 3289215976Sjmallett uint32_t aip : 1; /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR 3290215976Sjmallett However, the application must not change this field. */ 3291215976Sjmallett uint32_t mrlsp : 1; /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR 3292215976Sjmallett However, the application must not change this field. */ 3293215976Sjmallett uint32_t pcp : 1; /**< Power Controller Present, writable through PEM(0..1)_CFG_WR 3294215976Sjmallett However, the application must not change this field. */ 3295215976Sjmallett uint32_t abp : 1; /**< Attention Button Present, writable through PEM(0..1)_CFG_WR 3296215976Sjmallett However, the application must not change this field. */ 3297215976Sjmallett#else 3298215976Sjmallett uint32_t abp : 1; 3299215976Sjmallett uint32_t pcp : 1; 3300215976Sjmallett uint32_t mrlsp : 1; 3301215976Sjmallett uint32_t aip : 1; 3302215976Sjmallett uint32_t pip : 1; 3303215976Sjmallett uint32_t hp_s : 1; 3304215976Sjmallett uint32_t hp_c : 1; 3305215976Sjmallett uint32_t sp_lv : 8; 3306215976Sjmallett uint32_t sp_ls : 2; 3307215976Sjmallett uint32_t emip : 1; 3308215976Sjmallett uint32_t nccs : 1; 3309215976Sjmallett uint32_t ps_num : 13; 3310215976Sjmallett#endif 3311215976Sjmallett } s; 3312215976Sjmallett struct cvmx_pcieepx_cfg033_s cn52xx; 3313215976Sjmallett struct cvmx_pcieepx_cfg033_s cn52xxp1; 3314215976Sjmallett struct cvmx_pcieepx_cfg033_s cn56xx; 3315215976Sjmallett struct cvmx_pcieepx_cfg033_s cn56xxp1; 3316215976Sjmallett struct cvmx_pcieepx_cfg033_s cn63xx; 3317215976Sjmallett struct cvmx_pcieepx_cfg033_s cn63xxp1; 3318215976Sjmallett}; 3319215976Sjmalletttypedef union cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg033_t; 3320215976Sjmallett 3321215976Sjmallett/** 3322215976Sjmallett * cvmx_pcieep#_cfg034 3323215976Sjmallett * 3324215976Sjmallett * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space 3325215976Sjmallett * (Slot Control Register/Slot Status Register) 3326215976Sjmallett */ 3327232812Sjmallettunion cvmx_pcieepx_cfg034 { 3328215976Sjmallett uint32_t u32; 3329232812Sjmallett struct cvmx_pcieepx_cfg034_s { 3330232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3331215976Sjmallett uint32_t reserved_25_31 : 7; 3332215976Sjmallett uint32_t dlls_c : 1; /**< Data Link Layer State Changed 3333215976Sjmallett Not applicable for an upstream Port or Endpoint device, 3334215976Sjmallett hardwired to 0. */ 3335215976Sjmallett uint32_t emis : 1; /**< Electromechanical Interlock Status */ 3336215976Sjmallett uint32_t pds : 1; /**< Presence Detect State */ 3337215976Sjmallett uint32_t mrlss : 1; /**< MRL Sensor State */ 3338215976Sjmallett uint32_t ccint_d : 1; /**< Command Completed */ 3339215976Sjmallett uint32_t pd_c : 1; /**< Presence Detect Changed */ 3340215976Sjmallett uint32_t mrls_c : 1; /**< MRL Sensor Changed */ 3341215976Sjmallett uint32_t pf_d : 1; /**< Power Fault Detected */ 3342215976Sjmallett uint32_t abp_d : 1; /**< Attention Button Pressed */ 3343215976Sjmallett uint32_t reserved_13_15 : 3; 3344215976Sjmallett uint32_t dlls_en : 1; /**< Data Link Layer State Changed Enable 3345215976Sjmallett Not applicable for an upstream Port or Endpoint device, 3346215976Sjmallett hardwired to 0. */ 3347215976Sjmallett uint32_t emic : 1; /**< Electromechanical Interlock Control */ 3348215976Sjmallett uint32_t pcc : 1; /**< Power Controller Control */ 3349215976Sjmallett uint32_t pic : 2; /**< Power Indicator Control */ 3350215976Sjmallett uint32_t aic : 2; /**< Attention Indicator Control */ 3351215976Sjmallett uint32_t hpint_en : 1; /**< Hot-Plug Interrupt Enable */ 3352215976Sjmallett uint32_t ccint_en : 1; /**< Command Completed Interrupt Enable */ 3353215976Sjmallett uint32_t pd_en : 1; /**< Presence Detect Changed Enable */ 3354215976Sjmallett uint32_t mrls_en : 1; /**< MRL Sensor Changed Enable */ 3355215976Sjmallett uint32_t pf_en : 1; /**< Power Fault Detected Enable */ 3356215976Sjmallett uint32_t abp_en : 1; /**< Attention Button Pressed Enable */ 3357215976Sjmallett#else 3358215976Sjmallett uint32_t abp_en : 1; 3359215976Sjmallett uint32_t pf_en : 1; 3360215976Sjmallett uint32_t mrls_en : 1; 3361215976Sjmallett uint32_t pd_en : 1; 3362215976Sjmallett uint32_t ccint_en : 1; 3363215976Sjmallett uint32_t hpint_en : 1; 3364215976Sjmallett uint32_t aic : 2; 3365215976Sjmallett uint32_t pic : 2; 3366215976Sjmallett uint32_t pcc : 1; 3367215976Sjmallett uint32_t emic : 1; 3368215976Sjmallett uint32_t dlls_en : 1; 3369215976Sjmallett uint32_t reserved_13_15 : 3; 3370215976Sjmallett uint32_t abp_d : 1; 3371215976Sjmallett uint32_t pf_d : 1; 3372215976Sjmallett uint32_t mrls_c : 1; 3373215976Sjmallett uint32_t pd_c : 1; 3374215976Sjmallett uint32_t ccint_d : 1; 3375215976Sjmallett uint32_t mrlss : 1; 3376215976Sjmallett uint32_t pds : 1; 3377215976Sjmallett uint32_t emis : 1; 3378215976Sjmallett uint32_t dlls_c : 1; 3379215976Sjmallett uint32_t reserved_25_31 : 7; 3380215976Sjmallett#endif 3381215976Sjmallett } s; 3382215976Sjmallett struct cvmx_pcieepx_cfg034_s cn52xx; 3383215976Sjmallett struct cvmx_pcieepx_cfg034_s cn52xxp1; 3384215976Sjmallett struct cvmx_pcieepx_cfg034_s cn56xx; 3385215976Sjmallett struct cvmx_pcieepx_cfg034_s cn56xxp1; 3386215976Sjmallett struct cvmx_pcieepx_cfg034_s cn63xx; 3387215976Sjmallett struct cvmx_pcieepx_cfg034_s cn63xxp1; 3388215976Sjmallett}; 3389215976Sjmalletttypedef union cvmx_pcieepx_cfg034 cvmx_pcieepx_cfg034_t; 3390215976Sjmallett 3391215976Sjmallett/** 3392215976Sjmallett * cvmx_pcieep#_cfg037 3393215976Sjmallett * 3394215976Sjmallett * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 0 config space 3395215976Sjmallett * (Device Capabilities 2 Register) 3396215976Sjmallett */ 3397232812Sjmallettunion cvmx_pcieepx_cfg037 { 3398215976Sjmallett uint32_t u32; 3399232812Sjmallett struct cvmx_pcieepx_cfg037_s { 3400232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3401232812Sjmallett uint32_t reserved_20_31 : 12; 3402232812Sjmallett uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported 3403232812Sjmallett (Not Supported) */ 3404232812Sjmallett uint32_t reserved_12_17 : 6; 3405232812Sjmallett uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported 3406232812Sjmallett (Not Supported) */ 3407232812Sjmallett uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3408232812Sjmallett (This bit applies to RCs) */ 3409232812Sjmallett uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3410232812Sjmallett (Not Supported) */ 3411232812Sjmallett uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3412232812Sjmallett (Not Supported) */ 3413232812Sjmallett uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3414232812Sjmallett (Not Supported) */ 3415232812Sjmallett uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3416232812Sjmallett (Not Applicable for EP) */ 3417232812Sjmallett uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3418232812Sjmallett (Not Supported) */ 3419232812Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3420232812Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3421232812Sjmallett#else 3422232812Sjmallett uint32_t ctrs : 4; 3423232812Sjmallett uint32_t ctds : 1; 3424232812Sjmallett uint32_t ari : 1; 3425232812Sjmallett uint32_t atom_ops : 1; 3426232812Sjmallett uint32_t atom32s : 1; 3427232812Sjmallett uint32_t atom64s : 1; 3428232812Sjmallett uint32_t atom128s : 1; 3429232812Sjmallett uint32_t noroprpr : 1; 3430232812Sjmallett uint32_t ltrs : 1; 3431232812Sjmallett uint32_t reserved_12_17 : 6; 3432232812Sjmallett uint32_t obffs : 2; 3433232812Sjmallett uint32_t reserved_20_31 : 12; 3434232812Sjmallett#endif 3435232812Sjmallett } s; 3436232812Sjmallett struct cvmx_pcieepx_cfg037_cn52xx { 3437232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3438215976Sjmallett uint32_t reserved_5_31 : 27; 3439215976Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3440215976Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported 3441215976Sjmallett Value of 0 indicates that Completion Timeout Programming 3442215976Sjmallett is not supported 3443215976Sjmallett Completion timeout is 16.7ms. */ 3444215976Sjmallett#else 3445215976Sjmallett uint32_t ctrs : 4; 3446215976Sjmallett uint32_t ctds : 1; 3447215976Sjmallett uint32_t reserved_5_31 : 27; 3448215976Sjmallett#endif 3449232812Sjmallett } cn52xx; 3450232812Sjmallett struct cvmx_pcieepx_cfg037_cn52xx cn52xxp1; 3451232812Sjmallett struct cvmx_pcieepx_cfg037_cn52xx cn56xx; 3452232812Sjmallett struct cvmx_pcieepx_cfg037_cn52xx cn56xxp1; 3453232812Sjmallett struct cvmx_pcieepx_cfg037_cn61xx { 3454232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3455232812Sjmallett uint32_t reserved_14_31 : 18; 3456232812Sjmallett uint32_t tph : 2; /**< TPH Completer Supported 3457232812Sjmallett (Not Supported) */ 3458232812Sjmallett uint32_t reserved_11_11 : 1; 3459232812Sjmallett uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3460232812Sjmallett (This bit applies to RCs) */ 3461232812Sjmallett uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3462232812Sjmallett (Not Supported) */ 3463232812Sjmallett uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3464232812Sjmallett (Not Supported) */ 3465232812Sjmallett uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3466232812Sjmallett (Not Supported) */ 3467232812Sjmallett uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3468232812Sjmallett (Not Applicable for EP) */ 3469232812Sjmallett uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3470232812Sjmallett (Not Supported) */ 3471232812Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3472232812Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3473232812Sjmallett#else 3474232812Sjmallett uint32_t ctrs : 4; 3475232812Sjmallett uint32_t ctds : 1; 3476232812Sjmallett uint32_t ari : 1; 3477232812Sjmallett uint32_t atom_ops : 1; 3478232812Sjmallett uint32_t atom32s : 1; 3479232812Sjmallett uint32_t atom64s : 1; 3480232812Sjmallett uint32_t atom128s : 1; 3481232812Sjmallett uint32_t noroprpr : 1; 3482232812Sjmallett uint32_t reserved_11_11 : 1; 3483232812Sjmallett uint32_t tph : 2; 3484232812Sjmallett uint32_t reserved_14_31 : 18; 3485232812Sjmallett#endif 3486232812Sjmallett } cn61xx; 3487232812Sjmallett struct cvmx_pcieepx_cfg037_cn52xx cn63xx; 3488232812Sjmallett struct cvmx_pcieepx_cfg037_cn52xx cn63xxp1; 3489232812Sjmallett struct cvmx_pcieepx_cfg037_cn61xx cn66xx; 3490232812Sjmallett struct cvmx_pcieepx_cfg037_cn61xx cn68xx; 3491232812Sjmallett struct cvmx_pcieepx_cfg037_cn61xx cn68xxp1; 3492232812Sjmallett struct cvmx_pcieepx_cfg037_cnf71xx { 3493232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3494232812Sjmallett uint32_t reserved_20_31 : 12; 3495232812Sjmallett uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported 3496232812Sjmallett (Not Supported) */ 3497232812Sjmallett uint32_t reserved_14_17 : 4; 3498232812Sjmallett uint32_t tphs : 2; /**< TPH Completer Supported 3499232812Sjmallett (Not Supported) */ 3500232812Sjmallett uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported 3501232812Sjmallett (Not Supported) */ 3502232812Sjmallett uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3503232812Sjmallett (This bit applies to RCs) */ 3504232812Sjmallett uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3505232812Sjmallett (Not Supported) */ 3506232812Sjmallett uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3507232812Sjmallett (Not Supported) */ 3508232812Sjmallett uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3509232812Sjmallett (Not Supported) */ 3510232812Sjmallett uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3511232812Sjmallett (Not Applicable for EP) */ 3512232812Sjmallett uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3513232812Sjmallett (Not Supported) */ 3514232812Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3515232812Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3516232812Sjmallett#else 3517232812Sjmallett uint32_t ctrs : 4; 3518232812Sjmallett uint32_t ctds : 1; 3519232812Sjmallett uint32_t ari : 1; 3520232812Sjmallett uint32_t atom_ops : 1; 3521232812Sjmallett uint32_t atom32s : 1; 3522232812Sjmallett uint32_t atom64s : 1; 3523232812Sjmallett uint32_t atom128s : 1; 3524232812Sjmallett uint32_t noroprpr : 1; 3525232812Sjmallett uint32_t ltrs : 1; 3526232812Sjmallett uint32_t tphs : 2; 3527232812Sjmallett uint32_t reserved_14_17 : 4; 3528232812Sjmallett uint32_t obffs : 2; 3529232812Sjmallett uint32_t reserved_20_31 : 12; 3530232812Sjmallett#endif 3531232812Sjmallett } cnf71xx; 3532215976Sjmallett}; 3533215976Sjmalletttypedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t; 3534215976Sjmallett 3535215976Sjmallett/** 3536215976Sjmallett * cvmx_pcieep#_cfg038 3537215976Sjmallett * 3538215976Sjmallett * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 0 config space 3539215976Sjmallett * (Device Control 2 Register/Device Status 2 Register) 3540215976Sjmallett */ 3541232812Sjmallettunion cvmx_pcieepx_cfg038 { 3542215976Sjmallett uint32_t u32; 3543232812Sjmallett struct cvmx_pcieepx_cfg038_s { 3544232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3545232812Sjmallett uint32_t reserved_15_31 : 17; 3546232812Sjmallett uint32_t obffe : 2; /**< Optimized Buffer Flush Fill (OBFF) Enable 3547232812Sjmallett (Not Supported) */ 3548232812Sjmallett uint32_t reserved_11_12 : 2; 3549232812Sjmallett uint32_t ltre : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Enable 3550232812Sjmallett (Not Supported) */ 3551232812Sjmallett uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable 3552232812Sjmallett (Not Supported) */ 3553232812Sjmallett uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable 3554232812Sjmallett (Not Supported) */ 3555232812Sjmallett uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking 3556232812Sjmallett (Not Supported)m */ 3557232812Sjmallett uint32_t atom_op : 1; /**< AtomicOp Requester Enable 3558232812Sjmallett (Not Supported) */ 3559232812Sjmallett uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3560232812Sjmallett (Not Supported) */ 3561232812Sjmallett uint32_t ctd : 1; /**< Completion Timeout Disable */ 3562232812Sjmallett uint32_t ctv : 4; /**< Completion Timeout Value 3563232812Sjmallett Completion Timeout Programming is not supported 3564232812Sjmallett Completion timeout is the range of 16 ms to 55 ms. */ 3565232812Sjmallett#else 3566232812Sjmallett uint32_t ctv : 4; 3567232812Sjmallett uint32_t ctd : 1; 3568232812Sjmallett uint32_t ari : 1; 3569232812Sjmallett uint32_t atom_op : 1; 3570232812Sjmallett uint32_t atom_op_eb : 1; 3571232812Sjmallett uint32_t id0_rq : 1; 3572232812Sjmallett uint32_t id0_cp : 1; 3573232812Sjmallett uint32_t ltre : 1; 3574232812Sjmallett uint32_t reserved_11_12 : 2; 3575232812Sjmallett uint32_t obffe : 2; 3576232812Sjmallett uint32_t reserved_15_31 : 17; 3577232812Sjmallett#endif 3578232812Sjmallett } s; 3579232812Sjmallett struct cvmx_pcieepx_cfg038_cn52xx { 3580232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3581215976Sjmallett uint32_t reserved_5_31 : 27; 3582215976Sjmallett uint32_t ctd : 1; /**< Completion Timeout Disable */ 3583215976Sjmallett uint32_t ctv : 4; /**< Completion Timeout Value 3584215976Sjmallett Completion Timeout Programming is not supported 3585215976Sjmallett Completion timeout is 16.7ms. */ 3586215976Sjmallett#else 3587215976Sjmallett uint32_t ctv : 4; 3588215976Sjmallett uint32_t ctd : 1; 3589215976Sjmallett uint32_t reserved_5_31 : 27; 3590215976Sjmallett#endif 3591232812Sjmallett } cn52xx; 3592232812Sjmallett struct cvmx_pcieepx_cfg038_cn52xx cn52xxp1; 3593232812Sjmallett struct cvmx_pcieepx_cfg038_cn52xx cn56xx; 3594232812Sjmallett struct cvmx_pcieepx_cfg038_cn52xx cn56xxp1; 3595232812Sjmallett struct cvmx_pcieepx_cfg038_cn61xx { 3596232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3597232812Sjmallett uint32_t reserved_10_31 : 22; 3598232812Sjmallett uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable 3599232812Sjmallett (Not Supported) */ 3600232812Sjmallett uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable 3601232812Sjmallett (Not Supported) */ 3602232812Sjmallett uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking 3603232812Sjmallett (Not Supported)m */ 3604232812Sjmallett uint32_t atom_op : 1; /**< AtomicOp Requester Enable 3605232812Sjmallett (Not Supported) */ 3606232812Sjmallett uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3607232812Sjmallett (Not Supported) */ 3608232812Sjmallett uint32_t ctd : 1; /**< Completion Timeout Disable */ 3609232812Sjmallett uint32_t ctv : 4; /**< Completion Timeout Value 3610232812Sjmallett Completion Timeout Programming is not supported 3611232812Sjmallett Completion timeout is the range of 16 ms to 55 ms. */ 3612232812Sjmallett#else 3613232812Sjmallett uint32_t ctv : 4; 3614232812Sjmallett uint32_t ctd : 1; 3615232812Sjmallett uint32_t ari : 1; 3616232812Sjmallett uint32_t atom_op : 1; 3617232812Sjmallett uint32_t atom_op_eb : 1; 3618232812Sjmallett uint32_t id0_rq : 1; 3619232812Sjmallett uint32_t id0_cp : 1; 3620232812Sjmallett uint32_t reserved_10_31 : 22; 3621232812Sjmallett#endif 3622232812Sjmallett } cn61xx; 3623232812Sjmallett struct cvmx_pcieepx_cfg038_cn52xx cn63xx; 3624232812Sjmallett struct cvmx_pcieepx_cfg038_cn52xx cn63xxp1; 3625232812Sjmallett struct cvmx_pcieepx_cfg038_cn61xx cn66xx; 3626232812Sjmallett struct cvmx_pcieepx_cfg038_cn61xx cn68xx; 3627232812Sjmallett struct cvmx_pcieepx_cfg038_cn61xx cn68xxp1; 3628232812Sjmallett struct cvmx_pcieepx_cfg038_s cnf71xx; 3629215976Sjmallett}; 3630215976Sjmalletttypedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t; 3631215976Sjmallett 3632215976Sjmallett/** 3633215976Sjmallett * cvmx_pcieep#_cfg039 3634215976Sjmallett * 3635215976Sjmallett * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 0 config space 3636215976Sjmallett * (Link Capabilities 2 Register) 3637215976Sjmallett */ 3638232812Sjmallettunion cvmx_pcieepx_cfg039 { 3639215976Sjmallett uint32_t u32; 3640232812Sjmallett struct cvmx_pcieepx_cfg039_s { 3641232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3642232812Sjmallett uint32_t reserved_9_31 : 23; 3643232812Sjmallett uint32_t cls : 1; /**< Crosslink Supported */ 3644232812Sjmallett uint32_t slsv : 7; /**< Supported Link Speeds Vector 3645232812Sjmallett Indicates the supported Link speeds of the associated Port. 3646232812Sjmallett For each bit, a value of 1b indicates that the cooresponding 3647232812Sjmallett Link speed is supported; otherwise, the Link speed is not 3648232812Sjmallett supported. 3649232812Sjmallett Bit definitions are: 3650232812Sjmallett Bit 1 2.5 GT/s 3651232812Sjmallett Bit 2 5.0 GT/s 3652232812Sjmallett Bit 3 8.0 GT/s (Not Supported) 3653232812Sjmallett Bits 7:4 reserved 3654232812Sjmallett The reset value of this field is controlled by a value sent from 3655232812Sjmallett the lsb of the MIO_QLM#_SPD register 3656232812Sjmallett qlm#_spd[0] RST_VALUE NOTE 3657232812Sjmallett 1 0001b 2.5 GHz supported 3658232812Sjmallett 0 0011b 5.0 GHz and 2.5 GHz supported */ 3659232812Sjmallett uint32_t reserved_0_0 : 1; 3660232812Sjmallett#else 3661232812Sjmallett uint32_t reserved_0_0 : 1; 3662232812Sjmallett uint32_t slsv : 7; 3663232812Sjmallett uint32_t cls : 1; 3664232812Sjmallett uint32_t reserved_9_31 : 23; 3665232812Sjmallett#endif 3666232812Sjmallett } s; 3667232812Sjmallett struct cvmx_pcieepx_cfg039_cn52xx { 3668232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3669215976Sjmallett uint32_t reserved_0_31 : 32; 3670215976Sjmallett#else 3671215976Sjmallett uint32_t reserved_0_31 : 32; 3672215976Sjmallett#endif 3673232812Sjmallett } cn52xx; 3674232812Sjmallett struct cvmx_pcieepx_cfg039_cn52xx cn52xxp1; 3675232812Sjmallett struct cvmx_pcieepx_cfg039_cn52xx cn56xx; 3676232812Sjmallett struct cvmx_pcieepx_cfg039_cn52xx cn56xxp1; 3677232812Sjmallett struct cvmx_pcieepx_cfg039_s cn61xx; 3678215976Sjmallett struct cvmx_pcieepx_cfg039_s cn63xx; 3679232812Sjmallett struct cvmx_pcieepx_cfg039_cn52xx cn63xxp1; 3680232812Sjmallett struct cvmx_pcieepx_cfg039_s cn66xx; 3681232812Sjmallett struct cvmx_pcieepx_cfg039_s cn68xx; 3682232812Sjmallett struct cvmx_pcieepx_cfg039_s cn68xxp1; 3683232812Sjmallett struct cvmx_pcieepx_cfg039_s cnf71xx; 3684215976Sjmallett}; 3685215976Sjmalletttypedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t; 3686215976Sjmallett 3687215976Sjmallett/** 3688215976Sjmallett * cvmx_pcieep#_cfg040 3689215976Sjmallett * 3690215976Sjmallett * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 0 config space 3691215976Sjmallett * (Link Control 2 Register/Link Status 2 Register) 3692215976Sjmallett */ 3693232812Sjmallettunion cvmx_pcieepx_cfg040 { 3694215976Sjmallett uint32_t u32; 3695232812Sjmallett struct cvmx_pcieepx_cfg040_s { 3696232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3697215976Sjmallett uint32_t reserved_17_31 : 15; 3698215976Sjmallett uint32_t cdl : 1; /**< Current De-emphasis Level 3699215976Sjmallett When the Link is operating at 5 GT/s speed, this bit 3700215976Sjmallett reflects the level of de-emphasis. Encodings: 3701215976Sjmallett 1b: -3.5 dB 3702215976Sjmallett 0b: -6 dB 3703215976Sjmallett Note: The value in this bit is undefined when the Link is 3704215976Sjmallett operating at 2.5 GT/s speed */ 3705215976Sjmallett uint32_t reserved_13_15 : 3; 3706215976Sjmallett uint32_t cde : 1; /**< Compliance De-emphasis 3707215976Sjmallett This bit sets the de-emphasis level in Polling. Compliance 3708215976Sjmallett state if the entry occurred due to the Tx Compliance 3709215976Sjmallett Receive bit being 1b. Encodings: 3710215976Sjmallett 1b: -3.5 dB 3711215976Sjmallett 0b: -6 dB 3712215976Sjmallett Note: When the Link is operating at 2.5 GT/s, the setting 3713215976Sjmallett of this bit has no effect. */ 3714215976Sjmallett uint32_t csos : 1; /**< Compliance SOS 3715215976Sjmallett When set to 1b, the LTSSM is required to send SKP 3716215976Sjmallett Ordered Sets periodically in between the (modified) 3717215976Sjmallett compliance patterns. 3718215976Sjmallett Note: When the Link is operating at 2.5 GT/s, the setting 3719215976Sjmallett of this bit has no effect. */ 3720215976Sjmallett uint32_t emc : 1; /**< Enter Modified Compliance 3721215976Sjmallett When this bit is set to 1b, the device transmits a modified 3722215976Sjmallett compliance pattern if the LTSSM enters Polling. 3723215976Sjmallett Compliance state. */ 3724215976Sjmallett uint32_t tm : 3; /**< Transmit Margin 3725215976Sjmallett This field controls the value of the non-de-emphasized 3726232812Sjmallett voltage level at the Transmitter signals: 3727215976Sjmallett - 000: 800-1200 mV for full swing 400-600 mV for half-swing 3728215976Sjmallett - 001-010: values must be monotonic with a non-zero slope 3729215976Sjmallett - 011: 200-400 mV for full-swing and 100-200 mV for halfswing 3730215976Sjmallett - 100-111: reserved 3731215976Sjmallett This field is reset to 000b on entry to the LTSSM Polling. 3732215976Sjmallett Compliance substate. 3733215976Sjmallett When operating in 5.0 GT/s mode with full swing, the 3734215976Sjmallett de-emphasis ratio must be maintained within +/- 1 dB 3735215976Sjmallett from the specification-defined operational value 3736215976Sjmallett either -3.5 or -6 dB). */ 3737215976Sjmallett uint32_t sde : 1; /**< Selectable De-emphasis 3738215976Sjmallett Not applicable for an upstream Port or Endpoint device. 3739215976Sjmallett Hardwired to 0. */ 3740215976Sjmallett uint32_t hasd : 1; /**< Hardware Autonomous Speed Disable 3741215976Sjmallett When asserted, the 3742215976Sjmallett application must disable hardware from changing the Link 3743215976Sjmallett speed for device-specific reasons other than attempting to 3744215976Sjmallett correct unreliable Link operation by reducing Link speed. 3745215976Sjmallett Initial transition to the highest supported common link 3746215976Sjmallett speed is not blocked by this signal. */ 3747215976Sjmallett uint32_t ec : 1; /**< Enter Compliance 3748215976Sjmallett Software is permitted to force a link to enter Compliance 3749215976Sjmallett mode at the speed indicated in the Target Link Speed 3750215976Sjmallett field by setting this bit to 1b in both components on a link 3751215976Sjmallett and then initiating a hot reset on the link. */ 3752215976Sjmallett uint32_t tls : 4; /**< Target Link Speed 3753215976Sjmallett For Downstream ports, this field sets an upper limit on link 3754215976Sjmallett operational speed by restricting the values advertised by 3755215976Sjmallett the upstream component in its training sequences: 3756215976Sjmallett - 0001: 2.5Gb/s Target Link Speed 3757215976Sjmallett - 0010: 5Gb/s Target Link Speed 3758232812Sjmallett - 0100: 8Gb/s Target Link Speed (Not Supported) 3759215976Sjmallett All other encodings are reserved. 3760215976Sjmallett If a value is written to this field that does not correspond to 3761215976Sjmallett a speed included in the Supported Link Speeds field, the 3762215976Sjmallett result is undefined. 3763215976Sjmallett For both Upstream and Downstream ports, this field is 3764215976Sjmallett used to set the target compliance mode speed when 3765215976Sjmallett software is using the Enter Compliance bit to force a link 3766215976Sjmallett into compliance mode. 3767232812Sjmallett The reset value of this field is controlled by a value sent from 3768232812Sjmallett the lsb of the MIO_QLM#_SPD register. 3769232812Sjmallett qlm#_spd[0] RST_VALUE NOTE 3770232812Sjmallett 1 0001b 2.5 GHz supported 3771232812Sjmallett 0 0010b 5.0 GHz and 2.5 GHz supported */ 3772215976Sjmallett#else 3773215976Sjmallett uint32_t tls : 4; 3774215976Sjmallett uint32_t ec : 1; 3775215976Sjmallett uint32_t hasd : 1; 3776215976Sjmallett uint32_t sde : 1; 3777215976Sjmallett uint32_t tm : 3; 3778215976Sjmallett uint32_t emc : 1; 3779215976Sjmallett uint32_t csos : 1; 3780215976Sjmallett uint32_t cde : 1; 3781215976Sjmallett uint32_t reserved_13_15 : 3; 3782215976Sjmallett uint32_t cdl : 1; 3783215976Sjmallett uint32_t reserved_17_31 : 15; 3784215976Sjmallett#endif 3785215976Sjmallett } s; 3786232812Sjmallett struct cvmx_pcieepx_cfg040_cn52xx { 3787232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3788215976Sjmallett uint32_t reserved_0_31 : 32; 3789215976Sjmallett#else 3790215976Sjmallett uint32_t reserved_0_31 : 32; 3791215976Sjmallett#endif 3792215976Sjmallett } cn52xx; 3793215976Sjmallett struct cvmx_pcieepx_cfg040_cn52xx cn52xxp1; 3794215976Sjmallett struct cvmx_pcieepx_cfg040_cn52xx cn56xx; 3795215976Sjmallett struct cvmx_pcieepx_cfg040_cn52xx cn56xxp1; 3796232812Sjmallett struct cvmx_pcieepx_cfg040_s cn61xx; 3797215976Sjmallett struct cvmx_pcieepx_cfg040_s cn63xx; 3798215976Sjmallett struct cvmx_pcieepx_cfg040_s cn63xxp1; 3799232812Sjmallett struct cvmx_pcieepx_cfg040_s cn66xx; 3800232812Sjmallett struct cvmx_pcieepx_cfg040_s cn68xx; 3801232812Sjmallett struct cvmx_pcieepx_cfg040_s cn68xxp1; 3802232812Sjmallett struct cvmx_pcieepx_cfg040_s cnf71xx; 3803215976Sjmallett}; 3804215976Sjmalletttypedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t; 3805215976Sjmallett 3806215976Sjmallett/** 3807215976Sjmallett * cvmx_pcieep#_cfg041 3808215976Sjmallett * 3809215976Sjmallett * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space 3810215976Sjmallett * (Slot Capabilities 2 Register) 3811215976Sjmallett */ 3812232812Sjmallettunion cvmx_pcieepx_cfg041 { 3813215976Sjmallett uint32_t u32; 3814232812Sjmallett struct cvmx_pcieepx_cfg041_s { 3815232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3816215976Sjmallett uint32_t reserved_0_31 : 32; 3817215976Sjmallett#else 3818215976Sjmallett uint32_t reserved_0_31 : 32; 3819215976Sjmallett#endif 3820215976Sjmallett } s; 3821215976Sjmallett struct cvmx_pcieepx_cfg041_s cn52xx; 3822215976Sjmallett struct cvmx_pcieepx_cfg041_s cn52xxp1; 3823215976Sjmallett struct cvmx_pcieepx_cfg041_s cn56xx; 3824215976Sjmallett struct cvmx_pcieepx_cfg041_s cn56xxp1; 3825215976Sjmallett struct cvmx_pcieepx_cfg041_s cn63xx; 3826215976Sjmallett struct cvmx_pcieepx_cfg041_s cn63xxp1; 3827215976Sjmallett}; 3828215976Sjmalletttypedef union cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg041_t; 3829215976Sjmallett 3830215976Sjmallett/** 3831215976Sjmallett * cvmx_pcieep#_cfg042 3832215976Sjmallett * 3833215976Sjmallett * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space 3834215976Sjmallett * (Slot Control 2 Register/Slot Status 2 Register) 3835215976Sjmallett */ 3836232812Sjmallettunion cvmx_pcieepx_cfg042 { 3837215976Sjmallett uint32_t u32; 3838232812Sjmallett struct cvmx_pcieepx_cfg042_s { 3839232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3840215976Sjmallett uint32_t reserved_0_31 : 32; 3841215976Sjmallett#else 3842215976Sjmallett uint32_t reserved_0_31 : 32; 3843215976Sjmallett#endif 3844215976Sjmallett } s; 3845215976Sjmallett struct cvmx_pcieepx_cfg042_s cn52xx; 3846215976Sjmallett struct cvmx_pcieepx_cfg042_s cn52xxp1; 3847215976Sjmallett struct cvmx_pcieepx_cfg042_s cn56xx; 3848215976Sjmallett struct cvmx_pcieepx_cfg042_s cn56xxp1; 3849215976Sjmallett struct cvmx_pcieepx_cfg042_s cn63xx; 3850215976Sjmallett struct cvmx_pcieepx_cfg042_s cn63xxp1; 3851215976Sjmallett}; 3852215976Sjmalletttypedef union cvmx_pcieepx_cfg042 cvmx_pcieepx_cfg042_t; 3853215976Sjmallett 3854215976Sjmallett/** 3855215976Sjmallett * cvmx_pcieep#_cfg064 3856215976Sjmallett * 3857215976Sjmallett * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 0 config space 3858232812Sjmallett * (PCI Express Extended Capability Header) 3859215976Sjmallett */ 3860232812Sjmallettunion cvmx_pcieepx_cfg064 { 3861215976Sjmallett uint32_t u32; 3862232812Sjmallett struct cvmx_pcieepx_cfg064_s { 3863232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3864215976Sjmallett uint32_t nco : 12; /**< Next Capability Offset */ 3865215976Sjmallett uint32_t cv : 4; /**< Capability Version */ 3866215976Sjmallett uint32_t pcieec : 16; /**< PCIE Express Extended Capability */ 3867215976Sjmallett#else 3868215976Sjmallett uint32_t pcieec : 16; 3869215976Sjmallett uint32_t cv : 4; 3870215976Sjmallett uint32_t nco : 12; 3871215976Sjmallett#endif 3872215976Sjmallett } s; 3873215976Sjmallett struct cvmx_pcieepx_cfg064_s cn52xx; 3874215976Sjmallett struct cvmx_pcieepx_cfg064_s cn52xxp1; 3875215976Sjmallett struct cvmx_pcieepx_cfg064_s cn56xx; 3876215976Sjmallett struct cvmx_pcieepx_cfg064_s cn56xxp1; 3877232812Sjmallett struct cvmx_pcieepx_cfg064_s cn61xx; 3878215976Sjmallett struct cvmx_pcieepx_cfg064_s cn63xx; 3879215976Sjmallett struct cvmx_pcieepx_cfg064_s cn63xxp1; 3880232812Sjmallett struct cvmx_pcieepx_cfg064_s cn66xx; 3881232812Sjmallett struct cvmx_pcieepx_cfg064_s cn68xx; 3882232812Sjmallett struct cvmx_pcieepx_cfg064_s cn68xxp1; 3883232812Sjmallett struct cvmx_pcieepx_cfg064_s cnf71xx; 3884215976Sjmallett}; 3885215976Sjmalletttypedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t; 3886215976Sjmallett 3887215976Sjmallett/** 3888215976Sjmallett * cvmx_pcieep#_cfg065 3889215976Sjmallett * 3890215976Sjmallett * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 0 config space 3891215976Sjmallett * (Uncorrectable Error Status Register) 3892215976Sjmallett */ 3893232812Sjmallettunion cvmx_pcieepx_cfg065 { 3894215976Sjmallett uint32_t u32; 3895232812Sjmallett struct cvmx_pcieepx_cfg065_s { 3896232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3897232812Sjmallett uint32_t reserved_25_31 : 7; 3898232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 3899232812Sjmallett uint32_t reserved_23_23 : 1; 3900232812Sjmallett uint32_t ucies : 1; /**< Uncorrectable Internal Error Status */ 3901232812Sjmallett uint32_t reserved_21_21 : 1; 3902232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Status */ 3903232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Status */ 3904232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Status */ 3905232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Status */ 3906232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Status */ 3907232812Sjmallett uint32_t cas : 1; /**< Completer Abort Status */ 3908232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Status */ 3909232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3910232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3911232812Sjmallett uint32_t reserved_6_11 : 6; 3912232812Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3913232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3914232812Sjmallett uint32_t reserved_0_3 : 4; 3915232812Sjmallett#else 3916232812Sjmallett uint32_t reserved_0_3 : 4; 3917232812Sjmallett uint32_t dlpes : 1; 3918232812Sjmallett uint32_t sdes : 1; 3919232812Sjmallett uint32_t reserved_6_11 : 6; 3920232812Sjmallett uint32_t ptlps : 1; 3921232812Sjmallett uint32_t fcpes : 1; 3922232812Sjmallett uint32_t cts : 1; 3923232812Sjmallett uint32_t cas : 1; 3924232812Sjmallett uint32_t ucs : 1; 3925232812Sjmallett uint32_t ros : 1; 3926232812Sjmallett uint32_t mtlps : 1; 3927232812Sjmallett uint32_t ecrces : 1; 3928232812Sjmallett uint32_t ures : 1; 3929232812Sjmallett uint32_t reserved_21_21 : 1; 3930232812Sjmallett uint32_t ucies : 1; 3931232812Sjmallett uint32_t reserved_23_23 : 1; 3932232812Sjmallett uint32_t uatombs : 1; 3933232812Sjmallett uint32_t reserved_25_31 : 7; 3934232812Sjmallett#endif 3935232812Sjmallett } s; 3936232812Sjmallett struct cvmx_pcieepx_cfg065_cn52xx { 3937232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3938215976Sjmallett uint32_t reserved_21_31 : 11; 3939215976Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Status */ 3940215976Sjmallett uint32_t ecrces : 1; /**< ECRC Error Status */ 3941215976Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Status */ 3942215976Sjmallett uint32_t ros : 1; /**< Receiver Overflow Status */ 3943215976Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Status */ 3944215976Sjmallett uint32_t cas : 1; /**< Completer Abort Status */ 3945215976Sjmallett uint32_t cts : 1; /**< Completion Timeout Status */ 3946215976Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3947215976Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3948215976Sjmallett uint32_t reserved_6_11 : 6; 3949215976Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3950215976Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3951215976Sjmallett uint32_t reserved_0_3 : 4; 3952215976Sjmallett#else 3953215976Sjmallett uint32_t reserved_0_3 : 4; 3954215976Sjmallett uint32_t dlpes : 1; 3955215976Sjmallett uint32_t sdes : 1; 3956215976Sjmallett uint32_t reserved_6_11 : 6; 3957215976Sjmallett uint32_t ptlps : 1; 3958215976Sjmallett uint32_t fcpes : 1; 3959215976Sjmallett uint32_t cts : 1; 3960215976Sjmallett uint32_t cas : 1; 3961215976Sjmallett uint32_t ucs : 1; 3962215976Sjmallett uint32_t ros : 1; 3963215976Sjmallett uint32_t mtlps : 1; 3964215976Sjmallett uint32_t ecrces : 1; 3965215976Sjmallett uint32_t ures : 1; 3966215976Sjmallett uint32_t reserved_21_31 : 11; 3967215976Sjmallett#endif 3968232812Sjmallett } cn52xx; 3969232812Sjmallett struct cvmx_pcieepx_cfg065_cn52xx cn52xxp1; 3970232812Sjmallett struct cvmx_pcieepx_cfg065_cn52xx cn56xx; 3971232812Sjmallett struct cvmx_pcieepx_cfg065_cn52xx cn56xxp1; 3972232812Sjmallett struct cvmx_pcieepx_cfg065_cn61xx { 3973232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3974232812Sjmallett uint32_t reserved_25_31 : 7; 3975232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 3976232812Sjmallett uint32_t reserved_21_23 : 3; 3977232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Status */ 3978232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Status */ 3979232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Status */ 3980232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Status */ 3981232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Status */ 3982232812Sjmallett uint32_t cas : 1; /**< Completer Abort Status */ 3983232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Status */ 3984232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3985232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3986232812Sjmallett uint32_t reserved_6_11 : 6; 3987232812Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3988232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3989232812Sjmallett uint32_t reserved_0_3 : 4; 3990232812Sjmallett#else 3991232812Sjmallett uint32_t reserved_0_3 : 4; 3992232812Sjmallett uint32_t dlpes : 1; 3993232812Sjmallett uint32_t sdes : 1; 3994232812Sjmallett uint32_t reserved_6_11 : 6; 3995232812Sjmallett uint32_t ptlps : 1; 3996232812Sjmallett uint32_t fcpes : 1; 3997232812Sjmallett uint32_t cts : 1; 3998232812Sjmallett uint32_t cas : 1; 3999232812Sjmallett uint32_t ucs : 1; 4000232812Sjmallett uint32_t ros : 1; 4001232812Sjmallett uint32_t mtlps : 1; 4002232812Sjmallett uint32_t ecrces : 1; 4003232812Sjmallett uint32_t ures : 1; 4004232812Sjmallett uint32_t reserved_21_23 : 3; 4005232812Sjmallett uint32_t uatombs : 1; 4006232812Sjmallett uint32_t reserved_25_31 : 7; 4007232812Sjmallett#endif 4008232812Sjmallett } cn61xx; 4009232812Sjmallett struct cvmx_pcieepx_cfg065_cn52xx cn63xx; 4010232812Sjmallett struct cvmx_pcieepx_cfg065_cn52xx cn63xxp1; 4011232812Sjmallett struct cvmx_pcieepx_cfg065_cn61xx cn66xx; 4012232812Sjmallett struct cvmx_pcieepx_cfg065_cn61xx cn68xx; 4013232812Sjmallett struct cvmx_pcieepx_cfg065_cn52xx cn68xxp1; 4014232812Sjmallett struct cvmx_pcieepx_cfg065_cnf71xx { 4015232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4016232812Sjmallett uint32_t reserved_25_31 : 7; 4017232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 4018232812Sjmallett uint32_t reserved_23_23 : 1; 4019232812Sjmallett uint32_t ucies : 1; /**< Uncorrectable Internal Error Status */ 4020232812Sjmallett uint32_t reserved_21_21 : 1; 4021232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Status */ 4022232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Status */ 4023232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Status */ 4024232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Status */ 4025232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Status */ 4026232812Sjmallett uint32_t cas : 1; /**< Completer Abort Status */ 4027232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Status */ 4028232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 4029232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Status */ 4030232812Sjmallett uint32_t reserved_5_11 : 7; 4031232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 4032232812Sjmallett uint32_t reserved_0_3 : 4; 4033232812Sjmallett#else 4034232812Sjmallett uint32_t reserved_0_3 : 4; 4035232812Sjmallett uint32_t dlpes : 1; 4036232812Sjmallett uint32_t reserved_5_11 : 7; 4037232812Sjmallett uint32_t ptlps : 1; 4038232812Sjmallett uint32_t fcpes : 1; 4039232812Sjmallett uint32_t cts : 1; 4040232812Sjmallett uint32_t cas : 1; 4041232812Sjmallett uint32_t ucs : 1; 4042232812Sjmallett uint32_t ros : 1; 4043232812Sjmallett uint32_t mtlps : 1; 4044232812Sjmallett uint32_t ecrces : 1; 4045232812Sjmallett uint32_t ures : 1; 4046232812Sjmallett uint32_t reserved_21_21 : 1; 4047232812Sjmallett uint32_t ucies : 1; 4048232812Sjmallett uint32_t reserved_23_23 : 1; 4049232812Sjmallett uint32_t uatombs : 1; 4050232812Sjmallett uint32_t reserved_25_31 : 7; 4051232812Sjmallett#endif 4052232812Sjmallett } cnf71xx; 4053215976Sjmallett}; 4054215976Sjmalletttypedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t; 4055215976Sjmallett 4056215976Sjmallett/** 4057215976Sjmallett * cvmx_pcieep#_cfg066 4058215976Sjmallett * 4059215976Sjmallett * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 0 config space 4060215976Sjmallett * (Uncorrectable Error Mask Register) 4061215976Sjmallett */ 4062232812Sjmallettunion cvmx_pcieepx_cfg066 { 4063215976Sjmallett uint32_t u32; 4064232812Sjmallett struct cvmx_pcieepx_cfg066_s { 4065232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4066232812Sjmallett uint32_t reserved_25_31 : 7; 4067232812Sjmallett uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 4068232812Sjmallett uint32_t reserved_23_23 : 1; 4069232812Sjmallett uint32_t uciem : 1; /**< Uncorrectable Internal Error Mask */ 4070232812Sjmallett uint32_t reserved_21_21 : 1; 4071232812Sjmallett uint32_t urem : 1; /**< Unsupported Request Error Mask */ 4072232812Sjmallett uint32_t ecrcem : 1; /**< ECRC Error Mask */ 4073232812Sjmallett uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 4074232812Sjmallett uint32_t rom : 1; /**< Receiver Overflow Mask */ 4075232812Sjmallett uint32_t ucm : 1; /**< Unexpected Completion Mask */ 4076232812Sjmallett uint32_t cam : 1; /**< Completer Abort Mask */ 4077232812Sjmallett uint32_t ctm : 1; /**< Completion Timeout Mask */ 4078232812Sjmallett uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 4079232812Sjmallett uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 4080232812Sjmallett uint32_t reserved_6_11 : 6; 4081232812Sjmallett uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 4082232812Sjmallett uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 4083232812Sjmallett uint32_t reserved_0_3 : 4; 4084232812Sjmallett#else 4085232812Sjmallett uint32_t reserved_0_3 : 4; 4086232812Sjmallett uint32_t dlpem : 1; 4087232812Sjmallett uint32_t sdem : 1; 4088232812Sjmallett uint32_t reserved_6_11 : 6; 4089232812Sjmallett uint32_t ptlpm : 1; 4090232812Sjmallett uint32_t fcpem : 1; 4091232812Sjmallett uint32_t ctm : 1; 4092232812Sjmallett uint32_t cam : 1; 4093232812Sjmallett uint32_t ucm : 1; 4094232812Sjmallett uint32_t rom : 1; 4095232812Sjmallett uint32_t mtlpm : 1; 4096232812Sjmallett uint32_t ecrcem : 1; 4097232812Sjmallett uint32_t urem : 1; 4098232812Sjmallett uint32_t reserved_21_21 : 1; 4099232812Sjmallett uint32_t uciem : 1; 4100232812Sjmallett uint32_t reserved_23_23 : 1; 4101232812Sjmallett uint32_t uatombm : 1; 4102232812Sjmallett uint32_t reserved_25_31 : 7; 4103232812Sjmallett#endif 4104232812Sjmallett } s; 4105232812Sjmallett struct cvmx_pcieepx_cfg066_cn52xx { 4106232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4107215976Sjmallett uint32_t reserved_21_31 : 11; 4108215976Sjmallett uint32_t urem : 1; /**< Unsupported Request Error Mask */ 4109215976Sjmallett uint32_t ecrcem : 1; /**< ECRC Error Mask */ 4110215976Sjmallett uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 4111215976Sjmallett uint32_t rom : 1; /**< Receiver Overflow Mask */ 4112215976Sjmallett uint32_t ucm : 1; /**< Unexpected Completion Mask */ 4113215976Sjmallett uint32_t cam : 1; /**< Completer Abort Mask */ 4114215976Sjmallett uint32_t ctm : 1; /**< Completion Timeout Mask */ 4115215976Sjmallett uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 4116215976Sjmallett uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 4117215976Sjmallett uint32_t reserved_6_11 : 6; 4118215976Sjmallett uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 4119215976Sjmallett uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 4120215976Sjmallett uint32_t reserved_0_3 : 4; 4121215976Sjmallett#else 4122215976Sjmallett uint32_t reserved_0_3 : 4; 4123215976Sjmallett uint32_t dlpem : 1; 4124215976Sjmallett uint32_t sdem : 1; 4125215976Sjmallett uint32_t reserved_6_11 : 6; 4126215976Sjmallett uint32_t ptlpm : 1; 4127215976Sjmallett uint32_t fcpem : 1; 4128215976Sjmallett uint32_t ctm : 1; 4129215976Sjmallett uint32_t cam : 1; 4130215976Sjmallett uint32_t ucm : 1; 4131215976Sjmallett uint32_t rom : 1; 4132215976Sjmallett uint32_t mtlpm : 1; 4133215976Sjmallett uint32_t ecrcem : 1; 4134215976Sjmallett uint32_t urem : 1; 4135215976Sjmallett uint32_t reserved_21_31 : 11; 4136215976Sjmallett#endif 4137232812Sjmallett } cn52xx; 4138232812Sjmallett struct cvmx_pcieepx_cfg066_cn52xx cn52xxp1; 4139232812Sjmallett struct cvmx_pcieepx_cfg066_cn52xx cn56xx; 4140232812Sjmallett struct cvmx_pcieepx_cfg066_cn52xx cn56xxp1; 4141232812Sjmallett struct cvmx_pcieepx_cfg066_cn61xx { 4142232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4143232812Sjmallett uint32_t reserved_25_31 : 7; 4144232812Sjmallett uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 4145232812Sjmallett uint32_t reserved_21_23 : 3; 4146232812Sjmallett uint32_t urem : 1; /**< Unsupported Request Error Mask */ 4147232812Sjmallett uint32_t ecrcem : 1; /**< ECRC Error Mask */ 4148232812Sjmallett uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 4149232812Sjmallett uint32_t rom : 1; /**< Receiver Overflow Mask */ 4150232812Sjmallett uint32_t ucm : 1; /**< Unexpected Completion Mask */ 4151232812Sjmallett uint32_t cam : 1; /**< Completer Abort Mask */ 4152232812Sjmallett uint32_t ctm : 1; /**< Completion Timeout Mask */ 4153232812Sjmallett uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 4154232812Sjmallett uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 4155232812Sjmallett uint32_t reserved_6_11 : 6; 4156232812Sjmallett uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 4157232812Sjmallett uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 4158232812Sjmallett uint32_t reserved_0_3 : 4; 4159232812Sjmallett#else 4160232812Sjmallett uint32_t reserved_0_3 : 4; 4161232812Sjmallett uint32_t dlpem : 1; 4162232812Sjmallett uint32_t sdem : 1; 4163232812Sjmallett uint32_t reserved_6_11 : 6; 4164232812Sjmallett uint32_t ptlpm : 1; 4165232812Sjmallett uint32_t fcpem : 1; 4166232812Sjmallett uint32_t ctm : 1; 4167232812Sjmallett uint32_t cam : 1; 4168232812Sjmallett uint32_t ucm : 1; 4169232812Sjmallett uint32_t rom : 1; 4170232812Sjmallett uint32_t mtlpm : 1; 4171232812Sjmallett uint32_t ecrcem : 1; 4172232812Sjmallett uint32_t urem : 1; 4173232812Sjmallett uint32_t reserved_21_23 : 3; 4174232812Sjmallett uint32_t uatombm : 1; 4175232812Sjmallett uint32_t reserved_25_31 : 7; 4176232812Sjmallett#endif 4177232812Sjmallett } cn61xx; 4178232812Sjmallett struct cvmx_pcieepx_cfg066_cn52xx cn63xx; 4179232812Sjmallett struct cvmx_pcieepx_cfg066_cn52xx cn63xxp1; 4180232812Sjmallett struct cvmx_pcieepx_cfg066_cn61xx cn66xx; 4181232812Sjmallett struct cvmx_pcieepx_cfg066_cn61xx cn68xx; 4182232812Sjmallett struct cvmx_pcieepx_cfg066_cn52xx cn68xxp1; 4183232812Sjmallett struct cvmx_pcieepx_cfg066_cnf71xx { 4184232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4185232812Sjmallett uint32_t reserved_25_31 : 7; 4186232812Sjmallett uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 4187232812Sjmallett uint32_t reserved_23_23 : 1; 4188232812Sjmallett uint32_t uciem : 1; /**< Uncorrectable Internal Error Mask */ 4189232812Sjmallett uint32_t reserved_21_21 : 1; 4190232812Sjmallett uint32_t urem : 1; /**< Unsupported Request Error Mask */ 4191232812Sjmallett uint32_t ecrcem : 1; /**< ECRC Error Mask */ 4192232812Sjmallett uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 4193232812Sjmallett uint32_t rom : 1; /**< Receiver Overflow Mask */ 4194232812Sjmallett uint32_t ucm : 1; /**< Unexpected Completion Mask */ 4195232812Sjmallett uint32_t cam : 1; /**< Completer Abort Mask */ 4196232812Sjmallett uint32_t ctm : 1; /**< Completion Timeout Mask */ 4197232812Sjmallett uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 4198232812Sjmallett uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 4199232812Sjmallett uint32_t reserved_5_11 : 7; 4200232812Sjmallett uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 4201232812Sjmallett uint32_t reserved_0_3 : 4; 4202232812Sjmallett#else 4203232812Sjmallett uint32_t reserved_0_3 : 4; 4204232812Sjmallett uint32_t dlpem : 1; 4205232812Sjmallett uint32_t reserved_5_11 : 7; 4206232812Sjmallett uint32_t ptlpm : 1; 4207232812Sjmallett uint32_t fcpem : 1; 4208232812Sjmallett uint32_t ctm : 1; 4209232812Sjmallett uint32_t cam : 1; 4210232812Sjmallett uint32_t ucm : 1; 4211232812Sjmallett uint32_t rom : 1; 4212232812Sjmallett uint32_t mtlpm : 1; 4213232812Sjmallett uint32_t ecrcem : 1; 4214232812Sjmallett uint32_t urem : 1; 4215232812Sjmallett uint32_t reserved_21_21 : 1; 4216232812Sjmallett uint32_t uciem : 1; 4217232812Sjmallett uint32_t reserved_23_23 : 1; 4218232812Sjmallett uint32_t uatombm : 1; 4219232812Sjmallett uint32_t reserved_25_31 : 7; 4220232812Sjmallett#endif 4221232812Sjmallett } cnf71xx; 4222215976Sjmallett}; 4223215976Sjmalletttypedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t; 4224215976Sjmallett 4225215976Sjmallett/** 4226215976Sjmallett * cvmx_pcieep#_cfg067 4227215976Sjmallett * 4228215976Sjmallett * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 0 config space 4229215976Sjmallett * (Uncorrectable Error Severity Register) 4230215976Sjmallett */ 4231232812Sjmallettunion cvmx_pcieepx_cfg067 { 4232215976Sjmallett uint32_t u32; 4233232812Sjmallett struct cvmx_pcieepx_cfg067_s { 4234232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4235232812Sjmallett uint32_t reserved_25_31 : 7; 4236232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 4237232812Sjmallett uint32_t reserved_23_23 : 1; 4238232812Sjmallett uint32_t ucies : 1; /**< Uncorrectable Internal Error Severity */ 4239232812Sjmallett uint32_t reserved_21_21 : 1; 4240232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Severity */ 4241232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Severity */ 4242232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Severity */ 4243232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Severity */ 4244232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Severity */ 4245232812Sjmallett uint32_t cas : 1; /**< Completer Abort Severity */ 4246232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Severity */ 4247232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 4248232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 4249232812Sjmallett uint32_t reserved_6_11 : 6; 4250232812Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 4251232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 4252232812Sjmallett uint32_t reserved_0_3 : 4; 4253232812Sjmallett#else 4254232812Sjmallett uint32_t reserved_0_3 : 4; 4255232812Sjmallett uint32_t dlpes : 1; 4256232812Sjmallett uint32_t sdes : 1; 4257232812Sjmallett uint32_t reserved_6_11 : 6; 4258232812Sjmallett uint32_t ptlps : 1; 4259232812Sjmallett uint32_t fcpes : 1; 4260232812Sjmallett uint32_t cts : 1; 4261232812Sjmallett uint32_t cas : 1; 4262232812Sjmallett uint32_t ucs : 1; 4263232812Sjmallett uint32_t ros : 1; 4264232812Sjmallett uint32_t mtlps : 1; 4265232812Sjmallett uint32_t ecrces : 1; 4266232812Sjmallett uint32_t ures : 1; 4267232812Sjmallett uint32_t reserved_21_21 : 1; 4268232812Sjmallett uint32_t ucies : 1; 4269232812Sjmallett uint32_t reserved_23_23 : 1; 4270232812Sjmallett uint32_t uatombs : 1; 4271232812Sjmallett uint32_t reserved_25_31 : 7; 4272232812Sjmallett#endif 4273232812Sjmallett } s; 4274232812Sjmallett struct cvmx_pcieepx_cfg067_cn52xx { 4275232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4276215976Sjmallett uint32_t reserved_21_31 : 11; 4277215976Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Severity */ 4278215976Sjmallett uint32_t ecrces : 1; /**< ECRC Error Severity */ 4279215976Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Severity */ 4280215976Sjmallett uint32_t ros : 1; /**< Receiver Overflow Severity */ 4281215976Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Severity */ 4282215976Sjmallett uint32_t cas : 1; /**< Completer Abort Severity */ 4283215976Sjmallett uint32_t cts : 1; /**< Completion Timeout Severity */ 4284215976Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 4285215976Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 4286215976Sjmallett uint32_t reserved_6_11 : 6; 4287215976Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 4288215976Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 4289215976Sjmallett uint32_t reserved_0_3 : 4; 4290215976Sjmallett#else 4291215976Sjmallett uint32_t reserved_0_3 : 4; 4292215976Sjmallett uint32_t dlpes : 1; 4293215976Sjmallett uint32_t sdes : 1; 4294215976Sjmallett uint32_t reserved_6_11 : 6; 4295215976Sjmallett uint32_t ptlps : 1; 4296215976Sjmallett uint32_t fcpes : 1; 4297215976Sjmallett uint32_t cts : 1; 4298215976Sjmallett uint32_t cas : 1; 4299215976Sjmallett uint32_t ucs : 1; 4300215976Sjmallett uint32_t ros : 1; 4301215976Sjmallett uint32_t mtlps : 1; 4302215976Sjmallett uint32_t ecrces : 1; 4303215976Sjmallett uint32_t ures : 1; 4304215976Sjmallett uint32_t reserved_21_31 : 11; 4305215976Sjmallett#endif 4306232812Sjmallett } cn52xx; 4307232812Sjmallett struct cvmx_pcieepx_cfg067_cn52xx cn52xxp1; 4308232812Sjmallett struct cvmx_pcieepx_cfg067_cn52xx cn56xx; 4309232812Sjmallett struct cvmx_pcieepx_cfg067_cn52xx cn56xxp1; 4310232812Sjmallett struct cvmx_pcieepx_cfg067_cn61xx { 4311232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4312232812Sjmallett uint32_t reserved_25_31 : 7; 4313232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 4314232812Sjmallett uint32_t reserved_21_23 : 3; 4315232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Severity */ 4316232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Severity */ 4317232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Severity */ 4318232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Severity */ 4319232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Severity */ 4320232812Sjmallett uint32_t cas : 1; /**< Completer Abort Severity */ 4321232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Severity */ 4322232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 4323232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 4324232812Sjmallett uint32_t reserved_6_11 : 6; 4325232812Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 4326232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 4327232812Sjmallett uint32_t reserved_0_3 : 4; 4328232812Sjmallett#else 4329232812Sjmallett uint32_t reserved_0_3 : 4; 4330232812Sjmallett uint32_t dlpes : 1; 4331232812Sjmallett uint32_t sdes : 1; 4332232812Sjmallett uint32_t reserved_6_11 : 6; 4333232812Sjmallett uint32_t ptlps : 1; 4334232812Sjmallett uint32_t fcpes : 1; 4335232812Sjmallett uint32_t cts : 1; 4336232812Sjmallett uint32_t cas : 1; 4337232812Sjmallett uint32_t ucs : 1; 4338232812Sjmallett uint32_t ros : 1; 4339232812Sjmallett uint32_t mtlps : 1; 4340232812Sjmallett uint32_t ecrces : 1; 4341232812Sjmallett uint32_t ures : 1; 4342232812Sjmallett uint32_t reserved_21_23 : 3; 4343232812Sjmallett uint32_t uatombs : 1; 4344232812Sjmallett uint32_t reserved_25_31 : 7; 4345232812Sjmallett#endif 4346232812Sjmallett } cn61xx; 4347232812Sjmallett struct cvmx_pcieepx_cfg067_cn52xx cn63xx; 4348232812Sjmallett struct cvmx_pcieepx_cfg067_cn52xx cn63xxp1; 4349232812Sjmallett struct cvmx_pcieepx_cfg067_cn61xx cn66xx; 4350232812Sjmallett struct cvmx_pcieepx_cfg067_cn61xx cn68xx; 4351232812Sjmallett struct cvmx_pcieepx_cfg067_cn52xx cn68xxp1; 4352232812Sjmallett struct cvmx_pcieepx_cfg067_cnf71xx { 4353232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4354232812Sjmallett uint32_t reserved_25_31 : 7; 4355232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 4356232812Sjmallett uint32_t reserved_23_23 : 1; 4357232812Sjmallett uint32_t ucies : 1; /**< Uncorrectable Internal Error Severity */ 4358232812Sjmallett uint32_t reserved_21_21 : 1; 4359232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Severity */ 4360232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Severity */ 4361232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Severity */ 4362232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Severity */ 4363232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Severity */ 4364232812Sjmallett uint32_t cas : 1; /**< Completer Abort Severity */ 4365232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Severity */ 4366232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 4367232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 4368232812Sjmallett uint32_t reserved_5_11 : 7; 4369232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 4370232812Sjmallett uint32_t reserved_0_3 : 4; 4371232812Sjmallett#else 4372232812Sjmallett uint32_t reserved_0_3 : 4; 4373232812Sjmallett uint32_t dlpes : 1; 4374232812Sjmallett uint32_t reserved_5_11 : 7; 4375232812Sjmallett uint32_t ptlps : 1; 4376232812Sjmallett uint32_t fcpes : 1; 4377232812Sjmallett uint32_t cts : 1; 4378232812Sjmallett uint32_t cas : 1; 4379232812Sjmallett uint32_t ucs : 1; 4380232812Sjmallett uint32_t ros : 1; 4381232812Sjmallett uint32_t mtlps : 1; 4382232812Sjmallett uint32_t ecrces : 1; 4383232812Sjmallett uint32_t ures : 1; 4384232812Sjmallett uint32_t reserved_21_21 : 1; 4385232812Sjmallett uint32_t ucies : 1; 4386232812Sjmallett uint32_t reserved_23_23 : 1; 4387232812Sjmallett uint32_t uatombs : 1; 4388232812Sjmallett uint32_t reserved_25_31 : 7; 4389232812Sjmallett#endif 4390232812Sjmallett } cnf71xx; 4391215976Sjmallett}; 4392215976Sjmalletttypedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t; 4393215976Sjmallett 4394215976Sjmallett/** 4395215976Sjmallett * cvmx_pcieep#_cfg068 4396215976Sjmallett * 4397215976Sjmallett * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 0 config space 4398215976Sjmallett * (Correctable Error Status Register) 4399215976Sjmallett */ 4400232812Sjmallettunion cvmx_pcieepx_cfg068 { 4401215976Sjmallett uint32_t u32; 4402232812Sjmallett struct cvmx_pcieepx_cfg068_s { 4403232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4404232812Sjmallett uint32_t reserved_15_31 : 17; 4405232812Sjmallett uint32_t cies : 1; /**< Corrected Internal Error Status */ 4406232812Sjmallett uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 4407232812Sjmallett uint32_t rtts : 1; /**< Reply Timer Timeout Status */ 4408232812Sjmallett uint32_t reserved_9_11 : 3; 4409232812Sjmallett uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 4410232812Sjmallett uint32_t bdllps : 1; /**< Bad DLLP Status */ 4411232812Sjmallett uint32_t btlps : 1; /**< Bad TLP Status */ 4412232812Sjmallett uint32_t reserved_1_5 : 5; 4413232812Sjmallett uint32_t res : 1; /**< Receiver Error Status */ 4414232812Sjmallett#else 4415232812Sjmallett uint32_t res : 1; 4416232812Sjmallett uint32_t reserved_1_5 : 5; 4417232812Sjmallett uint32_t btlps : 1; 4418232812Sjmallett uint32_t bdllps : 1; 4419232812Sjmallett uint32_t rnrs : 1; 4420232812Sjmallett uint32_t reserved_9_11 : 3; 4421232812Sjmallett uint32_t rtts : 1; 4422232812Sjmallett uint32_t anfes : 1; 4423232812Sjmallett uint32_t cies : 1; 4424232812Sjmallett uint32_t reserved_15_31 : 17; 4425232812Sjmallett#endif 4426232812Sjmallett } s; 4427232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx { 4428232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4429215976Sjmallett uint32_t reserved_14_31 : 18; 4430215976Sjmallett uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 4431215976Sjmallett uint32_t rtts : 1; /**< Reply Timer Timeout Status */ 4432215976Sjmallett uint32_t reserved_9_11 : 3; 4433215976Sjmallett uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 4434215976Sjmallett uint32_t bdllps : 1; /**< Bad DLLP Status */ 4435215976Sjmallett uint32_t btlps : 1; /**< Bad TLP Status */ 4436215976Sjmallett uint32_t reserved_1_5 : 5; 4437215976Sjmallett uint32_t res : 1; /**< Receiver Error Status */ 4438215976Sjmallett#else 4439215976Sjmallett uint32_t res : 1; 4440215976Sjmallett uint32_t reserved_1_5 : 5; 4441215976Sjmallett uint32_t btlps : 1; 4442215976Sjmallett uint32_t bdllps : 1; 4443215976Sjmallett uint32_t rnrs : 1; 4444215976Sjmallett uint32_t reserved_9_11 : 3; 4445215976Sjmallett uint32_t rtts : 1; 4446215976Sjmallett uint32_t anfes : 1; 4447215976Sjmallett uint32_t reserved_14_31 : 18; 4448215976Sjmallett#endif 4449232812Sjmallett } cn52xx; 4450232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn52xxp1; 4451232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn56xx; 4452232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn56xxp1; 4453232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn61xx; 4454232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn63xx; 4455232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn63xxp1; 4456232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn66xx; 4457232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn68xx; 4458232812Sjmallett struct cvmx_pcieepx_cfg068_cn52xx cn68xxp1; 4459232812Sjmallett struct cvmx_pcieepx_cfg068_s cnf71xx; 4460215976Sjmallett}; 4461215976Sjmalletttypedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t; 4462215976Sjmallett 4463215976Sjmallett/** 4464215976Sjmallett * cvmx_pcieep#_cfg069 4465215976Sjmallett * 4466215976Sjmallett * PCIE_CFG069 = Seventieth 32-bits of PCIE type 0 config space 4467215976Sjmallett * (Correctable Error Mask Register) 4468215976Sjmallett */ 4469232812Sjmallettunion cvmx_pcieepx_cfg069 { 4470215976Sjmallett uint32_t u32; 4471232812Sjmallett struct cvmx_pcieepx_cfg069_s { 4472232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4473232812Sjmallett uint32_t reserved_15_31 : 17; 4474232812Sjmallett uint32_t ciem : 1; /**< Corrected Internal Error Mask */ 4475232812Sjmallett uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 4476232812Sjmallett uint32_t rttm : 1; /**< Reply Timer Timeout Mask */ 4477232812Sjmallett uint32_t reserved_9_11 : 3; 4478232812Sjmallett uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 4479232812Sjmallett uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 4480232812Sjmallett uint32_t btlpm : 1; /**< Bad TLP Mask */ 4481232812Sjmallett uint32_t reserved_1_5 : 5; 4482232812Sjmallett uint32_t rem : 1; /**< Receiver Error Mask */ 4483232812Sjmallett#else 4484232812Sjmallett uint32_t rem : 1; 4485232812Sjmallett uint32_t reserved_1_5 : 5; 4486232812Sjmallett uint32_t btlpm : 1; 4487232812Sjmallett uint32_t bdllpm : 1; 4488232812Sjmallett uint32_t rnrm : 1; 4489232812Sjmallett uint32_t reserved_9_11 : 3; 4490232812Sjmallett uint32_t rttm : 1; 4491232812Sjmallett uint32_t anfem : 1; 4492232812Sjmallett uint32_t ciem : 1; 4493232812Sjmallett uint32_t reserved_15_31 : 17; 4494232812Sjmallett#endif 4495232812Sjmallett } s; 4496232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx { 4497232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4498215976Sjmallett uint32_t reserved_14_31 : 18; 4499215976Sjmallett uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 4500215976Sjmallett uint32_t rttm : 1; /**< Reply Timer Timeout Mask */ 4501215976Sjmallett uint32_t reserved_9_11 : 3; 4502215976Sjmallett uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 4503215976Sjmallett uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 4504215976Sjmallett uint32_t btlpm : 1; /**< Bad TLP Mask */ 4505215976Sjmallett uint32_t reserved_1_5 : 5; 4506215976Sjmallett uint32_t rem : 1; /**< Receiver Error Mask */ 4507215976Sjmallett#else 4508215976Sjmallett uint32_t rem : 1; 4509215976Sjmallett uint32_t reserved_1_5 : 5; 4510215976Sjmallett uint32_t btlpm : 1; 4511215976Sjmallett uint32_t bdllpm : 1; 4512215976Sjmallett uint32_t rnrm : 1; 4513215976Sjmallett uint32_t reserved_9_11 : 3; 4514215976Sjmallett uint32_t rttm : 1; 4515215976Sjmallett uint32_t anfem : 1; 4516215976Sjmallett uint32_t reserved_14_31 : 18; 4517215976Sjmallett#endif 4518232812Sjmallett } cn52xx; 4519232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn52xxp1; 4520232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn56xx; 4521232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn56xxp1; 4522232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn61xx; 4523232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn63xx; 4524232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn63xxp1; 4525232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn66xx; 4526232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn68xx; 4527232812Sjmallett struct cvmx_pcieepx_cfg069_cn52xx cn68xxp1; 4528232812Sjmallett struct cvmx_pcieepx_cfg069_s cnf71xx; 4529215976Sjmallett}; 4530215976Sjmalletttypedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t; 4531215976Sjmallett 4532215976Sjmallett/** 4533215976Sjmallett * cvmx_pcieep#_cfg070 4534215976Sjmallett * 4535215976Sjmallett * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 0 config space 4536215976Sjmallett * (Advanced Error Capabilities and Control Register) 4537215976Sjmallett */ 4538232812Sjmallettunion cvmx_pcieepx_cfg070 { 4539215976Sjmallett uint32_t u32; 4540232812Sjmallett struct cvmx_pcieepx_cfg070_s { 4541232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4542215976Sjmallett uint32_t reserved_9_31 : 23; 4543215976Sjmallett uint32_t ce : 1; /**< ECRC Check Enable */ 4544215976Sjmallett uint32_t cc : 1; /**< ECRC Check Capable */ 4545215976Sjmallett uint32_t ge : 1; /**< ECRC Generation Enable */ 4546215976Sjmallett uint32_t gc : 1; /**< ECRC Generation Capability */ 4547215976Sjmallett uint32_t fep : 5; /**< First Error Pointer */ 4548215976Sjmallett#else 4549215976Sjmallett uint32_t fep : 5; 4550215976Sjmallett uint32_t gc : 1; 4551215976Sjmallett uint32_t ge : 1; 4552215976Sjmallett uint32_t cc : 1; 4553215976Sjmallett uint32_t ce : 1; 4554215976Sjmallett uint32_t reserved_9_31 : 23; 4555215976Sjmallett#endif 4556215976Sjmallett } s; 4557215976Sjmallett struct cvmx_pcieepx_cfg070_s cn52xx; 4558215976Sjmallett struct cvmx_pcieepx_cfg070_s cn52xxp1; 4559215976Sjmallett struct cvmx_pcieepx_cfg070_s cn56xx; 4560215976Sjmallett struct cvmx_pcieepx_cfg070_s cn56xxp1; 4561232812Sjmallett struct cvmx_pcieepx_cfg070_s cn61xx; 4562215976Sjmallett struct cvmx_pcieepx_cfg070_s cn63xx; 4563215976Sjmallett struct cvmx_pcieepx_cfg070_s cn63xxp1; 4564232812Sjmallett struct cvmx_pcieepx_cfg070_s cn66xx; 4565232812Sjmallett struct cvmx_pcieepx_cfg070_s cn68xx; 4566232812Sjmallett struct cvmx_pcieepx_cfg070_s cn68xxp1; 4567232812Sjmallett struct cvmx_pcieepx_cfg070_s cnf71xx; 4568215976Sjmallett}; 4569215976Sjmalletttypedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t; 4570215976Sjmallett 4571215976Sjmallett/** 4572215976Sjmallett * cvmx_pcieep#_cfg071 4573215976Sjmallett * 4574215976Sjmallett * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 0 config space 4575215976Sjmallett * (Header Log Register 1) 4576215976Sjmallett */ 4577232812Sjmallettunion cvmx_pcieepx_cfg071 { 4578215976Sjmallett uint32_t u32; 4579232812Sjmallett struct cvmx_pcieepx_cfg071_s { 4580232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4581215976Sjmallett uint32_t dword1 : 32; /**< Header Log Register (first DWORD) */ 4582215976Sjmallett#else 4583215976Sjmallett uint32_t dword1 : 32; 4584215976Sjmallett#endif 4585215976Sjmallett } s; 4586215976Sjmallett struct cvmx_pcieepx_cfg071_s cn52xx; 4587215976Sjmallett struct cvmx_pcieepx_cfg071_s cn52xxp1; 4588215976Sjmallett struct cvmx_pcieepx_cfg071_s cn56xx; 4589215976Sjmallett struct cvmx_pcieepx_cfg071_s cn56xxp1; 4590232812Sjmallett struct cvmx_pcieepx_cfg071_s cn61xx; 4591215976Sjmallett struct cvmx_pcieepx_cfg071_s cn63xx; 4592215976Sjmallett struct cvmx_pcieepx_cfg071_s cn63xxp1; 4593232812Sjmallett struct cvmx_pcieepx_cfg071_s cn66xx; 4594232812Sjmallett struct cvmx_pcieepx_cfg071_s cn68xx; 4595232812Sjmallett struct cvmx_pcieepx_cfg071_s cn68xxp1; 4596232812Sjmallett struct cvmx_pcieepx_cfg071_s cnf71xx; 4597215976Sjmallett}; 4598215976Sjmalletttypedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t; 4599215976Sjmallett 4600215976Sjmallett/** 4601215976Sjmallett * cvmx_pcieep#_cfg072 4602215976Sjmallett * 4603215976Sjmallett * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 0 config space 4604215976Sjmallett * (Header Log Register 2) 4605215976Sjmallett */ 4606232812Sjmallettunion cvmx_pcieepx_cfg072 { 4607215976Sjmallett uint32_t u32; 4608232812Sjmallett struct cvmx_pcieepx_cfg072_s { 4609232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4610215976Sjmallett uint32_t dword2 : 32; /**< Header Log Register (second DWORD) */ 4611215976Sjmallett#else 4612215976Sjmallett uint32_t dword2 : 32; 4613215976Sjmallett#endif 4614215976Sjmallett } s; 4615215976Sjmallett struct cvmx_pcieepx_cfg072_s cn52xx; 4616215976Sjmallett struct cvmx_pcieepx_cfg072_s cn52xxp1; 4617215976Sjmallett struct cvmx_pcieepx_cfg072_s cn56xx; 4618215976Sjmallett struct cvmx_pcieepx_cfg072_s cn56xxp1; 4619232812Sjmallett struct cvmx_pcieepx_cfg072_s cn61xx; 4620215976Sjmallett struct cvmx_pcieepx_cfg072_s cn63xx; 4621215976Sjmallett struct cvmx_pcieepx_cfg072_s cn63xxp1; 4622232812Sjmallett struct cvmx_pcieepx_cfg072_s cn66xx; 4623232812Sjmallett struct cvmx_pcieepx_cfg072_s cn68xx; 4624232812Sjmallett struct cvmx_pcieepx_cfg072_s cn68xxp1; 4625232812Sjmallett struct cvmx_pcieepx_cfg072_s cnf71xx; 4626215976Sjmallett}; 4627215976Sjmalletttypedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t; 4628215976Sjmallett 4629215976Sjmallett/** 4630215976Sjmallett * cvmx_pcieep#_cfg073 4631215976Sjmallett * 4632215976Sjmallett * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 0 config space 4633215976Sjmallett * (Header Log Register 3) 4634215976Sjmallett */ 4635232812Sjmallettunion cvmx_pcieepx_cfg073 { 4636215976Sjmallett uint32_t u32; 4637232812Sjmallett struct cvmx_pcieepx_cfg073_s { 4638232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4639215976Sjmallett uint32_t dword3 : 32; /**< Header Log Register (third DWORD) */ 4640215976Sjmallett#else 4641215976Sjmallett uint32_t dword3 : 32; 4642215976Sjmallett#endif 4643215976Sjmallett } s; 4644215976Sjmallett struct cvmx_pcieepx_cfg073_s cn52xx; 4645215976Sjmallett struct cvmx_pcieepx_cfg073_s cn52xxp1; 4646215976Sjmallett struct cvmx_pcieepx_cfg073_s cn56xx; 4647215976Sjmallett struct cvmx_pcieepx_cfg073_s cn56xxp1; 4648232812Sjmallett struct cvmx_pcieepx_cfg073_s cn61xx; 4649215976Sjmallett struct cvmx_pcieepx_cfg073_s cn63xx; 4650215976Sjmallett struct cvmx_pcieepx_cfg073_s cn63xxp1; 4651232812Sjmallett struct cvmx_pcieepx_cfg073_s cn66xx; 4652232812Sjmallett struct cvmx_pcieepx_cfg073_s cn68xx; 4653232812Sjmallett struct cvmx_pcieepx_cfg073_s cn68xxp1; 4654232812Sjmallett struct cvmx_pcieepx_cfg073_s cnf71xx; 4655215976Sjmallett}; 4656215976Sjmalletttypedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t; 4657215976Sjmallett 4658215976Sjmallett/** 4659215976Sjmallett * cvmx_pcieep#_cfg074 4660215976Sjmallett * 4661215976Sjmallett * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 0 config space 4662215976Sjmallett * (Header Log Register 4) 4663215976Sjmallett */ 4664232812Sjmallettunion cvmx_pcieepx_cfg074 { 4665215976Sjmallett uint32_t u32; 4666232812Sjmallett struct cvmx_pcieepx_cfg074_s { 4667232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4668215976Sjmallett uint32_t dword4 : 32; /**< Header Log Register (fourth DWORD) */ 4669215976Sjmallett#else 4670215976Sjmallett uint32_t dword4 : 32; 4671215976Sjmallett#endif 4672215976Sjmallett } s; 4673215976Sjmallett struct cvmx_pcieepx_cfg074_s cn52xx; 4674215976Sjmallett struct cvmx_pcieepx_cfg074_s cn52xxp1; 4675215976Sjmallett struct cvmx_pcieepx_cfg074_s cn56xx; 4676215976Sjmallett struct cvmx_pcieepx_cfg074_s cn56xxp1; 4677232812Sjmallett struct cvmx_pcieepx_cfg074_s cn61xx; 4678215976Sjmallett struct cvmx_pcieepx_cfg074_s cn63xx; 4679215976Sjmallett struct cvmx_pcieepx_cfg074_s cn63xxp1; 4680232812Sjmallett struct cvmx_pcieepx_cfg074_s cn66xx; 4681232812Sjmallett struct cvmx_pcieepx_cfg074_s cn68xx; 4682232812Sjmallett struct cvmx_pcieepx_cfg074_s cn68xxp1; 4683232812Sjmallett struct cvmx_pcieepx_cfg074_s cnf71xx; 4684215976Sjmallett}; 4685215976Sjmalletttypedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t; 4686215976Sjmallett 4687215976Sjmallett/** 4688215976Sjmallett * cvmx_pcieep#_cfg448 4689215976Sjmallett * 4690215976Sjmallett * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 0 config space 4691215976Sjmallett * (Ack Latency Timer and Replay Timer Register) 4692215976Sjmallett */ 4693232812Sjmallettunion cvmx_pcieepx_cfg448 { 4694215976Sjmallett uint32_t u32; 4695232812Sjmallett struct cvmx_pcieepx_cfg448_s { 4696232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4697215976Sjmallett uint32_t rtl : 16; /**< Replay Time Limit 4698215976Sjmallett The replay timer expires when it reaches this limit. The PCI 4699215976Sjmallett Express bus initiates a replay upon reception of a Nak or when 4700215976Sjmallett the replay timer expires. 4701232812Sjmallett This value will be set correctly by the hardware out of reset 4702232812Sjmallett or when the negotiated Link-Width or Payload-Size changes. If 4703232812Sjmallett the user changes this value through a CSR write or by an 4704232812Sjmallett EEPROM load then they should refer to the PCIe Specification 4705232812Sjmallett for the correct value. */ 4706215976Sjmallett uint32_t rtltl : 16; /**< Round Trip Latency Time Limit 4707215976Sjmallett The Ack/Nak latency timer expires when it reaches this limit. 4708232812Sjmallett This value will be set correctly by the hardware out of reset 4709232812Sjmallett or when the negotiated Link-Width or Payload-Size changes. If 4710232812Sjmallett the user changes this value through a CSR write or by an 4711232812Sjmallett EEPROM load then they should refer to the PCIe Specification 4712232812Sjmallett for the correct value. */ 4713215976Sjmallett#else 4714215976Sjmallett uint32_t rtltl : 16; 4715215976Sjmallett uint32_t rtl : 16; 4716215976Sjmallett#endif 4717215976Sjmallett } s; 4718215976Sjmallett struct cvmx_pcieepx_cfg448_s cn52xx; 4719215976Sjmallett struct cvmx_pcieepx_cfg448_s cn52xxp1; 4720215976Sjmallett struct cvmx_pcieepx_cfg448_s cn56xx; 4721215976Sjmallett struct cvmx_pcieepx_cfg448_s cn56xxp1; 4722232812Sjmallett struct cvmx_pcieepx_cfg448_s cn61xx; 4723215976Sjmallett struct cvmx_pcieepx_cfg448_s cn63xx; 4724215976Sjmallett struct cvmx_pcieepx_cfg448_s cn63xxp1; 4725232812Sjmallett struct cvmx_pcieepx_cfg448_s cn66xx; 4726232812Sjmallett struct cvmx_pcieepx_cfg448_s cn68xx; 4727232812Sjmallett struct cvmx_pcieepx_cfg448_s cn68xxp1; 4728232812Sjmallett struct cvmx_pcieepx_cfg448_s cnf71xx; 4729215976Sjmallett}; 4730215976Sjmalletttypedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t; 4731215976Sjmallett 4732215976Sjmallett/** 4733215976Sjmallett * cvmx_pcieep#_cfg449 4734215976Sjmallett * 4735215976Sjmallett * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 0 config space 4736215976Sjmallett * (Other Message Register) 4737215976Sjmallett */ 4738232812Sjmallettunion cvmx_pcieepx_cfg449 { 4739215976Sjmallett uint32_t u32; 4740232812Sjmallett struct cvmx_pcieepx_cfg449_s { 4741232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4742215976Sjmallett uint32_t omr : 32; /**< Other Message Register 4743215976Sjmallett This register can be used for either of the following purposes: 4744215976Sjmallett o To send a specific PCI Express Message, the application 4745215976Sjmallett writes the payload of the Message into this register, then 4746215976Sjmallett sets bit 0 of the Port Link Control Register to send the 4747215976Sjmallett Message. 4748215976Sjmallett o To store a corruption pattern for corrupting the LCRC on all 4749215976Sjmallett TLPs, the application places a 32-bit corruption pattern into 4750215976Sjmallett this register and enables this function by setting bit 25 of 4751215976Sjmallett the Port Link Control Register. When enabled, the transmit 4752215976Sjmallett LCRC result is XOR'd with this pattern before inserting 4753215976Sjmallett it into the packet. */ 4754215976Sjmallett#else 4755215976Sjmallett uint32_t omr : 32; 4756215976Sjmallett#endif 4757215976Sjmallett } s; 4758215976Sjmallett struct cvmx_pcieepx_cfg449_s cn52xx; 4759215976Sjmallett struct cvmx_pcieepx_cfg449_s cn52xxp1; 4760215976Sjmallett struct cvmx_pcieepx_cfg449_s cn56xx; 4761215976Sjmallett struct cvmx_pcieepx_cfg449_s cn56xxp1; 4762232812Sjmallett struct cvmx_pcieepx_cfg449_s cn61xx; 4763215976Sjmallett struct cvmx_pcieepx_cfg449_s cn63xx; 4764215976Sjmallett struct cvmx_pcieepx_cfg449_s cn63xxp1; 4765232812Sjmallett struct cvmx_pcieepx_cfg449_s cn66xx; 4766232812Sjmallett struct cvmx_pcieepx_cfg449_s cn68xx; 4767232812Sjmallett struct cvmx_pcieepx_cfg449_s cn68xxp1; 4768232812Sjmallett struct cvmx_pcieepx_cfg449_s cnf71xx; 4769215976Sjmallett}; 4770215976Sjmalletttypedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t; 4771215976Sjmallett 4772215976Sjmallett/** 4773215976Sjmallett * cvmx_pcieep#_cfg450 4774215976Sjmallett * 4775215976Sjmallett * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 0 config space 4776215976Sjmallett * (Port Force Link Register) 4777215976Sjmallett */ 4778232812Sjmallettunion cvmx_pcieepx_cfg450 { 4779215976Sjmallett uint32_t u32; 4780232812Sjmallett struct cvmx_pcieepx_cfg450_s { 4781232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4782215976Sjmallett uint32_t lpec : 8; /**< Low Power Entrance Count 4783215976Sjmallett The Power Management state will wait for this many clock cycles 4784215976Sjmallett for the associated completion of a CfgWr to PCIE_CFG017 register 4785215976Sjmallett Power State (PS) field register to go low-power. This register 4786215976Sjmallett is intended for applications that do not let the PCI Express 4787215976Sjmallett bus handle a completion for configuration request to the 4788215976Sjmallett Power Management Control and Status (PCIE_CFG017) register. */ 4789215976Sjmallett uint32_t reserved_22_23 : 2; 4790215976Sjmallett uint32_t link_state : 6; /**< Link State 4791215976Sjmallett The Link state that the PCI Express Bus will be forced to 4792215976Sjmallett when bit 15 (Force Link) is set. 4793215976Sjmallett State encoding: 4794215976Sjmallett o DETECT_QUIET 00h 4795215976Sjmallett o DETECT_ACT 01h 4796215976Sjmallett o POLL_ACTIVE 02h 4797215976Sjmallett o POLL_COMPLIANCE 03h 4798215976Sjmallett o POLL_CONFIG 04h 4799215976Sjmallett o PRE_DETECT_QUIET 05h 4800215976Sjmallett o DETECT_WAIT 06h 4801215976Sjmallett o CFG_LINKWD_START 07h 4802215976Sjmallett o CFG_LINKWD_ACEPT 08h 4803215976Sjmallett o CFG_LANENUM_WAIT 09h 4804215976Sjmallett o CFG_LANENUM_ACEPT 0Ah 4805215976Sjmallett o CFG_COMPLETE 0Bh 4806215976Sjmallett o CFG_IDLE 0Ch 4807215976Sjmallett o RCVRY_LOCK 0Dh 4808215976Sjmallett o RCVRY_SPEED 0Eh 4809215976Sjmallett o RCVRY_RCVRCFG 0Fh 4810215976Sjmallett o RCVRY_IDLE 10h 4811215976Sjmallett o L0 11h 4812215976Sjmallett o L0S 12h 4813215976Sjmallett o L123_SEND_EIDLE 13h 4814215976Sjmallett o L1_IDLE 14h 4815215976Sjmallett o L2_IDLE 15h 4816215976Sjmallett o L2_WAKE 16h 4817215976Sjmallett o DISABLED_ENTRY 17h 4818215976Sjmallett o DISABLED_IDLE 18h 4819215976Sjmallett o DISABLED 19h 4820215976Sjmallett o LPBK_ENTRY 1Ah 4821215976Sjmallett o LPBK_ACTIVE 1Bh 4822215976Sjmallett o LPBK_EXIT 1Ch 4823215976Sjmallett o LPBK_EXIT_TIMEOUT 1Dh 4824215976Sjmallett o HOT_RESET_ENTRY 1Eh 4825215976Sjmallett o HOT_RESET 1Fh */ 4826215976Sjmallett uint32_t force_link : 1; /**< Force Link 4827215976Sjmallett Forces the Link to the state specified by the Link State field. 4828215976Sjmallett The Force Link pulse will trigger Link re-negotiation. 4829215976Sjmallett * As the The Force Link is a pulse, writing a 1 to it does 4830215976Sjmallett trigger the forced link state event, even thought reading it 4831215976Sjmallett always returns a 0. */ 4832215976Sjmallett uint32_t reserved_8_14 : 7; 4833215976Sjmallett uint32_t link_num : 8; /**< Link Number 4834215976Sjmallett Not used for Endpoint */ 4835215976Sjmallett#else 4836215976Sjmallett uint32_t link_num : 8; 4837215976Sjmallett uint32_t reserved_8_14 : 7; 4838215976Sjmallett uint32_t force_link : 1; 4839215976Sjmallett uint32_t link_state : 6; 4840215976Sjmallett uint32_t reserved_22_23 : 2; 4841215976Sjmallett uint32_t lpec : 8; 4842215976Sjmallett#endif 4843215976Sjmallett } s; 4844215976Sjmallett struct cvmx_pcieepx_cfg450_s cn52xx; 4845215976Sjmallett struct cvmx_pcieepx_cfg450_s cn52xxp1; 4846215976Sjmallett struct cvmx_pcieepx_cfg450_s cn56xx; 4847215976Sjmallett struct cvmx_pcieepx_cfg450_s cn56xxp1; 4848232812Sjmallett struct cvmx_pcieepx_cfg450_s cn61xx; 4849215976Sjmallett struct cvmx_pcieepx_cfg450_s cn63xx; 4850215976Sjmallett struct cvmx_pcieepx_cfg450_s cn63xxp1; 4851232812Sjmallett struct cvmx_pcieepx_cfg450_s cn66xx; 4852232812Sjmallett struct cvmx_pcieepx_cfg450_s cn68xx; 4853232812Sjmallett struct cvmx_pcieepx_cfg450_s cn68xxp1; 4854232812Sjmallett struct cvmx_pcieepx_cfg450_s cnf71xx; 4855215976Sjmallett}; 4856215976Sjmalletttypedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t; 4857215976Sjmallett 4858215976Sjmallett/** 4859215976Sjmallett * cvmx_pcieep#_cfg451 4860215976Sjmallett * 4861215976Sjmallett * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 0 config space 4862215976Sjmallett * (Ack Frequency Register) 4863215976Sjmallett */ 4864232812Sjmallettunion cvmx_pcieepx_cfg451 { 4865215976Sjmallett uint32_t u32; 4866232812Sjmallett struct cvmx_pcieepx_cfg451_s { 4867232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4868232812Sjmallett uint32_t reserved_31_31 : 1; 4869232812Sjmallett uint32_t easpml1 : 1; /**< Enter ASPM L1 without receive in L0s 4870232812Sjmallett Allow core to enter ASPM L1 even when link partner did 4871232812Sjmallett not go to L0s (receive is not in L0s). 4872232812Sjmallett When not set, core goes to ASPM L1 only after idle period 4873232812Sjmallett during which both receive and transmit are in L0s. */ 4874232812Sjmallett uint32_t l1el : 3; /**< L1 Entrance Latency 4875232812Sjmallett Values correspond to: 4876232812Sjmallett o 000: 1 ms 4877232812Sjmallett o 001: 2 ms 4878232812Sjmallett o 010: 4 ms 4879232812Sjmallett o 011: 8 ms 4880232812Sjmallett o 100: 16 ms 4881232812Sjmallett o 101: 32 ms 4882232812Sjmallett o 110 or 111: 64 ms */ 4883232812Sjmallett uint32_t l0el : 3; /**< L0s Entrance Latency 4884232812Sjmallett Values correspond to: 4885232812Sjmallett o 000: 1 ms 4886232812Sjmallett o 001: 2 ms 4887232812Sjmallett o 010: 3 ms 4888232812Sjmallett o 011: 4 ms 4889232812Sjmallett o 100: 5 ms 4890232812Sjmallett o 101: 6 ms 4891232812Sjmallett o 110 or 111: 7 ms */ 4892232812Sjmallett uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 4893232812Sjmallett The number of Fast Training Sequence ordered sets to be 4894232812Sjmallett transmitted when transitioning from L0s to L0. The maximum 4895232812Sjmallett number of FTS ordered-sets that a component can request is 255. 4896232812Sjmallett Note: A value of zero is not supported; a value of 4897232812Sjmallett zero can cause the LTSSM to go into the recovery state 4898232812Sjmallett when exiting from L0s. */ 4899232812Sjmallett uint32_t n_fts : 8; /**< N_FTS 4900232812Sjmallett The number of Fast Training Sequence ordered sets to be 4901232812Sjmallett transmitted when transitioning from L0s to L0. The maximum 4902232812Sjmallett number of FTS ordered-sets that a component can request is 255. 4903232812Sjmallett Note: A value of zero is not supported; a value of 4904232812Sjmallett zero can cause the LTSSM to go into the recovery state 4905232812Sjmallett when exiting from L0s. */ 4906232812Sjmallett uint32_t ack_freq : 8; /**< Ack Frequency 4907232812Sjmallett The number of pending Ack's specified here (up to 255) before 4908232812Sjmallett sending an Ack. */ 4909232812Sjmallett#else 4910232812Sjmallett uint32_t ack_freq : 8; 4911232812Sjmallett uint32_t n_fts : 8; 4912232812Sjmallett uint32_t n_fts_cc : 8; 4913232812Sjmallett uint32_t l0el : 3; 4914232812Sjmallett uint32_t l1el : 3; 4915232812Sjmallett uint32_t easpml1 : 1; 4916232812Sjmallett uint32_t reserved_31_31 : 1; 4917232812Sjmallett#endif 4918232812Sjmallett } s; 4919232812Sjmallett struct cvmx_pcieepx_cfg451_cn52xx { 4920232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4921215976Sjmallett uint32_t reserved_30_31 : 2; 4922215976Sjmallett uint32_t l1el : 3; /**< L1 Entrance Latency 4923215976Sjmallett Values correspond to: 4924215976Sjmallett o 000: 1 ms 4925215976Sjmallett o 001: 2 ms 4926215976Sjmallett o 010: 4 ms 4927215976Sjmallett o 011: 8 ms 4928215976Sjmallett o 100: 16 ms 4929215976Sjmallett o 101: 32 ms 4930215976Sjmallett o 110 or 111: 64 ms */ 4931215976Sjmallett uint32_t l0el : 3; /**< L0s Entrance Latency 4932215976Sjmallett Values correspond to: 4933215976Sjmallett o 000: 1 ms 4934215976Sjmallett o 001: 2 ms 4935215976Sjmallett o 010: 3 ms 4936215976Sjmallett o 011: 4 ms 4937215976Sjmallett o 100: 5 ms 4938215976Sjmallett o 101: 6 ms 4939215976Sjmallett o 110 or 111: 7 ms */ 4940215976Sjmallett uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 4941215976Sjmallett The number of Fast Training Sequence ordered sets to be 4942215976Sjmallett transmitted when transitioning from L0s to L0. The maximum 4943215976Sjmallett number of FTS ordered-sets that a component can request is 255. 4944215976Sjmallett Note: A value of zero is not supported; a value of 4945215976Sjmallett zero can cause the LTSSM to go into the recovery state 4946215976Sjmallett when exiting from L0s. */ 4947215976Sjmallett uint32_t n_fts : 8; /**< N_FTS 4948215976Sjmallett The number of Fast Training Sequence ordered sets to be 4949215976Sjmallett transmitted when transitioning from L0s to L0. The maximum 4950215976Sjmallett number of FTS ordered-sets that a component can request is 255. 4951215976Sjmallett Note: A value of zero is not supported; a value of 4952215976Sjmallett zero can cause the LTSSM to go into the recovery state 4953215976Sjmallett when exiting from L0s. */ 4954215976Sjmallett uint32_t ack_freq : 8; /**< Ack Frequency 4955215976Sjmallett The number of pending Ack's specified here (up to 255) before 4956215976Sjmallett sending an Ack. */ 4957215976Sjmallett#else 4958215976Sjmallett uint32_t ack_freq : 8; 4959215976Sjmallett uint32_t n_fts : 8; 4960215976Sjmallett uint32_t n_fts_cc : 8; 4961215976Sjmallett uint32_t l0el : 3; 4962215976Sjmallett uint32_t l1el : 3; 4963215976Sjmallett uint32_t reserved_30_31 : 2; 4964215976Sjmallett#endif 4965232812Sjmallett } cn52xx; 4966232812Sjmallett struct cvmx_pcieepx_cfg451_cn52xx cn52xxp1; 4967232812Sjmallett struct cvmx_pcieepx_cfg451_cn52xx cn56xx; 4968232812Sjmallett struct cvmx_pcieepx_cfg451_cn52xx cn56xxp1; 4969232812Sjmallett struct cvmx_pcieepx_cfg451_s cn61xx; 4970232812Sjmallett struct cvmx_pcieepx_cfg451_cn52xx cn63xx; 4971232812Sjmallett struct cvmx_pcieepx_cfg451_cn52xx cn63xxp1; 4972232812Sjmallett struct cvmx_pcieepx_cfg451_s cn66xx; 4973232812Sjmallett struct cvmx_pcieepx_cfg451_s cn68xx; 4974232812Sjmallett struct cvmx_pcieepx_cfg451_s cn68xxp1; 4975232812Sjmallett struct cvmx_pcieepx_cfg451_s cnf71xx; 4976215976Sjmallett}; 4977215976Sjmalletttypedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t; 4978215976Sjmallett 4979215976Sjmallett/** 4980215976Sjmallett * cvmx_pcieep#_cfg452 4981215976Sjmallett * 4982215976Sjmallett * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 0 config space 4983215976Sjmallett * (Port Link Control Register) 4984215976Sjmallett */ 4985232812Sjmallettunion cvmx_pcieepx_cfg452 { 4986215976Sjmallett uint32_t u32; 4987232812Sjmallett struct cvmx_pcieepx_cfg452_s { 4988232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4989215976Sjmallett uint32_t reserved_26_31 : 6; 4990215976Sjmallett uint32_t eccrc : 1; /**< Enable Corrupted CRC 4991215976Sjmallett Causes corrupt LCRC for TLPs when set, 4992215976Sjmallett using the pattern contained in the Other Message register. 4993215976Sjmallett This is a test feature, not to be used in normal operation. */ 4994215976Sjmallett uint32_t reserved_22_24 : 3; 4995215976Sjmallett uint32_t lme : 6; /**< Link Mode Enable 4996215976Sjmallett o 000001: x1 4997232812Sjmallett o 000011: x2 (not supported) 4998232812Sjmallett o 000111: x4 (not supported) 4999232812Sjmallett o 001111: x8 (not supported) 5000232812Sjmallett o 011111: x16 (not supported) 5001232812Sjmallett o 111111: x32 (not supported) 5002232812Sjmallett This field indicates the MAXIMUM number of lanes supported 5003232812Sjmallett by the PCIe port. 5004232812Sjmallett See also MLW. 5005232812Sjmallett (Note: The value of this field does NOT indicate the number 5006232812Sjmallett of lanes in use by the PCIe. LME sets the max number of lanes 5007232812Sjmallett in the PCIe core that COULD be used. As per the PCIe specs, 5008232812Sjmallett the PCIe core can negotiate a smaller link width) */ 5009232812Sjmallett uint32_t reserved_8_15 : 8; 5010232812Sjmallett uint32_t flm : 1; /**< Fast Link Mode 5011232812Sjmallett Sets all internal timers to fast mode for simulation purposes. 5012232812Sjmallett If during an eeprom load, the first word loaded is 0xffffffff, 5013232812Sjmallett then the EEPROM load will be terminated and this bit will be set. */ 5014232812Sjmallett uint32_t reserved_6_6 : 1; 5015232812Sjmallett uint32_t dllle : 1; /**< DLL Link Enable 5016232812Sjmallett Enables Link initialization. If DLL Link Enable = 0, the PCI 5017232812Sjmallett Express bus does not transmit InitFC DLLPs and does not 5018232812Sjmallett establish a Link. */ 5019232812Sjmallett uint32_t reserved_4_4 : 1; 5020232812Sjmallett uint32_t ra : 1; /**< Reset Assert 5021232812Sjmallett Triggers a recovery and forces the LTSSM to the Hot Reset 5022232812Sjmallett state (downstream port only). */ 5023232812Sjmallett uint32_t le : 1; /**< Loopback Enable 5024232812Sjmallett Initiate loopback mode as a master. On a 0->1 transition, 5025232812Sjmallett the PCIe core sends TS ordered sets with the loopback bit set 5026232812Sjmallett to cause the link partner to enter into loopback mode as a 5027232812Sjmallett slave. Normal transmission is not possible when LE=1. To exit 5028232812Sjmallett loopback mode, take the link through a reset sequence. */ 5029232812Sjmallett uint32_t sd : 1; /**< Scramble Disable 5030232812Sjmallett Turns off data scrambling. */ 5031232812Sjmallett uint32_t omr : 1; /**< Other Message Request 5032232812Sjmallett When software writes a `1' to this bit, the PCI Express bus 5033232812Sjmallett transmits the Message contained in the Other Message register. */ 5034232812Sjmallett#else 5035232812Sjmallett uint32_t omr : 1; 5036232812Sjmallett uint32_t sd : 1; 5037232812Sjmallett uint32_t le : 1; 5038232812Sjmallett uint32_t ra : 1; 5039232812Sjmallett uint32_t reserved_4_4 : 1; 5040232812Sjmallett uint32_t dllle : 1; 5041232812Sjmallett uint32_t reserved_6_6 : 1; 5042232812Sjmallett uint32_t flm : 1; 5043232812Sjmallett uint32_t reserved_8_15 : 8; 5044232812Sjmallett uint32_t lme : 6; 5045232812Sjmallett uint32_t reserved_22_24 : 3; 5046232812Sjmallett uint32_t eccrc : 1; 5047232812Sjmallett uint32_t reserved_26_31 : 6; 5048232812Sjmallett#endif 5049232812Sjmallett } s; 5050232812Sjmallett struct cvmx_pcieepx_cfg452_s cn52xx; 5051232812Sjmallett struct cvmx_pcieepx_cfg452_s cn52xxp1; 5052232812Sjmallett struct cvmx_pcieepx_cfg452_s cn56xx; 5053232812Sjmallett struct cvmx_pcieepx_cfg452_s cn56xxp1; 5054232812Sjmallett struct cvmx_pcieepx_cfg452_cn61xx { 5055232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5056232812Sjmallett uint32_t reserved_22_31 : 10; 5057232812Sjmallett uint32_t lme : 6; /**< Link Mode Enable 5058232812Sjmallett o 000001: x1 5059215976Sjmallett o 000011: x2 5060215976Sjmallett o 000111: x4 5061215976Sjmallett o 001111: x8 (not supported) 5062215976Sjmallett o 011111: x16 (not supported) 5063215976Sjmallett o 111111: x32 (not supported) 5064215976Sjmallett This field indicates the MAXIMUM number of lanes supported 5065215976Sjmallett by the PCIe port. The value can be set less than 0x7 5066215976Sjmallett to limit the number of lanes the PCIe will attempt to use. 5067215976Sjmallett If the value of 0x7 set by the HW is not desired, 5068215976Sjmallett this field can be programmed to a smaller value (i.e. EEPROM) 5069215976Sjmallett See also MLW. 5070215976Sjmallett (Note: The value of this field does NOT indicate the number 5071215976Sjmallett of lanes in use by the PCIe. LME sets the max number of lanes 5072215976Sjmallett in the PCIe core that COULD be used. As per the PCIe specs, 5073215976Sjmallett the PCIe core can negotiate a smaller link width, so all 5074215976Sjmallett of x4, x2, and x1 are supported when LME=0x7, 5075215976Sjmallett for example.) */ 5076215976Sjmallett uint32_t reserved_8_15 : 8; 5077215976Sjmallett uint32_t flm : 1; /**< Fast Link Mode 5078215976Sjmallett Sets all internal timers to fast mode for simulation purposes. 5079215976Sjmallett If during an eeprom load, the first word loaded is 0xffffffff, 5080215976Sjmallett then the EEPROM load will be terminated and this bit will be set. */ 5081215976Sjmallett uint32_t reserved_6_6 : 1; 5082215976Sjmallett uint32_t dllle : 1; /**< DLL Link Enable 5083215976Sjmallett Enables Link initialization. If DLL Link Enable = 0, the PCI 5084215976Sjmallett Express bus does not transmit InitFC DLLPs and does not 5085215976Sjmallett establish a Link. */ 5086215976Sjmallett uint32_t reserved_4_4 : 1; 5087215976Sjmallett uint32_t ra : 1; /**< Reset Assert 5088215976Sjmallett Triggers a recovery and forces the LTSSM to the Hot Reset 5089215976Sjmallett state (downstream port only). */ 5090215976Sjmallett uint32_t le : 1; /**< Loopback Enable 5091215976Sjmallett Initiate loopback mode as a master. On a 0->1 transition, 5092215976Sjmallett the PCIe core sends TS ordered sets with the loopback bit set 5093215976Sjmallett to cause the link partner to enter into loopback mode as a 5094215976Sjmallett slave. Normal transmission is not possible when LE=1. To exit 5095215976Sjmallett loopback mode, take the link through a reset sequence. */ 5096215976Sjmallett uint32_t sd : 1; /**< Scramble Disable 5097215976Sjmallett Turns off data scrambling. */ 5098215976Sjmallett uint32_t omr : 1; /**< Other Message Request 5099215976Sjmallett When software writes a `1' to this bit, the PCI Express bus 5100215976Sjmallett transmits the Message contained in the Other Message register. */ 5101215976Sjmallett#else 5102215976Sjmallett uint32_t omr : 1; 5103215976Sjmallett uint32_t sd : 1; 5104215976Sjmallett uint32_t le : 1; 5105215976Sjmallett uint32_t ra : 1; 5106215976Sjmallett uint32_t reserved_4_4 : 1; 5107215976Sjmallett uint32_t dllle : 1; 5108215976Sjmallett uint32_t reserved_6_6 : 1; 5109215976Sjmallett uint32_t flm : 1; 5110215976Sjmallett uint32_t reserved_8_15 : 8; 5111215976Sjmallett uint32_t lme : 6; 5112232812Sjmallett uint32_t reserved_22_31 : 10; 5113215976Sjmallett#endif 5114232812Sjmallett } cn61xx; 5115215976Sjmallett struct cvmx_pcieepx_cfg452_s cn63xx; 5116215976Sjmallett struct cvmx_pcieepx_cfg452_s cn63xxp1; 5117232812Sjmallett struct cvmx_pcieepx_cfg452_cn61xx cn66xx; 5118232812Sjmallett struct cvmx_pcieepx_cfg452_cn61xx cn68xx; 5119232812Sjmallett struct cvmx_pcieepx_cfg452_cn61xx cn68xxp1; 5120232812Sjmallett struct cvmx_pcieepx_cfg452_cn61xx cnf71xx; 5121215976Sjmallett}; 5122215976Sjmalletttypedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t; 5123215976Sjmallett 5124215976Sjmallett/** 5125215976Sjmallett * cvmx_pcieep#_cfg453 5126215976Sjmallett * 5127215976Sjmallett * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 0 config space 5128215976Sjmallett * (Lane Skew Register) 5129215976Sjmallett */ 5130232812Sjmallettunion cvmx_pcieepx_cfg453 { 5131215976Sjmallett uint32_t u32; 5132232812Sjmallett struct cvmx_pcieepx_cfg453_s { 5133232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5134215976Sjmallett uint32_t dlld : 1; /**< Disable Lane-to-Lane Deskew 5135215976Sjmallett Disables the internal Lane-to-Lane deskew logic. */ 5136215976Sjmallett uint32_t reserved_26_30 : 5; 5137215976Sjmallett uint32_t ack_nak : 1; /**< Ack/Nak Disable 5138215976Sjmallett Prevents the PCI Express bus from sending Ack and Nak DLLPs. */ 5139215976Sjmallett uint32_t fcd : 1; /**< Flow Control Disable 5140215976Sjmallett Prevents the PCI Express bus from sending FC DLLPs. */ 5141215976Sjmallett uint32_t ilst : 24; /**< Insert Lane Skew for Transmit 5142215976Sjmallett Causes skew between lanes for test purposes. There are three 5143215976Sjmallett bits per Lane. The value is in units of one symbol time. For 5144215976Sjmallett example, the value 010b for a Lane forces a skew of two symbol 5145215976Sjmallett times for that Lane. The maximum skew value for any Lane is 5 5146215976Sjmallett symbol times. */ 5147215976Sjmallett#else 5148215976Sjmallett uint32_t ilst : 24; 5149215976Sjmallett uint32_t fcd : 1; 5150215976Sjmallett uint32_t ack_nak : 1; 5151215976Sjmallett uint32_t reserved_26_30 : 5; 5152215976Sjmallett uint32_t dlld : 1; 5153215976Sjmallett#endif 5154215976Sjmallett } s; 5155215976Sjmallett struct cvmx_pcieepx_cfg453_s cn52xx; 5156215976Sjmallett struct cvmx_pcieepx_cfg453_s cn52xxp1; 5157215976Sjmallett struct cvmx_pcieepx_cfg453_s cn56xx; 5158215976Sjmallett struct cvmx_pcieepx_cfg453_s cn56xxp1; 5159232812Sjmallett struct cvmx_pcieepx_cfg453_s cn61xx; 5160215976Sjmallett struct cvmx_pcieepx_cfg453_s cn63xx; 5161215976Sjmallett struct cvmx_pcieepx_cfg453_s cn63xxp1; 5162232812Sjmallett struct cvmx_pcieepx_cfg453_s cn66xx; 5163232812Sjmallett struct cvmx_pcieepx_cfg453_s cn68xx; 5164232812Sjmallett struct cvmx_pcieepx_cfg453_s cn68xxp1; 5165232812Sjmallett struct cvmx_pcieepx_cfg453_s cnf71xx; 5166215976Sjmallett}; 5167215976Sjmalletttypedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t; 5168215976Sjmallett 5169215976Sjmallett/** 5170215976Sjmallett * cvmx_pcieep#_cfg454 5171215976Sjmallett * 5172215976Sjmallett * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 0 config space 5173215976Sjmallett * (Symbol Number Register) 5174215976Sjmallett */ 5175232812Sjmallettunion cvmx_pcieepx_cfg454 { 5176215976Sjmallett uint32_t u32; 5177232812Sjmallett struct cvmx_pcieepx_cfg454_s { 5178232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5179232812Sjmallett uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1) 5180232812Sjmallett Configuration Requests targeted at function numbers above this 5181232812Sjmallett value will be returned with unsupported request */ 5182232812Sjmallett uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 5183232812Sjmallett Increases the timer value for the Flow Control watchdog timer, 5184232812Sjmallett in increments of 16 clock cycles. */ 5185232812Sjmallett uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 5186232812Sjmallett Increases the timer value for the Ack/Nak latency timer, in 5187232812Sjmallett increments of 64 clock cycles. */ 5188232812Sjmallett uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 5189232812Sjmallett Increases the timer value for the replay timer, in increments 5190232812Sjmallett of 64 clock cycles. */ 5191232812Sjmallett uint32_t reserved_11_13 : 3; 5192232812Sjmallett uint32_t nskps : 3; /**< Number of SKP Symbols */ 5193232812Sjmallett uint32_t reserved_0_7 : 8; 5194232812Sjmallett#else 5195232812Sjmallett uint32_t reserved_0_7 : 8; 5196232812Sjmallett uint32_t nskps : 3; 5197232812Sjmallett uint32_t reserved_11_13 : 3; 5198232812Sjmallett uint32_t tmrt : 5; 5199232812Sjmallett uint32_t tmanlt : 5; 5200232812Sjmallett uint32_t tmfcwt : 5; 5201232812Sjmallett uint32_t cx_nfunc : 3; 5202232812Sjmallett#endif 5203232812Sjmallett } s; 5204232812Sjmallett struct cvmx_pcieepx_cfg454_cn52xx { 5205232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5206215976Sjmallett uint32_t reserved_29_31 : 3; 5207215976Sjmallett uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 5208215976Sjmallett Increases the timer value for the Flow Control watchdog timer, 5209215976Sjmallett in increments of 16 clock cycles. */ 5210215976Sjmallett uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 5211215976Sjmallett Increases the timer value for the Ack/Nak latency timer, in 5212215976Sjmallett increments of 64 clock cycles. */ 5213215976Sjmallett uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 5214215976Sjmallett Increases the timer value for the replay timer, in increments 5215215976Sjmallett of 64 clock cycles. */ 5216215976Sjmallett uint32_t reserved_11_13 : 3; 5217215976Sjmallett uint32_t nskps : 3; /**< Number of SKP Symbols */ 5218215976Sjmallett uint32_t reserved_4_7 : 4; 5219215976Sjmallett uint32_t ntss : 4; /**< Number of TS Symbols 5220215976Sjmallett Sets the number of TS identifier symbols that are sent in TS1 5221215976Sjmallett and TS2 ordered sets. */ 5222215976Sjmallett#else 5223215976Sjmallett uint32_t ntss : 4; 5224215976Sjmallett uint32_t reserved_4_7 : 4; 5225215976Sjmallett uint32_t nskps : 3; 5226215976Sjmallett uint32_t reserved_11_13 : 3; 5227215976Sjmallett uint32_t tmrt : 5; 5228215976Sjmallett uint32_t tmanlt : 5; 5229215976Sjmallett uint32_t tmfcwt : 5; 5230215976Sjmallett uint32_t reserved_29_31 : 3; 5231215976Sjmallett#endif 5232232812Sjmallett } cn52xx; 5233232812Sjmallett struct cvmx_pcieepx_cfg454_cn52xx cn52xxp1; 5234232812Sjmallett struct cvmx_pcieepx_cfg454_cn52xx cn56xx; 5235232812Sjmallett struct cvmx_pcieepx_cfg454_cn52xx cn56xxp1; 5236232812Sjmallett struct cvmx_pcieepx_cfg454_cn61xx { 5237232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5238232812Sjmallett uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1) 5239232812Sjmallett Configuration Requests targeted at function numbers above this 5240232812Sjmallett value will be returned with unsupported request */ 5241232812Sjmallett uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 5242232812Sjmallett Increases the timer value for the Flow Control watchdog timer, 5243232812Sjmallett in increments of 16 clock cycles. */ 5244232812Sjmallett uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 5245232812Sjmallett Increases the timer value for the Ack/Nak latency timer, in 5246232812Sjmallett increments of 64 clock cycles. */ 5247232812Sjmallett uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 5248232812Sjmallett Increases the timer value for the replay timer, in increments 5249232812Sjmallett of 64 clock cycles. */ 5250232812Sjmallett uint32_t reserved_8_13 : 6; 5251232812Sjmallett uint32_t mfuncn : 8; /**< Max Number of Functions Supported */ 5252232812Sjmallett#else 5253232812Sjmallett uint32_t mfuncn : 8; 5254232812Sjmallett uint32_t reserved_8_13 : 6; 5255232812Sjmallett uint32_t tmrt : 5; 5256232812Sjmallett uint32_t tmanlt : 5; 5257232812Sjmallett uint32_t tmfcwt : 5; 5258232812Sjmallett uint32_t cx_nfunc : 3; 5259232812Sjmallett#endif 5260232812Sjmallett } cn61xx; 5261232812Sjmallett struct cvmx_pcieepx_cfg454_cn52xx cn63xx; 5262232812Sjmallett struct cvmx_pcieepx_cfg454_cn52xx cn63xxp1; 5263232812Sjmallett struct cvmx_pcieepx_cfg454_cn61xx cn66xx; 5264232812Sjmallett struct cvmx_pcieepx_cfg454_cn61xx cn68xx; 5265232812Sjmallett struct cvmx_pcieepx_cfg454_cn52xx cn68xxp1; 5266232812Sjmallett struct cvmx_pcieepx_cfg454_cn61xx cnf71xx; 5267215976Sjmallett}; 5268215976Sjmalletttypedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t; 5269215976Sjmallett 5270215976Sjmallett/** 5271215976Sjmallett * cvmx_pcieep#_cfg455 5272215976Sjmallett * 5273215976Sjmallett * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 0 config space 5274215976Sjmallett * (Symbol Timer Register/Filter Mask Register 1) 5275215976Sjmallett */ 5276232812Sjmallettunion cvmx_pcieepx_cfg455 { 5277215976Sjmallett uint32_t u32; 5278232812Sjmallett struct cvmx_pcieepx_cfg455_s { 5279232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5280215976Sjmallett uint32_t m_cfg0_filt : 1; /**< Mask filtering of received Configuration Requests (RC mode only) */ 5281215976Sjmallett uint32_t m_io_filt : 1; /**< Mask filtering of received I/O Requests (RC mode only) */ 5282215976Sjmallett uint32_t msg_ctrl : 1; /**< Message Control 5283215976Sjmallett The application must not change this field. */ 5284215976Sjmallett uint32_t m_cpl_ecrc_filt : 1; /**< Mask ECRC error filtering for Completions */ 5285215976Sjmallett uint32_t m_ecrc_filt : 1; /**< Mask ECRC error filtering */ 5286215976Sjmallett uint32_t m_cpl_len_err : 1; /**< Mask Length mismatch error for received Completions */ 5287215976Sjmallett uint32_t m_cpl_attr_err : 1; /**< Mask Attributes mismatch error for received Completions */ 5288215976Sjmallett uint32_t m_cpl_tc_err : 1; /**< Mask Traffic Class mismatch error for received Completions */ 5289215976Sjmallett uint32_t m_cpl_fun_err : 1; /**< Mask function mismatch error for received Completions */ 5290215976Sjmallett uint32_t m_cpl_rid_err : 1; /**< Mask Requester ID mismatch error for received Completions */ 5291215976Sjmallett uint32_t m_cpl_tag_err : 1; /**< Mask Tag error rules for received Completions */ 5292215976Sjmallett uint32_t m_lk_filt : 1; /**< Mask Locked Request filtering */ 5293215976Sjmallett uint32_t m_cfg1_filt : 1; /**< Mask Type 1 Configuration Request filtering */ 5294215976Sjmallett uint32_t m_bar_match : 1; /**< Mask BAR match filtering */ 5295215976Sjmallett uint32_t m_pois_filt : 1; /**< Mask poisoned TLP filtering */ 5296215976Sjmallett uint32_t m_fun : 1; /**< Mask function */ 5297215976Sjmallett uint32_t dfcwt : 1; /**< Disable FC Watchdog Timer */ 5298215976Sjmallett uint32_t reserved_11_14 : 4; 5299215976Sjmallett uint32_t skpiv : 11; /**< SKP Interval Value */ 5300215976Sjmallett#else 5301215976Sjmallett uint32_t skpiv : 11; 5302215976Sjmallett uint32_t reserved_11_14 : 4; 5303215976Sjmallett uint32_t dfcwt : 1; 5304215976Sjmallett uint32_t m_fun : 1; 5305215976Sjmallett uint32_t m_pois_filt : 1; 5306215976Sjmallett uint32_t m_bar_match : 1; 5307215976Sjmallett uint32_t m_cfg1_filt : 1; 5308215976Sjmallett uint32_t m_lk_filt : 1; 5309215976Sjmallett uint32_t m_cpl_tag_err : 1; 5310215976Sjmallett uint32_t m_cpl_rid_err : 1; 5311215976Sjmallett uint32_t m_cpl_fun_err : 1; 5312215976Sjmallett uint32_t m_cpl_tc_err : 1; 5313215976Sjmallett uint32_t m_cpl_attr_err : 1; 5314215976Sjmallett uint32_t m_cpl_len_err : 1; 5315215976Sjmallett uint32_t m_ecrc_filt : 1; 5316215976Sjmallett uint32_t m_cpl_ecrc_filt : 1; 5317215976Sjmallett uint32_t msg_ctrl : 1; 5318215976Sjmallett uint32_t m_io_filt : 1; 5319215976Sjmallett uint32_t m_cfg0_filt : 1; 5320215976Sjmallett#endif 5321215976Sjmallett } s; 5322215976Sjmallett struct cvmx_pcieepx_cfg455_s cn52xx; 5323215976Sjmallett struct cvmx_pcieepx_cfg455_s cn52xxp1; 5324215976Sjmallett struct cvmx_pcieepx_cfg455_s cn56xx; 5325215976Sjmallett struct cvmx_pcieepx_cfg455_s cn56xxp1; 5326232812Sjmallett struct cvmx_pcieepx_cfg455_s cn61xx; 5327215976Sjmallett struct cvmx_pcieepx_cfg455_s cn63xx; 5328215976Sjmallett struct cvmx_pcieepx_cfg455_s cn63xxp1; 5329232812Sjmallett struct cvmx_pcieepx_cfg455_s cn66xx; 5330232812Sjmallett struct cvmx_pcieepx_cfg455_s cn68xx; 5331232812Sjmallett struct cvmx_pcieepx_cfg455_s cn68xxp1; 5332232812Sjmallett struct cvmx_pcieepx_cfg455_s cnf71xx; 5333215976Sjmallett}; 5334215976Sjmalletttypedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t; 5335215976Sjmallett 5336215976Sjmallett/** 5337215976Sjmallett * cvmx_pcieep#_cfg456 5338215976Sjmallett * 5339215976Sjmallett * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 0 config space 5340215976Sjmallett * (Filter Mask Register 2) 5341215976Sjmallett */ 5342232812Sjmallettunion cvmx_pcieepx_cfg456 { 5343215976Sjmallett uint32_t u32; 5344232812Sjmallett struct cvmx_pcieepx_cfg456_s { 5345232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5346232812Sjmallett uint32_t reserved_4_31 : 28; 5347232812Sjmallett uint32_t m_handle_flush : 1; /**< Mask Core Filter to handle flush request */ 5348232812Sjmallett uint32_t m_dabort_4ucpl : 1; /**< Mask DLLP abort for unexpected CPL */ 5349232812Sjmallett uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 5350232812Sjmallett uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 5351232812Sjmallett#else 5352232812Sjmallett uint32_t m_vend0_drp : 1; 5353232812Sjmallett uint32_t m_vend1_drp : 1; 5354232812Sjmallett uint32_t m_dabort_4ucpl : 1; 5355232812Sjmallett uint32_t m_handle_flush : 1; 5356232812Sjmallett uint32_t reserved_4_31 : 28; 5357232812Sjmallett#endif 5358232812Sjmallett } s; 5359232812Sjmallett struct cvmx_pcieepx_cfg456_cn52xx { 5360232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5361215976Sjmallett uint32_t reserved_2_31 : 30; 5362215976Sjmallett uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 5363215976Sjmallett uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 5364215976Sjmallett#else 5365215976Sjmallett uint32_t m_vend0_drp : 1; 5366215976Sjmallett uint32_t m_vend1_drp : 1; 5367215976Sjmallett uint32_t reserved_2_31 : 30; 5368215976Sjmallett#endif 5369232812Sjmallett } cn52xx; 5370232812Sjmallett struct cvmx_pcieepx_cfg456_cn52xx cn52xxp1; 5371232812Sjmallett struct cvmx_pcieepx_cfg456_cn52xx cn56xx; 5372232812Sjmallett struct cvmx_pcieepx_cfg456_cn52xx cn56xxp1; 5373232812Sjmallett struct cvmx_pcieepx_cfg456_s cn61xx; 5374232812Sjmallett struct cvmx_pcieepx_cfg456_cn52xx cn63xx; 5375232812Sjmallett struct cvmx_pcieepx_cfg456_cn52xx cn63xxp1; 5376232812Sjmallett struct cvmx_pcieepx_cfg456_s cn66xx; 5377232812Sjmallett struct cvmx_pcieepx_cfg456_s cn68xx; 5378232812Sjmallett struct cvmx_pcieepx_cfg456_cn52xx cn68xxp1; 5379232812Sjmallett struct cvmx_pcieepx_cfg456_s cnf71xx; 5380215976Sjmallett}; 5381215976Sjmalletttypedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t; 5382215976Sjmallett 5383215976Sjmallett/** 5384215976Sjmallett * cvmx_pcieep#_cfg458 5385215976Sjmallett * 5386215976Sjmallett * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 0 config space 5387215976Sjmallett * (Debug Register 0) 5388215976Sjmallett */ 5389232812Sjmallettunion cvmx_pcieepx_cfg458 { 5390215976Sjmallett uint32_t u32; 5391232812Sjmallett struct cvmx_pcieepx_cfg458_s { 5392232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5393215976Sjmallett uint32_t dbg_info_l32 : 32; /**< Debug Info Lower 32 Bits */ 5394215976Sjmallett#else 5395215976Sjmallett uint32_t dbg_info_l32 : 32; 5396215976Sjmallett#endif 5397215976Sjmallett } s; 5398215976Sjmallett struct cvmx_pcieepx_cfg458_s cn52xx; 5399215976Sjmallett struct cvmx_pcieepx_cfg458_s cn52xxp1; 5400215976Sjmallett struct cvmx_pcieepx_cfg458_s cn56xx; 5401215976Sjmallett struct cvmx_pcieepx_cfg458_s cn56xxp1; 5402232812Sjmallett struct cvmx_pcieepx_cfg458_s cn61xx; 5403215976Sjmallett struct cvmx_pcieepx_cfg458_s cn63xx; 5404215976Sjmallett struct cvmx_pcieepx_cfg458_s cn63xxp1; 5405232812Sjmallett struct cvmx_pcieepx_cfg458_s cn66xx; 5406232812Sjmallett struct cvmx_pcieepx_cfg458_s cn68xx; 5407232812Sjmallett struct cvmx_pcieepx_cfg458_s cn68xxp1; 5408232812Sjmallett struct cvmx_pcieepx_cfg458_s cnf71xx; 5409215976Sjmallett}; 5410215976Sjmalletttypedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t; 5411215976Sjmallett 5412215976Sjmallett/** 5413215976Sjmallett * cvmx_pcieep#_cfg459 5414215976Sjmallett * 5415215976Sjmallett * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 0 config space 5416215976Sjmallett * (Debug Register 1) 5417215976Sjmallett */ 5418232812Sjmallettunion cvmx_pcieepx_cfg459 { 5419215976Sjmallett uint32_t u32; 5420232812Sjmallett struct cvmx_pcieepx_cfg459_s { 5421232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5422215976Sjmallett uint32_t dbg_info_u32 : 32; /**< Debug Info Upper 32 Bits */ 5423215976Sjmallett#else 5424215976Sjmallett uint32_t dbg_info_u32 : 32; 5425215976Sjmallett#endif 5426215976Sjmallett } s; 5427215976Sjmallett struct cvmx_pcieepx_cfg459_s cn52xx; 5428215976Sjmallett struct cvmx_pcieepx_cfg459_s cn52xxp1; 5429215976Sjmallett struct cvmx_pcieepx_cfg459_s cn56xx; 5430215976Sjmallett struct cvmx_pcieepx_cfg459_s cn56xxp1; 5431232812Sjmallett struct cvmx_pcieepx_cfg459_s cn61xx; 5432215976Sjmallett struct cvmx_pcieepx_cfg459_s cn63xx; 5433215976Sjmallett struct cvmx_pcieepx_cfg459_s cn63xxp1; 5434232812Sjmallett struct cvmx_pcieepx_cfg459_s cn66xx; 5435232812Sjmallett struct cvmx_pcieepx_cfg459_s cn68xx; 5436232812Sjmallett struct cvmx_pcieepx_cfg459_s cn68xxp1; 5437232812Sjmallett struct cvmx_pcieepx_cfg459_s cnf71xx; 5438215976Sjmallett}; 5439215976Sjmalletttypedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t; 5440215976Sjmallett 5441215976Sjmallett/** 5442215976Sjmallett * cvmx_pcieep#_cfg460 5443215976Sjmallett * 5444215976Sjmallett * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 0 config space 5445215976Sjmallett * (Transmit Posted FC Credit Status) 5446215976Sjmallett */ 5447232812Sjmallettunion cvmx_pcieepx_cfg460 { 5448215976Sjmallett uint32_t u32; 5449232812Sjmallett struct cvmx_pcieepx_cfg460_s { 5450232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5451215976Sjmallett uint32_t reserved_20_31 : 12; 5452215976Sjmallett uint32_t tphfcc : 8; /**< Transmit Posted Header FC Credits 5453215976Sjmallett The Posted Header credits advertised by the receiver at the 5454215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5455215976Sjmallett uint32_t tpdfcc : 12; /**< Transmit Posted Data FC Credits 5456215976Sjmallett The Posted Data credits advertised by the receiver at the other 5457215976Sjmallett end of the Link, updated with each UpdateFC DLLP. */ 5458215976Sjmallett#else 5459215976Sjmallett uint32_t tpdfcc : 12; 5460215976Sjmallett uint32_t tphfcc : 8; 5461215976Sjmallett uint32_t reserved_20_31 : 12; 5462215976Sjmallett#endif 5463215976Sjmallett } s; 5464215976Sjmallett struct cvmx_pcieepx_cfg460_s cn52xx; 5465215976Sjmallett struct cvmx_pcieepx_cfg460_s cn52xxp1; 5466215976Sjmallett struct cvmx_pcieepx_cfg460_s cn56xx; 5467215976Sjmallett struct cvmx_pcieepx_cfg460_s cn56xxp1; 5468232812Sjmallett struct cvmx_pcieepx_cfg460_s cn61xx; 5469215976Sjmallett struct cvmx_pcieepx_cfg460_s cn63xx; 5470215976Sjmallett struct cvmx_pcieepx_cfg460_s cn63xxp1; 5471232812Sjmallett struct cvmx_pcieepx_cfg460_s cn66xx; 5472232812Sjmallett struct cvmx_pcieepx_cfg460_s cn68xx; 5473232812Sjmallett struct cvmx_pcieepx_cfg460_s cn68xxp1; 5474232812Sjmallett struct cvmx_pcieepx_cfg460_s cnf71xx; 5475215976Sjmallett}; 5476215976Sjmalletttypedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t; 5477215976Sjmallett 5478215976Sjmallett/** 5479215976Sjmallett * cvmx_pcieep#_cfg461 5480215976Sjmallett * 5481215976Sjmallett * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 0 config space 5482215976Sjmallett * (Transmit Non-Posted FC Credit Status) 5483215976Sjmallett */ 5484232812Sjmallettunion cvmx_pcieepx_cfg461 { 5485215976Sjmallett uint32_t u32; 5486232812Sjmallett struct cvmx_pcieepx_cfg461_s { 5487232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5488215976Sjmallett uint32_t reserved_20_31 : 12; 5489215976Sjmallett uint32_t tchfcc : 8; /**< Transmit Non-Posted Header FC Credits 5490215976Sjmallett The Non-Posted Header credits advertised by the receiver at the 5491215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5492215976Sjmallett uint32_t tcdfcc : 12; /**< Transmit Non-Posted Data FC Credits 5493215976Sjmallett The Non-Posted Data credits advertised by the receiver at the 5494215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5495215976Sjmallett#else 5496215976Sjmallett uint32_t tcdfcc : 12; 5497215976Sjmallett uint32_t tchfcc : 8; 5498215976Sjmallett uint32_t reserved_20_31 : 12; 5499215976Sjmallett#endif 5500215976Sjmallett } s; 5501215976Sjmallett struct cvmx_pcieepx_cfg461_s cn52xx; 5502215976Sjmallett struct cvmx_pcieepx_cfg461_s cn52xxp1; 5503215976Sjmallett struct cvmx_pcieepx_cfg461_s cn56xx; 5504215976Sjmallett struct cvmx_pcieepx_cfg461_s cn56xxp1; 5505232812Sjmallett struct cvmx_pcieepx_cfg461_s cn61xx; 5506215976Sjmallett struct cvmx_pcieepx_cfg461_s cn63xx; 5507215976Sjmallett struct cvmx_pcieepx_cfg461_s cn63xxp1; 5508232812Sjmallett struct cvmx_pcieepx_cfg461_s cn66xx; 5509232812Sjmallett struct cvmx_pcieepx_cfg461_s cn68xx; 5510232812Sjmallett struct cvmx_pcieepx_cfg461_s cn68xxp1; 5511232812Sjmallett struct cvmx_pcieepx_cfg461_s cnf71xx; 5512215976Sjmallett}; 5513215976Sjmalletttypedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t; 5514215976Sjmallett 5515215976Sjmallett/** 5516215976Sjmallett * cvmx_pcieep#_cfg462 5517215976Sjmallett * 5518215976Sjmallett * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 0 config space 5519215976Sjmallett * (Transmit Completion FC Credit Status ) 5520215976Sjmallett */ 5521232812Sjmallettunion cvmx_pcieepx_cfg462 { 5522215976Sjmallett uint32_t u32; 5523232812Sjmallett struct cvmx_pcieepx_cfg462_s { 5524232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5525215976Sjmallett uint32_t reserved_20_31 : 12; 5526215976Sjmallett uint32_t tchfcc : 8; /**< Transmit Completion Header FC Credits 5527215976Sjmallett The Completion Header credits advertised by the receiver at the 5528215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5529215976Sjmallett uint32_t tcdfcc : 12; /**< Transmit Completion Data FC Credits 5530215976Sjmallett The Completion Data credits advertised by the receiver at the 5531215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5532215976Sjmallett#else 5533215976Sjmallett uint32_t tcdfcc : 12; 5534215976Sjmallett uint32_t tchfcc : 8; 5535215976Sjmallett uint32_t reserved_20_31 : 12; 5536215976Sjmallett#endif 5537215976Sjmallett } s; 5538215976Sjmallett struct cvmx_pcieepx_cfg462_s cn52xx; 5539215976Sjmallett struct cvmx_pcieepx_cfg462_s cn52xxp1; 5540215976Sjmallett struct cvmx_pcieepx_cfg462_s cn56xx; 5541215976Sjmallett struct cvmx_pcieepx_cfg462_s cn56xxp1; 5542232812Sjmallett struct cvmx_pcieepx_cfg462_s cn61xx; 5543215976Sjmallett struct cvmx_pcieepx_cfg462_s cn63xx; 5544215976Sjmallett struct cvmx_pcieepx_cfg462_s cn63xxp1; 5545232812Sjmallett struct cvmx_pcieepx_cfg462_s cn66xx; 5546232812Sjmallett struct cvmx_pcieepx_cfg462_s cn68xx; 5547232812Sjmallett struct cvmx_pcieepx_cfg462_s cn68xxp1; 5548232812Sjmallett struct cvmx_pcieepx_cfg462_s cnf71xx; 5549215976Sjmallett}; 5550215976Sjmalletttypedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t; 5551215976Sjmallett 5552215976Sjmallett/** 5553215976Sjmallett * cvmx_pcieep#_cfg463 5554215976Sjmallett * 5555215976Sjmallett * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 0 config space 5556215976Sjmallett * (Queue Status) 5557215976Sjmallett */ 5558232812Sjmallettunion cvmx_pcieepx_cfg463 { 5559215976Sjmallett uint32_t u32; 5560232812Sjmallett struct cvmx_pcieepx_cfg463_s { 5561232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5562215976Sjmallett uint32_t reserved_3_31 : 29; 5563215976Sjmallett uint32_t rqne : 1; /**< Received Queue Not Empty 5564215976Sjmallett Indicates there is data in one or more of the receive buffers. */ 5565215976Sjmallett uint32_t trbne : 1; /**< Transmit Retry Buffer Not Empty 5566215976Sjmallett Indicates that there is data in the transmit retry buffer. */ 5567215976Sjmallett uint32_t rtlpfccnr : 1; /**< Received TLP FC Credits Not Returned 5568215976Sjmallett Indicates that the PCI Express bus has sent a TLP but has not 5569215976Sjmallett yet received an UpdateFC DLLP indicating that the credits for 5570215976Sjmallett that TLP have been restored by the receiver at the other end of 5571215976Sjmallett the Link. */ 5572215976Sjmallett#else 5573215976Sjmallett uint32_t rtlpfccnr : 1; 5574215976Sjmallett uint32_t trbne : 1; 5575215976Sjmallett uint32_t rqne : 1; 5576215976Sjmallett uint32_t reserved_3_31 : 29; 5577215976Sjmallett#endif 5578215976Sjmallett } s; 5579215976Sjmallett struct cvmx_pcieepx_cfg463_s cn52xx; 5580215976Sjmallett struct cvmx_pcieepx_cfg463_s cn52xxp1; 5581215976Sjmallett struct cvmx_pcieepx_cfg463_s cn56xx; 5582215976Sjmallett struct cvmx_pcieepx_cfg463_s cn56xxp1; 5583232812Sjmallett struct cvmx_pcieepx_cfg463_s cn61xx; 5584215976Sjmallett struct cvmx_pcieepx_cfg463_s cn63xx; 5585215976Sjmallett struct cvmx_pcieepx_cfg463_s cn63xxp1; 5586232812Sjmallett struct cvmx_pcieepx_cfg463_s cn66xx; 5587232812Sjmallett struct cvmx_pcieepx_cfg463_s cn68xx; 5588232812Sjmallett struct cvmx_pcieepx_cfg463_s cn68xxp1; 5589232812Sjmallett struct cvmx_pcieepx_cfg463_s cnf71xx; 5590215976Sjmallett}; 5591215976Sjmalletttypedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t; 5592215976Sjmallett 5593215976Sjmallett/** 5594215976Sjmallett * cvmx_pcieep#_cfg464 5595215976Sjmallett * 5596215976Sjmallett * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 0 config space 5597215976Sjmallett * (VC Transmit Arbitration Register 1) 5598215976Sjmallett */ 5599232812Sjmallettunion cvmx_pcieepx_cfg464 { 5600215976Sjmallett uint32_t u32; 5601232812Sjmallett struct cvmx_pcieepx_cfg464_s { 5602232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5603215976Sjmallett uint32_t wrr_vc3 : 8; /**< WRR Weight for VC3 */ 5604215976Sjmallett uint32_t wrr_vc2 : 8; /**< WRR Weight for VC2 */ 5605215976Sjmallett uint32_t wrr_vc1 : 8; /**< WRR Weight for VC1 */ 5606215976Sjmallett uint32_t wrr_vc0 : 8; /**< WRR Weight for VC0 */ 5607215976Sjmallett#else 5608215976Sjmallett uint32_t wrr_vc0 : 8; 5609215976Sjmallett uint32_t wrr_vc1 : 8; 5610215976Sjmallett uint32_t wrr_vc2 : 8; 5611215976Sjmallett uint32_t wrr_vc3 : 8; 5612215976Sjmallett#endif 5613215976Sjmallett } s; 5614215976Sjmallett struct cvmx_pcieepx_cfg464_s cn52xx; 5615215976Sjmallett struct cvmx_pcieepx_cfg464_s cn52xxp1; 5616215976Sjmallett struct cvmx_pcieepx_cfg464_s cn56xx; 5617215976Sjmallett struct cvmx_pcieepx_cfg464_s cn56xxp1; 5618232812Sjmallett struct cvmx_pcieepx_cfg464_s cn61xx; 5619215976Sjmallett struct cvmx_pcieepx_cfg464_s cn63xx; 5620215976Sjmallett struct cvmx_pcieepx_cfg464_s cn63xxp1; 5621232812Sjmallett struct cvmx_pcieepx_cfg464_s cn66xx; 5622232812Sjmallett struct cvmx_pcieepx_cfg464_s cn68xx; 5623232812Sjmallett struct cvmx_pcieepx_cfg464_s cn68xxp1; 5624232812Sjmallett struct cvmx_pcieepx_cfg464_s cnf71xx; 5625215976Sjmallett}; 5626215976Sjmalletttypedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t; 5627215976Sjmallett 5628215976Sjmallett/** 5629215976Sjmallett * cvmx_pcieep#_cfg465 5630215976Sjmallett * 5631215976Sjmallett * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of PCIE type 0 config space 5632215976Sjmallett * (VC Transmit Arbitration Register 2) 5633215976Sjmallett */ 5634232812Sjmallettunion cvmx_pcieepx_cfg465 { 5635215976Sjmallett uint32_t u32; 5636232812Sjmallett struct cvmx_pcieepx_cfg465_s { 5637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5638215976Sjmallett uint32_t wrr_vc7 : 8; /**< WRR Weight for VC7 */ 5639215976Sjmallett uint32_t wrr_vc6 : 8; /**< WRR Weight for VC6 */ 5640215976Sjmallett uint32_t wrr_vc5 : 8; /**< WRR Weight for VC5 */ 5641215976Sjmallett uint32_t wrr_vc4 : 8; /**< WRR Weight for VC4 */ 5642215976Sjmallett#else 5643215976Sjmallett uint32_t wrr_vc4 : 8; 5644215976Sjmallett uint32_t wrr_vc5 : 8; 5645215976Sjmallett uint32_t wrr_vc6 : 8; 5646215976Sjmallett uint32_t wrr_vc7 : 8; 5647215976Sjmallett#endif 5648215976Sjmallett } s; 5649215976Sjmallett struct cvmx_pcieepx_cfg465_s cn52xx; 5650215976Sjmallett struct cvmx_pcieepx_cfg465_s cn52xxp1; 5651215976Sjmallett struct cvmx_pcieepx_cfg465_s cn56xx; 5652215976Sjmallett struct cvmx_pcieepx_cfg465_s cn56xxp1; 5653232812Sjmallett struct cvmx_pcieepx_cfg465_s cn61xx; 5654215976Sjmallett struct cvmx_pcieepx_cfg465_s cn63xx; 5655215976Sjmallett struct cvmx_pcieepx_cfg465_s cn63xxp1; 5656232812Sjmallett struct cvmx_pcieepx_cfg465_s cn66xx; 5657232812Sjmallett struct cvmx_pcieepx_cfg465_s cn68xx; 5658232812Sjmallett struct cvmx_pcieepx_cfg465_s cn68xxp1; 5659232812Sjmallett struct cvmx_pcieepx_cfg465_s cnf71xx; 5660215976Sjmallett}; 5661215976Sjmalletttypedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t; 5662215976Sjmallett 5663215976Sjmallett/** 5664215976Sjmallett * cvmx_pcieep#_cfg466 5665215976Sjmallett * 5666215976Sjmallett * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 0 config space 5667215976Sjmallett * (VC0 Posted Receive Queue Control) 5668215976Sjmallett */ 5669232812Sjmallettunion cvmx_pcieepx_cfg466 { 5670215976Sjmallett uint32_t u32; 5671232812Sjmallett struct cvmx_pcieepx_cfg466_s { 5672232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5673215976Sjmallett uint32_t rx_queue_order : 1; /**< VC Ordering for Receive Queues 5674215976Sjmallett Determines the VC ordering rule for the receive queues, used 5675215976Sjmallett only in the segmented-buffer configuration, 5676215976Sjmallett writable through PEM(0..1)_CFG_WR: 5677215976Sjmallett o 1: Strict ordering, higher numbered VCs have higher priority 5678215976Sjmallett o 0: Round robin 5679215976Sjmallett However, the application must not change this field. */ 5680215976Sjmallett uint32_t type_ordering : 1; /**< TLP Type Ordering for VC0 5681215976Sjmallett Determines the TLP type ordering rule for VC0 receive queues, 5682215976Sjmallett used only in the segmented-buffer configuration, writable 5683215976Sjmallett through PEM(0..1)_CFG_WR: 5684215976Sjmallett o 1: Ordering of received TLPs follows the rules in 5685215976Sjmallett PCI Express Base Specification 5686215976Sjmallett o 0: Strict ordering for received TLPs: Posted, then 5687215976Sjmallett Completion, then Non-Posted 5688215976Sjmallett However, the application must not change this field. */ 5689215976Sjmallett uint32_t reserved_24_29 : 6; 5690215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Posted TLP Queue Mode 5691215976Sjmallett The operating mode of the Posted receive queue for VC0, used 5692215976Sjmallett only in the segmented-buffer configuration, writable through 5693215976Sjmallett PEM(0..1)_CFG_WR. 5694215976Sjmallett However, the application must not change this field. 5695215976Sjmallett Only one bit can be set at a time: 5696215976Sjmallett o Bit 23: Bypass 5697215976Sjmallett o Bit 22: Cut-through 5698215976Sjmallett o Bit 21: Store-and-forward */ 5699215976Sjmallett uint32_t reserved_20_20 : 1; 5700215976Sjmallett uint32_t header_credits : 8; /**< VC0 Posted Header Credits 5701215976Sjmallett The number of initial Posted header credits for VC0, used for 5702215976Sjmallett all receive queue buffer configurations. 5703215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5704215976Sjmallett However, the application must not change this field. */ 5705215976Sjmallett uint32_t data_credits : 12; /**< VC0 Posted Data Credits 5706215976Sjmallett The number of initial Posted data credits for VC0, used for all 5707215976Sjmallett receive queue buffer configurations. 5708215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5709215976Sjmallett However, the application must not change this field. */ 5710215976Sjmallett#else 5711215976Sjmallett uint32_t data_credits : 12; 5712215976Sjmallett uint32_t header_credits : 8; 5713215976Sjmallett uint32_t reserved_20_20 : 1; 5714215976Sjmallett uint32_t queue_mode : 3; 5715215976Sjmallett uint32_t reserved_24_29 : 6; 5716215976Sjmallett uint32_t type_ordering : 1; 5717215976Sjmallett uint32_t rx_queue_order : 1; 5718215976Sjmallett#endif 5719215976Sjmallett } s; 5720215976Sjmallett struct cvmx_pcieepx_cfg466_s cn52xx; 5721215976Sjmallett struct cvmx_pcieepx_cfg466_s cn52xxp1; 5722215976Sjmallett struct cvmx_pcieepx_cfg466_s cn56xx; 5723215976Sjmallett struct cvmx_pcieepx_cfg466_s cn56xxp1; 5724232812Sjmallett struct cvmx_pcieepx_cfg466_s cn61xx; 5725215976Sjmallett struct cvmx_pcieepx_cfg466_s cn63xx; 5726215976Sjmallett struct cvmx_pcieepx_cfg466_s cn63xxp1; 5727232812Sjmallett struct cvmx_pcieepx_cfg466_s cn66xx; 5728232812Sjmallett struct cvmx_pcieepx_cfg466_s cn68xx; 5729232812Sjmallett struct cvmx_pcieepx_cfg466_s cn68xxp1; 5730232812Sjmallett struct cvmx_pcieepx_cfg466_s cnf71xx; 5731215976Sjmallett}; 5732215976Sjmalletttypedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t; 5733215976Sjmallett 5734215976Sjmallett/** 5735215976Sjmallett * cvmx_pcieep#_cfg467 5736215976Sjmallett * 5737215976Sjmallett * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 0 config space 5738215976Sjmallett * (VC0 Non-Posted Receive Queue Control) 5739215976Sjmallett */ 5740232812Sjmallettunion cvmx_pcieepx_cfg467 { 5741215976Sjmallett uint32_t u32; 5742232812Sjmallett struct cvmx_pcieepx_cfg467_s { 5743232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5744215976Sjmallett uint32_t reserved_24_31 : 8; 5745215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Non-Posted TLP Queue Mode 5746215976Sjmallett The operating mode of the Non-Posted receive queue for VC0, 5747215976Sjmallett used only in the segmented-buffer configuration, writable 5748215976Sjmallett through PEM(0..1)_CFG_WR. 5749215976Sjmallett Only one bit can be set at a time: 5750215976Sjmallett o Bit 23: Bypass 5751215976Sjmallett o Bit 22: Cut-through 5752215976Sjmallett o Bit 21: Store-and-forward 5753215976Sjmallett However, the application must not change this field. */ 5754215976Sjmallett uint32_t reserved_20_20 : 1; 5755215976Sjmallett uint32_t header_credits : 8; /**< VC0 Non-Posted Header Credits 5756215976Sjmallett The number of initial Non-Posted header credits for VC0, used 5757215976Sjmallett for all receive queue buffer configurations. 5758215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5759215976Sjmallett However, the application must not change this field. */ 5760215976Sjmallett uint32_t data_credits : 12; /**< VC0 Non-Posted Data Credits 5761215976Sjmallett The number of initial Non-Posted data credits for VC0, used for 5762215976Sjmallett all receive queue buffer configurations. 5763215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5764215976Sjmallett However, the application must not change this field. */ 5765215976Sjmallett#else 5766215976Sjmallett uint32_t data_credits : 12; 5767215976Sjmallett uint32_t header_credits : 8; 5768215976Sjmallett uint32_t reserved_20_20 : 1; 5769215976Sjmallett uint32_t queue_mode : 3; 5770215976Sjmallett uint32_t reserved_24_31 : 8; 5771215976Sjmallett#endif 5772215976Sjmallett } s; 5773215976Sjmallett struct cvmx_pcieepx_cfg467_s cn52xx; 5774215976Sjmallett struct cvmx_pcieepx_cfg467_s cn52xxp1; 5775215976Sjmallett struct cvmx_pcieepx_cfg467_s cn56xx; 5776215976Sjmallett struct cvmx_pcieepx_cfg467_s cn56xxp1; 5777232812Sjmallett struct cvmx_pcieepx_cfg467_s cn61xx; 5778215976Sjmallett struct cvmx_pcieepx_cfg467_s cn63xx; 5779215976Sjmallett struct cvmx_pcieepx_cfg467_s cn63xxp1; 5780232812Sjmallett struct cvmx_pcieepx_cfg467_s cn66xx; 5781232812Sjmallett struct cvmx_pcieepx_cfg467_s cn68xx; 5782232812Sjmallett struct cvmx_pcieepx_cfg467_s cn68xxp1; 5783232812Sjmallett struct cvmx_pcieepx_cfg467_s cnf71xx; 5784215976Sjmallett}; 5785215976Sjmalletttypedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t; 5786215976Sjmallett 5787215976Sjmallett/** 5788215976Sjmallett * cvmx_pcieep#_cfg468 5789215976Sjmallett * 5790215976Sjmallett * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 0 config space 5791215976Sjmallett * (VC0 Completion Receive Queue Control) 5792215976Sjmallett */ 5793232812Sjmallettunion cvmx_pcieepx_cfg468 { 5794215976Sjmallett uint32_t u32; 5795232812Sjmallett struct cvmx_pcieepx_cfg468_s { 5796232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5797215976Sjmallett uint32_t reserved_24_31 : 8; 5798215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Completion TLP Queue Mode 5799215976Sjmallett The operating mode of the Completion receive queue for VC0, 5800215976Sjmallett used only in the segmented-buffer configuration, writable 5801215976Sjmallett through PEM(0..1)_CFG_WR. 5802215976Sjmallett Only one bit can be set at a time: 5803215976Sjmallett o Bit 23: Bypass 5804215976Sjmallett o Bit 22: Cut-through 5805215976Sjmallett o Bit 21: Store-and-forward 5806215976Sjmallett However, the application must not change this field. */ 5807215976Sjmallett uint32_t reserved_20_20 : 1; 5808215976Sjmallett uint32_t header_credits : 8; /**< VC0 Completion Header Credits 5809215976Sjmallett The number of initial Completion header credits for VC0, used 5810215976Sjmallett for all receive queue buffer configurations. 5811215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5812215976Sjmallett However, the application must not change this field. */ 5813215976Sjmallett uint32_t data_credits : 12; /**< VC0 Completion Data Credits 5814215976Sjmallett The number of initial Completion data credits for VC0, used for 5815215976Sjmallett all receive queue buffer configurations. 5816215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5817215976Sjmallett However, the application must not change this field. */ 5818215976Sjmallett#else 5819215976Sjmallett uint32_t data_credits : 12; 5820215976Sjmallett uint32_t header_credits : 8; 5821215976Sjmallett uint32_t reserved_20_20 : 1; 5822215976Sjmallett uint32_t queue_mode : 3; 5823215976Sjmallett uint32_t reserved_24_31 : 8; 5824215976Sjmallett#endif 5825215976Sjmallett } s; 5826215976Sjmallett struct cvmx_pcieepx_cfg468_s cn52xx; 5827215976Sjmallett struct cvmx_pcieepx_cfg468_s cn52xxp1; 5828215976Sjmallett struct cvmx_pcieepx_cfg468_s cn56xx; 5829215976Sjmallett struct cvmx_pcieepx_cfg468_s cn56xxp1; 5830232812Sjmallett struct cvmx_pcieepx_cfg468_s cn61xx; 5831215976Sjmallett struct cvmx_pcieepx_cfg468_s cn63xx; 5832215976Sjmallett struct cvmx_pcieepx_cfg468_s cn63xxp1; 5833232812Sjmallett struct cvmx_pcieepx_cfg468_s cn66xx; 5834232812Sjmallett struct cvmx_pcieepx_cfg468_s cn68xx; 5835232812Sjmallett struct cvmx_pcieepx_cfg468_s cn68xxp1; 5836232812Sjmallett struct cvmx_pcieepx_cfg468_s cnf71xx; 5837215976Sjmallett}; 5838215976Sjmalletttypedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t; 5839215976Sjmallett 5840215976Sjmallett/** 5841215976Sjmallett * cvmx_pcieep#_cfg490 5842215976Sjmallett * 5843215976Sjmallett * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space 5844215976Sjmallett * (VC0 Posted Buffer Depth) 5845215976Sjmallett */ 5846232812Sjmallettunion cvmx_pcieepx_cfg490 { 5847215976Sjmallett uint32_t u32; 5848232812Sjmallett struct cvmx_pcieepx_cfg490_s { 5849232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5850215976Sjmallett uint32_t reserved_26_31 : 6; 5851215976Sjmallett uint32_t header_depth : 10; /**< VC0 Posted Header Queue Depth 5852215976Sjmallett Sets the number of entries in the Posted header queue for VC0 5853215976Sjmallett when using the segmented-buffer configuration, writable through 5854215976Sjmallett PEM(0..1)_CFG_WR. 5855215976Sjmallett However, the application must not change this field. */ 5856215976Sjmallett uint32_t reserved_14_15 : 2; 5857215976Sjmallett uint32_t data_depth : 14; /**< VC0 Posted Data Queue Depth 5858215976Sjmallett Sets the number of entries in the Posted data queue for VC0 5859215976Sjmallett when using the segmented-buffer configuration, writable 5860215976Sjmallett through PEM(0..1)_CFG_WR. 5861215976Sjmallett However, the application must not change this field. */ 5862215976Sjmallett#else 5863215976Sjmallett uint32_t data_depth : 14; 5864215976Sjmallett uint32_t reserved_14_15 : 2; 5865215976Sjmallett uint32_t header_depth : 10; 5866215976Sjmallett uint32_t reserved_26_31 : 6; 5867215976Sjmallett#endif 5868215976Sjmallett } s; 5869215976Sjmallett struct cvmx_pcieepx_cfg490_s cn52xx; 5870215976Sjmallett struct cvmx_pcieepx_cfg490_s cn52xxp1; 5871215976Sjmallett struct cvmx_pcieepx_cfg490_s cn56xx; 5872215976Sjmallett struct cvmx_pcieepx_cfg490_s cn56xxp1; 5873232812Sjmallett struct cvmx_pcieepx_cfg490_s cn61xx; 5874215976Sjmallett struct cvmx_pcieepx_cfg490_s cn63xx; 5875215976Sjmallett struct cvmx_pcieepx_cfg490_s cn63xxp1; 5876232812Sjmallett struct cvmx_pcieepx_cfg490_s cn66xx; 5877232812Sjmallett struct cvmx_pcieepx_cfg490_s cn68xx; 5878232812Sjmallett struct cvmx_pcieepx_cfg490_s cn68xxp1; 5879232812Sjmallett struct cvmx_pcieepx_cfg490_s cnf71xx; 5880215976Sjmallett}; 5881215976Sjmalletttypedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t; 5882215976Sjmallett 5883215976Sjmallett/** 5884215976Sjmallett * cvmx_pcieep#_cfg491 5885215976Sjmallett * 5886215976Sjmallett * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space 5887215976Sjmallett * (VC0 Non-Posted Buffer Depth) 5888215976Sjmallett */ 5889232812Sjmallettunion cvmx_pcieepx_cfg491 { 5890215976Sjmallett uint32_t u32; 5891232812Sjmallett struct cvmx_pcieepx_cfg491_s { 5892232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5893215976Sjmallett uint32_t reserved_26_31 : 6; 5894215976Sjmallett uint32_t header_depth : 10; /**< VC0 Non-Posted Header Queue Depth 5895215976Sjmallett Sets the number of entries in the Non-Posted header queue for 5896215976Sjmallett VC0 when using the segmented-buffer configuration, writable 5897215976Sjmallett through PEM(0..1)_CFG_WR. 5898215976Sjmallett However, the application must not change this field. */ 5899215976Sjmallett uint32_t reserved_14_15 : 2; 5900215976Sjmallett uint32_t data_depth : 14; /**< VC0 Non-Posted Data Queue Depth 5901215976Sjmallett Sets the number of entries in the Non-Posted data queue for VC0 5902215976Sjmallett when using the segmented-buffer configuration, writable 5903215976Sjmallett through PEM(0..1)_CFG_WR. 5904215976Sjmallett However, the application must not change this field. */ 5905215976Sjmallett#else 5906215976Sjmallett uint32_t data_depth : 14; 5907215976Sjmallett uint32_t reserved_14_15 : 2; 5908215976Sjmallett uint32_t header_depth : 10; 5909215976Sjmallett uint32_t reserved_26_31 : 6; 5910215976Sjmallett#endif 5911215976Sjmallett } s; 5912215976Sjmallett struct cvmx_pcieepx_cfg491_s cn52xx; 5913215976Sjmallett struct cvmx_pcieepx_cfg491_s cn52xxp1; 5914215976Sjmallett struct cvmx_pcieepx_cfg491_s cn56xx; 5915215976Sjmallett struct cvmx_pcieepx_cfg491_s cn56xxp1; 5916232812Sjmallett struct cvmx_pcieepx_cfg491_s cn61xx; 5917215976Sjmallett struct cvmx_pcieepx_cfg491_s cn63xx; 5918215976Sjmallett struct cvmx_pcieepx_cfg491_s cn63xxp1; 5919232812Sjmallett struct cvmx_pcieepx_cfg491_s cn66xx; 5920232812Sjmallett struct cvmx_pcieepx_cfg491_s cn68xx; 5921232812Sjmallett struct cvmx_pcieepx_cfg491_s cn68xxp1; 5922232812Sjmallett struct cvmx_pcieepx_cfg491_s cnf71xx; 5923215976Sjmallett}; 5924215976Sjmalletttypedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t; 5925215976Sjmallett 5926215976Sjmallett/** 5927215976Sjmallett * cvmx_pcieep#_cfg492 5928215976Sjmallett * 5929215976Sjmallett * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space 5930215976Sjmallett * (VC0 Completion Buffer Depth) 5931215976Sjmallett */ 5932232812Sjmallettunion cvmx_pcieepx_cfg492 { 5933215976Sjmallett uint32_t u32; 5934232812Sjmallett struct cvmx_pcieepx_cfg492_s { 5935232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5936215976Sjmallett uint32_t reserved_26_31 : 6; 5937215976Sjmallett uint32_t header_depth : 10; /**< VC0 Completion Header Queue Depth 5938215976Sjmallett Sets the number of entries in the Completion header queue for 5939215976Sjmallett VC0 when using the segmented-buffer configuration, writable 5940215976Sjmallett through PEM(0..1)_CFG_WR. 5941215976Sjmallett However, the application must not change this field. */ 5942215976Sjmallett uint32_t reserved_14_15 : 2; 5943215976Sjmallett uint32_t data_depth : 14; /**< VC0 Completion Data Queue Depth 5944215976Sjmallett Sets the number of entries in the Completion data queue for VC0 5945215976Sjmallett when using the segmented-buffer configuration, writable 5946215976Sjmallett through PEM(0..1)_CFG_WR. 5947215976Sjmallett However, the application must not change this field. */ 5948215976Sjmallett#else 5949215976Sjmallett uint32_t data_depth : 14; 5950215976Sjmallett uint32_t reserved_14_15 : 2; 5951215976Sjmallett uint32_t header_depth : 10; 5952215976Sjmallett uint32_t reserved_26_31 : 6; 5953215976Sjmallett#endif 5954215976Sjmallett } s; 5955215976Sjmallett struct cvmx_pcieepx_cfg492_s cn52xx; 5956215976Sjmallett struct cvmx_pcieepx_cfg492_s cn52xxp1; 5957215976Sjmallett struct cvmx_pcieepx_cfg492_s cn56xx; 5958215976Sjmallett struct cvmx_pcieepx_cfg492_s cn56xxp1; 5959232812Sjmallett struct cvmx_pcieepx_cfg492_s cn61xx; 5960215976Sjmallett struct cvmx_pcieepx_cfg492_s cn63xx; 5961215976Sjmallett struct cvmx_pcieepx_cfg492_s cn63xxp1; 5962232812Sjmallett struct cvmx_pcieepx_cfg492_s cn66xx; 5963232812Sjmallett struct cvmx_pcieepx_cfg492_s cn68xx; 5964232812Sjmallett struct cvmx_pcieepx_cfg492_s cn68xxp1; 5965232812Sjmallett struct cvmx_pcieepx_cfg492_s cnf71xx; 5966215976Sjmallett}; 5967215976Sjmalletttypedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t; 5968215976Sjmallett 5969215976Sjmallett/** 5970215976Sjmallett * cvmx_pcieep#_cfg515 5971215976Sjmallett * 5972215976Sjmallett * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 0 config space 5973215976Sjmallett * (Port Logic Register (Gen2)) 5974215976Sjmallett */ 5975232812Sjmallettunion cvmx_pcieepx_cfg515 { 5976215976Sjmallett uint32_t u32; 5977232812Sjmallett struct cvmx_pcieepx_cfg515_s { 5978232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5979215976Sjmallett uint32_t reserved_21_31 : 11; 5980215976Sjmallett uint32_t s_d_e : 1; /**< SEL_DE_EMPHASIS 5981215976Sjmallett Used to set the de-emphasis level for upstream ports. */ 5982215976Sjmallett uint32_t ctcrb : 1; /**< Config Tx Compliance Receive Bit 5983215976Sjmallett When set to 1, signals LTSSM to transmit TS ordered sets 5984215976Sjmallett with the compliance receive bit assert (equal to 1). */ 5985215976Sjmallett uint32_t cpyts : 1; /**< Config PHY Tx Swing 5986215976Sjmallett Indicates the voltage level the PHY should drive. When set to 5987215976Sjmallett 1, indicates Full Swing. When set to 0, indicates Low Swing */ 5988215976Sjmallett uint32_t dsc : 1; /**< Directed Speed Change 5989232812Sjmallett o a write of '1' will initiate a speed change 5990232812Sjmallett o always reads a zero */ 5991215976Sjmallett uint32_t le : 9; /**< Lane Enable 5992215976Sjmallett Indicates the number of lanes to check for exit from electrical 5993215976Sjmallett idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2, 5994215976Sjmallett etc. Used to limit the maximum link width to ignore broken 5995215976Sjmallett lanes that detect a receiver, but will not exit electrical 5996215976Sjmallett idle and 5997215976Sjmallett would otherwise prevent a valid link from being configured. */ 5998215976Sjmallett uint32_t n_fts : 8; /**< N_FTS 5999215976Sjmallett Sets the Number of Fast Training Sequences (N_FTS) that 6000215976Sjmallett the core advertises as its N_FTS during GEN2 Link training. 6001215976Sjmallett This value is used to inform the Link partner about the PHYs 6002215976Sjmallett ability to recover synchronization after a low power state. 6003215976Sjmallett Note: Do not set N_FTS to zero; doing so can cause the 6004215976Sjmallett LTSSM to go into the recovery state when exiting from 6005215976Sjmallett L0s. */ 6006215976Sjmallett#else 6007215976Sjmallett uint32_t n_fts : 8; 6008215976Sjmallett uint32_t le : 9; 6009215976Sjmallett uint32_t dsc : 1; 6010215976Sjmallett uint32_t cpyts : 1; 6011215976Sjmallett uint32_t ctcrb : 1; 6012215976Sjmallett uint32_t s_d_e : 1; 6013215976Sjmallett uint32_t reserved_21_31 : 11; 6014215976Sjmallett#endif 6015215976Sjmallett } s; 6016232812Sjmallett struct cvmx_pcieepx_cfg515_s cn61xx; 6017215976Sjmallett struct cvmx_pcieepx_cfg515_s cn63xx; 6018215976Sjmallett struct cvmx_pcieepx_cfg515_s cn63xxp1; 6019232812Sjmallett struct cvmx_pcieepx_cfg515_s cn66xx; 6020232812Sjmallett struct cvmx_pcieepx_cfg515_s cn68xx; 6021232812Sjmallett struct cvmx_pcieepx_cfg515_s cn68xxp1; 6022232812Sjmallett struct cvmx_pcieepx_cfg515_s cnf71xx; 6023215976Sjmallett}; 6024215976Sjmalletttypedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t; 6025215976Sjmallett 6026215976Sjmallett/** 6027215976Sjmallett * cvmx_pcieep#_cfg516 6028215976Sjmallett * 6029215976Sjmallett * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 0 config space 6030215976Sjmallett * (PHY Status Register) 6031215976Sjmallett */ 6032232812Sjmallettunion cvmx_pcieepx_cfg516 { 6033215976Sjmallett uint32_t u32; 6034232812Sjmallett struct cvmx_pcieepx_cfg516_s { 6035232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6036215976Sjmallett uint32_t phy_stat : 32; /**< PHY Status */ 6037215976Sjmallett#else 6038215976Sjmallett uint32_t phy_stat : 32; 6039215976Sjmallett#endif 6040215976Sjmallett } s; 6041215976Sjmallett struct cvmx_pcieepx_cfg516_s cn52xx; 6042215976Sjmallett struct cvmx_pcieepx_cfg516_s cn52xxp1; 6043215976Sjmallett struct cvmx_pcieepx_cfg516_s cn56xx; 6044215976Sjmallett struct cvmx_pcieepx_cfg516_s cn56xxp1; 6045232812Sjmallett struct cvmx_pcieepx_cfg516_s cn61xx; 6046215976Sjmallett struct cvmx_pcieepx_cfg516_s cn63xx; 6047215976Sjmallett struct cvmx_pcieepx_cfg516_s cn63xxp1; 6048232812Sjmallett struct cvmx_pcieepx_cfg516_s cn66xx; 6049232812Sjmallett struct cvmx_pcieepx_cfg516_s cn68xx; 6050232812Sjmallett struct cvmx_pcieepx_cfg516_s cn68xxp1; 6051232812Sjmallett struct cvmx_pcieepx_cfg516_s cnf71xx; 6052215976Sjmallett}; 6053215976Sjmalletttypedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t; 6054215976Sjmallett 6055215976Sjmallett/** 6056215976Sjmallett * cvmx_pcieep#_cfg517 6057215976Sjmallett * 6058215976Sjmallett * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 0 config space 6059215976Sjmallett * (PHY Control Register) 6060215976Sjmallett */ 6061232812Sjmallettunion cvmx_pcieepx_cfg517 { 6062215976Sjmallett uint32_t u32; 6063232812Sjmallett struct cvmx_pcieepx_cfg517_s { 6064232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6065215976Sjmallett uint32_t phy_ctrl : 32; /**< PHY Control */ 6066215976Sjmallett#else 6067215976Sjmallett uint32_t phy_ctrl : 32; 6068215976Sjmallett#endif 6069215976Sjmallett } s; 6070215976Sjmallett struct cvmx_pcieepx_cfg517_s cn52xx; 6071215976Sjmallett struct cvmx_pcieepx_cfg517_s cn52xxp1; 6072215976Sjmallett struct cvmx_pcieepx_cfg517_s cn56xx; 6073215976Sjmallett struct cvmx_pcieepx_cfg517_s cn56xxp1; 6074232812Sjmallett struct cvmx_pcieepx_cfg517_s cn61xx; 6075215976Sjmallett struct cvmx_pcieepx_cfg517_s cn63xx; 6076215976Sjmallett struct cvmx_pcieepx_cfg517_s cn63xxp1; 6077232812Sjmallett struct cvmx_pcieepx_cfg517_s cn66xx; 6078232812Sjmallett struct cvmx_pcieepx_cfg517_s cn68xx; 6079232812Sjmallett struct cvmx_pcieepx_cfg517_s cn68xxp1; 6080232812Sjmallett struct cvmx_pcieepx_cfg517_s cnf71xx; 6081215976Sjmallett}; 6082215976Sjmalletttypedef union cvmx_pcieepx_cfg517 cvmx_pcieepx_cfg517_t; 6083215976Sjmallett 6084215976Sjmallett#endif 6085