1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * This header defines the CVMX interface to the NAND flash controller. The 50 * basic operations common to all NAND devices are supported by this API, but 51 * many more advanced functions are not support. The low level hardware supports 52 * all types of transactions, but this API only implements the must commonly 53 * used operations. This API performs no locking, so it is the responsibility of 54 * the caller to make sure only one thread of execution is accessing the NAND 55 * controller at a time. Most applications should not use this API directly but 56 * instead use a flash logical layer supplied through a secondary system. For 57 * example, the Linux MTD layer provides a driver for running JFFS2 on top of 58 * NAND flash. 59 * 60 * <h2>Selecting the NAND Chip</h2> 61 * 62 * Octeon's NAND controller assumes a single NAND chip is connected to a boot 63 * bus chip select. Throughout this API, NAND chips are referred to by the chip 64 * select they are connected to (0-7). Chip select 0 will only be a NAND chip 65 * when you are booting from NAND flash. 66 * 67 * <h2>NAND Addressing</h2> 68 * 69 * Various functions in cvmx-nand use addresses to index into NAND flash. All 70 * functions us a uniform address translation scheme to map the passed address 71 * into a NAND block, page, and column. In NAND flash a page represents the 72 * basic unit of reads and writes. Each page contains a power of two number of 73 * bytes and some number of extra out of band (OOB) bytes. A fixed number of 74 * pages fit into each NAND block. Here is the mapping of bits in the cvmx-nand 75 * address to the NAND hardware: 76 * <pre> 77 * 63 56 48 40 32 24 16 8 0 78 * +-------+-------+-------+-------+-------+-------+-------+------+ 79 * | 64 bit cvmx-nand nand_address| 80 * +------------------------------------------------+----+--------+ 81 * | block |page| column | 82 * +-------+-------+-------+-------+-------+--------+----+--------+ 83 * 63 56 48 40 32 24 16 8 0 84 * </pre> 85 * Basically the block, page, and column addresses are packet together. Before 86 * being sent out the NAND pins for addressing the column is padded out to an 87 * even number of bytes. This means that column address are 2 bytes, or 2 88 * address cycles, for page sizes between 512 and 65536 bytes. Page sizes 89 * between 128KB and 16MB would use 3 column address cycles. NAND device 90 * normally either have 32 or 64 pages per block, needing either 5 or 6 address 91 * bits respectively. This means you have 10 bits for block address using 4 92 * address cycles, or 18 for 5 address cycles. Using the cvmx-nand addressing 93 * scheme, it is not possible to directly index the OOB data. Instead you can 94 * access it by reading or writing more data than the normal page size would 95 * allow. Logically the OOB data is appended onto the the page data. For 96 * example, this means that a read of 65 bytes from a column address of 0x7ff 97 * would yield byte 2047 of the page and then 64 bytes of OOB data. 98 * 99 * <hr>$Revision: 35726 $<hr> 100 */ 101 102#ifndef __CVMX_NAND_H__ 103#define __CVMX_NAND_H__ 104 105#ifdef __cplusplus 106extern "C" { 107#endif 108 109/* Maxium PAGE + OOB size supported. This is used to size 110** buffers, some that must be statically allocated. */ 111#define CVMX_NAND_MAX_PAGE_AND_OOB_SIZE (4096 + 256) 112 113 114/* Block size for boot ECC */ 115#define CVMX_NAND_BOOT_ECC_BLOCK_SIZE (256) 116/* ECC bytes for each block */ 117#define CVMX_NAND_BOOT_ECC_ECC_SIZE (8) 118 119/** 120 * Flags to be passed to the initialize function 121 */ 122typedef enum 123{ 124 CVMX_NAND_INITIALIZE_FLAGS_16BIT = 1<<0, 125 CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE = 1<<1, 126 CVMX_NAND_INITIALIZE_FLAGS_DEBUG = 1<<15, 127} cvmx_nand_initialize_flags_t; 128 129/** 130 * Return codes from NAND functions 131 */ 132typedef enum 133{ 134 CVMX_NAND_SUCCESS = 0, 135 CVMX_NAND_NO_MEMORY = -1, 136 CVMX_NAND_BUSY = -2, 137 CVMX_NAND_INVALID_PARAM = -3, 138 CVMX_NAND_TIMEOUT = -4, 139 CVMX_NAND_ERROR = -5, 140 CVMX_NAND_NO_DEVICE = -6, 141} cvmx_nand_status_t; 142 143/** 144 * NAND NOP command definition 145 */ 146typedef struct 147{ 148 uint64_t reserved_64_127 : 64; 149 uint64_t reserved_4_63 : 60; 150 uint64_t zero : 4; 151} cvmx_nand_cmd_nop_t; 152 153/** 154 * NAND SET_TM_PAR command definition 155 */ 156typedef struct 157{ 158 uint64_t reserved_64_127 : 64; 159 uint64_t tim_par7 : 8; 160 uint64_t tim_par6 : 8; 161 uint64_t tim_par5 : 8; 162 uint64_t tim_par4 : 8; 163 uint64_t tim_par3 : 8; 164 uint64_t tim_par2 : 8; 165 uint64_t tim_par1 : 8; 166 uint64_t tim_mult : 4; 167 uint64_t one : 4; 168} cvmx_nand_cmd_set_tm_par_t; 169 170/** 171 * NAND WAIT command definition 172 */ 173typedef struct 174{ 175 uint64_t reserved_64_127 : 64; 176 uint64_t reserved_11_63 : 53; 177 uint64_t n : 3; 178 uint64_t reserved_5_7 : 3; 179 uint64_t r_b : 1; 180 uint64_t two : 4; 181} cvmx_nand_cmd_wait_t; 182 183/** 184 * NAND CHIP_EN command definition 185 */ 186typedef struct 187{ 188 uint64_t reserved_64_127 : 64; 189 uint64_t reserved_10_63 : 54; 190 uint64_t width : 2; 191 uint64_t one : 1; 192 uint64_t chip : 3; 193 uint64_t three : 4; 194} cvmx_nand_cmd_chip_en_t; 195 196/** 197 * NAND CHIP_DIS command definition 198 */ 199typedef struct 200{ 201 uint64_t reserved_64_127 : 64; 202 uint64_t reserved_4_63 : 60; 203 uint64_t three : 4; 204} cvmx_nand_cmd_chip_dis_t; 205 206/** 207 * NAND CLE command definition 208 */ 209typedef struct 210{ 211 uint64_t reserved_64_127 : 64; 212 uint64_t reserved_25_63 : 39; 213 uint64_t clen3 : 3; 214 uint64_t clen2 : 3; 215 uint64_t clen1 : 3; 216 uint64_t cmd_data : 8; 217 uint64_t reserved_4_7 : 4; 218 uint64_t four : 4; 219} cvmx_nand_cmd_cle_t; 220 221/** 222 * NAND ALE command definition 223 */ 224typedef struct 225{ 226 uint64_t reserved_96_127 : 32; 227 uint64_t adr_bytes_h : 32; 228 uint64_t adr_bytes_l : 32; 229 uint64_t reserved_28_31 : 4; 230 uint64_t alen4 : 3; 231 uint64_t alen3 : 3; 232 uint64_t alen2 : 3; 233 uint64_t alen1 : 3; 234 uint64_t reserved_12_15 : 4; 235 uint64_t adr_byte_num : 4; 236 uint64_t reserved_4_7 : 4; 237 uint64_t five : 4; 238} cvmx_nand_cmd_ale_t; 239 240/** 241 * NAND WR command definition 242 */ 243typedef struct 244{ 245 uint64_t reserved_64_127 : 64; 246 uint64_t reserved_31_63 : 34; 247 uint64_t wrn2 : 3; 248 uint64_t wrn1 : 3; 249 uint64_t reserved_20_24 : 4; 250 uint64_t data_bytes : 16; 251 uint64_t eight : 4; 252} cvmx_nand_cmd_wr_t; 253 254/** 255 * NAND RD command definition 256 */ 257typedef struct 258{ 259 uint64_t reserved_64_127 : 64; 260 uint64_t reserved_32_63 : 32; 261 uint64_t rdn4 : 3; 262 uint64_t rdn3 : 3; 263 uint64_t rdn2 : 3; 264 uint64_t rdn1 : 3; 265 uint64_t data_bytes : 16; 266 uint64_t nine : 4; 267} cvmx_nand_cmd_rd_t; 268 269/** 270 * NAND RD_EDO command definition 271 */ 272typedef struct 273{ 274 uint64_t reserved_64_127 : 64; 275 uint64_t reserved_32_63 : 32; 276 uint64_t rdn4 : 3; 277 uint64_t rdn3 : 3; 278 uint64_t rdn2 : 3; 279 uint64_t rdn1 : 3; 280 uint64_t data_bytes : 16; 281 uint64_t ten : 4; 282} cvmx_nand_cmd_rd_edo_t; 283 284/** 285 * NAND WAIT_STATUS command definition 286 */ 287typedef struct 288{ 289 uint64_t rdn4 : 3; 290 uint64_t rdn3 : 3; 291 uint64_t rdn2 : 3; 292 uint64_t rdn1 : 3; 293 uint64_t comp_byte : 8; 294 uint64_t and_mask : 8; 295 uint64_t nine : 4; 296 uint64_t reserved_28_95 : 64; 297 uint64_t clen4 : 3; 298 uint64_t clen3 : 3; 299 uint64_t clen2 : 3; 300 uint64_t clen1 : 3; 301 uint64_t data : 8; 302 uint64_t reserved_4_7 : 4; 303 uint64_t eleven : 4; 304} cvmx_nand_cmd_wait_status_t; 305 306/** 307 * NAND WAIT_STATUS_ALE command definition 308 */ 309typedef struct 310{ 311 uint64_t rdn4 : 3; 312 uint64_t rdn3 : 3; 313 uint64_t rdn2 : 3; 314 uint64_t rdn1 : 3; 315 uint64_t comp_byte : 8; 316 uint64_t and_mask : 8; 317 uint64_t nine : 4; 318 uint64_t adr_bytes : 32; 319 uint64_t reserved_60_63 : 4; 320 uint64_t alen4 : 3; 321 uint64_t alen3 : 3; 322 uint64_t alen2 : 3; 323 uint64_t alen1 : 3; 324 uint64_t reserved_44_47 : 4; 325 uint64_t adr_byte_num : 4; 326 uint64_t five : 4; 327 uint64_t reserved_25_31 : 7; 328 uint64_t clen3 : 3; 329 uint64_t clen2 : 3; 330 uint64_t clen1 : 3; 331 uint64_t data : 8; 332 uint64_t reserved_4_7 : 4; 333 uint64_t eleven : 4; 334} cvmx_nand_cmd_wait_status_ale_t; 335 336/** 337 * NAND BUS_ACQ command definition 338 */ 339typedef struct 340{ 341 uint64_t reserved_64_127 : 64; 342 uint64_t reserved_8_63 : 56; 343 uint64_t one : 4; 344 uint64_t fifteen : 4; 345} cvmx_nand_cmd_bus_acq_t; 346 347/** 348 * NAND BUS_REL command definition 349 */ 350typedef struct 351{ 352 uint64_t reserved_64_127 : 64; 353 uint64_t reserved_8_63 : 56; 354 uint64_t zero : 4; 355 uint64_t fifteen : 4; 356} cvmx_nand_cmd_bus_rel_t; 357 358/** 359 * NAND command union of all possible commands 360 */ 361typedef union 362{ 363 uint64_t u64[2]; 364 cvmx_nand_cmd_nop_t nop; 365 cvmx_nand_cmd_set_tm_par_t set_tm_par; 366 cvmx_nand_cmd_wait_t wait; 367 cvmx_nand_cmd_chip_en_t chip_en; 368 cvmx_nand_cmd_chip_dis_t chip_dis; 369 cvmx_nand_cmd_cle_t cle; 370 cvmx_nand_cmd_ale_t ale; 371 cvmx_nand_cmd_rd_t rd; 372 cvmx_nand_cmd_rd_edo_t rd_edo; 373 cvmx_nand_cmd_wr_t wr; 374 cvmx_nand_cmd_wait_status_t wait_status; 375 cvmx_nand_cmd_wait_status_ale_t wait_status_ale; 376 cvmx_nand_cmd_bus_acq_t bus_acq; 377 cvmx_nand_cmd_bus_rel_t bus_rel; 378 struct 379 { 380 uint64_t reserved_64_127: 64; 381 uint64_t reserved_4_63 : 60; 382 uint64_t op_code : 4; 383 } s; 384} cvmx_nand_cmd_t; 385 386 387typedef struct __attribute__ ((packed)) 388{ 389 char onfi[4]; /**< Bytes 0-3: The ASCII characters 'O', 'N', 'F', 'I' */ 390 uint16_t revision_number; /**< Bytes 4-5: ONFI revision number 391 - 2-15 Reserved (0) 392 - 1 1 = supports ONFI version 1.0 393 - 0 Reserved (0) */ 394 uint16_t features; /**< Bytes 6-7: Features supported 395 - 5-15 Reserved (0) 396 - 4 1 = supports odd to even page Copyback 397 - 3 1 = supports interleaved operations 398 - 2 1 = supports non-sequential page programming 399 - 1 1 = supports multiple LUN operations 400 - 0 1 = supports 16-bit data bus width */ 401 uint16_t optional_commands; /**< Bytes 8-9: Optional commands supported 402 - 6-15 Reserved (0) 403 - 5 1 = supports Read Unique ID 404 - 4 1 = supports Copyback 405 - 3 1 = supports Read Status Enhanced 406 - 2 1 = supports Get Features and Set Features 407 - 1 1 = supports Read Cache commands 408 - 0 1 = supports Page Cache Program command */ 409 uint8_t reserved_10_31[22]; /**< Bytes 10-31: Reserved */ 410 411 char manufacturer[12]; /**< Bytes 32-43: Device manufacturer (12 ASCII characters) */ 412 char model[20]; /**< Bytes 40-63: Device model (20 ASCII characters) */ 413 uint8_t jedec_id; /**< Byte 64: JEDEC manufacturer ID */ 414 uint16_t date_code; /**< Byte 65-66: Date code */ 415 uint8_t reserved_67_79[13]; /**< Bytes 67-79: Reserved */ 416 417 uint32_t page_data_bytes; /**< Bytes 80-83: Number of data bytes per page */ 418 uint16_t page_spare_bytes; /**< Bytes 84-85: Number of spare bytes per page */ 419 uint32_t partial_page_data_bytes; /**< Bytes 86-89: Number of data bytes per partial page */ 420 uint16_t partial_page_spare_bytes; /**< Bytes 90-91: Number of spare bytes per partial page */ 421 uint32_t pages_per_block; /**< Bytes 92-95: Number of pages per block */ 422 uint32_t blocks_per_lun; /**< Bytes 96-99: Number of blocks per logical unit (LUN) */ 423 uint8_t number_lun; /**< Byte 100: Number of logical units (LUNs) */ 424 uint8_t address_cycles; /**< Byte 101: Number of address cycles 425 - 4-7 Column address cycles 426 - 0-3 Row address cycles */ 427 uint8_t bits_per_cell; /**< Byte 102: Number of bits per cell */ 428 uint16_t bad_block_per_lun; /**< Bytes 103-104: Bad blocks maximum per LUN */ 429 uint16_t block_endurance; /**< Bytes 105-106: Block endurance */ 430 uint8_t good_blocks; /**< Byte 107: Guaranteed valid blocks at beginning of target */ 431 uint16_t good_block_endurance; /**< Bytes 108-109: Block endurance for guaranteed valid blocks */ 432 uint8_t programs_per_page; /**< Byte 110: Number of programs per page */ 433 uint8_t partial_program_attrib; /**< Byte 111: Partial programming attributes 434 - 5-7 Reserved 435 - 4 1 = partial page layout is partial page data followed by partial page spare 436 - 1-3 Reserved 437 - 0 1 = partial page programming has constraints */ 438 uint8_t bits_ecc; /**< Byte 112: Number of bits ECC correctability */ 439 uint8_t interleaved_address_bits; /**< Byte 113: Number of interleaved address bits 440 - 4-7 Reserved (0) 441 - 0-3 Number of interleaved address bits */ 442 uint8_t interleaved_attrib; /**< Byte 114: Interleaved operation attributes 443 - 4-7 Reserved (0) 444 - 3 Address restrictions for program cache 445 - 2 1 = program cache supported 446 - 1 1 = no block address restrictions 447 - 0 Overlapped / concurrent interleaving support */ 448 uint8_t reserved_115_127[13]; /**< Bytes 115-127: Reserved (0) */ 449 450 uint8_t pin_capacitance; /**< Byte 128: I/O pin capacitance */ 451 uint16_t timing_mode; /**< Byte 129-130: Timing mode support 452 - 6-15 Reserved (0) 453 - 5 1 = supports timing mode 5 454 - 4 1 = supports timing mode 4 455 - 3 1 = supports timing mode 3 456 - 2 1 = supports timing mode 2 457 - 1 1 = supports timing mode 1 458 - 0 1 = supports timing mode 0, shall be 1 */ 459 uint16_t cache_timing_mode; /**< Byte 131-132: Program cache timing mode support 460 - 6-15 Reserved (0) 461 - 5 1 = supports timing mode 5 462 - 4 1 = supports timing mode 4 463 - 3 1 = supports timing mode 3 464 - 2 1 = supports timing mode 2 465 - 1 1 = supports timing mode 1 466 - 0 1 = supports timing mode 0 */ 467 uint16_t t_prog; /**< Byte 133-134: Maximum page program time (us) */ 468 uint16_t t_bers; /**< Byte 135-136: Maximum block erase time (us) */ 469 uint16_t t_r; /**< Byte 137-148: Maximum page read time (us) */ 470 uint16_t t_ccs; /**< Byte 139-140: Minimum change column setup time (ns) */ 471 uint8_t reserved_141_163[23]; /**< Byte 141-163: Reserved (0) */ 472 473 uint16_t vendor_revision; /**< Byte 164-165: Vendor specific Revision number */ 474 uint8_t vendor_specific[88]; /**< Byte 166-253: Vendor specific */ 475 uint16_t crc; /**< Byte 254-255: Integrity CRC */ 476} cvmx_nand_onfi_param_page_t; 477 478 479/** 480 * Called to initialize the NAND controller for use. Note that 481 * you must be running out of L2 or memory and not NAND before 482 * calling this function. 483 * When probing for NAND chips, this function attempts to autoconfigure based on the NAND parts detected. 484 * It currently supports autodetection for ONFI parts (with valid parameter pages), and some Samsung NAND 485 * parts (decoding ID bits.) If autoconfiguration fails, the defaults set with __set_chip_defaults() 486 * prior to calling cvmx_nand_initialize() are used. 487 * If defaults are set and the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is provided, the defaults are used 488 * for all chips in the active_chips mask. 489 * 490 * @param flags Optional initialization flags 491 * If the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is passed, chips are not probed, 492 * and the default parameters (if set with cvmx_nand_set_defaults) are used for all chips 493 * in the active_chips mask. 494 * @param active_chips 495 * Each bit in this parameter represents a chip select that might 496 * contain NAND flash. Any chip select present in this bitmask may 497 * be connected to NAND. It is normally safe to pass 0xff here and 498 * let the API probe all 8 chip selects. 499 * 500 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 501 */ 502extern cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int active_chips); 503 504 505 506/** 507 * This function may be called before cvmx_nand_initialize to set default values that will be used 508 * for NAND chips that do not identify themselves in a way that allows autoconfiguration. (ONFI chip with 509 * missing parameter page, for example.) 510 * The parameters set by this function will be used by _all_ non-autoconfigured NAND chips. 511 * 512 * 513 * NOTE: This function signature is _NOT_ stable, and will change in the future as required to support 514 * various NAND chips. 515 * 516 * @param page_size page size in bytes 517 * @param oob_size Out of band size in bytes (per page) 518 * @param pages_per_block 519 * number of pages per block 520 * @param blocks Total number of blocks in device 521 * @param onfi_timing_mode 522 * ONFI timing mode 523 * 524 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 525 */ 526extern cvmx_nand_status_t cvmx_nand_set_defaults(int page_size, int oob_size, int pages_per_block, int blocks, int onfi_timing_mode); 527 528 529/** 530 * Call to shutdown the NAND controller after all transactions 531 * are done. In most setups this will never be called. 532 * 533 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 534 */ 535extern cvmx_nand_status_t cvmx_nand_shutdown(void); 536 537 538/** 539 * Returns a bitmask representing the chip selects that are 540 * connected to NAND chips. This can be called after the 541 * initialize to determine the actual number of NAND chips 542 * found. Each bit in the response coresponds to a chip select. 543 * 544 * @return Zero if no NAND chips were found. Otherwise a bit is set for 545 * each chip select (1<<chip). 546 */ 547extern int cvmx_nand_get_active_chips(void); 548 549 550/** 551 * Override the timing parameters for a NAND chip 552 * 553 * @param chip Chip select to override 554 * @param tim_mult 555 * @param tim_par 556 * @param clen 557 * @param alen 558 * @param rdn 559 * @param wrn 560 * 561 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 562 */ 563extern cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[7], int clen[4], int alen[4], int rdn[4], int wrn[2]); 564 565 566/** 567 * Submit a command to the NAND command queue. Generally this 568 * will not be used directly. Instead most programs will use the other 569 * higher level NAND functions. 570 * 571 * @param cmd Command to submit 572 * 573 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 574 */ 575extern cvmx_nand_status_t cvmx_nand_submit(cvmx_nand_cmd_t cmd); 576 577/** 578 * Read a page from NAND. If the buffer has room, the out of band 579 * data will be included. 580 * 581 * @param chip Chip select for NAND flash 582 * @param nand_address 583 * Location in NAND to read. See description in file comment 584 * @param buffer_address 585 * Physical address to store the result at 586 * @param buffer_length 587 * Number of bytes to read 588 * 589 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure 590 */ 591extern int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length); 592 593/** 594 * Write a page to NAND. The buffer must contain the entire page 595 * including the out of band data. 596 * 597 * @param chip Chip select for NAND flash 598 * @param nand_address 599 * Location in NAND to write. See description in file comment 600 * @param buffer_address 601 * Physical address to read the data from 602 * 603 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 604 */ 605extern cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address); 606 607/** 608 * Erase a NAND block. A single block contains multiple pages. 609 * 610 * @param chip Chip select for NAND flash 611 * @param nand_address 612 * Location in NAND to erase. See description in file comment 613 * 614 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 615 */ 616extern cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address); 617 618/** 619 * Read the NAND ID information 620 * 621 * @param chip Chip select for NAND flash 622 * @param nand_address 623 * NAND address to read ID from. Usually this is either 0x0 or 0x20. 624 * @param buffer_address 625 * Physical address to store data in 626 * @param buffer_length 627 * Length of the buffer. Usually this is 4 bytes 628 * 629 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure 630 */ 631extern int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length); 632 633/** 634 * Read the NAND parameter page 635 * 636 * @param chip Chip select for NAND flash 637 * @param buffer_address 638 * Physical address to store data in 639 * @param buffer_length 640 * Length of the buffer. Usually this is 4 bytes 641 * 642 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure 643 */ 644extern int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length); 645 646/** 647 * Get the status of the NAND flash 648 * 649 * @param chip Chip select for NAND flash 650 * 651 * @return NAND status or a negative cvmx_nand_status_t error code on failure 652 */ 653extern int cvmx_nand_get_status(int chip); 654 655/** 656 * Get the page size, excluding out of band data. This function 657 * will return zero for chip selects not connected to NAND. 658 * 659 * @param chip Chip select for NAND flash 660 * 661 * @return Page size in bytes or a negative cvmx_nand_status_t error code on failure 662 */ 663extern int cvmx_nand_get_page_size(int chip); 664 665/** 666 * Get the OOB size. 667 * 668 * @param chip Chip select for NAND flash 669 * 670 * @return OOB in bytes or a negative cvmx_nand_status_t error code on failure 671 */ 672extern int cvmx_nand_get_oob_size(int chip); 673 674/** 675 * Get the number of pages per NAND block 676 * 677 * @param chip Chip select for NAND flash 678 * 679 * @return Numboer of pages in each block or a negative cvmx_nand_status_t error code on failure 680 */ 681extern int cvmx_nand_get_pages_per_block(int chip); 682 683/** 684 * Get the number of blocks in the NAND flash 685 * 686 * @param chip Chip select for NAND flash 687 * 688 * @return Number of blocks or a negative cvmx_nand_status_t error code on failure 689 */ 690extern int cvmx_nand_get_blocks(int chip); 691 692/** 693 * Reset the NAND flash 694 * 695 * @param chip Chip select for NAND flash 696 * 697 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 698 */ 699extern cvmx_nand_status_t cvmx_nand_reset(int chip); 700 701/** 702 * This function computes the Octeon specific ECC data used by the NAND boot 703 * feature. 704 * 705 * @param block pointer to 256 bytes of data 706 * @param eccp pointer to where 8 bytes of ECC data will be stored 707 */ 708extern void cvmx_nand_compute_boot_ecc(unsigned char *block, unsigned char *eccp); 709 710 711extern int cvmx_nand_correct_boot_ecc(uint8_t *block); 712#ifdef __cplusplus 713} 714#endif 715 716#endif /* __CVMX_NAND_H__ */ 717