1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-l2d-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon l2d. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_L2D_DEFS_H__ 53232812Sjmallett#define __CVMX_L2D_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_L2D_BST0_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 60215976Sjmallett cvmx_warn("CVMX_L2D_BST0 not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000780ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_L2D_BST1_FUNC(void) 69215976Sjmallett{ 70215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 71215976Sjmallett cvmx_warn("CVMX_L2D_BST1 not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000788ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_L2D_BST2_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 82215976Sjmallett cvmx_warn("CVMX_L2D_BST2 not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000790ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_L2D_BST3_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 93215976Sjmallett cvmx_warn("CVMX_L2D_BST3 not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000798ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_L2D_ERR_FUNC(void) 102215976Sjmallett{ 103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 104215976Sjmallett cvmx_warn("CVMX_L2D_ERR not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000010ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_L2D_FADR_FUNC(void) 113215976Sjmallett{ 114215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 115215976Sjmallett cvmx_warn("CVMX_L2D_FADR not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000018ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_L2D_FSYN0_FUNC(void) 124215976Sjmallett{ 125215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 126215976Sjmallett cvmx_warn("CVMX_L2D_FSYN0 not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000020ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_L2D_FSYN1_FUNC(void) 135215976Sjmallett{ 136215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 137215976Sjmallett cvmx_warn("CVMX_L2D_FSYN1 not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000028ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallett#define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC() 145215976Sjmallettstatic inline uint64_t CVMX_L2D_FUS0_FUNC(void) 146215976Sjmallett{ 147215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 148215976Sjmallett cvmx_warn("CVMX_L2D_FUS0 not supported on this chip\n"); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007A0ull); 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull)) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallett#define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC() 156215976Sjmallettstatic inline uint64_t CVMX_L2D_FUS1_FUNC(void) 157215976Sjmallett{ 158215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 159215976Sjmallett cvmx_warn("CVMX_L2D_FUS1 not supported on this chip\n"); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007A8ull); 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull)) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallett#define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC() 167215976Sjmallettstatic inline uint64_t CVMX_L2D_FUS2_FUNC(void) 168215976Sjmallett{ 169215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 170215976Sjmallett cvmx_warn("CVMX_L2D_FUS2 not supported on this chip\n"); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007B0ull); 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull)) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallett#define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC() 178215976Sjmallettstatic inline uint64_t CVMX_L2D_FUS3_FUNC(void) 179215976Sjmallett{ 180215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 181215976Sjmallett cvmx_warn("CVMX_L2D_FUS3 not supported on this chip\n"); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007B8ull); 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) 186215976Sjmallett#endif 187215976Sjmallett 188215976Sjmallett/** 189215976Sjmallett * cvmx_l2d_bst0 190215976Sjmallett * 191215976Sjmallett * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register 192215976Sjmallett * 193215976Sjmallett */ 194232812Sjmallettunion cvmx_l2d_bst0 { 195215976Sjmallett uint64_t u64; 196232812Sjmallett struct cvmx_l2d_bst0_s { 197232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 198215976Sjmallett uint64_t reserved_35_63 : 29; 199215976Sjmallett uint64_t ftl : 1; /**< L2C Data Store Fatal Defect(across all QUADs) 200215976Sjmallett 2 or more columns were detected bad across all 201215976Sjmallett QUADs[0-3]. Please refer to individual quad failures 202215976Sjmallett for bad column = 0x7e to determine which QUAD was in 203215976Sjmallett error. */ 204215976Sjmallett uint64_t q0stat : 34; /**< Bist Results for QUAD0 205215976Sjmallett Failure \#1 Status 206215976Sjmallett [16:14] bad bank 207215976Sjmallett [13:7] bad high column 208215976Sjmallett [6:0] bad low column 209215976Sjmallett Failure \#2 Status 210215976Sjmallett [33:31] bad bank 211215976Sjmallett [30:24] bad high column 212215976Sjmallett [23:17] bad low column 213215976Sjmallett NOTES: For bad high/low column reporting: 214215976Sjmallett 0x7f: No failure 215215976Sjmallett 0x7e: Fatal Defect: 2 or more bad columns 216215976Sjmallett 0-0x45: Bad column 217215976Sjmallett NOTE: If there are less than 2 failures then the 218215976Sjmallett bad bank will be 0x7. */ 219215976Sjmallett#else 220215976Sjmallett uint64_t q0stat : 34; 221215976Sjmallett uint64_t ftl : 1; 222215976Sjmallett uint64_t reserved_35_63 : 29; 223215976Sjmallett#endif 224215976Sjmallett } s; 225215976Sjmallett struct cvmx_l2d_bst0_s cn30xx; 226215976Sjmallett struct cvmx_l2d_bst0_s cn31xx; 227215976Sjmallett struct cvmx_l2d_bst0_s cn38xx; 228215976Sjmallett struct cvmx_l2d_bst0_s cn38xxp2; 229215976Sjmallett struct cvmx_l2d_bst0_s cn50xx; 230215976Sjmallett struct cvmx_l2d_bst0_s cn52xx; 231215976Sjmallett struct cvmx_l2d_bst0_s cn52xxp1; 232215976Sjmallett struct cvmx_l2d_bst0_s cn56xx; 233215976Sjmallett struct cvmx_l2d_bst0_s cn56xxp1; 234215976Sjmallett struct cvmx_l2d_bst0_s cn58xx; 235215976Sjmallett struct cvmx_l2d_bst0_s cn58xxp1; 236215976Sjmallett}; 237215976Sjmalletttypedef union cvmx_l2d_bst0 cvmx_l2d_bst0_t; 238215976Sjmallett 239215976Sjmallett/** 240215976Sjmallett * cvmx_l2d_bst1 241215976Sjmallett * 242215976Sjmallett * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register 243215976Sjmallett * 244215976Sjmallett */ 245232812Sjmallettunion cvmx_l2d_bst1 { 246215976Sjmallett uint64_t u64; 247232812Sjmallett struct cvmx_l2d_bst1_s { 248232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 249215976Sjmallett uint64_t reserved_34_63 : 30; 250215976Sjmallett uint64_t q1stat : 34; /**< Bist Results for QUAD1 251215976Sjmallett Failure \#1 Status 252215976Sjmallett [16:14] bad bank 253215976Sjmallett [13:7] bad high column 254215976Sjmallett [6:0] bad low column 255215976Sjmallett Failure \#2 Status 256215976Sjmallett [33:31] bad bank 257215976Sjmallett [30:24] bad high column 258215976Sjmallett [23:17] bad low column 259215976Sjmallett NOTES: For bad high/low column reporting: 260215976Sjmallett 0x7f: No failure 261215976Sjmallett 0x7e: Fatal Defect: 2 or more bad columns 262215976Sjmallett 0-0x45: Bad column 263215976Sjmallett NOTE: If there are less than 2 failures then the 264215976Sjmallett bad bank will be 0x7. */ 265215976Sjmallett#else 266215976Sjmallett uint64_t q1stat : 34; 267215976Sjmallett uint64_t reserved_34_63 : 30; 268215976Sjmallett#endif 269215976Sjmallett } s; 270215976Sjmallett struct cvmx_l2d_bst1_s cn30xx; 271215976Sjmallett struct cvmx_l2d_bst1_s cn31xx; 272215976Sjmallett struct cvmx_l2d_bst1_s cn38xx; 273215976Sjmallett struct cvmx_l2d_bst1_s cn38xxp2; 274215976Sjmallett struct cvmx_l2d_bst1_s cn50xx; 275215976Sjmallett struct cvmx_l2d_bst1_s cn52xx; 276215976Sjmallett struct cvmx_l2d_bst1_s cn52xxp1; 277215976Sjmallett struct cvmx_l2d_bst1_s cn56xx; 278215976Sjmallett struct cvmx_l2d_bst1_s cn56xxp1; 279215976Sjmallett struct cvmx_l2d_bst1_s cn58xx; 280215976Sjmallett struct cvmx_l2d_bst1_s cn58xxp1; 281215976Sjmallett}; 282215976Sjmalletttypedef union cvmx_l2d_bst1 cvmx_l2d_bst1_t; 283215976Sjmallett 284215976Sjmallett/** 285215976Sjmallett * cvmx_l2d_bst2 286215976Sjmallett * 287215976Sjmallett * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register 288215976Sjmallett * 289215976Sjmallett */ 290232812Sjmallettunion cvmx_l2d_bst2 { 291215976Sjmallett uint64_t u64; 292232812Sjmallett struct cvmx_l2d_bst2_s { 293232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 294215976Sjmallett uint64_t reserved_34_63 : 30; 295215976Sjmallett uint64_t q2stat : 34; /**< Bist Results for QUAD2 296215976Sjmallett Failure \#1 Status 297215976Sjmallett [16:14] bad bank 298215976Sjmallett [13:7] bad high column 299215976Sjmallett [6:0] bad low column 300215976Sjmallett Failure \#2 Status 301215976Sjmallett [33:31] bad bank 302215976Sjmallett [30:24] bad high column 303215976Sjmallett [23:17] bad low column 304215976Sjmallett NOTES: For bad high/low column reporting: 305215976Sjmallett 0x7f: No failure 306215976Sjmallett 0x7e: Fatal Defect: 2 or more bad columns 307215976Sjmallett 0-0x45: Bad column 308215976Sjmallett NOTE: If there are less than 2 failures then the 309215976Sjmallett bad bank will be 0x7. */ 310215976Sjmallett#else 311215976Sjmallett uint64_t q2stat : 34; 312215976Sjmallett uint64_t reserved_34_63 : 30; 313215976Sjmallett#endif 314215976Sjmallett } s; 315215976Sjmallett struct cvmx_l2d_bst2_s cn30xx; 316215976Sjmallett struct cvmx_l2d_bst2_s cn31xx; 317215976Sjmallett struct cvmx_l2d_bst2_s cn38xx; 318215976Sjmallett struct cvmx_l2d_bst2_s cn38xxp2; 319215976Sjmallett struct cvmx_l2d_bst2_s cn50xx; 320215976Sjmallett struct cvmx_l2d_bst2_s cn52xx; 321215976Sjmallett struct cvmx_l2d_bst2_s cn52xxp1; 322215976Sjmallett struct cvmx_l2d_bst2_s cn56xx; 323215976Sjmallett struct cvmx_l2d_bst2_s cn56xxp1; 324215976Sjmallett struct cvmx_l2d_bst2_s cn58xx; 325215976Sjmallett struct cvmx_l2d_bst2_s cn58xxp1; 326215976Sjmallett}; 327215976Sjmalletttypedef union cvmx_l2d_bst2 cvmx_l2d_bst2_t; 328215976Sjmallett 329215976Sjmallett/** 330215976Sjmallett * cvmx_l2d_bst3 331215976Sjmallett * 332215976Sjmallett * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register 333215976Sjmallett * 334215976Sjmallett */ 335232812Sjmallettunion cvmx_l2d_bst3 { 336215976Sjmallett uint64_t u64; 337232812Sjmallett struct cvmx_l2d_bst3_s { 338232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 339215976Sjmallett uint64_t reserved_34_63 : 30; 340215976Sjmallett uint64_t q3stat : 34; /**< Bist Results for QUAD3 341215976Sjmallett Failure \#1 Status 342215976Sjmallett [16:14] bad bank 343215976Sjmallett [13:7] bad high column 344215976Sjmallett [6:0] bad low column 345215976Sjmallett Failure \#2 Status 346215976Sjmallett [33:31] bad bank 347215976Sjmallett [30:24] bad high column 348215976Sjmallett [23:17] bad low column 349215976Sjmallett NOTES: For bad high/low column reporting: 350215976Sjmallett 0x7f: No failure 351215976Sjmallett 0x7e: Fatal Defect: 2 or more bad columns 352215976Sjmallett 0-0x45: Bad column 353215976Sjmallett NOTE: If there are less than 2 failures then the 354215976Sjmallett bad bank will be 0x7. */ 355215976Sjmallett#else 356215976Sjmallett uint64_t q3stat : 34; 357215976Sjmallett uint64_t reserved_34_63 : 30; 358215976Sjmallett#endif 359215976Sjmallett } s; 360215976Sjmallett struct cvmx_l2d_bst3_s cn30xx; 361215976Sjmallett struct cvmx_l2d_bst3_s cn31xx; 362215976Sjmallett struct cvmx_l2d_bst3_s cn38xx; 363215976Sjmallett struct cvmx_l2d_bst3_s cn38xxp2; 364215976Sjmallett struct cvmx_l2d_bst3_s cn50xx; 365215976Sjmallett struct cvmx_l2d_bst3_s cn52xx; 366215976Sjmallett struct cvmx_l2d_bst3_s cn52xxp1; 367215976Sjmallett struct cvmx_l2d_bst3_s cn56xx; 368215976Sjmallett struct cvmx_l2d_bst3_s cn56xxp1; 369215976Sjmallett struct cvmx_l2d_bst3_s cn58xx; 370215976Sjmallett struct cvmx_l2d_bst3_s cn58xxp1; 371215976Sjmallett}; 372215976Sjmalletttypedef union cvmx_l2d_bst3 cvmx_l2d_bst3_t; 373215976Sjmallett 374215976Sjmallett/** 375215976Sjmallett * cvmx_l2d_err 376215976Sjmallett * 377215976Sjmallett * L2D_ERR = L2 Data Errors 378215976Sjmallett * 379215976Sjmallett * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable 380215976Sjmallett */ 381232812Sjmallettunion cvmx_l2d_err { 382215976Sjmallett uint64_t u64; 383232812Sjmallett struct cvmx_l2d_err_s { 384232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 385215976Sjmallett uint64_t reserved_6_63 : 58; 386215976Sjmallett uint64_t bmhclsel : 1; /**< L2 Bit Map Half CacheLine ECC Selector 387215976Sjmallett 388215976Sjmallett When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects 389215976Sjmallett which half cacheline to conditionally latch into 390215976Sjmallett the L2D_FSYN0/L2D_FSYN1 registers when an LDD command 391215976Sjmallett is detected from the diagnostic PP (see L2C_DBG[PPNUM]). 392215976Sjmallett - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to 393215976Sjmallett be conditionally latched into the L2D_FSYN0/1 CSRs. 394215976Sjmallett - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to 395215976Sjmallett be conditionally latched into 396215976Sjmallett the L2D_FSYN0/1 CSRs. */ 397215976Sjmallett uint64_t ded_err : 1; /**< L2D Double Error detected (DED) */ 398215976Sjmallett uint64_t sec_err : 1; /**< L2D Single Error corrected (SEC) */ 399215976Sjmallett uint64_t ded_intena : 1; /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit 400215976Sjmallett When set, allows interrupts to be reported on double bit 401215976Sjmallett (uncorrectable) errors from the L2 Data Arrays. */ 402215976Sjmallett uint64_t sec_intena : 1; /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit 403215976Sjmallett When set, allows interrupts to be reported on single bit 404215976Sjmallett (correctable) errors from the L2 Data Arrays. */ 405215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Data ECC Enable 406215976Sjmallett When set, enables 10-bit SEC/DED codeword for 128bit L2 407215976Sjmallett Data Arrays. */ 408215976Sjmallett#else 409215976Sjmallett uint64_t ecc_ena : 1; 410215976Sjmallett uint64_t sec_intena : 1; 411215976Sjmallett uint64_t ded_intena : 1; 412215976Sjmallett uint64_t sec_err : 1; 413215976Sjmallett uint64_t ded_err : 1; 414215976Sjmallett uint64_t bmhclsel : 1; 415215976Sjmallett uint64_t reserved_6_63 : 58; 416215976Sjmallett#endif 417215976Sjmallett } s; 418215976Sjmallett struct cvmx_l2d_err_s cn30xx; 419215976Sjmallett struct cvmx_l2d_err_s cn31xx; 420215976Sjmallett struct cvmx_l2d_err_s cn38xx; 421215976Sjmallett struct cvmx_l2d_err_s cn38xxp2; 422215976Sjmallett struct cvmx_l2d_err_s cn50xx; 423215976Sjmallett struct cvmx_l2d_err_s cn52xx; 424215976Sjmallett struct cvmx_l2d_err_s cn52xxp1; 425215976Sjmallett struct cvmx_l2d_err_s cn56xx; 426215976Sjmallett struct cvmx_l2d_err_s cn56xxp1; 427215976Sjmallett struct cvmx_l2d_err_s cn58xx; 428215976Sjmallett struct cvmx_l2d_err_s cn58xxp1; 429215976Sjmallett}; 430215976Sjmalletttypedef union cvmx_l2d_err cvmx_l2d_err_t; 431215976Sjmallett 432215976Sjmallett/** 433215976Sjmallett * cvmx_l2d_fadr 434215976Sjmallett * 435215976Sjmallett * L2D_FADR = L2 Failing Address 436215976Sjmallett * 437215976Sjmallett * Description: L2 Data ECC SEC/DED Failing Address 438215976Sjmallett * 439215976Sjmallett * Notes: 440215976Sjmallett * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index. 441215976Sjmallett * (A DED Error will always overwrite a SEC Error SYNDROME and FADR). 442215976Sjmallett */ 443232812Sjmallettunion cvmx_l2d_fadr { 444215976Sjmallett uint64_t u64; 445232812Sjmallett struct cvmx_l2d_fadr_s { 446232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 447215976Sjmallett uint64_t reserved_19_63 : 45; 448215976Sjmallett uint64_t fadru : 1; /**< Failing L2 Data Store Upper Index bit(MSB) */ 449215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 450215976Sjmallett error) */ 451215976Sjmallett uint64_t fset : 3; /**< Failing SET# */ 452215976Sjmallett uint64_t fadr : 11; /**< Failing L2 Data Store Lower Index bits 453215976Sjmallett (NOTE: L2 Data Store Index is for each 1/2 cacheline) 454215976Sjmallett [FADRU, FADR[10:1]]: cacheline index[17:7] 455215976Sjmallett FADR[0]: 1/2 cacheline index 456215976Sjmallett NOTE: FADR[1] is used to select between upper/lower 1MB 457215976Sjmallett physical L2 Data Store banks. */ 458215976Sjmallett#else 459215976Sjmallett uint64_t fadr : 11; 460215976Sjmallett uint64_t fset : 3; 461215976Sjmallett uint64_t fowmsk : 4; 462215976Sjmallett uint64_t fadru : 1; 463215976Sjmallett uint64_t reserved_19_63 : 45; 464215976Sjmallett#endif 465215976Sjmallett } s; 466232812Sjmallett struct cvmx_l2d_fadr_cn30xx { 467232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 468215976Sjmallett uint64_t reserved_18_63 : 46; 469215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 470215976Sjmallett error) */ 471215976Sjmallett uint64_t reserved_13_13 : 1; 472215976Sjmallett uint64_t fset : 2; /**< Failing SET# */ 473215976Sjmallett uint64_t reserved_9_10 : 2; 474215976Sjmallett uint64_t fadr : 9; /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */ 475215976Sjmallett#else 476215976Sjmallett uint64_t fadr : 9; 477215976Sjmallett uint64_t reserved_9_10 : 2; 478215976Sjmallett uint64_t fset : 2; 479215976Sjmallett uint64_t reserved_13_13 : 1; 480215976Sjmallett uint64_t fowmsk : 4; 481215976Sjmallett uint64_t reserved_18_63 : 46; 482215976Sjmallett#endif 483215976Sjmallett } cn30xx; 484232812Sjmallett struct cvmx_l2d_fadr_cn31xx { 485232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 486215976Sjmallett uint64_t reserved_18_63 : 46; 487215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 488215976Sjmallett error) */ 489215976Sjmallett uint64_t reserved_13_13 : 1; 490215976Sjmallett uint64_t fset : 2; /**< Failing SET# */ 491215976Sjmallett uint64_t reserved_10_10 : 1; 492215976Sjmallett uint64_t fadr : 10; /**< Failing L2 Data Store Index 493215976Sjmallett (1 of 1024 = half cacheline indices) */ 494215976Sjmallett#else 495215976Sjmallett uint64_t fadr : 10; 496215976Sjmallett uint64_t reserved_10_10 : 1; 497215976Sjmallett uint64_t fset : 2; 498215976Sjmallett uint64_t reserved_13_13 : 1; 499215976Sjmallett uint64_t fowmsk : 4; 500215976Sjmallett uint64_t reserved_18_63 : 46; 501215976Sjmallett#endif 502215976Sjmallett } cn31xx; 503232812Sjmallett struct cvmx_l2d_fadr_cn38xx { 504232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 505215976Sjmallett uint64_t reserved_18_63 : 46; 506215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 507215976Sjmallett error) */ 508215976Sjmallett uint64_t fset : 3; /**< Failing SET# */ 509215976Sjmallett uint64_t fadr : 11; /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */ 510215976Sjmallett#else 511215976Sjmallett uint64_t fadr : 11; 512215976Sjmallett uint64_t fset : 3; 513215976Sjmallett uint64_t fowmsk : 4; 514215976Sjmallett uint64_t reserved_18_63 : 46; 515215976Sjmallett#endif 516215976Sjmallett } cn38xx; 517215976Sjmallett struct cvmx_l2d_fadr_cn38xx cn38xxp2; 518232812Sjmallett struct cvmx_l2d_fadr_cn50xx { 519232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 520215976Sjmallett uint64_t reserved_18_63 : 46; 521215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 522215976Sjmallett error) */ 523215976Sjmallett uint64_t fset : 3; /**< Failing SET# */ 524215976Sjmallett uint64_t reserved_8_10 : 3; 525215976Sjmallett uint64_t fadr : 8; /**< Failing L2 Data Store Lower Index bits 526215976Sjmallett (NOTE: L2 Data Store Index is for each 1/2 cacheline) 527215976Sjmallett FADR[7:1]: cacheline index[13:7] 528215976Sjmallett FADR[0]: 1/2 cacheline index */ 529215976Sjmallett#else 530215976Sjmallett uint64_t fadr : 8; 531215976Sjmallett uint64_t reserved_8_10 : 3; 532215976Sjmallett uint64_t fset : 3; 533215976Sjmallett uint64_t fowmsk : 4; 534215976Sjmallett uint64_t reserved_18_63 : 46; 535215976Sjmallett#endif 536215976Sjmallett } cn50xx; 537232812Sjmallett struct cvmx_l2d_fadr_cn52xx { 538232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 539215976Sjmallett uint64_t reserved_18_63 : 46; 540215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 541215976Sjmallett error) */ 542215976Sjmallett uint64_t fset : 3; /**< Failing SET# */ 543215976Sjmallett uint64_t reserved_10_10 : 1; 544215976Sjmallett uint64_t fadr : 10; /**< Failing L2 Data Store Lower Index bits 545215976Sjmallett (NOTE: L2 Data Store Index is for each 1/2 cacheline) 546215976Sjmallett FADR[9:1]: cacheline index[15:7] 547215976Sjmallett FADR[0]: 1/2 cacheline index */ 548215976Sjmallett#else 549215976Sjmallett uint64_t fadr : 10; 550215976Sjmallett uint64_t reserved_10_10 : 1; 551215976Sjmallett uint64_t fset : 3; 552215976Sjmallett uint64_t fowmsk : 4; 553215976Sjmallett uint64_t reserved_18_63 : 46; 554215976Sjmallett#endif 555215976Sjmallett } cn52xx; 556215976Sjmallett struct cvmx_l2d_fadr_cn52xx cn52xxp1; 557215976Sjmallett struct cvmx_l2d_fadr_s cn56xx; 558215976Sjmallett struct cvmx_l2d_fadr_s cn56xxp1; 559215976Sjmallett struct cvmx_l2d_fadr_s cn58xx; 560215976Sjmallett struct cvmx_l2d_fadr_s cn58xxp1; 561215976Sjmallett}; 562215976Sjmalletttypedef union cvmx_l2d_fadr cvmx_l2d_fadr_t; 563215976Sjmallett 564215976Sjmallett/** 565215976Sjmallett * cvmx_l2d_fsyn0 566215976Sjmallett * 567215976Sjmallett * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5] 568215976Sjmallett * 569215976Sjmallett * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line 570215976Sjmallett * 571215976Sjmallett * Notes: 572215976Sjmallett * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome. 573215976Sjmallett * (A DED Error will always overwrite a SEC Error SYNDROME and FADR). 574215976Sjmallett */ 575232812Sjmallettunion cvmx_l2d_fsyn0 { 576215976Sjmallett uint64_t u64; 577232812Sjmallett struct cvmx_l2d_fsyn0_s { 578232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 579215976Sjmallett uint64_t reserved_20_63 : 44; 580215976Sjmallett uint64_t fsyn_ow1 : 10; /**< Failing L2 Data Store SYNDROME OW[1,5] 581215976Sjmallett When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR] 582215976Sjmallett or L2D_ERR[DED_ERR] are set, this field represents 583215976Sjmallett the failing OWECC syndrome for the half cacheline 584215976Sjmallett indexed by L2D_FADR[FADR]. 585215976Sjmallett NOTE: The L2D_FADR[FOWMSK] further qualifies which 586215976Sjmallett OW lane(1of4) detected the error. 587215976Sjmallett When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD 588215976Sjmallett command from the diagnostic PP will conditionally latch 589215976Sjmallett the raw OWECC for the selected half cacheline. 590215976Sjmallett (see: L2D_ERR[BMHCLSEL] */ 591215976Sjmallett uint64_t fsyn_ow0 : 10; /**< Failing L2 Data Store SYNDROME OW[0,4] 592215976Sjmallett When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR] 593215976Sjmallett or L2D_ERR[DED_ERR] are set, this field represents 594215976Sjmallett the failing OWECC syndrome for the half cacheline 595215976Sjmallett indexed by L2D_FADR[FADR]. 596215976Sjmallett NOTE: The L2D_FADR[FOWMSK] further qualifies which 597215976Sjmallett OW lane(1of4) detected the error. 598215976Sjmallett When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD 599215976Sjmallett (L1 load-miss) from the diagnostic PP will conditionally 600215976Sjmallett latch the raw OWECC for the selected half cacheline. 601215976Sjmallett (see: L2D_ERR[BMHCLSEL] */ 602215976Sjmallett#else 603215976Sjmallett uint64_t fsyn_ow0 : 10; 604215976Sjmallett uint64_t fsyn_ow1 : 10; 605215976Sjmallett uint64_t reserved_20_63 : 44; 606215976Sjmallett#endif 607215976Sjmallett } s; 608215976Sjmallett struct cvmx_l2d_fsyn0_s cn30xx; 609215976Sjmallett struct cvmx_l2d_fsyn0_s cn31xx; 610215976Sjmallett struct cvmx_l2d_fsyn0_s cn38xx; 611215976Sjmallett struct cvmx_l2d_fsyn0_s cn38xxp2; 612215976Sjmallett struct cvmx_l2d_fsyn0_s cn50xx; 613215976Sjmallett struct cvmx_l2d_fsyn0_s cn52xx; 614215976Sjmallett struct cvmx_l2d_fsyn0_s cn52xxp1; 615215976Sjmallett struct cvmx_l2d_fsyn0_s cn56xx; 616215976Sjmallett struct cvmx_l2d_fsyn0_s cn56xxp1; 617215976Sjmallett struct cvmx_l2d_fsyn0_s cn58xx; 618215976Sjmallett struct cvmx_l2d_fsyn0_s cn58xxp1; 619215976Sjmallett}; 620215976Sjmalletttypedef union cvmx_l2d_fsyn0 cvmx_l2d_fsyn0_t; 621215976Sjmallett 622215976Sjmallett/** 623215976Sjmallett * cvmx_l2d_fsyn1 624215976Sjmallett * 625215976Sjmallett * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7] 626215976Sjmallett * 627215976Sjmallett * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line 628215976Sjmallett * 629215976Sjmallett * Notes: 630215976Sjmallett * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome. 631215976Sjmallett * (A DED Error will always overwrite a SEC Error SYNDROME and FADR). 632215976Sjmallett */ 633232812Sjmallettunion cvmx_l2d_fsyn1 { 634215976Sjmallett uint64_t u64; 635232812Sjmallett struct cvmx_l2d_fsyn1_s { 636232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 637215976Sjmallett uint64_t reserved_20_63 : 44; 638215976Sjmallett uint64_t fsyn_ow3 : 10; /**< Failing L2 Data Store SYNDROME OW[3,7] */ 639215976Sjmallett uint64_t fsyn_ow2 : 10; /**< Failing L2 Data Store SYNDROME OW[2,5] */ 640215976Sjmallett#else 641215976Sjmallett uint64_t fsyn_ow2 : 10; 642215976Sjmallett uint64_t fsyn_ow3 : 10; 643215976Sjmallett uint64_t reserved_20_63 : 44; 644215976Sjmallett#endif 645215976Sjmallett } s; 646215976Sjmallett struct cvmx_l2d_fsyn1_s cn30xx; 647215976Sjmallett struct cvmx_l2d_fsyn1_s cn31xx; 648215976Sjmallett struct cvmx_l2d_fsyn1_s cn38xx; 649215976Sjmallett struct cvmx_l2d_fsyn1_s cn38xxp2; 650215976Sjmallett struct cvmx_l2d_fsyn1_s cn50xx; 651215976Sjmallett struct cvmx_l2d_fsyn1_s cn52xx; 652215976Sjmallett struct cvmx_l2d_fsyn1_s cn52xxp1; 653215976Sjmallett struct cvmx_l2d_fsyn1_s cn56xx; 654215976Sjmallett struct cvmx_l2d_fsyn1_s cn56xxp1; 655215976Sjmallett struct cvmx_l2d_fsyn1_s cn58xx; 656215976Sjmallett struct cvmx_l2d_fsyn1_s cn58xxp1; 657215976Sjmallett}; 658215976Sjmalletttypedef union cvmx_l2d_fsyn1 cvmx_l2d_fsyn1_t; 659215976Sjmallett 660215976Sjmallett/** 661215976Sjmallett * cvmx_l2d_fus0 662215976Sjmallett * 663215976Sjmallett * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register 664215976Sjmallett * 665215976Sjmallett */ 666232812Sjmallettunion cvmx_l2d_fus0 { 667215976Sjmallett uint64_t u64; 668232812Sjmallett struct cvmx_l2d_fus0_s { 669232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 670215976Sjmallett uint64_t reserved_34_63 : 30; 671215976Sjmallett uint64_t q0fus : 34; /**< Fuse Register for QUAD0 672215976Sjmallett This is purely for debug and not needed in the general 673215976Sjmallett manufacturing flow. 674215976Sjmallett Note that the fuse are complementary (Assigning a 675215976Sjmallett fuse to 1 will read as a zero). This means the case 676215976Sjmallett where no fuses are blown result in these csr's showing 677215976Sjmallett all ones. 678215976Sjmallett Failure \#1 Fuse Mapping 679215976Sjmallett [16:14] bad bank 680215976Sjmallett [13:7] bad high column 681215976Sjmallett [6:0] bad low column 682215976Sjmallett Failure \#2 Fuse Mapping 683215976Sjmallett [33:31] bad bank 684215976Sjmallett [30:24] bad high column 685215976Sjmallett [23:17] bad low column */ 686215976Sjmallett#else 687215976Sjmallett uint64_t q0fus : 34; 688215976Sjmallett uint64_t reserved_34_63 : 30; 689215976Sjmallett#endif 690215976Sjmallett } s; 691215976Sjmallett struct cvmx_l2d_fus0_s cn30xx; 692215976Sjmallett struct cvmx_l2d_fus0_s cn31xx; 693215976Sjmallett struct cvmx_l2d_fus0_s cn38xx; 694215976Sjmallett struct cvmx_l2d_fus0_s cn38xxp2; 695215976Sjmallett struct cvmx_l2d_fus0_s cn50xx; 696215976Sjmallett struct cvmx_l2d_fus0_s cn52xx; 697215976Sjmallett struct cvmx_l2d_fus0_s cn52xxp1; 698215976Sjmallett struct cvmx_l2d_fus0_s cn56xx; 699215976Sjmallett struct cvmx_l2d_fus0_s cn56xxp1; 700215976Sjmallett struct cvmx_l2d_fus0_s cn58xx; 701215976Sjmallett struct cvmx_l2d_fus0_s cn58xxp1; 702215976Sjmallett}; 703215976Sjmalletttypedef union cvmx_l2d_fus0 cvmx_l2d_fus0_t; 704215976Sjmallett 705215976Sjmallett/** 706215976Sjmallett * cvmx_l2d_fus1 707215976Sjmallett * 708215976Sjmallett * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register 709215976Sjmallett * 710215976Sjmallett */ 711232812Sjmallettunion cvmx_l2d_fus1 { 712215976Sjmallett uint64_t u64; 713232812Sjmallett struct cvmx_l2d_fus1_s { 714232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 715215976Sjmallett uint64_t reserved_34_63 : 30; 716215976Sjmallett uint64_t q1fus : 34; /**< Fuse Register for QUAD1 717215976Sjmallett This is purely for debug and not needed in the general 718215976Sjmallett manufacturing flow. 719215976Sjmallett Note that the fuse are complementary (Assigning a 720215976Sjmallett fuse to 1 will read as a zero). This means the case 721215976Sjmallett where no fuses are blown result in these csr's showing 722215976Sjmallett all ones. 723215976Sjmallett Failure \#1 Fuse Mapping 724215976Sjmallett [16:14] bad bank 725215976Sjmallett [13:7] bad high column 726215976Sjmallett [6:0] bad low column 727215976Sjmallett Failure \#2 Fuse Mapping 728215976Sjmallett [33:31] bad bank 729215976Sjmallett [30:24] bad high column 730215976Sjmallett [23:17] bad low column */ 731215976Sjmallett#else 732215976Sjmallett uint64_t q1fus : 34; 733215976Sjmallett uint64_t reserved_34_63 : 30; 734215976Sjmallett#endif 735215976Sjmallett } s; 736215976Sjmallett struct cvmx_l2d_fus1_s cn30xx; 737215976Sjmallett struct cvmx_l2d_fus1_s cn31xx; 738215976Sjmallett struct cvmx_l2d_fus1_s cn38xx; 739215976Sjmallett struct cvmx_l2d_fus1_s cn38xxp2; 740215976Sjmallett struct cvmx_l2d_fus1_s cn50xx; 741215976Sjmallett struct cvmx_l2d_fus1_s cn52xx; 742215976Sjmallett struct cvmx_l2d_fus1_s cn52xxp1; 743215976Sjmallett struct cvmx_l2d_fus1_s cn56xx; 744215976Sjmallett struct cvmx_l2d_fus1_s cn56xxp1; 745215976Sjmallett struct cvmx_l2d_fus1_s cn58xx; 746215976Sjmallett struct cvmx_l2d_fus1_s cn58xxp1; 747215976Sjmallett}; 748215976Sjmalletttypedef union cvmx_l2d_fus1 cvmx_l2d_fus1_t; 749215976Sjmallett 750215976Sjmallett/** 751215976Sjmallett * cvmx_l2d_fus2 752215976Sjmallett * 753215976Sjmallett * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register 754215976Sjmallett * 755215976Sjmallett */ 756232812Sjmallettunion cvmx_l2d_fus2 { 757215976Sjmallett uint64_t u64; 758232812Sjmallett struct cvmx_l2d_fus2_s { 759232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 760215976Sjmallett uint64_t reserved_34_63 : 30; 761215976Sjmallett uint64_t q2fus : 34; /**< Fuse Register for QUAD2 762215976Sjmallett This is purely for debug and not needed in the general 763215976Sjmallett manufacturing flow. 764215976Sjmallett Note that the fuse are complementary (Assigning a 765215976Sjmallett fuse to 1 will read as a zero). This means the case 766215976Sjmallett where no fuses are blown result in these csr's showing 767215976Sjmallett all ones. 768215976Sjmallett Failure \#1 Fuse Mapping 769215976Sjmallett [16:14] bad bank 770215976Sjmallett [13:7] bad high column 771215976Sjmallett [6:0] bad low column 772215976Sjmallett Failure \#2 Fuse Mapping 773215976Sjmallett [33:31] bad bank 774215976Sjmallett [30:24] bad high column 775215976Sjmallett [23:17] bad low column */ 776215976Sjmallett#else 777215976Sjmallett uint64_t q2fus : 34; 778215976Sjmallett uint64_t reserved_34_63 : 30; 779215976Sjmallett#endif 780215976Sjmallett } s; 781215976Sjmallett struct cvmx_l2d_fus2_s cn30xx; 782215976Sjmallett struct cvmx_l2d_fus2_s cn31xx; 783215976Sjmallett struct cvmx_l2d_fus2_s cn38xx; 784215976Sjmallett struct cvmx_l2d_fus2_s cn38xxp2; 785215976Sjmallett struct cvmx_l2d_fus2_s cn50xx; 786215976Sjmallett struct cvmx_l2d_fus2_s cn52xx; 787215976Sjmallett struct cvmx_l2d_fus2_s cn52xxp1; 788215976Sjmallett struct cvmx_l2d_fus2_s cn56xx; 789215976Sjmallett struct cvmx_l2d_fus2_s cn56xxp1; 790215976Sjmallett struct cvmx_l2d_fus2_s cn58xx; 791215976Sjmallett struct cvmx_l2d_fus2_s cn58xxp1; 792215976Sjmallett}; 793215976Sjmalletttypedef union cvmx_l2d_fus2 cvmx_l2d_fus2_t; 794215976Sjmallett 795215976Sjmallett/** 796215976Sjmallett * cvmx_l2d_fus3 797215976Sjmallett * 798215976Sjmallett * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register 799215976Sjmallett * 800215976Sjmallett */ 801232812Sjmallettunion cvmx_l2d_fus3 { 802215976Sjmallett uint64_t u64; 803232812Sjmallett struct cvmx_l2d_fus3_s { 804232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 805215976Sjmallett uint64_t reserved_40_63 : 24; 806215976Sjmallett uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control 807215976Sjmallett These bits are used to 'observe' the EMA[1:0] inputs 808215976Sjmallett for the L2 Data Store RAMs which are controlled by 809215976Sjmallett either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR. 810215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 811215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 812215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 813215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 814215976Sjmallett (until dc_ok). */ 815215976Sjmallett uint64_t reserved_34_36 : 3; 816215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 817215976Sjmallett This is purely for debug and not needed in the general 818215976Sjmallett manufacturing flow. 819215976Sjmallett Note that the fuses are complementary (Assigning a 820215976Sjmallett fuse to 1 will read as a zero). This means the case 821215976Sjmallett where no fuses are blown result in these csr's showing 822215976Sjmallett all ones. 823215976Sjmallett Failure \#1 Fuse Mapping 824215976Sjmallett [16:14] bad bank 825215976Sjmallett [13:7] bad high column 826215976Sjmallett [6:0] bad low column 827215976Sjmallett Failure \#2 Fuse Mapping 828215976Sjmallett [33:31] bad bank 829215976Sjmallett [30:24] bad high column 830215976Sjmallett [23:17] bad low column */ 831215976Sjmallett#else 832215976Sjmallett uint64_t q3fus : 34; 833215976Sjmallett uint64_t reserved_34_36 : 3; 834215976Sjmallett uint64_t ema_ctl : 3; 835215976Sjmallett uint64_t reserved_40_63 : 24; 836215976Sjmallett#endif 837215976Sjmallett } s; 838232812Sjmallett struct cvmx_l2d_fus3_cn30xx { 839232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 840215976Sjmallett uint64_t reserved_35_63 : 29; 841215976Sjmallett uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general 842215976Sjmallett manufacturing flow. 843215976Sjmallett If the FUSE is not-blown, then this bit should read 844215976Sjmallett as 0. If the FUSE is blown, then this bit should read 845215976Sjmallett as 1. */ 846215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 847215976Sjmallett This is purely for debug and not needed in the general 848215976Sjmallett manufacturing flow. 849215976Sjmallett Note that the fuses are complementary (Assigning a 850215976Sjmallett fuse to 1 will read as a zero). This means the case 851215976Sjmallett where no fuses are blown result in these csr's showing 852215976Sjmallett all ones. 853215976Sjmallett Failure \#1 Fuse Mapping 854215976Sjmallett [16:15] UNUSED 855215976Sjmallett [14] bad bank 856215976Sjmallett [13:7] bad high column 857215976Sjmallett [6:0] bad low column 858215976Sjmallett Failure \#2 Fuse Mapping 859215976Sjmallett [33:32] UNUSED 860215976Sjmallett [31] bad bank 861215976Sjmallett [30:24] bad high column 862215976Sjmallett [23:17] bad low column */ 863215976Sjmallett#else 864215976Sjmallett uint64_t q3fus : 34; 865215976Sjmallett uint64_t crip_64k : 1; 866215976Sjmallett uint64_t reserved_35_63 : 29; 867215976Sjmallett#endif 868215976Sjmallett } cn30xx; 869232812Sjmallett struct cvmx_l2d_fus3_cn31xx { 870232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 871215976Sjmallett uint64_t reserved_35_63 : 29; 872215976Sjmallett uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general 873215976Sjmallett manufacturing flow. 874215976Sjmallett If the FUSE is not-blown, then this bit should read 875215976Sjmallett as 0. If the FUSE is blown, then this bit should read 876215976Sjmallett as 1. */ 877215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 878215976Sjmallett This is purely for debug and not needed in the general 879215976Sjmallett manufacturing flow. 880215976Sjmallett Note that the fuses are complementary (Assigning a 881215976Sjmallett fuse to 1 will read as a zero). This means the case 882215976Sjmallett where no fuses are blown result in these csr's showing 883215976Sjmallett all ones. 884215976Sjmallett Failure \#1 Fuse Mapping 885215976Sjmallett [16:15] UNUSED 886215976Sjmallett [14] bad bank 887215976Sjmallett [13:7] bad high column 888215976Sjmallett [6:0] bad low column 889215976Sjmallett Failure \#2 Fuse Mapping 890215976Sjmallett [33:32] UNUSED 891215976Sjmallett [31] bad bank 892215976Sjmallett [30:24] bad high column 893215976Sjmallett [23:17] bad low column */ 894215976Sjmallett#else 895215976Sjmallett uint64_t q3fus : 34; 896215976Sjmallett uint64_t crip_128k : 1; 897215976Sjmallett uint64_t reserved_35_63 : 29; 898215976Sjmallett#endif 899215976Sjmallett } cn31xx; 900232812Sjmallett struct cvmx_l2d_fus3_cn38xx { 901232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 902215976Sjmallett uint64_t reserved_36_63 : 28; 903215976Sjmallett uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general 904215976Sjmallett manufacturing flow. 905215976Sjmallett If the FUSE is not-blown, then this bit should read 906215976Sjmallett as 0. If the FUSE is blown, then this bit should read 907215976Sjmallett as 1. 908215976Sjmallett *** NOTE: Pass2 Addition */ 909215976Sjmallett uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general 910215976Sjmallett manufacturing flow. 911215976Sjmallett If the FUSE is not-blown, then this bit should read 912215976Sjmallett as 0. If the FUSE is blown, then this bit should read 913215976Sjmallett as 1. 914215976Sjmallett *** NOTE: Pass2 Addition */ 915215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 916215976Sjmallett This is purely for debug and not needed in the general 917215976Sjmallett manufacturing flow. 918215976Sjmallett Note that the fuses are complementary (Assigning a 919215976Sjmallett fuse to 1 will read as a zero). This means the case 920215976Sjmallett where no fuses are blown result in these csr's showing 921215976Sjmallett all ones. 922215976Sjmallett Failure \#1 Fuse Mapping 923215976Sjmallett [16:14] bad bank 924215976Sjmallett [13:7] bad high column 925215976Sjmallett [6:0] bad low column 926215976Sjmallett Failure \#2 Fuse Mapping 927215976Sjmallett [33:31] bad bank 928215976Sjmallett [30:24] bad high column 929215976Sjmallett [23:17] bad low column */ 930215976Sjmallett#else 931215976Sjmallett uint64_t q3fus : 34; 932215976Sjmallett uint64_t crip_512k : 1; 933215976Sjmallett uint64_t crip_256k : 1; 934215976Sjmallett uint64_t reserved_36_63 : 28; 935215976Sjmallett#endif 936215976Sjmallett } cn38xx; 937215976Sjmallett struct cvmx_l2d_fus3_cn38xx cn38xxp2; 938232812Sjmallett struct cvmx_l2d_fus3_cn50xx { 939232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 940215976Sjmallett uint64_t reserved_40_63 : 24; 941215976Sjmallett uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control 942215976Sjmallett These bits are used to 'observe' the EMA[2:0] inputs 943215976Sjmallett for the L2 Data Store RAMs which are controlled by 944215976Sjmallett either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR. 945215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 946215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 947215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 948215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 949215976Sjmallett (until dc_ok). */ 950215976Sjmallett uint64_t reserved_36_36 : 1; 951215976Sjmallett uint64_t crip_32k : 1; /**< This is purely for debug and not needed in the general 952215976Sjmallett manufacturing flow. 953215976Sjmallett If the FUSE is not-blown, then this bit should read 954215976Sjmallett as 0. If the FUSE is blown, then this bit should read 955215976Sjmallett as 1. */ 956215976Sjmallett uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general 957215976Sjmallett manufacturing flow. 958215976Sjmallett If the FUSE is not-blown, then this bit should read 959215976Sjmallett as 0. If the FUSE is blown, then this bit should read 960215976Sjmallett as 1. */ 961215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 962215976Sjmallett This is purely for debug and not needed in the general 963215976Sjmallett manufacturing flow. 964215976Sjmallett Note that the fuses are complementary (Assigning a 965215976Sjmallett fuse to 1 will read as a zero). This means the case 966215976Sjmallett where no fuses are blown result in these csr's showing 967215976Sjmallett all ones. 968215976Sjmallett Failure \#1 Fuse Mapping 969215976Sjmallett [16:14] UNUSED (5020 uses single physical bank per quad) 970215976Sjmallett [13:7] bad high column 971215976Sjmallett [6:0] bad low column 972215976Sjmallett Failure \#2 Fuse Mapping 973215976Sjmallett [33:31] UNUSED (5020 uses single physical bank per quad) 974215976Sjmallett [30:24] bad high column 975215976Sjmallett [23:17] bad low column */ 976215976Sjmallett#else 977215976Sjmallett uint64_t q3fus : 34; 978215976Sjmallett uint64_t crip_64k : 1; 979215976Sjmallett uint64_t crip_32k : 1; 980215976Sjmallett uint64_t reserved_36_36 : 1; 981215976Sjmallett uint64_t ema_ctl : 3; 982215976Sjmallett uint64_t reserved_40_63 : 24; 983215976Sjmallett#endif 984215976Sjmallett } cn50xx; 985232812Sjmallett struct cvmx_l2d_fus3_cn52xx { 986232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 987215976Sjmallett uint64_t reserved_40_63 : 24; 988215976Sjmallett uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control 989215976Sjmallett These bits are used to 'observe' the EMA[2:0] inputs 990215976Sjmallett for the L2 Data Store RAMs which are controlled by 991215976Sjmallett either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR. 992215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 993215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 994215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 995215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 996215976Sjmallett (until dc_ok). */ 997215976Sjmallett uint64_t reserved_36_36 : 1; 998215976Sjmallett uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general 999215976Sjmallett manufacturing flow. 1000215976Sjmallett If the FUSE is not-blown, then this bit should read 1001215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1002215976Sjmallett as 1. */ 1003215976Sjmallett uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general 1004215976Sjmallett manufacturing flow. 1005215976Sjmallett If the FUSE is not-blown, then this bit should read 1006215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1007215976Sjmallett as 1. */ 1008215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 1009215976Sjmallett This is purely for debug and not needed in the general 1010215976Sjmallett manufacturing flow. 1011215976Sjmallett Note that the fuses are complementary (Assigning a 1012215976Sjmallett fuse to 1 will read as a zero). This means the case 1013215976Sjmallett where no fuses are blown result in these csr's showing 1014215976Sjmallett all ones. 1015215976Sjmallett Failure \#1 Fuse Mapping 1016215976Sjmallett [16:14] UNUSED (5020 uses single physical bank per quad) 1017215976Sjmallett [13:7] bad high column 1018215976Sjmallett [6:0] bad low column 1019215976Sjmallett Failure \#2 Fuse Mapping 1020215976Sjmallett [33:31] UNUSED (5020 uses single physical bank per quad) 1021215976Sjmallett [30:24] bad high column 1022215976Sjmallett [23:17] bad low column */ 1023215976Sjmallett#else 1024215976Sjmallett uint64_t q3fus : 34; 1025215976Sjmallett uint64_t crip_256k : 1; 1026215976Sjmallett uint64_t crip_128k : 1; 1027215976Sjmallett uint64_t reserved_36_36 : 1; 1028215976Sjmallett uint64_t ema_ctl : 3; 1029215976Sjmallett uint64_t reserved_40_63 : 24; 1030215976Sjmallett#endif 1031215976Sjmallett } cn52xx; 1032215976Sjmallett struct cvmx_l2d_fus3_cn52xx cn52xxp1; 1033232812Sjmallett struct cvmx_l2d_fus3_cn56xx { 1034232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1035215976Sjmallett uint64_t reserved_40_63 : 24; 1036215976Sjmallett uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control 1037215976Sjmallett These bits are used to 'observe' the EMA[2:0] inputs 1038215976Sjmallett for the L2 Data Store RAMs which are controlled by 1039215976Sjmallett either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR. 1040215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 1041215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 1042215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 1043215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 1044215976Sjmallett (until dc_ok). */ 1045215976Sjmallett uint64_t reserved_36_36 : 1; 1046215976Sjmallett uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general 1047215976Sjmallett manufacturing flow. 1048215976Sjmallett If the FUSE is not-blown, then this bit should read 1049215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1050215976Sjmallett as 1. 1051215976Sjmallett *** NOTE: Pass2 Addition */ 1052215976Sjmallett uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general 1053215976Sjmallett manufacturing flow. 1054215976Sjmallett If the FUSE is not-blown, then this bit should read 1055215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1056215976Sjmallett as 1. 1057215976Sjmallett *** NOTE: Pass2 Addition */ 1058215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 1059215976Sjmallett This is purely for debug and not needed in the general 1060215976Sjmallett manufacturing flow. 1061215976Sjmallett Note that the fuses are complementary (Assigning a 1062215976Sjmallett fuse to 1 will read as a zero). This means the case 1063215976Sjmallett where no fuses are blown result in these csr's showing 1064215976Sjmallett all ones. 1065215976Sjmallett Failure \#1 Fuse Mapping 1066215976Sjmallett [16:14] bad bank 1067215976Sjmallett [13:7] bad high column 1068215976Sjmallett [6:0] bad low column 1069215976Sjmallett Failure \#2 Fuse Mapping 1070215976Sjmallett [33:31] bad bank 1071215976Sjmallett [30:24] bad high column 1072215976Sjmallett [23:17] bad low column */ 1073215976Sjmallett#else 1074215976Sjmallett uint64_t q3fus : 34; 1075215976Sjmallett uint64_t crip_1024k : 1; 1076215976Sjmallett uint64_t crip_512k : 1; 1077215976Sjmallett uint64_t reserved_36_36 : 1; 1078215976Sjmallett uint64_t ema_ctl : 3; 1079215976Sjmallett uint64_t reserved_40_63 : 24; 1080215976Sjmallett#endif 1081215976Sjmallett } cn56xx; 1082215976Sjmallett struct cvmx_l2d_fus3_cn56xx cn56xxp1; 1083232812Sjmallett struct cvmx_l2d_fus3_cn58xx { 1084232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1085215976Sjmallett uint64_t reserved_39_63 : 25; 1086215976Sjmallett uint64_t ema_ctl : 2; /**< L2 Data Store EMA Control 1087215976Sjmallett These bits are used to 'observe' the EMA[1:0] inputs 1088215976Sjmallett for the L2 Data Store RAMs which are controlled by 1089215976Sjmallett either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR. 1090215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 1091215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 1092215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 1093215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 1094215976Sjmallett (until dc_ok). */ 1095215976Sjmallett uint64_t reserved_36_36 : 1; 1096215976Sjmallett uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general 1097215976Sjmallett manufacturing flow. 1098215976Sjmallett If the FUSE is not-blown, then this bit should read 1099215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1100215976Sjmallett as 1. 1101215976Sjmallett *** NOTE: Pass2 Addition */ 1102215976Sjmallett uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general 1103215976Sjmallett manufacturing flow. 1104215976Sjmallett If the FUSE is not-blown, then this bit should read 1105215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1106215976Sjmallett as 1. 1107215976Sjmallett *** NOTE: Pass2 Addition */ 1108215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 1109215976Sjmallett This is purely for debug and not needed in the general 1110215976Sjmallett manufacturing flow. 1111215976Sjmallett Note that the fuses are complementary (Assigning a 1112215976Sjmallett fuse to 1 will read as a zero). This means the case 1113215976Sjmallett where no fuses are blown result in these csr's showing 1114215976Sjmallett all ones. 1115215976Sjmallett Failure \#1 Fuse Mapping 1116215976Sjmallett [16:14] bad bank 1117215976Sjmallett [13:7] bad high column 1118215976Sjmallett [6:0] bad low column 1119215976Sjmallett Failure \#2 Fuse Mapping 1120215976Sjmallett [33:31] bad bank 1121215976Sjmallett [30:24] bad high column 1122215976Sjmallett [23:17] bad low column */ 1123215976Sjmallett#else 1124215976Sjmallett uint64_t q3fus : 34; 1125215976Sjmallett uint64_t crip_1024k : 1; 1126215976Sjmallett uint64_t crip_512k : 1; 1127215976Sjmallett uint64_t reserved_36_36 : 1; 1128215976Sjmallett uint64_t ema_ctl : 2; 1129215976Sjmallett uint64_t reserved_39_63 : 25; 1130215976Sjmallett#endif 1131215976Sjmallett } cn58xx; 1132215976Sjmallett struct cvmx_l2d_fus3_cn58xx cn58xxp1; 1133215976Sjmallett}; 1134215976Sjmalletttypedef union cvmx_l2d_fus3 cvmx_l2d_fus3_t; 1135215976Sjmallett 1136215976Sjmallett#endif 1137