1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-asx0-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon asx0. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_ASX0_DEFS_H__ 53232812Sjmallett#define __CVMX_ASX0_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 60215976Sjmallett cvmx_warn("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000208ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_ASX0_DBG_DATA_DRV (CVMX_ADD_IO_SEG(0x00011800B0000208ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void) 69215976Sjmallett{ 70215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 71215976Sjmallett cvmx_warn("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000200ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_ASX0_DBG_DATA_ENABLE (CVMX_ADD_IO_SEG(0x00011800B0000200ull)) 76215976Sjmallett#endif 77215976Sjmallett 78215976Sjmallett/** 79215976Sjmallett * cvmx_asx0_dbg_data_drv 80215976Sjmallett * 81215976Sjmallett * ASX_DBG_DATA_DRV 82215976Sjmallett * 83215976Sjmallett */ 84232812Sjmallettunion cvmx_asx0_dbg_data_drv { 85215976Sjmallett uint64_t u64; 86232812Sjmallett struct cvmx_asx0_dbg_data_drv_s { 87232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 88215976Sjmallett uint64_t reserved_9_63 : 55; 89215976Sjmallett uint64_t pctl : 5; /**< These bits control the driving strength of the dbg 90215976Sjmallett interface. */ 91215976Sjmallett uint64_t nctl : 4; /**< These bits control the driving strength of the dbg 92215976Sjmallett interface. */ 93215976Sjmallett#else 94215976Sjmallett uint64_t nctl : 4; 95215976Sjmallett uint64_t pctl : 5; 96215976Sjmallett uint64_t reserved_9_63 : 55; 97215976Sjmallett#endif 98215976Sjmallett } s; 99232812Sjmallett struct cvmx_asx0_dbg_data_drv_cn38xx { 100232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 101215976Sjmallett uint64_t reserved_8_63 : 56; 102215976Sjmallett uint64_t pctl : 4; /**< These bits control the driving strength of the dbg 103215976Sjmallett interface. */ 104215976Sjmallett uint64_t nctl : 4; /**< These bits control the driving strength of the dbg 105215976Sjmallett interface. */ 106215976Sjmallett#else 107215976Sjmallett uint64_t nctl : 4; 108215976Sjmallett uint64_t pctl : 4; 109215976Sjmallett uint64_t reserved_8_63 : 56; 110215976Sjmallett#endif 111215976Sjmallett } cn38xx; 112215976Sjmallett struct cvmx_asx0_dbg_data_drv_cn38xx cn38xxp2; 113215976Sjmallett struct cvmx_asx0_dbg_data_drv_s cn58xx; 114215976Sjmallett struct cvmx_asx0_dbg_data_drv_s cn58xxp1; 115215976Sjmallett}; 116215976Sjmalletttypedef union cvmx_asx0_dbg_data_drv cvmx_asx0_dbg_data_drv_t; 117215976Sjmallett 118215976Sjmallett/** 119215976Sjmallett * cvmx_asx0_dbg_data_enable 120215976Sjmallett * 121215976Sjmallett * ASX_DBG_DATA_ENABLE 122215976Sjmallett * 123215976Sjmallett */ 124232812Sjmallettunion cvmx_asx0_dbg_data_enable { 125215976Sjmallett uint64_t u64; 126232812Sjmallett struct cvmx_asx0_dbg_data_enable_s { 127232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 128215976Sjmallett uint64_t reserved_1_63 : 63; 129215976Sjmallett uint64_t en : 1; /**< A 1->0 transistion, turns the dbg interface OFF. */ 130215976Sjmallett#else 131215976Sjmallett uint64_t en : 1; 132215976Sjmallett uint64_t reserved_1_63 : 63; 133215976Sjmallett#endif 134215976Sjmallett } s; 135215976Sjmallett struct cvmx_asx0_dbg_data_enable_s cn38xx; 136215976Sjmallett struct cvmx_asx0_dbg_data_enable_s cn38xxp2; 137215976Sjmallett struct cvmx_asx0_dbg_data_enable_s cn58xx; 138215976Sjmallett struct cvmx_asx0_dbg_data_enable_s cn58xxp1; 139215976Sjmallett}; 140215976Sjmalletttypedef union cvmx_asx0_dbg_data_enable cvmx_asx0_dbg_data_enable_t; 141215976Sjmallett 142215976Sjmallett#endif 143