1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#ifndef _ATH_AR9300_H_ 18250003Sadrian#define _ATH_AR9300_H_ 19250003Sadrian 20250008Sadrian#include "ar9300_freebsd_inc.h" 21250008Sadrian 22250008Sadrian#define AH_BIG_ENDIAN 4321 23250008Sadrian#define AH_LITTLE_ENDIAN 1234 24250008Sadrian 25250008Sadrian#if _BYTE_ORDER == _BIG_ENDIAN 26250008Sadrian#define AH_BYTE_ORDER AH_BIG_ENDIAN 27250008Sadrian#else 28250008Sadrian#define AH_BYTE_ORDER AH_LITTLE_ENDIAN 29250008Sadrian#endif 30250008Sadrian 31250008Sadrian/* XXX doesn't belong here */ 32250008Sadrian#define AR_EEPROM_MODAL_SPURS 5 33250008Sadrian 34250008Sadrian/* 35250008Sadrian * (a) this should be N(a), 36250008Sadrian * (b) FreeBSD does define nitems, 37250008Sadrian * (c) it doesn't have an AH_ prefix, sigh. 38250008Sadrian */ 39250008Sadrian#define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0])) 40250008Sadrian 41250003Sadrian#include "ah_internal.h" 42250003Sadrian#include "ah_eeprom.h" 43250003Sadrian#include "ah_devid.h" 44250003Sadrian#include "ar9300eep.h" /* For Eeprom definitions */ 45250003Sadrian 46250003Sadrian 47250003Sadrian#define AR9300_MAGIC 0x19741014 48250003Sadrian 49250003Sadrian 50250003Sadrian/* MAC register values */ 51250003Sadrian 52250003Sadrian#define INIT_CONFIG_STATUS 0x00000000 53250003Sadrian#define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 54250003Sadrian#define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */ 55250003Sadrian 56250003Sadrian/* 57250003Sadrian * Various fifo fill before Tx start, in 64-byte units 58250003Sadrian * i.e. put the frame in the air while still DMAing 59250003Sadrian */ 60250003Sadrian#define MIN_TX_FIFO_THRESHOLD 0x1 61250003Sadrian#define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) 62250003Sadrian#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 63250003Sadrian 64250003Sadrian #define CHANSEL_DIV 15 65250003Sadrian #define FCLK 40 66250003Sadrian 67250003Sadrian#define COEFF ((FCLK * 5) / 2) 68250003Sadrian#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) 69250003Sadrian#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) 70250003Sadrian#define CHANSEL_5G_DOT5MHZ 2188 71250003Sadrian 72250003Sadrian/* 73250003Sadrian * Receive Queue Fifo depth. 74250003Sadrian */ 75250003Sadrianenum RX_FIFO_DEPTH { 76250003Sadrian HAL_HP_RXFIFO_DEPTH = 16, 77250003Sadrian HAL_LP_RXFIFO_DEPTH = 128, 78250003Sadrian}; 79250003Sadrian 80250003Sadrian/* 81250003Sadrian * Gain support. 82250003Sadrian */ 83250003Sadrian#define NUM_CORNER_FIX_BITS_2133 7 84250003Sadrian#define CCK_OFDM_GAIN_DELTA 15 85250003Sadrian 86250003Sadrianenum GAIN_PARAMS { 87250003Sadrian GP_TXCLIP, 88250003Sadrian GP_PD90, 89250003Sadrian GP_PD84, 90250003Sadrian GP_GSEL 91250003Sadrian}; 92250003Sadrian 93250003Sadrianenum GAIN_PARAMS_2133 { 94250003Sadrian GP_MIXGAIN_OVR, 95250003Sadrian GP_PWD_138, 96250003Sadrian GP_PWD_137, 97250003Sadrian GP_PWD_136, 98250003Sadrian GP_PWD_132, 99250003Sadrian GP_PWD_131, 100250003Sadrian GP_PWD_130, 101250003Sadrian}; 102250003Sadrian 103250003Sadrianenum { 104250003Sadrian HAL_RESET_POWER_ON, 105250003Sadrian HAL_RESET_WARM, 106250003Sadrian HAL_RESET_COLD, 107250003Sadrian}; 108250003Sadrian 109250003Sadriantypedef struct _gain_opt_step { 110250003Sadrian int16_t paramVal[NUM_CORNER_FIX_BITS_2133]; 111250003Sadrian int32_t stepGain; 112250003Sadrian int8_t stepName[16]; 113250003Sadrian} GAIN_OPTIMIZATION_STEP; 114250003Sadrian 115250003Sadriantypedef struct { 116250003Sadrian u_int32_t numStepsInLadder; 117250003Sadrian u_int32_t defaultStepNum; 118250003Sadrian GAIN_OPTIMIZATION_STEP optStep[10]; 119250003Sadrian} GAIN_OPTIMIZATION_LADDER; 120250003Sadrian 121250003Sadriantypedef struct { 122250003Sadrian u_int32_t currStepNum; 123250003Sadrian u_int32_t currGain; 124250003Sadrian u_int32_t targetGain; 125250003Sadrian u_int32_t loTrig; 126250003Sadrian u_int32_t hiTrig; 127250003Sadrian u_int32_t gainFCorrection; 128250003Sadrian u_int32_t active; 129250003Sadrian GAIN_OPTIMIZATION_STEP *curr_step; 130250003Sadrian} GAIN_VALUES; 131250003Sadrian 132250003Sadriantypedef struct { 133250003Sadrian u_int16_t synth_center; 134250003Sadrian u_int16_t ctl_center; 135250003Sadrian u_int16_t ext_center; 136250003Sadrian} CHAN_CENTERS; 137250003Sadrian 138250003Sadrian/* RF HAL structures */ 139250003Sadriantypedef struct rf_hal_funcs { 140250008Sadrian HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *); 141250008Sadrian HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, 142250008Sadrian struct ieee80211_channel *chan); 143250003Sadrian} RF_HAL_FUNCS; 144250003Sadrian 145250003Sadrianstruct ar9300_ani_default { 146250003Sadrian u_int16_t m1_thresh_low; 147250003Sadrian u_int16_t m2_thresh_low; 148250003Sadrian u_int16_t m1_thresh; 149250003Sadrian u_int16_t m2_thresh; 150250003Sadrian u_int16_t m2_count_thr; 151250003Sadrian u_int16_t m2_count_thr_low; 152250003Sadrian u_int16_t m1_thresh_low_ext; 153250003Sadrian u_int16_t m2_thresh_low_ext; 154250003Sadrian u_int16_t m1_thresh_ext; 155250003Sadrian u_int16_t m2_thresh_ext; 156250003Sadrian u_int16_t firstep; 157250003Sadrian u_int16_t firstep_low; 158250003Sadrian u_int16_t cycpwr_thr1; 159250003Sadrian u_int16_t cycpwr_thr1_ext; 160250003Sadrian}; 161250003Sadrian 162250003Sadrian/* 163250003Sadrian * Per-channel ANI state private to the driver. 164250003Sadrian */ 165250003Sadrianstruct ar9300_ani_state { 166250008Sadrian struct ieee80211_channel c; /* XXX ew? */ 167250003Sadrian HAL_BOOL must_restore; 168250003Sadrian HAL_BOOL ofdms_turn; 169250003Sadrian u_int8_t ofdm_noise_immunity_level; 170250003Sadrian u_int8_t cck_noise_immunity_level; 171250003Sadrian u_int8_t spur_immunity_level; 172250003Sadrian u_int8_t firstep_level; 173250003Sadrian u_int8_t ofdm_weak_sig_detect_off; 174250003Sadrian u_int8_t mrc_cck_off; 175250003Sadrian 176250003Sadrian /* Thresholds */ 177250003Sadrian u_int32_t listen_time; 178250003Sadrian u_int32_t ofdm_trig_high; 179250003Sadrian u_int32_t ofdm_trig_low; 180250003Sadrian int32_t cck_trig_high; 181250003Sadrian int32_t cck_trig_low; 182250003Sadrian int32_t rssi_thr_low; 183250003Sadrian int32_t rssi_thr_high; 184250003Sadrian 185250003Sadrian int32_t rssi; /* The current RSSI */ 186250003Sadrian u_int32_t tx_frame_count; /* Last tx_frame_count */ 187250003Sadrian u_int32_t rx_frame_count; /* Last rx Frame count */ 188250003Sadrian u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */ 189250003Sadrian u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */ 190250003Sadrian u_int32_t cck_phy_err_count; /* CCK err count since last reset */ 191250003Sadrian 192250003Sadrian struct ar9300_ani_default ini_def; /* INI default values for ANI registers */ 193250003Sadrian HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */ 194250003Sadrian}; 195250003Sadrian 196250003Sadrian#define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */ 197250003Sadrian 198250003Sadrian#define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */ 199250003Sadrian 200250003Sadrian#define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ 201250003Sadrian#define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */ 202250003Sadrian#define HAL_AR_EN 0x40000000 /* AR detect is capable */ 203250003Sadrian 204250003Sadrian#define DO_ANI(ah) \ 205250003Sadrian ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI)) 206250003Sadrian 207250003Sadrianstruct ar9300_stats { 208250003Sadrian u_int32_t ast_ani_niup; /* ANI increased noise immunity */ 209250003Sadrian u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */ 210250003Sadrian u_int32_t ast_ani_spurup; /* ANI increased spur immunity */ 211250003Sadrian u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 212250003Sadrian u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 213250003Sadrian u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 214250003Sadrian u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 215250003Sadrian u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 216250003Sadrian u_int32_t ast_ani_stepup; /* ANI increased first step level */ 217250003Sadrian u_int32_t ast_ani_stepdown;/* ANI decreased first step level */ 218250003Sadrian u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 219250003Sadrian u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 220250003Sadrian u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 221250003Sadrian u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */ 222250003Sadrian u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 223250003Sadrian HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 224250003Sadrian HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 225250003Sadrian}; 226250003Sadrian 227250003Sadrianstruct ar9300_rad_reader { 228250003Sadrian u_int16_t rd_index; 229250003Sadrian u_int16_t rd_expSeq; 230250003Sadrian u_int32_t rd_resetVal; 231250003Sadrian u_int8_t rd_start; 232250003Sadrian}; 233250003Sadrian 234250003Sadrianstruct ar9300_rad_writer { 235250003Sadrian u_int16_t wr_index; 236250003Sadrian u_int16_t wr_seq; 237250003Sadrian}; 238250003Sadrian 239250003Sadrianstruct ar9300_radar_event { 240250003Sadrian u_int32_t re_ts; /* 32 bit time stamp */ 241250003Sadrian u_int8_t re_rssi; /* rssi of radar event */ 242250003Sadrian u_int8_t re_dur; /* duration of radar pulse */ 243250003Sadrian u_int8_t re_chanIndex; /* Channel of event */ 244250003Sadrian}; 245250003Sadrian 246250003Sadrianstruct ar9300_radar_q_elem { 247250003Sadrian u_int32_t rq_seqNum; 248250003Sadrian u_int32_t rq_busy; /* 32 bit to insure atomic read/write */ 249250003Sadrian struct ar9300_radar_event rq_event; /* Radar event */ 250250003Sadrian}; 251250003Sadrian 252250003Sadrianstruct ar9300_radar_q_info { 253250003Sadrian u_int16_t ri_qsize; /* q size */ 254250003Sadrian u_int16_t ri_seqSize; /* Size of sequence ring */ 255250003Sadrian struct ar9300_rad_reader ri_reader; /* State for the q reader */ 256250003Sadrian struct ar9300_rad_writer ri_writer; /* state for the q writer */ 257250003Sadrian}; 258250003Sadrian 259250003Sadrian#define HAL_MAX_ACK_RADAR_DUR 511 260250003Sadrian#define HAL_MAX_NUM_PEAKS 3 261250003Sadrian#define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */ 262250003Sadrian#define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */ 263250003Sadrian#define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */ 264250003Sadrian#define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */ 265250003Sadrian#define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */ 266250003Sadrian 267250003Sadrianstruct ar9300_ar_state { 268250003Sadrian u_int16_t ar_prev_time_stamp; 269250003Sadrian u_int32_t ar_prev_width; 270250003Sadrian u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR]; 271250003Sadrian u_int32_t ar_ack_sum; 272250003Sadrian u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS]; 273250003Sadrian u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */ 274250003Sadrian u_int32_t ar_par_threshold; /* Thresh to determine peak */ 275250003Sadrian u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */ 276250003Sadrian}; 277250003Sadrian 278250003Sadrianstruct ar9300_radar_state { 279250008Sadrian struct ieee80211_channel *rs_chan; /* Channel info */ 280250003Sadrian u_int8_t rs_chan_index; /* Channel index in radar structure */ 281250003Sadrian u_int32_t rs_num_radar_events; /* Number of radar events */ 282250003Sadrian int32_t rs_firpwr; /* Thresh to check radar sig is gone */ 283250003Sadrian u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */ 284250003Sadrian u_int32_t rs_height; /* Thresh for pulse height (dB)*/ 285250003Sadrian u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */ 286250003Sadrian u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */ 287250003Sadrian}; 288250003Sadriantypedef struct { 289250003Sadrian u_int8_t uc_receiver_errors; 290250003Sadrian u_int8_t uc_bad_tlp_errors; 291250003Sadrian u_int8_t uc_bad_dllp_errors; 292250003Sadrian u_int8_t uc_replay_timeout_errors; 293250003Sadrian u_int8_t uc_replay_number_rollover_errors; 294250003Sadrian} ar_pcie_error_moniter_counters; 295250003Sadrian 296250003Sadrian#define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */ 297250003Sadrian#define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */ 298250003Sadrian#define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */ 299250003Sadrian#define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */ 300250003Sadrian#define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */ 301250003Sadrian#define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */ 302250003Sadrian 303250003Sadrian/* 304250003Sadrian * For Kite and later chipsets, the following bits are not being programmed in EEPROM 305250003Sadrian * and so need to be enabled always. 306250003Sadrian * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40 307250003Sadrian * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40 308250003Sadrian */ 309250003Sadrian#define AR9300_RDEXT_DEFAULT 0x1F 310250003Sadrian 311250003Sadrian#define AR9300_MAX_CHAINS 3 312250003Sadrian#define AR9300_NUM_CHAINS(chainmask) \ 313250003Sadrian (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1)) 314250003Sadrian#define AR9300_CHAIN0_MASK 0x1 315250003Sadrian#define AR9300_CHAIN1_MASK 0x2 316250003Sadrian#define AR9300_CHAIN2_MASK 0x4 317250003Sadrian 318250003Sadrian/* Support for multiple INIs */ 319250003Sadrianstruct ar9300_ini_array { 320250003Sadrian u_int32_t *ia_array; 321250003Sadrian u_int32_t ia_rows; 322250003Sadrian u_int32_t ia_columns; 323250003Sadrian}; 324250003Sadrian#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 325250003Sadrian (iniarray)->ia_array = (u_int32_t *)(array); \ 326250003Sadrian (iniarray)->ia_rows = (rows); \ 327250003Sadrian (iniarray)->ia_columns = (columns); \ 328250003Sadrian} while (0) 329250003Sadrian#define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) 330250003Sadrian 331250003Sadrian#define INIT_CAL(_perCal) \ 332250003Sadrian (_perCal)->cal_state = CAL_WAITING; \ 333250003Sadrian (_perCal)->cal_next = AH_NULL; 334250003Sadrian 335250003Sadrian#define INSERT_CAL(_ahp, _perCal) \ 336250003Sadriando { \ 337250003Sadrian if ((_ahp)->ah_cal_list_last == AH_NULL) { \ 338250003Sadrian (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \ 339250003Sadrian ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 340250003Sadrian } else { \ 341250003Sadrian ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 342250003Sadrian (_ahp)->ah_cal_list_last = (_perCal); \ 343250003Sadrian (_perCal)->cal_next = (_ahp)->ah_cal_list; \ 344250003Sadrian } \ 345250003Sadrian} while (0) 346250003Sadrian 347250003Sadriantypedef enum cal_types { 348250003Sadrian IQ_MISMATCH_CAL = 0x1, 349250003Sadrian TEMP_COMP_CAL = 0x2, 350250003Sadrian} HAL_CAL_TYPES; 351250003Sadrian 352250003Sadriantypedef enum cal_state { 353250003Sadrian CAL_INACTIVE, 354250003Sadrian CAL_WAITING, 355250003Sadrian CAL_RUNNING, 356250003Sadrian CAL_DONE 357250003Sadrian} HAL_CAL_STATE; /* Calibrate state */ 358250003Sadrian 359250003Sadrian#define MIN_CAL_SAMPLES 1 360250003Sadrian#define MAX_CAL_SAMPLES 64 361250003Sadrian#define INIT_LOG_COUNT 5 362250003Sadrian#define PER_MIN_LOG_COUNT 2 363250003Sadrian#define PER_MAX_LOG_COUNT 10 364250003Sadrian 365250003Sadrian#define AR9300_NUM_BT_WEIGHTS 4 366250003Sadrian#define AR9300_NUM_WLAN_WEIGHTS 4 367250003Sadrian 368250003Sadrian/* Per Calibration data structure */ 369250003Sadriantypedef struct per_cal_data { 370250003Sadrian HAL_CAL_TYPES cal_type; // Type of calibration 371250003Sadrian u_int32_t cal_num_samples; // Number of SW samples to collect 372250003Sadrian u_int32_t cal_count_max; // Number of HW samples to collect 373250003Sadrian void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func 374250003Sadrian void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func 375250003Sadrian} HAL_PERCAL_DATA; 376250003Sadrian 377250003Sadrian/* List structure for calibration data */ 378250003Sadriantypedef struct cal_list { 379250003Sadrian const HAL_PERCAL_DATA *cal_data; 380250003Sadrian HAL_CAL_STATE cal_state; 381250003Sadrian struct cal_list *cal_next; 382250003Sadrian} HAL_CAL_LIST; 383250003Sadrian 384250003Sadrian#define AR9300_NUM_CAL_TYPES 2 385250003Sadrian#define AR9300_PAPRD_TABLE_SZ 24 386250003Sadrian#define AR9300_PAPRD_GAIN_TABLE_SZ 32 387250003Sadrian#define AR9382_MAX_GPIO_PIN_NUM (16) 388250003Sadrian#define AR9382_GPIO_PIN_8_RESERVED (8) 389250003Sadrian#define AR9382_GPIO_9_INPUT_ONLY (9) 390250003Sadrian#define AR9382_MAX_GPIO_INPUT_PIN_NUM (13) 391250003Sadrian#define AR9382_GPIO_PIN_11_RESERVED (11) 392250003Sadrian#define AR9382_MAX_JTAG_GPIO_PIN_NUM (3) 393250003Sadrian 394250003Sadrian/* Paprd tx power adjust data structure */ 395250003Sadrianstruct ar9300_paprd_pwr_adjust { 396250003Sadrian u_int32_t target_rate; // rate index 397250003Sadrian u_int32_t reg_addr; // register offset 398250003Sadrian u_int32_t reg_mask; // mask of register 399250003Sadrian u_int32_t reg_mask_offset; // mask offset of register 400250003Sadrian u_int32_t sub_db; // offset value unit of dB 401250003Sadrian}; 402250003Sadrian 403250008Sadrianstruct ar9300NfLimits { 404250008Sadrian int16_t max; 405250008Sadrian int16_t min; 406250008Sadrian int16_t nominal; 407250008Sadrian}; 408250008Sadrian 409250003Sadrian#define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ 410250003Sadrianstruct ath_hal_9300 { 411250008Sadrian struct ath_hal_private ah_priv; /* base class */ 412250003Sadrian 413250003Sadrian /* 414250003Sadrian * Information retrieved from EEPROM. 415250003Sadrian */ 416250003Sadrian ar9300_eeprom_t ah_eeprom; 417250003Sadrian 418250003Sadrian GAIN_VALUES ah_gain_values; 419250003Sadrian 420250003Sadrian u_int8_t ah_macaddr[IEEE80211_ADDR_LEN]; 421250003Sadrian u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; 422250003Sadrian u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN]; 423250003Sadrian u_int16_t ah_assoc_id; 424250003Sadrian 425250003Sadrian /* 426250003Sadrian * Runtime state. 427250003Sadrian */ 428250003Sadrian u_int32_t ah_mask_reg; /* copy of AR_IMR */ 429250003Sadrian u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */ 430250003Sadrian u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */ 431250003Sadrian os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */ 432250003Sadrian struct ar9300_stats ah_stats; /* various statistics */ 433250003Sadrian RF_HAL_FUNCS ah_rf_hal; 434250003Sadrian u_int32_t ah_tx_desc_mask; /* mask for TXDESC */ 435250003Sadrian u_int32_t ah_tx_ok_interrupt_mask; 436250003Sadrian u_int32_t ah_tx_err_interrupt_mask; 437250003Sadrian u_int32_t ah_tx_desc_interrupt_mask; 438250003Sadrian u_int32_t ah_tx_eol_interrupt_mask; 439250003Sadrian u_int32_t ah_tx_urn_interrupt_mask; 440250003Sadrian HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 441250003Sadrian HAL_SMPS_MODE ah_sm_power_mode; 442250003Sadrian HAL_BOOL ah_chip_full_sleep; 443250003Sadrian u_int32_t ah_atim_window; 444250003Sadrian HAL_ANT_SETTING ah_diversity_control; /* antenna setting */ 445250003Sadrian u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */ 446250003Sadrian u_int8_t ah_tx_chainmask_cfg; /* chain mask config */ 447250003Sadrian u_int8_t ah_rx_chainmask_cfg; 448250003Sadrian u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */ 449250003Sadrian /* Calibration related fields */ 450250003Sadrian HAL_CAL_TYPES ah_supp_cals; 451250003Sadrian HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */ 452250003Sadrian HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */ 453250003Sadrian HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */ 454250003Sadrian HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */ 455250003Sadrian HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */ 456250003Sadrian// IQ Cal aliases 457250003Sadrian#define ah_total_power_meas_i ah_meas0.unsign 458250003Sadrian#define ah_total_power_meas_q ah_meas1.unsign 459250003Sadrian#define ah_total_iq_corr_meas ah_meas2.sign 460250003Sadrian union { 461250003Sadrian u_int32_t unsign[AR9300_MAX_CHAINS]; 462250003Sadrian int32_t sign[AR9300_MAX_CHAINS]; 463250003Sadrian } ah_meas0; 464250003Sadrian union { 465250003Sadrian u_int32_t unsign[AR9300_MAX_CHAINS]; 466250003Sadrian int32_t sign[AR9300_MAX_CHAINS]; 467250003Sadrian } ah_meas1; 468250003Sadrian union { 469250003Sadrian u_int32_t unsign[AR9300_MAX_CHAINS]; 470250003Sadrian int32_t sign[AR9300_MAX_CHAINS]; 471250003Sadrian } ah_meas2; 472250003Sadrian union { 473250003Sadrian u_int32_t unsign[AR9300_MAX_CHAINS]; 474250003Sadrian int32_t sign[AR9300_MAX_CHAINS]; 475250003Sadrian } ah_meas3; 476250003Sadrian u_int16_t ah_cal_samples; 477250003Sadrian /* end - Calibration related fields */ 478250003Sadrian u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */ 479250003Sadrian u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */ 480250003Sadrian u_int32_t ah_misc_mode; /* MISC_MODE settings */ 481250003Sadrian HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */ 482250003Sadrian enum { 483250003Sadrian AUTO_32KHZ, /* use it if 32kHz crystal present */ 484250003Sadrian USE_32KHZ, /* do it regardless */ 485250003Sadrian DONT_USE_32KHZ, /* don't use it regardless */ 486250003Sadrian } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */ 487250003Sadrian 488250003Sadrian u_int32_t ah_ofdm_tx_power; 489250003Sadrian int16_t ah_tx_power_index_offset; 490250003Sadrian 491250003Sadrian u_int ah_slot_time; /* user-specified slot time */ 492250003Sadrian u_int ah_ack_timeout; /* user-specified ack timeout */ 493250003Sadrian /* 494250003Sadrian * XXX 495250003Sadrian * 11g-specific stuff; belongs in the driver. 496250003Sadrian */ 497250003Sadrian u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */ 498250003Sadrian u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */ 499250003Sadrian u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */ 500250003Sadrian /* 501250003Sadrian * RF Silent handling; setup according to the EEPROM. 502250003Sadrian */ 503250003Sadrian u_int32_t ah_gpio_select; /* GPIO pin to use */ 504250003Sadrian u_int32_t ah_polarity; /* polarity to disable RF */ 505250003Sadrian u_int32_t ah_gpio_bit; /* after init, prev value */ 506250003Sadrian HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */ 507250003Sadrian 508250003Sadrian#ifdef ATH_BT_COEX 509250003Sadrian /* 510250003Sadrian * Bluetooth coexistence static setup according to the registry 511250003Sadrian */ 512250003Sadrian HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */ 513250003Sadrian u_int8_t ah_bt_coex_config_type; /* BT coex configuration */ 514250003Sadrian u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */ 515250003Sadrian u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */ 516250003Sadrian u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */ 517250003Sadrian u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */ 518250003Sadrian HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */ 519250003Sadrian u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */ 520250003Sadrian /* 521250003Sadrian * Bluetooth coexistence runtime settings 522250003Sadrian */ 523250003Sadrian HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */ 524250003Sadrian u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ 525250003Sadrian u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 526250003Sadrian u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 527250003Sadrian u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ 528250003Sadrian u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */ 529250003Sadrian#endif 530250003Sadrian 531250003Sadrian /* 532250003Sadrian * Generic timer support 533250003Sadrian */ 534250003Sadrian u_int32_t ah_avail_gen_timers; /* mask of available timers */ 535250003Sadrian u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */ 536250003Sadrian u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */ 537250003Sadrian HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */ 538250003Sadrian 539250003Sadrian /* 540250003Sadrian * ANI & Radar support. 541250003Sadrian */ 542250003Sadrian u_int32_t ah_proc_phy_err; /* Process Phy errs */ 543250003Sadrian u_int32_t ah_ani_period; /* ani update list period */ 544250003Sadrian struct ar9300_ani_state *ah_curani; /* cached last reference */ 545250003Sadrian struct ar9300_ani_state ah_ani[255]; /* per-channel state */ 546250003Sadrian struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */ 547250003Sadrian struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */ 548250003Sadrian struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */ 549250003Sadrian struct ar9300_ar_state ah_ar; /* AR detector state */ 550250003Sadrian struct ar9300_radar_q_elem *ah_arq; /* AR event queue */ 551250003Sadrian struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */ 552250003Sadrian 553250003Sadrian /* 554250003Sadrian * Transmit power state. Note these are maintained 555250003Sadrian * here so they can be retrieved by diagnostic tools. 556250003Sadrian */ 557250003Sadrian u_int16_t ah_rates_array[16]; 558250003Sadrian 559250003Sadrian /* 560250003Sadrian * Tx queue interrupt state. 561250003Sadrian */ 562250003Sadrian u_int32_t ah_intr_txqs; 563250003Sadrian 564250003Sadrian HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */ 565250003Sadrian HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */ 566250003Sadrian 567250003Sadrian /* 568250003Sadrian * Extension Channel Rx Clear State 569250003Sadrian */ 570250003Sadrian u_int32_t ah_cycle_count; 571250003Sadrian u_int32_t ah_ctl_busy; 572250003Sadrian u_int32_t ah_ext_busy; 573250003Sadrian 574250003Sadrian /* HT CWM state */ 575250003Sadrian HAL_HT_EXTPROTSPACING ah_ext_prot_spacing; 576250003Sadrian u_int8_t ah_tx_chainmask; /* tx chain mask */ 577250003Sadrian u_int8_t ah_rx_chainmask; /* rx chain mask */ 578250003Sadrian 579250003Sadrian u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */ 580250003Sadrian u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */ 581250003Sadrian 582250003Sadrian int ah_hwp; 583250003Sadrian void *ah_cal_mem; 584250003Sadrian HAL_BOOL ah_emu_eeprom; 585250003Sadrian 586250003Sadrian HAL_ANI_CMD ah_ani_function; 587250003Sadrian HAL_BOOL ah_rifs_enabled; 588250003Sadrian u_int32_t ah_rifs_reg[11]; 589250003Sadrian u_int32_t ah_rifs_sec_cnt; 590250003Sadrian 591250003Sadrian /* open-loop power control */ 592250003Sadrian u_int32_t original_gain[22]; 593250003Sadrian int32_t init_pdadc; 594250003Sadrian int32_t pdadc_delta; 595250003Sadrian 596250003Sadrian /* cycle counts for beacon stuck diagnostics */ 597250003Sadrian u_int32_t ah_cycles; 598250003Sadrian u_int32_t ah_rx_clear; 599250003Sadrian u_int32_t ah_rx_frame; 600250003Sadrian u_int32_t ah_tx_frame; 601250003Sadrian 602250003Sadrian#define BB_HANG_SIG1 0 603250003Sadrian#define BB_HANG_SIG2 1 604250003Sadrian#define BB_HANG_SIG3 2 605250003Sadrian#define BB_HANG_SIG4 3 606250003Sadrian#define MAC_HANG_SIG1 4 607250003Sadrian#define MAC_HANG_SIG2 5 608250003Sadrian /* bb hang detection */ 609250003Sadrian int ah_hang[6]; 610250003Sadrian hal_hw_hangs_t ah_hang_wars; 611250008Sadrian 612250003Sadrian /* 613250008Sadrian * Keytable type table 614250008Sadrian */ 615250008Sadrian#define AR_KEYTABLE_SIZE 128 /* XXX! */ 616250008Sadrian uint8_t ah_keytype[AR_KEYTABLE_SIZE]; 617250008Sadrian#undef AR_KEYTABLE_SIZE 618250008Sadrian /* 619250003Sadrian * Support for ar9300 multiple INIs 620250003Sadrian */ 621250003Sadrian struct ar9300_ini_array ah_ini_pcie_serdes; 622250003Sadrian struct ar9300_ini_array ah_ini_pcie_serdes_low_power; 623250003Sadrian struct ar9300_ini_array ah_ini_modes_additional; 624250003Sadrian struct ar9300_ini_array ah_ini_modes_additional_40mhz; 625250003Sadrian struct ar9300_ini_array ah_ini_modes_rxgain; 626250003Sadrian struct ar9300_ini_array ah_ini_modes_rxgain_bounds; 627250003Sadrian struct ar9300_ini_array ah_ini_modes_txgain; 628250003Sadrian struct ar9300_ini_array ah_ini_japan2484; 629250003Sadrian struct ar9300_ini_array ah_ini_radio_post_sys2ant; 630250003Sadrian struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR; 631250003Sadrian /* 632250003Sadrian * New INI format starting with Osprey 2.0 INI. 633250003Sadrian * Pre, core, post arrays for each sub-system (mac, bb, radio, soc) 634250003Sadrian */ 635250003Sadrian #define ATH_INI_PRE 0 636250003Sadrian #define ATH_INI_CORE 1 637250003Sadrian #define ATH_INI_POST 2 638250003Sadrian #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1) 639250003Sadrian struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */ 640250003Sadrian struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */ 641250003Sadrian struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */ 642250003Sadrian struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */ 643250003Sadrian 644250003Sadrian /* 645250003Sadrian * Added to support DFS postamble array in INI that we need to apply 646250003Sadrian * in DFS channels 647250003Sadrian */ 648250003Sadrian 649250003Sadrian struct ar9300_ini_array ah_ini_dfs; 650250003Sadrian 651250003Sadrian#if ATH_WOW 652250003Sadrian struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */ 653250003Sadrian#endif 654250003Sadrian 655250003Sadrian /* To indicate EEPROM mapping used */ 656250003Sadrian u_int32_t ah_immunity_vals[6]; 657250003Sadrian HAL_BOOL ah_immunity_on; 658250003Sadrian /* 659250003Sadrian * snap shot of counter register for debug purposes 660250003Sadrian */ 661250003Sadrian#ifdef AH_DEBUG 662250003Sadrian u_int32_t last_tf; 663250003Sadrian u_int32_t last_rf; 664250003Sadrian u_int32_t last_rc; 665250003Sadrian u_int32_t last_cc; 666250003Sadrian#endif 667250003Sadrian HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */ 668250003Sadrian u_int32_t nf_tsf32; /* timestamp for NF calibration duration */ 669250003Sadrian 670250003Sadrian u_int32_t reg_dmn; /* Regulatory Domain */ 671250003Sadrian int16_t twice_antenna_gain; /* Antenna Gain */ 672250003Sadrian u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */ 673250003Sadrian 674250003Sadrian /* 675250003Sadrian * Upper limit after factoring in the regulatory max, antenna gain and 676250003Sadrian * multichain factor. No TxBF, CDD or STBC gain factored 677250003Sadrian */ 678250003Sadrian int16_t upper_limit[AR9300_MAX_CHAINS]; 679250003Sadrian 680250003Sadrian /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ 681250003Sadrian int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 682250003Sadrian 683250003Sadrian /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ 684250003Sadrian int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 685250003Sadrian 686250003Sadrian /* Transmit Status ring support */ 687250003Sadrian struct ar9300_txs *ts_ring; 688250003Sadrian u_int16_t ts_tail; 689250003Sadrian u_int16_t ts_size; 690250003Sadrian u_int32_t ts_paddr_start; 691250003Sadrian u_int32_t ts_paddr_end; 692250003Sadrian 693250003Sadrian /* Receive Buffer size */ 694250003Sadrian#define HAL_RXBUFSIZE_DEFAULT 0xfff 695250003Sadrian u_int16_t rx_buf_size; 696250003Sadrian 697250003Sadrian u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states). 698250003Sadrian 699250003Sadrian /* Indicate the PLL source clock rate is 25Mhz or not. 700250003Sadrian * clk_25mhz = 0 by default. 701250003Sadrian */ 702250003Sadrian u_int8_t clk_25mhz; 703250003Sadrian /* For PAPRD uses */ 704250003Sadrian u_int16_t small_signal_gain[AH_MAX_CHAINS]; 705250003Sadrian u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ]; 706250003Sadrian u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ]; 707250003Sadrian u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ]; 708250003Sadrian u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */ 709250003Sadrian u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */ 710250003Sadrian u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */ 711250003Sadrian u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */ 712250003Sadrian u_int32_t paprd_training_power; 713250003Sadrian /* For GreenTx use to store the default tx power */ 714250003Sadrian u_int8_t ah_default_tx_power[ar9300_rate_size]; 715250003Sadrian HAL_BOOL ah_paprd_broken; 716250003Sadrian 717250003Sadrian /* To store offsets of host interface registers */ 718250003Sadrian struct { 719250003Sadrian u_int32_t AR_RC; 720250003Sadrian u_int32_t AR_WA; 721250003Sadrian u_int32_t AR_PM_STATE; 722250003Sadrian u_int32_t AR_H_INFOL; 723250003Sadrian u_int32_t AR_H_INFOH; 724250003Sadrian u_int32_t AR_PCIE_PM_CTRL; 725250003Sadrian u_int32_t AR_HOST_TIMEOUT; 726250003Sadrian u_int32_t AR_EEPROM; 727250003Sadrian u_int32_t AR_SREV; 728250003Sadrian u_int32_t AR_INTR_SYNC_CAUSE; 729250003Sadrian u_int32_t AR_INTR_SYNC_CAUSE_CLR; 730250003Sadrian u_int32_t AR_INTR_SYNC_ENABLE; 731250003Sadrian u_int32_t AR_INTR_ASYNC_MASK; 732250003Sadrian u_int32_t AR_INTR_SYNC_MASK; 733250003Sadrian u_int32_t AR_INTR_ASYNC_CAUSE_CLR; 734250003Sadrian u_int32_t AR_INTR_ASYNC_CAUSE; 735250003Sadrian u_int32_t AR_INTR_ASYNC_ENABLE; 736250003Sadrian u_int32_t AR_PCIE_SERDES; 737250003Sadrian u_int32_t AR_PCIE_SERDES2; 738250003Sadrian u_int32_t AR_GPIO_OUT; 739250003Sadrian u_int32_t AR_GPIO_IN; 740250003Sadrian u_int32_t AR_GPIO_OE_OUT; 741250003Sadrian u_int32_t AR_GPIO_OE1_OUT; 742250003Sadrian u_int32_t AR_GPIO_INTR_POL; 743250003Sadrian u_int32_t AR_GPIO_INPUT_EN_VAL; 744250003Sadrian u_int32_t AR_GPIO_INPUT_MUX1; 745250003Sadrian u_int32_t AR_GPIO_INPUT_MUX2; 746250003Sadrian u_int32_t AR_GPIO_OUTPUT_MUX1; 747250003Sadrian u_int32_t AR_GPIO_OUTPUT_MUX2; 748250003Sadrian u_int32_t AR_GPIO_OUTPUT_MUX3; 749250003Sadrian u_int32_t AR_INPUT_STATE; 750250003Sadrian u_int32_t AR_SPARE; 751250003Sadrian u_int32_t AR_PCIE_CORE_RESET_EN; 752250003Sadrian u_int32_t AR_CLKRUN; 753250003Sadrian u_int32_t AR_EEPROM_STATUS_DATA; 754250003Sadrian u_int32_t AR_OBS; 755250003Sadrian u_int32_t AR_RFSILENT; 756250003Sadrian u_int32_t AR_GPIO_PDPU; 757250003Sadrian u_int32_t AR_GPIO_DS; 758250003Sadrian u_int32_t AR_MISC; 759250003Sadrian u_int32_t AR_PCIE_MSI; 760250003Sadrian u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE; 761250003Sadrian u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY; 762250003Sadrian u_int32_t AR_TSF_SNAPSHOT_BT_CNTL; 763250003Sadrian u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ; 764250003Sadrian u_int32_t AR_TDMA_CCA_CNTL; 765250003Sadrian u_int32_t AR_TXAPSYNC; 766250003Sadrian u_int32_t AR_TXSYNC_INIT_SYNC_TMR; 767250003Sadrian u_int32_t AR_INTR_PRIO_SYNC_CAUSE; 768250003Sadrian u_int32_t AR_INTR_PRIO_SYNC_ENABLE; 769250003Sadrian u_int32_t AR_INTR_PRIO_ASYNC_MASK; 770250003Sadrian u_int32_t AR_INTR_PRIO_SYNC_MASK; 771250003Sadrian u_int32_t AR_INTR_PRIO_ASYNC_CAUSE; 772250003Sadrian u_int32_t AR_INTR_PRIO_ASYNC_ENABLE; 773250003Sadrian } ah_hostifregs; 774250003Sadrian 775250003Sadrian u_int32_t ah_enterprise_mode; 776250003Sadrian u_int32_t ah_radar1; 777250003Sadrian u_int32_t ah_dc_offset; 778250003Sadrian HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */ 779250003Sadrian HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */ 780250003Sadrian u_int32_t ah_disable_cck; 781250003Sadrian HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */ 782250003Sadrian 783250003Sadrian 784250003Sadrian /* 785250003Sadrian * Different types of memory where the calibration data might be stored. 786250003Sadrian * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp. 787250003Sadrian * To disable searching a type, set its parameter to 0. 788250003Sadrian */ 789250003Sadrian int try_dram; 790250003Sadrian int try_flash; 791250003Sadrian int try_eeprom; 792250003Sadrian int try_otp; 793250003Sadrian#ifdef ATH_CAL_NAND_FLASH 794250003Sadrian int try_nand; 795250003Sadrian#endif 796250003Sadrian /* 797250003Sadrian * This is where we found the calibration data. 798250003Sadrian */ 799250003Sadrian int calibration_data_source; 800250003Sadrian int calibration_data_source_address; 801250003Sadrian /* 802250003Sadrian * This is where we look for the calibration data. must be set before ath_attach() is called 803250003Sadrian */ 804250003Sadrian int calibration_data_try; 805250003Sadrian int calibration_data_try_address; 806250003Sadrian u_int8_t 807250003Sadrian tx_iq_cal_enable : 1, 808250003Sadrian tx_iq_cal_during_agc_cal : 1, 809250003Sadrian tx_cl_cal_enable : 1; 810250003Sadrian 811250003Sadrian#if ATH_SUPPORT_MCI 812250003Sadrian /* For MCI */ 813250003Sadrian HAL_BOOL ah_mci_ready; 814250003Sadrian u_int32_t ah_mci_int_raw; 815250003Sadrian u_int32_t ah_mci_int_rx_msg; 816250003Sadrian u_int32_t ah_mci_rx_status; 817250003Sadrian u_int32_t ah_mci_cont_status; 818250003Sadrian u_int8_t ah_mci_bt_state; 819250003Sadrian u_int32_t ah_mci_gpm_addr; 820250003Sadrian u_int8_t *ah_mci_gpm_buf; 821250003Sadrian u_int32_t ah_mci_gpm_len; 822250003Sadrian u_int32_t ah_mci_gpm_idx; 823250003Sadrian u_int32_t ah_mci_sched_addr; 824250003Sadrian u_int8_t *ah_mci_sched_buf; 825250003Sadrian u_int8_t ah_mci_coex_major_version_wlan; 826250003Sadrian u_int8_t ah_mci_coex_minor_version_wlan; 827250003Sadrian u_int8_t ah_mci_coex_major_version_bt; 828250003Sadrian u_int8_t ah_mci_coex_minor_version_bt; 829250003Sadrian HAL_BOOL ah_mci_coex_bt_version_known; 830250003Sadrian HAL_BOOL ah_mci_coex_wlan_channels_update; 831250003Sadrian u_int32_t ah_mci_coex_wlan_channels[4]; 832250003Sadrian HAL_BOOL ah_mci_coex_2g5g_update; 833250003Sadrian HAL_BOOL ah_mci_coex_is_2g; 834250003Sadrian HAL_BOOL ah_mci_query_bt; 835250003Sadrian HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */ 836250003Sadrian HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */ 837250003Sadrian HAL_BOOL ah_mci_need_flush_btinfo; 838250003Sadrian HAL_BOOL ah_mci_concur_tx_en; 839250003Sadrian u_int8_t ah_mci_stomp_low_tx_pri; 840250003Sadrian u_int8_t ah_mci_stomp_all_tx_pri; 841250003Sadrian u_int8_t ah_mci_stomp_none_tx_pri; 842250003Sadrian u_int32_t ah_mci_wlan_cal_seq; 843250003Sadrian u_int32_t ah_mci_wlan_cal_done; 844250003Sadrian#if ATH_SUPPORT_AIC 845250003Sadrian HAL_BOOL ah_aic_enabled; 846250003Sadrian u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL]; 847250003Sadrian#endif 848250003Sadrian#endif /* ATH_SUPPORT_MCI */ 849250003Sadrian u_int8_t ah_cac_quiet_enabled; 850250003Sadrian#if ATH_WOW_OFFLOAD 851250003Sadrian u_int32_t ah_mcast_filter_l32_set; 852250003Sadrian u_int32_t ah_mcast_filter_u32_set; 853250003Sadrian#endif 854250008Sadrian HAL_BOOL ah_reduced_self_gen_mask; 855250008Sadrian 856250008Sadrian /* Local additions for FreeBSD */ 857250008Sadrian /* 858250008Sadrian * These fields are in the top level HAL in the atheros 859250008Sadrian * codebase; here we place them in the AR9300 HAL and 860250008Sadrian * access them via accessor methods if the driver requires them. 861250008Sadrian */ 862250008Sadrian u_int32_t ah_ob_db1[3]; 863250008Sadrian u_int32_t ah_db2[3]; 864250008Sadrian u_int32_t ah_bb_panic_timeout_ms; 865250008Sadrian u_int32_t ah_bb_panic_last_status; 866250008Sadrian u_int32_t ah_tx_trig_level; 867250008Sadrian u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2]; 868250008Sadrian int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW interf threshold */ 869250008Sadrian int ah_phyrestart_disabled; 870250008Sadrian HAL_RSSI_TX_POWER green_tx_status; 871250008Sadrian int green_ap_ps_on; 872250008Sadrian int ah_enable_keysearch_always; 873250008Sadrian int ah_fccaifs; 874250008Sadrian int ah_reset_reason; 875250008Sadrian int ah_dcs_enable; 876250008Sadrian 877250008Sadrian struct ar9300NfLimits nf_2GHz; 878250008Sadrian struct ar9300NfLimits nf_5GHz; 879250008Sadrian struct ar9300NfLimits *nfp; 880250008Sadrian 881250003Sadrian}; 882250003Sadrian 883250003Sadrian#define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) 884250003Sadrian 885250003Sadrian#define IS_9300_EMU(ah) \ 886250003Sadrian (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE) 887250003Sadrian 888250003Sadrian#define ar9300_eep_data_in_flash(_ah) \ 889250003Sadrian (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) 890250003Sadrian 891250008Sadrian#ifdef notyet 892250003Sadrian// Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. 893250003Sadrian&& \ 894250003Sadrian ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ 895250003Sadrian (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G)))) 896250003Sadrian#endif 897250003Sadrian 898250003Sadrian/* 899250003Sadrian * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows 900250003Sadrian * other cards' DMA reads to complete in the middle of our reset. 901250003Sadrian */ 902250003Sadrian#define WAR_6773(x) do { \ 903250003Sadrian if ((++(x) % 64) == 0) \ 904250003Sadrian OS_DELAY(1); \ 905250003Sadrian} while (0) 906250003Sadrian 907250003Sadrian#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 908250003Sadrian int r; \ 909250003Sadrian for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 910250003Sadrian OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\ 911250003Sadrian WAR_6773(regWr); \ 912250003Sadrian } \ 913250003Sadrian} while (0) 914250003Sadrian 915250003Sadrian#define UPPER_5G_SUB_BANDSTART 5700 916250003Sadrian#define MID_5G_SUB_BANDSTART 5400 917250003Sadrian#define TRAINPOWER_DB_OFFSET 6 918250003Sadrian 919250003Sadrian#define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \ 920250003Sadrian } else { \ 921250003Sadrian if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \ 922250003Sadrian else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \ 923250003Sadrian { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \ 924250003Sadrian else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0) 925250003Sadrian 926250003Sadrian#ifdef AH_ASSERT 927250003Sadrian #define ar9300FeatureNotSupported(feature, ah, func) \ 928250003Sadrian ath_hal_printf(ah, # feature \ 929250003Sadrian " not supported but called from %s\n", (func)), \ 930250003Sadrian hal_assert(0) 931250003Sadrian#else 932250003Sadrian #define ar9300FeatureNotSupported(feature, ah, func) \ 933250003Sadrian ath_hal_printf(ah, # feature \ 934250003Sadrian " not supported but called from %s\n", (func)) 935250003Sadrian#endif /* AH_ASSERT */ 936250003Sadrian 937250003Sadrian/* 938250003Sadrian * Green Tx, Based on different RSSI of Received Beacon thresholds, 939250003Sadrian * using different tx power by modified register tx power related values. 940250003Sadrian * The thresholds are decided by system team. 941250003Sadrian */ 942250003Sadrian#define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */ 943250003Sadrian#define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */ 944250003Sadrian#define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta 945250003Sadrian Calibration Offset */ 946250003Sadrian#define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value 947250003Sadrian in short distance*/ 948250003Sadrian#define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value 949250003Sadrian in middle distance */ 950250003Sadrian#define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value 951250003Sadrian in long distance */ 952250003Sadrian#define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen Tx 953250003Sadrian BB_powertx_rate9 reg 954250003Sadrian value in short 955250003Sadrian distance */ 956250003Sadrian#define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen Tx 957250003Sadrian BB_powertx_rate9 reg 958250003Sadrian value in middle 959250003Sadrian distance */ 960250003Sadrian 961250003Sadrian 962250003Sadrian/* Tx power for short distacnce in SwGreenTx.*/ 963250003Sadrianstatic const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = { 964250003Sadrian 6, /*ALL_TARGET_LEGACY_6_24*/ 965250003Sadrian 6, /*ALL_TARGET_LEGACY_36*/ 966250003Sadrian 6, /*ALL_TARGET_LEGACY_48*/ 967250003Sadrian 4, /*ALL_TARGET_LEGACY_54*/ 968250003Sadrian 6, /*ALL_TARGET_LEGACY_1L_5L*/ 969250003Sadrian 6, /*ALL_TARGET_LEGACY_5S*/ 970250003Sadrian 6, /*ALL_TARGET_LEGACY_11L*/ 971250003Sadrian 6, /*ALL_TARGET_LEGACY_11S*/ 972250003Sadrian 6, /*ALL_TARGET_HT20_0_8_16*/ 973250003Sadrian 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 974250003Sadrian 4, /*ALL_TARGET_HT20_4*/ 975250003Sadrian 4, /*ALL_TARGET_HT20_5*/ 976250003Sadrian 4, /*ALL_TARGET_HT20_6*/ 977250003Sadrian 2, /*ALL_TARGET_HT20_7*/ 978250003Sadrian 0, /*ALL_TARGET_HT20_12*/ 979250003Sadrian 0, /*ALL_TARGET_HT20_13*/ 980250003Sadrian 0, /*ALL_TARGET_HT20_14*/ 981250003Sadrian 0, /*ALL_TARGET_HT20_15*/ 982250003Sadrian 0, /*ALL_TARGET_HT20_20*/ 983250003Sadrian 0, /*ALL_TARGET_HT20_21*/ 984250003Sadrian 0, /*ALL_TARGET_HT20_22*/ 985250003Sadrian 0, /*ALL_TARGET_HT20_23*/ 986250003Sadrian 6, /*ALL_TARGET_HT40_0_8_16*/ 987250003Sadrian 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 988250003Sadrian 4, /*ALL_TARGET_HT40_4*/ 989250003Sadrian 4, /*ALL_TARGET_HT40_5*/ 990250003Sadrian 4, /*ALL_TARGET_HT40_6*/ 991250003Sadrian 2, /*ALL_TARGET_HT40_7*/ 992250003Sadrian 0, /*ALL_TARGET_HT40_12*/ 993250003Sadrian 0, /*ALL_TARGET_HT40_13*/ 994250003Sadrian 0, /*ALL_TARGET_HT40_14*/ 995250003Sadrian 0, /*ALL_TARGET_HT40_15*/ 996250003Sadrian 0, /*ALL_TARGET_HT40_20*/ 997250003Sadrian 0, /*ALL_TARGET_HT40_21*/ 998250003Sadrian 0, /*ALL_TARGET_HT40_22*/ 999250003Sadrian 0 /*ALL_TARGET_HT40_23*/ 1000250003Sadrian}; 1001250003Sadrian 1002250003Sadrian/* Tx power for middle distacnce in SwGreenTx.*/ 1003250003Sadrianstatic const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = { 1004250003Sadrian 14, /*ALL_TARGET_LEGACY_6_24*/ 1005250003Sadrian 14, /*ALL_TARGET_LEGACY_36*/ 1006250003Sadrian 14, /*ALL_TARGET_LEGACY_48*/ 1007250003Sadrian 12, /*ALL_TARGET_LEGACY_54*/ 1008250003Sadrian 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1009250003Sadrian 14, /*ALL_TARGET_LEGACY_5S*/ 1010250003Sadrian 14, /*ALL_TARGET_LEGACY_11L*/ 1011250003Sadrian 14, /*ALL_TARGET_LEGACY_11S*/ 1012250003Sadrian 14, /*ALL_TARGET_HT20_0_8_16*/ 1013250003Sadrian 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1014250003Sadrian 14, /*ALL_TARGET_HT20_4*/ 1015250003Sadrian 14, /*ALL_TARGET_HT20_5*/ 1016250003Sadrian 12, /*ALL_TARGET_HT20_6*/ 1017250003Sadrian 10, /*ALL_TARGET_HT20_7*/ 1018250003Sadrian 0, /*ALL_TARGET_HT20_12*/ 1019250003Sadrian 0, /*ALL_TARGET_HT20_13*/ 1020250003Sadrian 0, /*ALL_TARGET_HT20_14*/ 1021250003Sadrian 0, /*ALL_TARGET_HT20_15*/ 1022250003Sadrian 0, /*ALL_TARGET_HT20_20*/ 1023250003Sadrian 0, /*ALL_TARGET_HT20_21*/ 1024250003Sadrian 0, /*ALL_TARGET_HT20_22*/ 1025250003Sadrian 0, /*ALL_TARGET_HT20_23*/ 1026250003Sadrian 14, /*ALL_TARGET_HT40_0_8_16*/ 1027250003Sadrian 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1028250003Sadrian 14, /*ALL_TARGET_HT40_4*/ 1029250003Sadrian 14, /*ALL_TARGET_HT40_5*/ 1030250003Sadrian 12, /*ALL_TARGET_HT40_6*/ 1031250003Sadrian 10, /*ALL_TARGET_HT40_7*/ 1032250003Sadrian 0, /*ALL_TARGET_HT40_12*/ 1033250003Sadrian 0, /*ALL_TARGET_HT40_13*/ 1034250003Sadrian 0, /*ALL_TARGET_HT40_14*/ 1035250003Sadrian 0, /*ALL_TARGET_HT40_15*/ 1036250003Sadrian 0, /*ALL_TARGET_HT40_20*/ 1037250003Sadrian 0, /*ALL_TARGET_HT40_21*/ 1038250003Sadrian 0, /*ALL_TARGET_HT40_22*/ 1039250003Sadrian 0 /*ALL_TARGET_HT40_23*/ 1040250003Sadrian}; 1041250003Sadrian 1042250003Sadrian/* OLPC DeltaCalibration Offset unit in half dB.*/ 1043250003Sadrianstatic const u_int8_t wb225_gtx_olpc_cal_offset[6] = { 1044250003Sadrian 0, /* OB0*/ 1045250003Sadrian 16, /* OB1*/ 1046250003Sadrian 9, /* OB2*/ 1047250003Sadrian 5, /* OB3*/ 1048250003Sadrian 2, /* OB4*/ 1049250003Sadrian 0, /* OB5*/ 1050250003Sadrian}; 1051250003Sadrian 1052250003Sadrian/* 1053250003Sadrian * Definitions for HwGreenTx 1054250003Sadrian */ 1055250003Sadrian#define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */ 1056250003Sadrian#define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */ 1057250003Sadrian#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen Tx 1058250003Sadrian BB_powertx_rate9 reg 1059250003Sadrian value in short 1060250003Sadrian distance */ 1061250003Sadrian#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For HwGreenTx 1062250003Sadrian BB_powertx_rate9 reg 1063250003Sadrian value in middle 1064250003Sadrian distance */ 1065250003Sadrian 1066250003Sadrian/* Tx power for short distacnce in HwGreenTx.*/ 1067250003Sadrianstatic const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = { 1068250003Sadrian 14, /*ALL_TARGET_LEGACY_6_24*/ 1069250003Sadrian 14, /*ALL_TARGET_LEGACY_36*/ 1070250003Sadrian 8, /*ALL_TARGET_LEGACY_48*/ 1071250003Sadrian 2, /*ALL_TARGET_LEGACY_54*/ 1072250003Sadrian 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1073250003Sadrian 14, /*ALL_TARGET_LEGACY_5S*/ 1074250003Sadrian 14, /*ALL_TARGET_LEGACY_11L*/ 1075250003Sadrian 14, /*ALL_TARGET_LEGACY_11S*/ 1076250003Sadrian 12, /*ALL_TARGET_HT20_0_8_16*/ 1077250003Sadrian 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1078250003Sadrian 12, /*ALL_TARGET_HT20_4*/ 1079250003Sadrian 12, /*ALL_TARGET_HT20_5*/ 1080250003Sadrian 8, /*ALL_TARGET_HT20_6*/ 1081250003Sadrian 2, /*ALL_TARGET_HT20_7*/ 1082250003Sadrian 0, /*ALL_TARGET_HT20_12*/ 1083250003Sadrian 0, /*ALL_TARGET_HT20_13*/ 1084250003Sadrian 0, /*ALL_TARGET_HT20_14*/ 1085250003Sadrian 0, /*ALL_TARGET_HT20_15*/ 1086250003Sadrian 0, /*ALL_TARGET_HT20_20*/ 1087250003Sadrian 0, /*ALL_TARGET_HT20_21*/ 1088250003Sadrian 0, /*ALL_TARGET_HT20_22*/ 1089250003Sadrian 0, /*ALL_TARGET_HT20_23*/ 1090250003Sadrian 10, /*ALL_TARGET_HT40_0_8_16*/ 1091250003Sadrian 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1092250003Sadrian 10, /*ALL_TARGET_HT40_4*/ 1093250003Sadrian 10, /*ALL_TARGET_HT40_5*/ 1094250003Sadrian 6, /*ALL_TARGET_HT40_6*/ 1095250003Sadrian 2, /*ALL_TARGET_HT40_7*/ 1096250003Sadrian 0, /*ALL_TARGET_HT40_12*/ 1097250003Sadrian 0, /*ALL_TARGET_HT40_13*/ 1098250003Sadrian 0, /*ALL_TARGET_HT40_14*/ 1099250003Sadrian 0, /*ALL_TARGET_HT40_15*/ 1100250003Sadrian 0, /*ALL_TARGET_HT40_20*/ 1101250003Sadrian 0, /*ALL_TARGET_HT40_21*/ 1102250003Sadrian 0, /*ALL_TARGET_HT40_22*/ 1103250003Sadrian 0 /*ALL_TARGET_HT40_23*/ 1104250003Sadrian}; 1105250003Sadrian 1106250003Sadrian/* Tx power for middle distacnce in HwGreenTx.*/ 1107250003Sadrianstatic const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = { 1108250003Sadrian 18, /*ALL_TARGET_LEGACY_6_24*/ 1109250003Sadrian 18, /*ALL_TARGET_LEGACY_36*/ 1110250003Sadrian 14, /*ALL_TARGET_LEGACY_48*/ 1111250003Sadrian 12, /*ALL_TARGET_LEGACY_54*/ 1112250003Sadrian 18, /*ALL_TARGET_LEGACY_1L_5L*/ 1113250003Sadrian 18, /*ALL_TARGET_LEGACY_5S*/ 1114250003Sadrian 18, /*ALL_TARGET_LEGACY_11L*/ 1115250003Sadrian 18, /*ALL_TARGET_LEGACY_11S*/ 1116250003Sadrian 16, /*ALL_TARGET_HT20_0_8_16*/ 1117250003Sadrian 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1118250003Sadrian 16, /*ALL_TARGET_HT20_4*/ 1119250003Sadrian 16, /*ALL_TARGET_HT20_5*/ 1120250003Sadrian 14, /*ALL_TARGET_HT20_6*/ 1121250003Sadrian 12, /*ALL_TARGET_HT20_7*/ 1122250003Sadrian 0, /*ALL_TARGET_HT20_12*/ 1123250003Sadrian 0, /*ALL_TARGET_HT20_13*/ 1124250003Sadrian 0, /*ALL_TARGET_HT20_14*/ 1125250003Sadrian 0, /*ALL_TARGET_HT20_15*/ 1126250003Sadrian 0, /*ALL_TARGET_HT20_20*/ 1127250003Sadrian 0, /*ALL_TARGET_HT20_21*/ 1128250003Sadrian 0, /*ALL_TARGET_HT20_22*/ 1129250003Sadrian 0, /*ALL_TARGET_HT20_23*/ 1130250003Sadrian 14, /*ALL_TARGET_HT40_0_8_16*/ 1131250003Sadrian 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1132250003Sadrian 14, /*ALL_TARGET_HT40_4*/ 1133250003Sadrian 14, /*ALL_TARGET_HT40_5*/ 1134250003Sadrian 14, /*ALL_TARGET_HT40_6*/ 1135250003Sadrian 12, /*ALL_TARGET_HT40_7*/ 1136250003Sadrian 0, /*ALL_TARGET_HT40_12*/ 1137250003Sadrian 0, /*ALL_TARGET_HT40_13*/ 1138250003Sadrian 0, /*ALL_TARGET_HT40_14*/ 1139250003Sadrian 0, /*ALL_TARGET_HT40_15*/ 1140250003Sadrian 0, /*ALL_TARGET_HT40_20*/ 1141250003Sadrian 0, /*ALL_TARGET_HT40_21*/ 1142250003Sadrian 0, /*ALL_TARGET_HT40_22*/ 1143250003Sadrian 0 /*ALL_TARGET_HT40_23*/ 1144250003Sadrian}; 1145250003Sadrian 1146250003Sadrian/* MIMO Modes used in TPC calculations */ 1147250003Sadriantypedef enum { 1148250003Sadrian AR9300_DEF_MODE = 0, /* Could be CDD or Direct */ 1149250003Sadrian AR9300_TXBF_MODE, 1150250003Sadrian AR9300_STBC_MODE 1151250003Sadrian} AR9300_TXMODES; 1152250003Sadriantypedef enum { 1153250003Sadrian POSEIDON_STORED_REG_OBDB = 0, /* default OB/DB setting from ini */ 1154250003Sadrian POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */ 1155250003Sadrian POSEIDON_STORED_REG_BB_PWRTX_RATE9 = 2, /* default txpower value in 1156250003Sadrian * BB_powertx_rate9 reg 1157250003Sadrian */ 1158250003Sadrian POSEIDON_STORED_REG_SZ /* Can not add anymore */ 1159250003Sadrian} POSEIDON_STORED_REGS; 1160250003Sadrian 1161250003Sadriantypedef enum { 1162250003Sadrian POSEIDON_STORED_REG_G2_OLPC_OFFSET = 0,/* default OB/DB setting from ini */ 1163250003Sadrian POSEIDON_STORED_REG_G2_SZ /* should not exceed 3 */ 1164250003Sadrian} POSEIDON_STORED_REGS_G2; 1165250003Sadrian 1166250003Sadrian#if AH_NEED_TX_DATA_SWAP 1167250003Sadrian#if AH_NEED_RX_DATA_SWAP 1168250003Sadrian#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0) 1169250003Sadrian#else 1170250003Sadrian#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0) 1171250003Sadrian#endif 1172250003Sadrian#elif AH_NEED_RX_DATA_SWAP 1173250003Sadrian#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0) 1174250003Sadrian#else 1175250003Sadrian#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0) 1176250003Sadrian#endif 1177250003Sadrian 1178250003Sadrianextern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *); 1179250003Sadrian 1180250003Sadrianstruct ath_hal; 1181250003Sadrian 1182250003Sadrianextern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, 1183250008Sadrian HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1184250008Sadrian HAL_STATUS *status); 1185250003Sadrianextern struct ath_hal * ar9300_attach(u_int16_t devid, 1186250008Sadrian HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1187250003Sadrian HAL_STATUS *status); 1188250003Sadrianextern void ar9300_detach(struct ath_hal *ah); 1189250003Sadrianextern void ar9300_read_revisions(struct ath_hal *ah); 1190250003Sadrianextern HAL_BOOL ar9300_chip_test(struct ath_hal *ah); 1191250003Sadrianextern HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah, 1192250003Sadrian u_int16_t flags, u_int16_t *low, u_int16_t *high); 1193250003Sadrianextern HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah); 1194250003Sadrian 1195250003Sadrianextern void ar9300_beacon_init(struct ath_hal *ah, 1196250003Sadrian u_int32_t next_beacon, u_int32_t beacon_period, HAL_OPMODE opmode); 1197250003Sadrianextern void ar9300_set_sta_beacon_timers(struct ath_hal *ah, 1198250003Sadrian const HAL_BEACON_STATE *); 1199250003Sadrian 1200250003Sadrianextern HAL_BOOL ar9300_is_interrupt_pending(struct ath_hal *ah); 1201250003Sadrianextern HAL_BOOL ar9300_get_pending_interrupts(struct ath_hal *ah, HAL_INT *, HAL_INT_TYPE, u_int8_t, HAL_BOOL); 1202250003Sadrianextern HAL_INT ar9300_get_interrupts(struct ath_hal *ah); 1203250003Sadrianextern HAL_INT ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL); 1204250003Sadrianextern void ar9300_set_intr_mitigation_timer(struct ath_hal* ah, 1205250003Sadrian HAL_INT_MITIGATION reg, u_int32_t value); 1206250003Sadrianextern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah, 1207250003Sadrian HAL_INT_MITIGATION reg); 1208250003Sadrianextern u_int32_t ar9300_get_key_cache_size(struct ath_hal *); 1209250003Sadrianextern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry); 1210250003Sadrianextern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry); 1211250008Sadrianextern HAL_CHANNEL_INTERNAL * ar9300_check_chan(struct ath_hal *ah, 1212250008Sadrian const struct ieee80211_channel *chan); 1213250008Sadrian 1214250003Sadrianextern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *, 1215250003Sadrian u_int16_t entry, const u_int8_t *mac); 1216250003Sadrianextern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, 1217250003Sadrian const HAL_KEYVAL *k, const u_int8_t *mac, int xor_key); 1218250003Sadrianextern HAL_BOOL ar9300_print_keycache(struct ath_hal *ah); 1219250003Sadrian 1220250003Sadrianextern void ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac); 1221250003Sadrianextern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *); 1222250003Sadrianextern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac); 1223250003Sadrianextern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *); 1224250003Sadrianextern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg); 1225250003Sadrianextern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah, 1226250003Sadrian u_int16_t reg_domain, HAL_STATUS *stats); 1227250003Sadrianextern u_int ar9300_get_wireless_modes(struct ath_hal *ah); 1228250003Sadrianextern void ar9300_enable_rf_kill(struct ath_hal *); 1229250008Sadrianextern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); 1230250008Sadrianextern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); 1231250003Sadrianextern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio); 1232250003Sadrianextern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val); 1233250003Sadrianextern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio); 1234250003Sadrianextern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah); 1235250003Sadrianextern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel); 1236250003Sadrianextern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah); 1237250003Sadrianextern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t); 1238250003Sadrianextern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah); 1239250003Sadrianextern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map); 1240250003Sadrianextern void ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state); 1241250003Sadrianextern void ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enable); 1242250003Sadrianextern void ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enable); 1243250003Sadrianextern void ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 1244250003Sadrian u_int16_t assoc_id); 1245250003Sadrianextern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *); 1246250003Sadrianextern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *); 1247250003Sadrianextern int ar9300_ppm_get_trigger(struct ath_hal *); 1248250003Sadrianextern u_int32_t ar9300_ppm_force(struct ath_hal *); 1249250003Sadrianextern void ar9300_ppm_un_force(struct ath_hal *); 1250250003Sadrianextern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); 1251250003Sadrianextern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t); 1252250003Sadrianextern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah); 1253250003Sadrianextern u_int32_t ar9300_get_tsf32(struct ath_hal *ah); 1254250003Sadrianextern u_int64_t ar9300_get_tsf64(struct ath_hal *ah); 1255250003Sadrianextern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah); 1256250003Sadrianextern void ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf); 1257250003Sadrianextern void ar9300_reset_tsf(struct ath_hal *ah); 1258250003Sadrianextern void ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *pSet); 1259250003Sadrianextern u_int32_t ar9300_get_random_seed(struct ath_hal *ah); 1260250003Sadrianextern HAL_BOOL ar9300_detect_card_present(struct ath_hal *ah); 1261250003Sadrianextern void ar9300_update_mib_mac_stats(struct ath_hal *ah); 1262250003Sadrianextern void ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats); 1263250003Sadrianextern HAL_BOOL ar9300_is_japan_channel_spread_supported(struct ath_hal *ah); 1264250003Sadrianextern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah); 1265250003Sadrianextern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah); 1266250003Sadrianextern u_int ar9300_get_def_antenna(struct ath_hal *ah); 1267250003Sadrianextern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna); 1268250003Sadrianextern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah, 1269250008Sadrian HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 1270250008Sadrian u_int8_t *, u_int8_t *, u_int8_t *); 1271250003Sadrianextern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah); 1272250003Sadrianextern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int); 1273250003Sadrianextern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int); 1274250003Sadrianextern u_int ar9300_get_ack_timeout(struct ath_hal *); 1275250003Sadrianextern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 1276250003Sadrian u_int32_t next_start, HAL_QUIET_FLAG flag); 1277250003Sadrianextern void ar9300_set_pcu_config(struct ath_hal *); 1278250003Sadrianextern HAL_STATUS ar9300_get_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1279250003Sadrian u_int32_t, u_int32_t *); 1280250003Sadrianextern HAL_BOOL ar9300_set_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1281250003Sadrian u_int32_t, u_int32_t, HAL_STATUS *); 1282250003Sadrianextern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request, 1283250003Sadrian const void *args, u_int32_t argsize, 1284250003Sadrian void **result, u_int32_t *resultsize); 1285250003Sadrianextern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); 1286250008Sadrianextern uint32_t ar9300_get_11n_ext_busy(struct ath_hal *ah); 1287250003Sadrianextern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); 1288250003Sadrianextern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah); 1289250003Sadrianextern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); 1290250003Sadrianextern HAL_BOOL ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, 1291250003Sadrian int set_chip); 1292250003Sadrianextern HAL_POWER_MODE ar9300_get_power_mode(struct ath_hal *ah); 1293250003Sadrianextern HAL_BOOL ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip); 1294250003Sadrianextern void ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode); 1295250003Sadrian 1296250003Sadrianextern void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off); 1297250003Sadrian 1298250003Sadrianextern void ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 1299250003Sadrian u_int16_t assoc_id); 1300250003Sadrian 1301250003Sadrian 1302250003Sadrian#if ATH_WOW 1303250003Sadrianextern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_pattern, 1304250003Sadrian u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len); 1305250003Sadrian//extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes); 1306250003Sadrianextern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable); 1307250008Sadrianextern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, 1308250003Sadrian HAL_BOOL offloadEnable); 1309250003Sadrian#if ATH_WOW_OFFLOAD 1310250003Sadrian/* ARP offload */ 1311250003Sadrian#define WOW_OFFLOAD_ARP_INFO_MAX 2 1312250003Sadrian 1313250003Sadrianstruct hal_wow_offload_arp_info { 1314250003Sadrian u_int32_t valid; 1315250003Sadrian u_int32_t id; 1316250003Sadrian 1317250003Sadrian u_int32_t Flags; 1318250003Sadrian union { 1319250003Sadrian u_int8_t u8[4]; 1320250003Sadrian u_int32_t u32; 1321250003Sadrian } RemoteIPv4Address; 1322250003Sadrian union { 1323250003Sadrian u_int8_t u8[4]; 1324250003Sadrian u_int32_t u32; 1325250003Sadrian } HostIPv4Address; 1326250003Sadrian union { 1327250003Sadrian u_int8_t u8[6]; 1328250003Sadrian u_int32_t u32[2]; 1329250003Sadrian } MacAddress; 1330250003Sadrian}; 1331250003Sadrian 1332250003Sadrian/* NS offload */ 1333250003Sadrian#define WOW_OFFLOAD_NS_INFO_MAX 2 1334250003Sadrian 1335250003Sadrianstruct hal_wow_offload_ns_info { 1336250003Sadrian u_int32_t valid; 1337250003Sadrian u_int32_t id; 1338250003Sadrian 1339250003Sadrian u_int32_t Flags; 1340250003Sadrian union { 1341250003Sadrian u_int8_t u8[16]; 1342250003Sadrian u_int32_t u32[4]; 1343250003Sadrian } RemoteIPv6Address; 1344250003Sadrian union { 1345250003Sadrian u_int8_t u8[16]; 1346250003Sadrian u_int32_t u32[4]; 1347250003Sadrian } SolicitedNodeIPv6Address; 1348250003Sadrian union { 1349250003Sadrian u_int8_t u8[6]; 1350250003Sadrian u_int32_t u32[2]; 1351250003Sadrian } MacAddress; 1352250003Sadrian union { 1353250003Sadrian u_int8_t u8[16]; 1354250003Sadrian u_int32_t u32[4]; 1355250003Sadrian } TargetIPv6Addresses[2]; 1356250003Sadrian}; 1357250003Sadrian 1358250003Sadrianextern void ar9300_wowoffload_prep(struct ath_hal *ah); 1359250003Sadrianextern void ar9300_wowoffload_post(struct ath_hal *ah); 1360250003Sadrianextern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size); 1361250003Sadrianextern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param); 1362250003Sadrianextern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes); 1363250003Sadrianextern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap); 1364250003Sadrianextern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1365250003Sadrianextern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1366250003Sadrian#endif /* ATH_WOW_OFFLOAD */ 1367250003Sadrian#endif 1368250003Sadrian 1369250008Sadrianextern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, 1370250008Sadrian struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, 1371250003Sadrian u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing, 1372250003Sadrian HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan); 1373250008Sadrianextern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, 1374250003Sadrian HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask); 1375250003Sadrianextern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type); 1376250008Sadrianextern void ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan); 1377250003Sadrianextern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask); 1378250003Sadrianextern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah); 1379250003Sadrianextern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode); 1380250003Sadrianextern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah); 1381250003Sadrianextern HAL_BOOL ar9300_disable(struct ath_hal *ah); 1382250008Sadrianextern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *); 1383250008Sadrianextern HAL_BOOL ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, 1384250003Sadrian u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals); 1385250008Sadrianextern void ar9300_reset_cal_valid(struct ath_hal *ah, 1386250008Sadrian const struct ieee80211_channel *chan, 1387250008Sadrian HAL_BOOL *isIQdone, u_int32_t cal_type); 1388250003Sadrianextern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains); 1389250003Sadrianextern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains); 1390250003Sadrianextern void ar9300_temp_comp_cal_collect(struct ath_hal *ah); 1391250003Sadrianextern void ar9300_temp_comp_calibration(struct ath_hal *ah, u_int8_t num_chains); 1392250003Sadrianextern int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah); 1393250003Sadrianextern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfarray[]); 1394250003Sadrian 1395250003Sadrianextern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, 1396250003Sadrian u_int16_t extra_txpow, u_int16_t tpc_in_db); 1397250003Sadrianextern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, 1398250008Sadrian struct ieee80211_channel *chan, int is_scan); 1399250003Sadrianextern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]); 1400250003Sadrian 1401250003Sadrianextern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah); 1402250003Sadrianextern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode); 1403250003Sadrianextern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, 1404250003Sadrian u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode); 1405250003Sadrianextern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, 1406250008Sadrian const struct ieee80211_channel *chan, 1407250003Sadrian u_int8_t powerPerRate[], 1408250003Sadrian u_int8_t chainmask); 1409250003Sadrianextern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, 1410250003Sadrian u_int8_t powerPerRate[]); 1411250008Sadrianextern HAL_STATUS ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, 1412250008Sadrian u_int16_t freq, int8_t *max_rate_power, int8_t *min_rate_power); 1413250008Sadrian 1414250003Sadrianextern void ar9300_reset_tx_status_ring(struct ath_hal *ah); 1415250003Sadrianextern void ar9300_enable_mib_counters(struct ath_hal *); 1416250003Sadrianextern void ar9300_disable_mib_counters(struct ath_hal *); 1417250003Sadrianextern void ar9300_ani_attach(struct ath_hal *); 1418250003Sadrianextern void ar9300_ani_detach(struct ath_hal *); 1419250003Sadrianextern struct ar9300_ani_state *ar9300_ani_get_current_state(struct ath_hal *); 1420250003Sadrianextern struct ar9300_stats *ar9300_ani_get_current_stats(struct ath_hal *); 1421250003Sadrianextern HAL_BOOL ar9300_ani_control(struct ath_hal *, HAL_ANI_CMD cmd, int param); 1422250003Sadrianstruct ath_rx_status; 1423250003Sadrian 1424250003Sadrianextern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *); 1425250003Sadrianextern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *, 1426250008Sadrian const struct ieee80211_channel *, HAL_ANISTATS *); 1427250003Sadrianextern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning); 1428250003Sadrianextern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode); 1429250003Sadrianextern void ar9300_enable_tpc(struct ath_hal *); 1430250003Sadrian 1431250003Sadrianextern HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is2GHz); 1432250003Sadrianextern void ar9300_rx_gain_table_apply(struct ath_hal *ah); 1433250003Sadrianextern void ar9300_tx_gain_table_apply(struct ath_hal *ah); 1434250003Sadrianextern void ar9300_mat_enable(struct ath_hal *ah, int enable); 1435250003Sadrianextern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry); 1436250008Sadrianextern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, const struct ieee80211_channel * chan); 1437250003Sadrian 1438250003Sadrian/* BB Panic Watchdog declarations */ 1439250003Sadrian#define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */ 1440250003Sadrian#define HAL_BB_PANIC_WD_TMO_HORNET 85 1441250003Sadrianextern void ar9300_config_bb_panic_watchdog(struct ath_hal *); 1442250003Sadrianextern void ar9300_handle_bb_panic(struct ath_hal *); 1443250003Sadrianextern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic); 1444250003Sadrianextern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah); 1445250003Sadrianextern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason); 1446250003Sadrian 1447250003Sadrian/* DFS declarations */ 1448250008Sadrianextern void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan); 1449250008Sadrianextern void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, 1450250003Sadrian u_int64_t nolTime); 1451250003Sadrianextern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1452250003Sadrianextern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1453250008Sadrianextern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan); 1454250003Sadrianextern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah, 1455250003Sadrian u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, 1456250003Sadrian int *numb5radars, HAL_PHYERR_PARAM *pe); 1457250003Sadrianextern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val); 1458250003Sadrianextern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable); 1459250003Sadrianextern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable); 1460250003Sadrianextern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start); 1461250003Sadrian 1462250008Sadrianextern struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah); 1463250003Sadrianextern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah); 1464250003Sadrian 1465250003Sadrian 1466250003Sadrianextern void ar9300_mark_phy_inactive(struct ath_hal *ah); 1467250003Sadrian 1468250003Sadrian/* Spectral scan declarations */ 1469250003Sadrianextern void ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1470250003Sadrianextern void ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62); 1471250003Sadrianextern void ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1472250003Sadrianextern HAL_BOOL ar9300_is_spectral_active(struct ath_hal *ah); 1473250003Sadrianextern HAL_BOOL ar9300_is_spectral_enabled(struct ath_hal *ah); 1474250003Sadrianextern void ar9300_start_spectral_scan(struct ath_hal *ah); 1475250003Sadrianextern void ar9300_stop_spectral_scan(struct ath_hal *ah); 1476250003Sadrianextern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah); 1477250003Sadrianextern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval); 1478250003Sadrianint16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah); 1479250003Sadrianint16_t ar9300_get_ext_chan_nf(struct ath_hal *ah); 1480250003Sadrian/* End spectral scan declarations */ 1481250003Sadrian 1482250003Sadrian/* Raw ADC capture functions */ 1483250003Sadrianextern void ar9300_enable_test_addac_mode(struct ath_hal *ah); 1484250003Sadrianextern void ar9300_disable_test_addac_mode(struct ath_hal *ah); 1485250003Sadrianextern void ar9300_begin_adc_capture(struct ath_hal *ah, int auto_agc_gain); 1486250003Sadrianextern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples); 1487250003Sadrianextern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, int16_t *sample_min, int16_t *sample_max, int32_t *chain_ref_pwr, int num_chain_ref_pwr); 1488250003Sadrianextern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain); 1489250003Sadrian 1490250003Sadrianextern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode, 1491250008Sadrian struct ieee80211_channel *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); 1492250003Sadrianextern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now); 1493250003Sadrian 1494250003Sadrianextern void ar9300_get_channel_centers(struct ath_hal *ah, 1495250008Sadrian const struct ieee80211_channel *chan, 1496250003Sadrian CHAN_CENTERS *centers); 1497250003Sadrianextern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah, 1498250008Sadrian const struct ieee80211_channel *chan); 1499250003Sadrianextern u_int16_t ar9300_get_ext_center(struct ath_hal *ah, 1500250008Sadrian const struct ieee80211_channel *chan); 1501250003Sadrianextern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*); 1502250003Sadrian 1503250003Sadrianextern void ar9300_dma_reg_dump(struct ath_hal *); 1504250003Sadrianextern HAL_BOOL ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable); 1505250003Sadrianextern HAL_BOOL ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable); 1506250003Sadrianextern HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable); 1507250003Sadrianextern HAL_BOOL ar9300_detect_bb_hang(struct ath_hal *ah); 1508250003Sadrianextern HAL_BOOL ar9300_detect_mac_hang(struct ath_hal *ah); 1509250003Sadrian 1510250003Sadrian#ifdef ATH_BT_COEX 1511250003Sadrianextern void ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo); 1512250003Sadrianextern void ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf); 1513250003Sadrianextern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum); 1514250003Sadrianextern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1515250003Sadrianextern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh); 1516250003Sadrianextern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value); 1517250003Sadrianextern void ar9300_bt_coex_disable(struct ath_hal *ah); 1518250003Sadrianextern int ar9300_bt_coex_enable(struct ath_hal *ah); 1519250003Sadrianextern void ar9300_init_bt_coex(struct ath_hal *ah); 1520250003Sadrianextern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg); 1521250003Sadrianextern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn); 1522250003Sadrian#endif 1523250003Sadrianextern int ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf); 1524250003Sadrianextern void ar9300_free_generic_timer(struct ath_hal *ah, int index); 1525250003Sadrianextern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next, 1526250003Sadrian u_int32_t timer_period); 1527250003Sadrianextern void ar9300_stop_generic_timer(struct ath_hal *ah, int index); 1528250003Sadrianextern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger, 1529250003Sadrian u_int32_t *thresh); 1530250003Sadrianextern void ar9300_start_tsf2(struct ath_hal *ah); 1531250003Sadrian 1532250003Sadrianextern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi); 1533250003Sadrianextern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah); 1534250003Sadrianextern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah); 1535250003Sadrianextern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value); 1536250008Sadrianextern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); 1537250003Sadrianextern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah); 1538250003Sadrianextern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah); 1539250003Sadrianextern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 1540250003Sadrian u_int32_t rssi_threshold); 1541250003Sadrianextern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah); 1542250003Sadrianextern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on); 1543250003Sadrianextern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats, 1544250003Sadrian u_int8_t); 1545250003Sadrian 1546250003Sadrianextern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq); 1547250003Sadrianextern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq); 1548250003Sadrianextern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah); 1549250008Sadrianextern HAL_BOOL ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_SURVEY_SAMPLE *); 1550250003Sadrianextern void ar9300_clear_mib_counters(struct ath_hal *ah); 1551250003Sadrian 1552250003Sadrian/* EEPROM interface functions */ 1553250003Sadrian/* Common Interface functions */ 1554250003Sadrianextern HAL_STATUS ar9300_eeprom_attach(struct ath_hal *); 1555250003Sadrianextern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param); 1556250003Sadrian 1557250003Sadrianextern u_int32_t ar9300_ini_fixup(struct ath_hal *ah, 1558250003Sadrian ar9300_eeprom_t *p_eep_data, 1559250003Sadrian u_int32_t reg, 1560250003Sadrian u_int32_t val); 1561250003Sadrian 1562250003Sadrianextern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah, 1563250008Sadrian ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan, 1564250003Sadrian u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction, 1565250003Sadrian u_int16_t twice_max_regulatory_power, u_int16_t power_limit); 1566250008Sadrianextern void ar9300_eeprom_set_addac(struct ath_hal *, struct ieee80211_channel *); 1567250003Sadrianextern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value); 1568250008Sadrianextern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, const struct ieee80211_channel *); 1569250003Sadrianextern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data); 1570250003Sadrianextern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 1571250003Sadrianextern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi); 1572250003Sadrian 1573250003Sadrianextern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data); 1574250003Sadrianextern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data); 1575250003Sadrianextern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e); 1576250003Sadrianextern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band); 1577250008Sadrianextern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, const struct ieee80211_channel *chan, 1578250003Sadrian u_int8_t index, u_int16_t *config); 1579250003Sadrianextern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp); 1580250003Sadrianextern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz); 1581250003Sadrianextern HAL_BOOL ar9300_interference_is_present(struct ath_hal *ah); 1582250003Sadrianextern HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah); 1583250003Sadrianextern void ar9300_disp_tpc_tables(struct ath_hal *ah); 1584250003Sadrianextern u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah); 1585250003Sadrianextern u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, int *tx_gain_max); 1586250003Sadrianextern u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel); 1587250003Sadrian 1588250003Sadrian/* Common EEPROM Help function */ 1589250003Sadrianextern void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable); 1590250003Sadrianextern void ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs); 1591250003Sadrian 1592250003Sadrianextern u_int ar9300_mac_to_clks(struct ath_hal *ah, u_int clks); 1593250003Sadrian 1594250003Sadrian/* tx_bf interface */ 1595250003Sadrian#define ar9300_init_txbf(ah) 1596250003Sadrian#define ar9300_set_11n_txbf_sounding(ah, ds, series, cec, opt) 1597250003Sadrian#define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 1598250003Sadrian#define ar9300_txbf_save_cv_from_compress( \ 1599250003Sadrian ah, key_idx, mimo_control, compress_rpt) \ 1600250003Sadrian false 1601250003Sadrian#define ar9300_txbf_save_cv_from_non_compress( \ 1602250003Sadrian ah, key_idx, mimo_control, non_compress_rpt) \ 1603250003Sadrian false 1604250003Sadrian#define ar9300_txbf_rc_update( \ 1605250003Sadrian ah, rx_status, local_h, csi_frame, ness_a, ness_b, bw) \ 1606250003Sadrian false 1607250003Sadrian#define ar9300_fill_csi_frame( \ 1608250003Sadrian ah, rx_status, bandwidth, local_h, csi_frame_body) \ 1609250003Sadrian 0 1610250003Sadrian#define ar9300_fill_txbf_capabilities(ah) 1611250003Sadrian#define ar9300_get_txbf_capabilities(ah) NULL 1612250003Sadrian#define ar9300_txbf_set_key( \ 1613250003Sadrian ah, entry, rx_staggered_sounding, channel_estimation_cap, mmss) 1614250003Sadrian#define ar9300_read_key_cache_mac(ah, entry, mac) false 1615250003Sadrian#define ar9300_txbf_get_cv_cache_nr(ah, key_idx, nr) 1616250003Sadrian#define ar9300_set_selfgenrate_limit(ah, ts_ratecode) 1617250003Sadrian#define ar9300_reset_lowest_txrate(ah) 1618250003Sadrian#define ar9300_txbf_set_basic_set(ah) 1619250003Sadrian 1620250003Sadrianextern void ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs); 1621250003Sadrianextern void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah); 1622250003Sadrian 1623250003Sadrian 1624250003Sadrian 1625250003Sadrian#if ATH_SUPPORT_MCI 1626250003Sadrianextern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1627250003Sadrianextern void ar9300_mci_bt_coex_disable(struct ath_hal *ah); 1628250003Sadrianextern int ar9300_mci_bt_coex_enable(struct ath_hal *ah); 1629250003Sadrianextern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr, 1630250003Sadrian void *gpm_buf, u_int16_t len, 1631250003Sadrian u_int32_t sched_addr); 1632250003Sadrianextern void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done); 1633250003Sadrianextern void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done); 1634250003Sadrianextern void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done); 1635250003Sadrianextern HAL_BOOL ar9300_mci_send_message (struct ath_hal *ah, u_int8_t header, 1636250003Sadrian u_int32_t flag, u_int32_t *payload, u_int8_t len, 1637250003Sadrian HAL_BOOL wait_done, HAL_BOOL check_bt); 1638250003Sadrianextern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah, 1639250003Sadrian u_int32_t *mci_int, 1640250003Sadrian u_int32_t *mci_int_rx_msg); 1641250003Sadrianextern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data); 1642250003Sadrianextern void ar9300_mci_reset (struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, HAL_BOOL is_full_sleep); 1643250003Sadrianextern void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, HAL_BOOL halt, HAL_BOOL wait_done); 1644250003Sadrianextern void ar9300_mci_mute_bt(struct ath_hal *ah); 1645250003Sadrianextern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out); 1646250003Sadrianextern void ar9300_mci_enable_interrupt(struct ath_hal *ah); 1647250003Sadrianextern void ar9300_mci_disable_interrupt(struct ath_hal *ah); 1648250003Sadrianextern void ar9300_mci_detach (struct ath_hal *ah); 1649250003Sadrianextern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints); 1650250003Sadrianextern void ar9300_mci_sync_bt_state (struct ath_hal *ah); 1651250003Sadrianextern void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g); 1652250003Sadrianextern void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done); 1653250003Sadrian#if ATH_SUPPORT_AIC 1654250003Sadrianextern u_int32_t ar9300_aic_calibration (struct ath_hal *ah); 1655250003Sadrianextern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah); 1656250003Sadrian#endif 1657250003Sadrian#endif 1658250003Sadrian 1659250003Sadrianextern HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable); 1660250003Sadrian 1661250003Sadrianextern HAL_BOOL ar9300_regulatory_domain_override( 1662250003Sadrian struct ath_hal *ah, u_int16_t regdmn); 1663250003Sadrian#if ATH_ANT_DIV_COMB 1664250003Sadrianextern void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1665250003Sadrianextern void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1666250003Sadrian#endif /* ATH_ANT_DIV_COMB */ 1667250003Sadrianextern void ar9300_disable_phy_restart(struct ath_hal *ah, 1668250003Sadrian int disable_phy_restart); 1669250003Sadrianextern void ar9300_enable_keysearch_always(struct ath_hal *ah, int enable); 1670250003Sadrianextern HAL_BOOL ar9300ForceVCS( struct ath_hal *ah); 1671250003Sadrianextern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val); 1672250003Sadrianextern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah); 1673250003Sadrian 1674250003Sadrian#ifdef ATH_TX99_DIAG 1675250003Sadrian#ifndef ATH_SUPPORT_HTC 1676250008Sadrianextern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower); 1677250003Sadrianextern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask); 1678250003Sadrianextern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype); 1679250003Sadrianextern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data); 1680250003Sadrianextern void ar9300_tx99_stop(struct ath_hal *ah); 1681250003Sadrian#endif /* ATH_SUPPORT_HTC */ 1682250003Sadrian#endif /* ATH_TX99_DIAG */ 1683250003Sadrian 1684250003Sadrianenum { 1685250003Sadrian AR9300_COEFF_TX_TYPE = 0, 1686250003Sadrian AR9300_COEFF_RX_TYPE 1687250003Sadrian}; 1688250003Sadrian 1689250003Sadrian#endif /* _ATH_AR9300_H_ */ 1690