1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2139735Simp/*- 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38139735Simp/*- 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 81129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 82129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 83129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 84129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 85129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 86129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 87129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 88129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 89129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 90129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 91129198Scognet * POSSIBILITY OF SUCH DAMAGE. 92129198Scognet */ 93129198Scognet 94139735Simp/*- 95129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 96129198Scognet * Copyright (c) 1994 Brini. 97129198Scognet * All rights reserved. 98139735Simp * 99129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 100129198Scognet * 101129198Scognet * Redistribution and use in source and binary forms, with or without 102129198Scognet * modification, are permitted provided that the following conditions 103129198Scognet * are met: 104129198Scognet * 1. Redistributions of source code must retain the above copyright 105129198Scognet * notice, this list of conditions and the following disclaimer. 106129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 107129198Scognet * notice, this list of conditions and the following disclaimer in the 108129198Scognet * documentation and/or other materials provided with the distribution. 109129198Scognet * 3. All advertising materials mentioning features or use of this software 110129198Scognet * must display the following acknowledgement: 111129198Scognet * This product includes software developed by Mark Brinicombe. 112129198Scognet * 4. The name of the author may not be used to endorse or promote products 113129198Scognet * derived from this software without specific prior written permission. 114129198Scognet * 115129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 116129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 117129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 118129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 119129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 120129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 121129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 122129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 123129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 124129198Scognet * 125129198Scognet * RiscBSD kernel project 126129198Scognet * 127129198Scognet * pmap.c 128129198Scognet * 129129198Scognet * Machine dependant vm stuff 130129198Scognet * 131129198Scognet * Created : 20/09/94 132129198Scognet */ 133129198Scognet 134129198Scognet/* 135129198Scognet * Special compilation symbols 136129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 137129198Scognet */ 138129198Scognet/* Include header files */ 139135641Scognet 140137552Scognet#include "opt_vm.h" 141137552Scognet 142129198Scognet#include <sys/cdefs.h> 143129198Scognet__FBSDID("$FreeBSD$"); 144129198Scognet#include <sys/param.h> 145129198Scognet#include <sys/systm.h> 146129198Scognet#include <sys/kernel.h> 147183838Sraj#include <sys/ktr.h> 148240983Salc#include <sys/lock.h> 149129198Scognet#include <sys/proc.h> 150129198Scognet#include <sys/malloc.h> 151129198Scognet#include <sys/msgbuf.h> 152240983Salc#include <sys/mutex.h> 153129198Scognet#include <sys/vmmeter.h> 154129198Scognet#include <sys/mman.h> 155239934Salc#include <sys/rwlock.h> 156129198Scognet#include <sys/smp.h> 157129198Scognet#include <sys/sched.h> 158129198Scognet 159129198Scognet#include <vm/vm.h> 160239065Skib#include <vm/vm_param.h> 161129198Scognet#include <vm/uma.h> 162129198Scognet#include <vm/pmap.h> 163129198Scognet#include <vm/vm_kern.h> 164129198Scognet#include <vm/vm_object.h> 165129198Scognet#include <vm/vm_map.h> 166129198Scognet#include <vm/vm_page.h> 167129198Scognet#include <vm/vm_pageout.h> 168243132Skib#include <vm/vm_phys.h> 169129198Scognet#include <vm/vm_extern.h> 170240983Salc 171129198Scognet#include <machine/md_var.h> 172129198Scognet#include <machine/cpu.h> 173129198Scognet#include <machine/cpufunc.h> 174129198Scognet#include <machine/pcb.h> 175129198Scognet 176129198Scognet#ifdef PMAP_DEBUG 177129198Scognet#define PDEBUG(_lev_,_stat_) \ 178129198Scognet if (pmap_debug_level >= (_lev_)) \ 179129198Scognet ((_stat_)) 180129198Scognet#define dprintf printf 181129198Scognet 182129198Scognetint pmap_debug_level = 0; 183236991Simp#define PMAP_INLINE 184129198Scognet#else /* PMAP_DEBUG */ 185129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 186129198Scognet#define dprintf(x, arg...) 187135641Scognet#define PMAP_INLINE __inline 188129198Scognet#endif /* PMAP_DEBUG */ 189129198Scognet 190129198Scognetextern struct pv_addr systempage; 191225988Smarcel 192225988Smarcelextern int last_fault_code; 193225988Smarcel 194129198Scognet/* 195129198Scognet * Internal function prototypes 196129198Scognet */ 197135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 198129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 199129198Scognet 200159127Salcstatic void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t, 201160260Scognet vm_prot_t, boolean_t, int); 202240983Salcstatic vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va); 203194459Sthompsastatic void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t); 204129198Scognetstatic void pmap_alloc_l1(pmap_t); 205129198Scognetstatic void pmap_free_l1(pmap_t); 206129198Scognet 207135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 208129198Scognet 209129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 210129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 211129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 212129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 213129198Scognet 214129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 215129198Scognet 216129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 217129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 218135641Scognetvm_offset_t pmap_curmaxkvaddr; 219150865Scognetvm_paddr_t kernel_l1pa; 220129198Scognet 221129198Scognetvm_offset_t kernel_vm_end = 0; 222129198Scognet 223246926Salcvm_offset_t vm_max_kernel_address; 224246926Salc 225129198Scognetstruct pmap kernel_pmap_store; 226129198Scognet 227129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 228129198Scognetstatic vm_offset_t csrcp, cdstp; 229159088Scognetstatic struct mtx cmtx; 230159088Scognet 231129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 232129198Scognet/* 233129198Scognet * These routines are called when the CPU type is identified to set up 234129198Scognet * the PTE prototypes, cache modes, etc. 235129198Scognet * 236129198Scognet * The variables are always here, just in case LKMs need to reference 237129198Scognet * them (though, they shouldn't). 238129198Scognet */ 239129198Scognet 240129198Scognetpt_entry_t pte_l1_s_cache_mode; 241129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 242129198Scognetpt_entry_t pte_l1_s_cache_mask; 243129198Scognet 244129198Scognetpt_entry_t pte_l2_l_cache_mode; 245129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 246129198Scognetpt_entry_t pte_l2_l_cache_mask; 247129198Scognet 248129198Scognetpt_entry_t pte_l2_s_cache_mode; 249129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 250129198Scognetpt_entry_t pte_l2_s_cache_mask; 251129198Scognet 252129198Scognetpt_entry_t pte_l2_s_prot_u; 253129198Scognetpt_entry_t pte_l2_s_prot_w; 254129198Scognetpt_entry_t pte_l2_s_prot_mask; 255129198Scognet 256129198Scognetpt_entry_t pte_l1_s_proto; 257129198Scognetpt_entry_t pte_l1_c_proto; 258129198Scognetpt_entry_t pte_l2_s_proto; 259129198Scognet 260129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 261248280Skibvoid (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 262248280Skib vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, 263248280Skib int cnt); 264129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 265129198Scognet 266129198Scognetstruct msgbuf *msgbufp = 0; 267129198Scognet 268184728Sraj/* 269184728Sraj * Crashdump maps. 270184728Sraj */ 271184728Srajstatic caddr_t crashdumpmap; 272184728Sraj 273129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 274129198Scognetextern void bzero_page(vm_offset_t); 275137362Scognet 276164079Scognetextern vm_offset_t alloc_firstaddr; 277164079Scognet 278137362Scognetchar *_tmppt; 279137362Scognet 280129198Scognet/* 281129198Scognet * Metadata for L1 translation tables. 282129198Scognet */ 283129198Scognetstruct l1_ttable { 284129198Scognet /* Entry on the L1 Table list */ 285129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 286129198Scognet 287129198Scognet /* Entry on the L1 Least Recently Used list */ 288129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 289129198Scognet 290129198Scognet /* Track how many domains are allocated from this L1 */ 291129198Scognet volatile u_int l1_domain_use_count; 292129198Scognet 293129198Scognet /* 294129198Scognet * A free-list of domain numbers for this L1. 295129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 296129198Scognet * is slow on ARM. 297129198Scognet */ 298129198Scognet u_int8_t l1_domain_first; 299129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 300129198Scognet 301129198Scognet /* Physical address of this L1 page table */ 302129198Scognet vm_paddr_t l1_physaddr; 303129198Scognet 304129198Scognet /* KVA of this L1 page table */ 305129198Scognet pd_entry_t *l1_kva; 306129198Scognet}; 307129198Scognet 308129198Scognet/* 309129198Scognet * Convert a virtual address into its L1 table index. That is, the 310129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 311129198Scognet * This is basically used to index l1->l1_kva[]. 312129198Scognet * 313129198Scognet * Each L2 descriptor table represents 1MB of VA space. 314129198Scognet */ 315129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 316129198Scognet 317129198Scognet/* 318129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 319129198Scognet * - New L1s are allocated from the HEAD. 320129198Scognet * - Freed L1s are added to the TAIl. 321129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 322129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 323129198Scognet */ 324129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 325135641Scognet/* 326135641Scognet * A list of all L1 tables 327135641Scognet */ 328135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 329129198Scognetstatic struct mtx l1_lru_lock; 330129198Scognet 331129198Scognet/* 332129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 333129198Scognet * 334129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 335129198Scognet * Reference counts are maintained for L2 descriptors so they can be 336129198Scognet * freed when empty. 337129198Scognet */ 338129198Scognetstruct l2_dtable { 339129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 340129198Scognet u_int l2_occupancy; 341129198Scognet 342129198Scognet /* List of L2 page descriptors */ 343129198Scognet struct l2_bucket { 344129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 345129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 346129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 347129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 348129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 349129198Scognet}; 350129198Scognet 351135641Scognet/* pmap_kenter_internal flags */ 352135641Scognet#define KENTER_CACHE 0x1 353142570Scognet#define KENTER_USER 0x2 354135641Scognet 355129198Scognet/* 356129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 357129198Scognet * and bucket index within the l2_dtable. 358129198Scognet */ 359129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 360129198Scognet (L2_SIZE - 1)) 361129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 362129198Scognet 363129198Scognet/* 364129198Scognet * Given a virtual address, this macro returns the 365129198Scognet * virtual address required to drop into the next L2 bucket. 366129198Scognet */ 367129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 368129198Scognet 369129198Scognet/* 370129198Scognet * We try to map the page tables write-through, if possible. However, not 371129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 372129198Scognet * the cache when we frob page tables. 373129198Scognet * 374129198Scognet * We try to evaluate this at compile time, if possible. However, it's 375129198Scognet * not always possible to do that, hence this run-time var. 376129198Scognet */ 377129198Scognetint pmap_needs_pte_sync; 378129198Scognet 379129198Scognet/* 380129198Scognet * Macro to determine if a mapping might be resident in the 381129198Scognet * instruction cache and/or TLB 382129198Scognet */ 383129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 384129198Scognet 385129198Scognet/* 386129198Scognet * Macro to determine if a mapping might be resident in the 387129198Scognet * data cache and/or TLB 388129198Scognet */ 389129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 390129198Scognet 391129198Scognet#ifndef PMAP_SHPGPERPROC 392129198Scognet#define PMAP_SHPGPERPROC 200 393129198Scognet#endif 394129198Scognet 395135641Scognet#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 396135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 397194459Sthompsastatic uma_zone_t pvzone = NULL; 398147114Scognetuma_zone_t l2zone; 399129198Scognetstatic uma_zone_t l2table_zone; 400135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 401135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 402135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 403129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 404239934Salcstatic struct rwlock pvh_global_lock; 405129198Scognet 406248280Skibvoid pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs, 407248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 408248280Skib#if ARM_MMU_XSCALE == 1 409248280Skibvoid pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs, 410248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 411248280Skib#endif 412248280Skib 413129198Scognet/* 414129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 415129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 416129198Scognet * find them as necessary. 417129198Scognet * 418129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 419129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 420129198Scognet */ 421129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 422129198Scognet 423129198Scognetstatic void 424129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 425129198Scognet{ 426129198Scognet int i; 427129198Scognet 428129198Scognet l1->l1_kva = l1pt; 429129198Scognet l1->l1_domain_use_count = 0; 430174181Scognet l1->l1_domain_first = 0; 431129198Scognet 432129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 433174181Scognet l1->l1_domain_free[i] = i + 1; 434129198Scognet 435129198Scognet /* 436129198Scognet * Copy the kernel's L1 entries to each new L1. 437129198Scognet */ 438147249Scognet if (l1pt != pmap_kernel()->pm_l1->l1_kva) 439129198Scognet memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 440129198Scognet 441129198Scognet if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 442129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 443135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 444129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 445129198Scognet} 446129198Scognet 447129198Scognetstatic vm_offset_t 448129198Scognetkernel_pt_lookup(vm_paddr_t pa) 449129198Scognet{ 450129198Scognet struct pv_addr *pv; 451129198Scognet 452129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 453129198Scognet if (pv->pv_pa == pa) 454129198Scognet return (pv->pv_va); 455129198Scognet } 456129198Scognet return (0); 457129198Scognet} 458129198Scognet 459129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 460129198Scognetvoid 461129198Scognetpmap_pte_init_generic(void) 462129198Scognet{ 463129198Scognet 464129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 465129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 466129198Scognet 467129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 468129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 469129198Scognet 470129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 471129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 472129198Scognet 473129198Scognet /* 474129198Scognet * If we have a write-through cache, set B and C. If 475129198Scognet * we have a write-back cache, then we assume setting 476129198Scognet * only C will make those pages write-through. 477129198Scognet */ 478129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 479129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 480129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 481129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 482129198Scognet } else { 483129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 484129198Scognet pte_l2_l_cache_mode_pt = L2_C; 485129198Scognet pte_l2_s_cache_mode_pt = L2_C; 486129198Scognet } 487129198Scognet 488129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 489129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 490129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 491129198Scognet 492129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 493129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 494129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 495129198Scognet 496129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 497248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_generic; 498129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 499129198Scognet} 500129198Scognet 501129198Scognet#if defined(CPU_ARM8) 502129198Scognetvoid 503129198Scognetpmap_pte_init_arm8(void) 504129198Scognet{ 505129198Scognet 506129198Scognet /* 507129198Scognet * ARM8 is compatible with generic, but we need to use 508129198Scognet * the page tables uncached. 509129198Scognet */ 510129198Scognet pmap_pte_init_generic(); 511129198Scognet 512129198Scognet pte_l1_s_cache_mode_pt = 0; 513129198Scognet pte_l2_l_cache_mode_pt = 0; 514129198Scognet pte_l2_s_cache_mode_pt = 0; 515129198Scognet} 516129198Scognet#endif /* CPU_ARM8 */ 517129198Scognet 518129198Scognet#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 519129198Scognetvoid 520129198Scognetpmap_pte_init_arm9(void) 521129198Scognet{ 522129198Scognet 523129198Scognet /* 524129198Scognet * ARM9 is compatible with generic, but we want to use 525129198Scognet * write-through caching for now. 526129198Scognet */ 527129198Scognet pmap_pte_init_generic(); 528129198Scognet 529129198Scognet pte_l1_s_cache_mode = L1_S_C; 530129198Scognet pte_l2_l_cache_mode = L2_C; 531129198Scognet pte_l2_s_cache_mode = L2_C; 532129198Scognet 533129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 534129198Scognet pte_l2_l_cache_mode_pt = L2_C; 535129198Scognet pte_l2_s_cache_mode_pt = L2_C; 536129198Scognet} 537129198Scognet#endif /* CPU_ARM9 */ 538129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 539129198Scognet 540129198Scognet#if defined(CPU_ARM10) 541129198Scognetvoid 542129198Scognetpmap_pte_init_arm10(void) 543129198Scognet{ 544129198Scognet 545129198Scognet /* 546129198Scognet * ARM10 is compatible with generic, but we want to use 547129198Scognet * write-through caching for now. 548129198Scognet */ 549129198Scognet pmap_pte_init_generic(); 550129198Scognet 551129198Scognet pte_l1_s_cache_mode = L1_S_B | L1_S_C; 552129198Scognet pte_l2_l_cache_mode = L2_B | L2_C; 553129198Scognet pte_l2_s_cache_mode = L2_B | L2_C; 554129198Scognet 555129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 556129198Scognet pte_l2_l_cache_mode_pt = L2_C; 557129198Scognet pte_l2_s_cache_mode_pt = L2_C; 558129198Scognet 559129198Scognet} 560129198Scognet#endif /* CPU_ARM10 */ 561129198Scognet 562129198Scognet#if ARM_MMU_SA1 == 1 563129198Scognetvoid 564129198Scognetpmap_pte_init_sa1(void) 565129198Scognet{ 566129198Scognet 567129198Scognet /* 568129198Scognet * The StrongARM SA-1 cache does not have a write-through 569129198Scognet * mode. So, do the generic initialization, then reset 570129198Scognet * the page table cache mode to B=1,C=1, and note that 571129198Scognet * the PTEs need to be sync'd. 572129198Scognet */ 573129198Scognet pmap_pte_init_generic(); 574129198Scognet 575129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 576129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 577129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 578129198Scognet 579129198Scognet pmap_needs_pte_sync = 1; 580129198Scognet} 581129198Scognet#endif /* ARM_MMU_SA1 == 1*/ 582129198Scognet 583129198Scognet#if ARM_MMU_XSCALE == 1 584164778Scognet#if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3) 585129198Scognetstatic u_int xscale_use_minidata; 586129198Scognet#endif 587129198Scognet 588129198Scognetvoid 589129198Scognetpmap_pte_init_xscale(void) 590129198Scognet{ 591129198Scognet uint32_t auxctl; 592129198Scognet int write_through = 0; 593129198Scognet 594135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 595129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 596129198Scognet 597129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 598129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 599129198Scognet 600129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 601129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 602129198Scognet 603129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 604129198Scognet pte_l2_l_cache_mode_pt = L2_C; 605129198Scognet pte_l2_s_cache_mode_pt = L2_C; 606129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 607129198Scognet /* 608129198Scognet * The XScale core has an enhanced mode where writes that 609129198Scognet * miss the cache cause a cache line to be allocated. This 610129198Scognet * is significantly faster than the traditional, write-through 611129198Scognet * behavior of this case. 612129198Scognet */ 613129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 614129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 615129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 616129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 617129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 618129198Scognet /* 619129198Scognet * Some versions of the XScale core have various bugs in 620129198Scognet * their cache units, the work-around for which is to run 621129198Scognet * the cache in write-through mode. Unfortunately, this 622129198Scognet * has a major (negative) impact on performance. So, we 623129198Scognet * go ahead and run fast-and-loose, in the hopes that we 624129198Scognet * don't line up the planets in a way that will trip the 625129198Scognet * bugs. 626129198Scognet * 627129198Scognet * However, we give you the option to be slow-but-correct. 628129198Scognet */ 629129198Scognet write_through = 1; 630129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 631129198Scognet /* force write back cache mode */ 632129198Scognet write_through = 0; 633129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 634129198Scognet /* 635129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 636129198Scognet * write-back cache on revision 4 and earlier (stepping 637129198Scognet * A[01] and B[012]). Fixed for C0 and later. 638129198Scognet */ 639129198Scognet { 640129198Scognet uint32_t id, type; 641129198Scognet 642129198Scognet id = cpufunc_id(); 643129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 644129198Scognet 645129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 646129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 647129198Scognet /* write through for stepping A0-1 and B0-2 */ 648129198Scognet write_through = 1; 649129198Scognet } 650129198Scognet } 651129198Scognet } 652129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 653129198Scognet 654129198Scognet if (write_through) { 655129198Scognet pte_l1_s_cache_mode = L1_S_C; 656129198Scognet pte_l2_l_cache_mode = L2_C; 657129198Scognet pte_l2_s_cache_mode = L2_C; 658129198Scognet } 659129198Scognet 660129198Scognet#if (ARM_NMMUS > 1) 661129198Scognet xscale_use_minidata = 1; 662129198Scognet#endif 663129198Scognet 664129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 665129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 666129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 667129198Scognet 668129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 669129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 670129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 671129198Scognet 672164778Scognet#ifdef CPU_XSCALE_CORE3 673164778Scognet pmap_copy_page_func = pmap_copy_page_generic; 674248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_generic; 675164778Scognet pmap_zero_page_func = pmap_zero_page_generic; 676164778Scognet xscale_use_minidata = 0; 677171620Scognet /* Make sure it is L2-cachable */ 678171620Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T); 679171620Scognet pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P; 680171620Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ; 681171620Scognet pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode; 682171620Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T); 683171620Scognet pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 684171620Scognet 685164778Scognet#else 686129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 687248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_xscale; 688129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 689164778Scognet#endif 690129198Scognet 691129198Scognet /* 692129198Scognet * Disable ECC protection of page table access, for now. 693129198Scognet */ 694129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 695129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 696129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 697129198Scognet} 698129198Scognet 699129198Scognet/* 700129198Scognet * xscale_setup_minidata: 701129198Scognet * 702129198Scognet * Set up the mini-data cache clean area. We require the 703129198Scognet * caller to allocate the right amount of physically and 704129198Scognet * virtually contiguous space. 705129198Scognet */ 706129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 707129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 708129198Scognetvoid 709129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 710129198Scognet{ 711129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 712129198Scognet pt_entry_t *pte; 713129198Scognet vm_size_t size; 714129198Scognet uint32_t auxctl; 715129198Scognet 716129198Scognet xscale_minidata_clean_addr = va; 717129198Scognet 718129198Scognet /* Round it to page size. */ 719129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 720129198Scognet 721129198Scognet for (; size != 0; 722129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 723129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 724129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 725129198Scognet if (pte == NULL) 726129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 727129198Scognet "VA 0x%08x", (u_int32_t) va); 728129198Scognet pte[l2pte_index(va)] = 729129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 730129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 731129198Scognet } 732129198Scognet 733129198Scognet /* 734129198Scognet * Configure the mini-data cache for write-back with 735129198Scognet * read/write-allocate. 736129198Scognet * 737129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 738129198Scognet * make sure it contains no valid data! In order to do that, 739129198Scognet * we must issue a global data cache invalidate command! 740129198Scognet * 741129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 742129198Scognet * THIS IS VERY IMPORTANT! 743129198Scognet */ 744129198Scognet 745129198Scognet /* Invalidate data and mini-data. */ 746129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 747129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 748129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 749129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 750129198Scognet} 751129198Scognet#endif 752129198Scognet 753129198Scognet/* 754129198Scognet * Allocate an L1 translation table for the specified pmap. 755129198Scognet * This is called at pmap creation time. 756129198Scognet */ 757129198Scognetstatic void 758129198Scognetpmap_alloc_l1(pmap_t pm) 759129198Scognet{ 760129198Scognet struct l1_ttable *l1; 761129198Scognet u_int8_t domain; 762129198Scognet 763129198Scognet /* 764129198Scognet * Remove the L1 at the head of the LRU list 765129198Scognet */ 766129198Scognet mtx_lock(&l1_lru_lock); 767129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 768129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 769129198Scognet 770129198Scognet /* 771129198Scognet * Pick the first available domain number, and update 772129198Scognet * the link to the next number. 773129198Scognet */ 774129198Scognet domain = l1->l1_domain_first; 775129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 776129198Scognet 777129198Scognet /* 778129198Scognet * If there are still free domain numbers in this L1, 779129198Scognet * put it back on the TAIL of the LRU list. 780129198Scognet */ 781129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 782129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 783129198Scognet 784129198Scognet mtx_unlock(&l1_lru_lock); 785129198Scognet 786129198Scognet /* 787129198Scognet * Fix up the relevant bits in the pmap structure 788129198Scognet */ 789129198Scognet pm->pm_l1 = l1; 790174181Scognet pm->pm_domain = domain + 1; 791129198Scognet} 792129198Scognet 793129198Scognet/* 794129198Scognet * Free an L1 translation table. 795129198Scognet * This is called at pmap destruction time. 796129198Scognet */ 797129198Scognetstatic void 798129198Scognetpmap_free_l1(pmap_t pm) 799129198Scognet{ 800129198Scognet struct l1_ttable *l1 = pm->pm_l1; 801129198Scognet 802129198Scognet mtx_lock(&l1_lru_lock); 803129198Scognet 804129198Scognet /* 805129198Scognet * If this L1 is currently on the LRU list, remove it. 806129198Scognet */ 807129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 808129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 809129198Scognet 810129198Scognet /* 811129198Scognet * Free up the domain number which was allocated to the pmap 812129198Scognet */ 813174181Scognet l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 814174181Scognet l1->l1_domain_first = pm->pm_domain - 1; 815129198Scognet l1->l1_domain_use_count--; 816129198Scognet 817129198Scognet /* 818129198Scognet * The L1 now must have at least 1 free domain, so add 819129198Scognet * it back to the LRU list. If the use count is zero, 820129198Scognet * put it at the head of the list, otherwise it goes 821129198Scognet * to the tail. 822129198Scognet */ 823129198Scognet if (l1->l1_domain_use_count == 0) { 824129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 825129198Scognet } else 826129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 827129198Scognet 828129198Scognet mtx_unlock(&l1_lru_lock); 829129198Scognet} 830129198Scognet 831129198Scognet/* 832129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 833129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 834129198Scognet */ 835129198Scognetstatic PMAP_INLINE struct l2_bucket * 836129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 837129198Scognet{ 838129198Scognet struct l2_dtable *l2; 839129198Scognet struct l2_bucket *l2b; 840129198Scognet u_short l1idx; 841129198Scognet 842129198Scognet l1idx = L1_IDX(va); 843129198Scognet 844129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 845129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 846129198Scognet return (NULL); 847129198Scognet 848129198Scognet return (l2b); 849129198Scognet} 850129198Scognet 851129198Scognet/* 852129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 853129198Scognet * and VA. 854129198Scognet * 855129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 856129198Scognet * bucket/page table in place. 857129198Scognet * 858129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 859236991Simp * increment the bucket occupancy counter appropriately *before* 860129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 861129198Scognet * the bucket/page in the meantime. 862129198Scognet */ 863129198Scognetstatic struct l2_bucket * 864129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 865129198Scognet{ 866129198Scognet struct l2_dtable *l2; 867129198Scognet struct l2_bucket *l2b; 868129198Scognet u_short l1idx; 869129198Scognet 870129198Scognet l1idx = L1_IDX(va); 871129198Scognet 872159352Salc PMAP_ASSERT_LOCKED(pm); 873239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 874129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 875129198Scognet /* 876129198Scognet * No mapping at this address, as there is 877129198Scognet * no entry in the L1 table. 878129198Scognet * Need to allocate a new l2_dtable. 879129198Scognet */ 880159352Salc PMAP_UNLOCK(pm); 881239934Salc rw_wunlock(&pvh_global_lock); 882240803Salc if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) { 883239934Salc rw_wlock(&pvh_global_lock); 884159352Salc PMAP_LOCK(pm); 885129198Scognet return (NULL); 886129198Scognet } 887239934Salc rw_wlock(&pvh_global_lock); 888159352Salc PMAP_LOCK(pm); 889159108Scognet if (pm->pm_l2[L2_IDX(l1idx)] != NULL) { 890159108Scognet /* 891159108Scognet * Someone already allocated the l2_dtable while 892159108Scognet * we were doing the same. 893159108Scognet */ 894240803Salc uma_zfree(l2table_zone, l2); 895240803Salc l2 = pm->pm_l2[L2_IDX(l1idx)]; 896159108Scognet } else { 897159108Scognet bzero(l2, sizeof(*l2)); 898159108Scognet /* 899159108Scognet * Link it into the parent pmap 900159108Scognet */ 901159108Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 902159108Scognet } 903236991Simp } 904129198Scognet 905129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 906129198Scognet 907129198Scognet /* 908129198Scognet * Fetch pointer to the L2 page table associated with the address. 909129198Scognet */ 910129198Scognet if (l2b->l2b_kva == NULL) { 911129198Scognet pt_entry_t *ptep; 912129198Scognet 913129198Scognet /* 914129198Scognet * No L2 page table has been allocated. Chances are, this 915129198Scognet * is because we just allocated the l2_dtable, above. 916129198Scognet */ 917159352Salc PMAP_UNLOCK(pm); 918239934Salc rw_wunlock(&pvh_global_lock); 919240803Salc ptep = uma_zalloc(l2zone, M_NOWAIT); 920239934Salc rw_wlock(&pvh_global_lock); 921159352Salc PMAP_LOCK(pm); 922159108Scognet if (l2b->l2b_kva != 0) { 923159108Scognet /* We lost the race. */ 924159108Scognet uma_zfree(l2zone, ptep); 925159108Scognet return (l2b); 926159108Scognet } 927129198Scognet l2b->l2b_phys = vtophys(ptep); 928129198Scognet if (ptep == NULL) { 929129198Scognet /* 930129198Scognet * Oops, no more L2 page tables available at this 931129198Scognet * time. We may need to deallocate the l2_dtable 932129198Scognet * if we allocated a new one above. 933129198Scognet */ 934129198Scognet if (l2->l2_occupancy == 0) { 935129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 936240803Salc uma_zfree(l2table_zone, l2); 937129198Scognet } 938129198Scognet return (NULL); 939129198Scognet } 940129198Scognet 941129198Scognet l2->l2_occupancy++; 942129198Scognet l2b->l2b_kva = ptep; 943129198Scognet l2b->l2b_l1idx = l1idx; 944129198Scognet } 945129198Scognet 946129198Scognet return (l2b); 947129198Scognet} 948129198Scognet 949129198Scognetstatic PMAP_INLINE void 950129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 951129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 952129198Scognet#else 953129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 954129198Scognet#endif 955129198Scognet{ 956129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 957129198Scognet /* 958129198Scognet * Note: With a write-back cache, we may need to sync this 959129198Scognet * L2 table before re-using it. 960129198Scognet * This is because it may have belonged to a non-current 961129198Scognet * pmap, in which case the cache syncs would have been 962129198Scognet * skipped when the pages were being unmapped. If the 963129198Scognet * L2 table were then to be immediately re-allocated to 964129198Scognet * the *current* pmap, it may well contain stale mappings 965129198Scognet * which have not yet been cleared by a cache write-back 966129198Scognet * and so would still be visible to the mmu. 967129198Scognet */ 968129198Scognet if (need_sync) 969129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 970129198Scognet#endif 971129198Scognet uma_zfree(l2zone, l2); 972129198Scognet} 973129198Scognet/* 974129198Scognet * One or more mappings in the specified L2 descriptor table have just been 975129198Scognet * invalidated. 976129198Scognet * 977129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 978129198Scognet * 979129198Scognet * The pmap lock must be acquired when this is called (not necessary 980129198Scognet * for the kernel pmap). 981129198Scognet */ 982129198Scognetstatic void 983129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 984129198Scognet{ 985129198Scognet struct l2_dtable *l2; 986129198Scognet pd_entry_t *pl1pd, l1pd; 987129198Scognet pt_entry_t *ptep; 988129198Scognet u_short l1idx; 989129198Scognet 990129198Scognet 991129198Scognet /* 992129198Scognet * Update the bucket's reference count according to how many 993129198Scognet * PTEs the caller has just invalidated. 994129198Scognet */ 995129198Scognet l2b->l2b_occupancy -= count; 996129198Scognet 997129198Scognet /* 998129198Scognet * Note: 999129198Scognet * 1000129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 1001129198Scognet * as that would require checking all Level 1 page tables and 1002129198Scognet * removing any references to the Level 2 page table. See also the 1003129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 1004129198Scognet * 1005129198Scognet * We make do with just invalidating the mapping in the L2 table. 1006129198Scognet * 1007129198Scognet * This isn't really a big deal in practice and, in fact, leads 1008129198Scognet * to a performance win over time as we don't need to continually 1009129198Scognet * alloc/free. 1010129198Scognet */ 1011129198Scognet if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1012129198Scognet return; 1013129198Scognet 1014129198Scognet /* 1015129198Scognet * There are no more valid mappings in this level 2 page table. 1016129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 1017129198Scognet * free the page table. 1018129198Scognet */ 1019129198Scognet l1idx = l2b->l2b_l1idx; 1020129198Scognet ptep = l2b->l2b_kva; 1021129198Scognet l2b->l2b_kva = NULL; 1022129198Scognet 1023129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1024129198Scognet 1025129198Scognet /* 1026129198Scognet * If the L1 slot matches the pmap's domain 1027129198Scognet * number, then invalidate it. 1028129198Scognet */ 1029129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1030129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1031129198Scognet *pl1pd = 0; 1032129198Scognet PTE_SYNC(pl1pd); 1033129198Scognet } 1034129198Scognet 1035129198Scognet /* 1036129198Scognet * Release the L2 descriptor table back to the pool cache. 1037129198Scognet */ 1038129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1039129198Scognet pmap_free_l2_ptp(ptep); 1040129198Scognet#else 1041135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1042129198Scognet#endif 1043129198Scognet 1044129198Scognet /* 1045129198Scognet * Update the reference count in the associated l2_dtable 1046129198Scognet */ 1047129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1048129198Scognet if (--l2->l2_occupancy > 0) 1049129198Scognet return; 1050129198Scognet 1051129198Scognet /* 1052129198Scognet * There are no more valid mappings in any of the Level 1 1053129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 1054129198Scognet * the pointer in the parent pmap and free the l2_dtable. 1055129198Scognet */ 1056129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 1057240803Salc uma_zfree(l2table_zone, l2); 1058129198Scognet} 1059129198Scognet 1060129198Scognet/* 1061129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 1062129198Scognet * structures. 1063129198Scognet */ 1064133237Scognetstatic int 1065133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1066129198Scognet{ 1067129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1068129198Scognet struct l2_bucket *l2b; 1069129198Scognet pt_entry_t *ptep, pte; 1070147417Scognet#ifdef ARM_USE_SMALL_ALLOC 1071147417Scognet pd_entry_t *pde; 1072147417Scognet#endif 1073129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1074129198Scognet 1075129198Scognet /* 1076129198Scognet * The mappings for these page tables were initially made using 1077135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1078129198Scognet * mode will not be right for page table mappings. To avoid 1079135641Scognet * polluting the pmap_kenter() code with a special case for 1080129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1081129198Scognet * correct. 1082129198Scognet */ 1083147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1084147417Scognet pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)]; 1085147417Scognet if (!l1pte_section_p(*pde)) { 1086147114Scognet#endif 1087147114Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1088147114Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1089147114Scognet pte = *ptep; 1090161105Scognet 1091147114Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1092147114Scognet /* 1093236991Simp * Page tables must have the cache-mode set to 1094147114Scognet * Write-Thru. 1095147114Scognet */ 1096147114Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1097147114Scognet PTE_SYNC(ptep); 1098147114Scognet cpu_tlb_flushD_SE(va); 1099147114Scognet cpu_cpwait(); 1100147114Scognet } 1101147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1102129198Scognet } 1103129198Scognet#endif 1104147114Scognet#endif 1105129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1106129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1107133237Scognet return (0); 1108129198Scognet} 1109129198Scognet 1110129198Scognet/* 1111129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1112129198Scognet * on whether the specified pmap actually needs to be flushed at any 1113129198Scognet * given time. 1114129198Scognet */ 1115129198Scognetstatic PMAP_INLINE void 1116129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1117129198Scognet{ 1118129198Scognet 1119135641Scognet if (pmap_is_current(pm)) 1120129198Scognet cpu_tlb_flushID_SE(va); 1121129198Scognet} 1122129198Scognet 1123129198Scognetstatic PMAP_INLINE void 1124129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1125129198Scognet{ 1126129198Scognet 1127135641Scognet if (pmap_is_current(pm)) 1128129198Scognet cpu_tlb_flushD_SE(va); 1129129198Scognet} 1130129198Scognet 1131129198Scognetstatic PMAP_INLINE void 1132129198Scognetpmap_tlb_flushID(pmap_t pm) 1133129198Scognet{ 1134129198Scognet 1135135641Scognet if (pmap_is_current(pm)) 1136129198Scognet cpu_tlb_flushID(); 1137129198Scognet} 1138129198Scognetstatic PMAP_INLINE void 1139129198Scognetpmap_tlb_flushD(pmap_t pm) 1140129198Scognet{ 1141129198Scognet 1142135641Scognet if (pmap_is_current(pm)) 1143129198Scognet cpu_tlb_flushD(); 1144129198Scognet} 1145129198Scognet 1146203637Srajstatic int 1147203637Srajpmap_has_valid_mapping(pmap_t pm, vm_offset_t va) 1148183838Sraj{ 1149183838Sraj pd_entry_t *pde; 1150183838Sraj pt_entry_t *ptep; 1151183838Sraj 1152203637Sraj if (pmap_get_pde_pte(pm, va, &pde, &ptep) && 1153203637Sraj ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV)) 1154203637Sraj return (1); 1155183838Sraj 1156203637Sraj return (0); 1157183838Sraj} 1158183838Sraj 1159183838Srajstatic PMAP_INLINE void 1160129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1161129198Scognet{ 1162183838Sraj vm_size_t rest; 1163129198Scognet 1164203637Sraj CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x" 1165203637Sraj " len 0x%x ", pm, pm == pmap_kernel(), va, len); 1166183838Sraj 1167203637Sraj if (pmap_is_current(pm) || pm == pmap_kernel()) { 1168203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1169203637Sraj while (len > 0) { 1170203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1171203637Sraj cpu_idcache_wbinv_range(va, rest); 1172203637Sraj cpu_l2cache_wbinv_range(va, rest); 1173203637Sraj } 1174203637Sraj len -= rest; 1175203637Sraj va += rest; 1176203637Sraj rest = MIN(PAGE_SIZE, len); 1177203637Sraj } 1178183838Sraj } 1179183838Sraj} 1180183838Sraj 1181183838Srajstatic PMAP_INLINE void 1182183838Srajpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv, 1183183838Sraj boolean_t rd_only) 1184183838Sraj{ 1185203637Sraj vm_size_t rest; 1186184730Sraj 1187183838Sraj CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x " 1188183838Sraj "len 0x%x ", pm, pm == pmap_kernel(), va, len); 1189183838Sraj CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only); 1190183838Sraj 1191135641Scognet if (pmap_is_current(pm)) { 1192203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1193203637Sraj while (len > 0) { 1194203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1195203637Sraj if (do_inv && rd_only) { 1196203637Sraj cpu_dcache_inv_range(va, rest); 1197203637Sraj cpu_l2cache_inv_range(va, rest); 1198203637Sraj } else if (do_inv) { 1199203637Sraj cpu_dcache_wbinv_range(va, rest); 1200203637Sraj cpu_l2cache_wbinv_range(va, rest); 1201203637Sraj } else if (!rd_only) { 1202203637Sraj cpu_dcache_wb_range(va, rest); 1203203637Sraj cpu_l2cache_wb_range(va, rest); 1204203637Sraj } 1205183838Sraj } 1206203637Sraj len -= rest; 1207203637Sraj va += rest; 1208203637Sraj 1209203637Sraj rest = MIN(PAGE_SIZE, len); 1210183838Sraj } 1211129198Scognet } 1212129198Scognet} 1213129198Scognet 1214129198Scognetstatic PMAP_INLINE void 1215129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1216129198Scognet{ 1217129198Scognet 1218183838Sraj if (pmap_is_current(pm)) { 1219129198Scognet cpu_idcache_wbinv_all(); 1220183838Sraj cpu_l2cache_wbinv_all(); 1221183838Sraj } 1222129198Scognet} 1223129198Scognet 1224197770Sstas#ifdef notyet 1225129198Scognetstatic PMAP_INLINE void 1226129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1227129198Scognet{ 1228129198Scognet 1229183838Sraj if (pmap_is_current(pm)) { 1230129198Scognet cpu_dcache_wbinv_all(); 1231183838Sraj cpu_l2cache_wbinv_all(); 1232183838Sraj } 1233129198Scognet} 1234197770Sstas#endif 1235129198Scognet 1236129198Scognet/* 1237129198Scognet * PTE_SYNC_CURRENT: 1238129198Scognet * 1239129198Scognet * Make sure the pte is written out to RAM. 1240129198Scognet * We need to do this for one of two cases: 1241129198Scognet * - We're dealing with the kernel pmap 1242129198Scognet * - There is no pmap active in the cache/tlb. 1243129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1244129198Scognet */ 1245129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1246129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1247129198Scognetdo { \ 1248129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1249135641Scognet pmap_is_current(pm)) \ 1250129198Scognet PTE_SYNC(ptep); \ 1251129198Scognet} while (/*CONSTCOND*/0) 1252129198Scognet#else 1253129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1254129198Scognet#endif 1255129198Scognet 1256129198Scognet/* 1257175840Scognet * cacheable == -1 means we must make the entry uncacheable, 1 means 1258175840Scognet * cacheable; 1259129198Scognet */ 1260129198Scognetstatic __inline void 1261175840Scognetpmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable) 1262129198Scognet{ 1263175840Scognet struct l2_bucket *l2b; 1264175840Scognet pt_entry_t *ptep, pte; 1265129198Scognet 1266175840Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1267175840Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1268129198Scognet 1269175840Scognet if (cacheable == 1) { 1270175840Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1271175840Scognet if (l2pte_valid(pte)) { 1272175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1273175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1274175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1275175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 1276175840Scognet } 1277175840Scognet } 1278175840Scognet } else { 1279175840Scognet pte = *ptep &~ L2_S_CACHE_MASK; 1280175840Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1281175840Scognet l2pte_valid(pte)) { 1282175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1283175840Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1284175840Scognet pv->pv_va, PAGE_SIZE); 1285175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1286175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1287175840Scognet pmap_dcache_wb_range(pv->pv_pmap, 1288175840Scognet pv->pv_va, PAGE_SIZE, TRUE, 1289175840Scognet (pv->pv_flags & PVF_WRITE) == 0); 1290175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1291175840Scognet pv->pv_va); 1292175840Scognet } 1293175840Scognet } 1294129198Scognet } 1295175840Scognet *ptep = pte; 1296175840Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1297129198Scognet} 1298129198Scognet 1299129198Scognetstatic void 1300175840Scognetpmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1301129198Scognet{ 1302175840Scognet int pmwc = 0; 1303175840Scognet int writable = 0, kwritable = 0, uwritable = 0; 1304175840Scognet int entries = 0, kentries = 0, uentries = 0; 1305129198Scognet struct pv_entry *pv; 1306129198Scognet 1307239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1308129198Scognet 1309175840Scognet /* the cache gets written back/invalidated on context switch. 1310175840Scognet * therefore, if a user page shares an entry in the same page or 1311175840Scognet * with the kernel map and at least one is writable, then the 1312175840Scognet * cache entry must be set write-through. 1313129198Scognet */ 1314129198Scognet 1315175840Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1316175840Scognet /* generate a count of the pv_entry uses */ 1317175840Scognet if (pv->pv_flags & PVF_WRITE) { 1318175840Scognet if (pv->pv_pmap == pmap_kernel()) 1319175840Scognet kwritable++; 1320175840Scognet else if (pv->pv_pmap == pm) 1321175840Scognet uwritable++; 1322175840Scognet writable++; 1323129198Scognet } 1324175840Scognet if (pv->pv_pmap == pmap_kernel()) 1325175840Scognet kentries++; 1326175840Scognet else { 1327175840Scognet if (pv->pv_pmap == pm) 1328175840Scognet uentries++; 1329175840Scognet entries++; 1330175840Scognet } 1331129198Scognet } 1332175840Scognet /* 1333175840Scognet * check if the user duplicate mapping has 1334175840Scognet * been removed. 1335175840Scognet */ 1336175840Scognet if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) || 1337175840Scognet (uwritable > 1))) 1338175840Scognet pmwc = 1; 1339129198Scognet 1340129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1341175840Scognet /* check for user uncachable conditions - order is important */ 1342175840Scognet if (pm != pmap_kernel() && 1343175840Scognet (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) { 1344129198Scognet 1345175840Scognet if ((uentries > 1 && uwritable) || uwritable > 1) { 1346129198Scognet 1347175840Scognet /* user duplicate mapping */ 1348175840Scognet if (pv->pv_pmap != pmap_kernel()) 1349175840Scognet pv->pv_flags |= PVF_MWC; 1350129198Scognet 1351175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1352175840Scognet pv->pv_flags |= PVF_NC; 1353175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1354175840Scognet } 1355129198Scognet continue; 1356175840Scognet } else /* no longer a duplicate user */ 1357175840Scognet pv->pv_flags &= ~PVF_MWC; 1358175840Scognet } 1359129198Scognet 1360175840Scognet /* 1361175840Scognet * check for kernel uncachable conditions 1362175840Scognet * kernel writable or kernel readable with writable user entry 1363175840Scognet */ 1364209223Scognet if ((kwritable && (entries || kentries > 1)) || 1365194459Sthompsa (kwritable > 1) || 1366175840Scognet ((kwritable != writable) && kentries && 1367175840Scognet (pv->pv_pmap == pmap_kernel() || 1368175840Scognet (pv->pv_flags & PVF_WRITE) || 1369175840Scognet (pv->pv_flags & PVF_MWC)))) { 1370129198Scognet 1371175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1372175840Scognet pv->pv_flags |= PVF_NC; 1373175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1374129198Scognet } 1375175840Scognet continue; 1376129198Scognet } 1377129198Scognet 1378175840Scognet /* kernel and user are cachable */ 1379175840Scognet if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) && 1380175840Scognet (pv->pv_flags & PVF_NC)) { 1381175840Scognet 1382129198Scognet pv->pv_flags &= ~PVF_NC; 1383244574Scognet if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 1384244414Scognet pmap_set_cache_entry(pv, pm, va, 1); 1385175840Scognet continue; 1386175840Scognet } 1387175840Scognet /* user is no longer sharable and writable */ 1388194459Sthompsa if (pm != pmap_kernel() && 1389194459Sthompsa (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) && 1390175840Scognet !pmwc && (pv->pv_flags & PVF_NC)) { 1391129198Scognet 1392175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1393244574Scognet if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 1394244414Scognet pmap_set_cache_entry(pv, pm, va, 1); 1395129198Scognet } 1396129198Scognet } 1397175840Scognet 1398175840Scognet if ((kwritable == 0) && (writable == 0)) { 1399175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1400225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1401175840Scognet return; 1402175840Scognet } 1403129198Scognet} 1404129198Scognet 1405129198Scognet/* 1406129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1407129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1408129198Scognet * constants and the latter would require an extra inversion at run-time. 1409129198Scognet */ 1410236991Simpstatic int 1411129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1412129198Scognet{ 1413129198Scognet struct l2_bucket *l2b; 1414129198Scognet struct pv_entry *pv; 1415129198Scognet pt_entry_t *ptep, npte, opte; 1416129198Scognet pmap_t pm; 1417129198Scognet vm_offset_t va; 1418129198Scognet u_int oflags; 1419135641Scognet int count = 0; 1420129198Scognet 1421239934Salc rw_wlock(&pvh_global_lock); 1422159352Salc 1423175840Scognet if (maskbits & PVF_WRITE) 1424175840Scognet maskbits |= PVF_MOD; 1425129198Scognet /* 1426129198Scognet * Clear saved attributes (modify, reference) 1427129198Scognet */ 1428129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1429129198Scognet 1430129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1431239934Salc rw_wunlock(&pvh_global_lock); 1432135641Scognet return (0); 1433129198Scognet } 1434129198Scognet 1435129198Scognet /* 1436129198Scognet * Loop over all current mappings setting/clearing as appropos 1437129198Scognet */ 1438129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1439129198Scognet va = pv->pv_va; 1440129198Scognet pm = pv->pv_pmap; 1441129198Scognet oflags = pv->pv_flags; 1442175840Scognet 1443175840Scognet if (!(oflags & maskbits)) { 1444175840Scognet if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) { 1445244574Scognet if (pg->md.pv_memattr != 1446244574Scognet VM_MEMATTR_UNCACHEABLE) { 1447244414Scognet PMAP_LOCK(pm); 1448244414Scognet l2b = pmap_get_l2_bucket(pm, va); 1449244414Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1450244414Scognet *ptep |= pte_l2_s_cache_mode; 1451244414Scognet PTE_SYNC(ptep); 1452244414Scognet PMAP_UNLOCK(pm); 1453244414Scognet } 1454175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1455175840Scognet } 1456175840Scognet continue; 1457175840Scognet } 1458129198Scognet pv->pv_flags &= ~maskbits; 1459129198Scognet 1460159352Salc PMAP_LOCK(pm); 1461129198Scognet 1462129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1463129198Scognet 1464129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1465129198Scognet npte = opte = *ptep; 1466129198Scognet 1467157970Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1468129198Scognet if ((pv->pv_flags & PVF_NC)) { 1469236991Simp /* 1470129198Scognet * Entry is not cacheable: 1471129198Scognet * 1472236991Simp * Don't turn caching on again if this is a 1473129198Scognet * modified emulation. This would be 1474129198Scognet * inconsitent with the settings created by 1475175840Scognet * pmap_fix_cache(). Otherwise, it's safe 1476129198Scognet * to re-enable cacheing. 1477129198Scognet * 1478175840Scognet * There's no need to call pmap_fix_cache() 1479129198Scognet * here: all pages are losing their write 1480129198Scognet * permission. 1481129198Scognet */ 1482129198Scognet if (maskbits & PVF_WRITE) { 1483244574Scognet if (pg->md.pv_memattr != 1484244574Scognet VM_MEMATTR_UNCACHEABLE) 1485244414Scognet npte |= pte_l2_s_cache_mode; 1486175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1487129198Scognet } 1488129198Scognet } else 1489129198Scognet if (opte & L2_S_PROT_W) { 1490144760Scognet vm_page_dirty(pg); 1491236991Simp /* 1492129198Scognet * Entry is writable/cacheable: check if pmap 1493129198Scognet * is current if it is flush it, otherwise it 1494129198Scognet * won't be in the cache 1495129198Scognet */ 1496129198Scognet if (PV_BEEN_EXECD(oflags)) 1497129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1498129198Scognet PAGE_SIZE); 1499129198Scognet else 1500129198Scognet if (PV_BEEN_REFD(oflags)) 1501129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1502129198Scognet PAGE_SIZE, 1503129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1504129198Scognet FALSE); 1505129198Scognet } 1506129198Scognet 1507129198Scognet /* make the pte read only */ 1508129198Scognet npte &= ~L2_S_PROT_W; 1509129198Scognet } 1510129198Scognet 1511157970Scognet if (maskbits & PVF_REF) { 1512129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1513129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1514129198Scognet /* 1515129198Scognet * Check npte here; we may have already 1516129198Scognet * done the wbinv above, and the validity 1517129198Scognet * of the PTE is the same for opte and 1518129198Scognet * npte. 1519129198Scognet */ 1520129198Scognet if (npte & L2_S_PROT_W) { 1521129198Scognet if (PV_BEEN_EXECD(oflags)) 1522129198Scognet pmap_idcache_wbinv_range(pm, 1523129198Scognet pv->pv_va, PAGE_SIZE); 1524129198Scognet else 1525129198Scognet if (PV_BEEN_REFD(oflags)) 1526129198Scognet pmap_dcache_wb_range(pm, 1527129198Scognet pv->pv_va, PAGE_SIZE, 1528129198Scognet TRUE, FALSE); 1529129198Scognet } else 1530129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1531129198Scognet /* XXXJRT need idcache_inv_range */ 1532129198Scognet if (PV_BEEN_EXECD(oflags)) 1533129198Scognet pmap_idcache_wbinv_range(pm, 1534129198Scognet pv->pv_va, PAGE_SIZE); 1535129198Scognet else 1536129198Scognet if (PV_BEEN_REFD(oflags)) 1537129198Scognet pmap_dcache_wb_range(pm, 1538129198Scognet pv->pv_va, PAGE_SIZE, 1539129198Scognet TRUE, TRUE); 1540129198Scognet } 1541129198Scognet } 1542129198Scognet 1543129198Scognet /* 1544129198Scognet * Make the PTE invalid so that we will take a 1545129198Scognet * page fault the next time the mapping is 1546129198Scognet * referenced. 1547129198Scognet */ 1548129198Scognet npte &= ~L2_TYPE_MASK; 1549129198Scognet npte |= L2_TYPE_INV; 1550129198Scognet } 1551129198Scognet 1552129198Scognet if (npte != opte) { 1553135641Scognet count++; 1554129198Scognet *ptep = npte; 1555129198Scognet PTE_SYNC(ptep); 1556129198Scognet /* Flush the TLB entry if a current pmap. */ 1557129198Scognet if (PV_BEEN_EXECD(oflags)) 1558129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1559129198Scognet else 1560129198Scognet if (PV_BEEN_REFD(oflags)) 1561129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1562129198Scognet } 1563129198Scognet 1564159352Salc PMAP_UNLOCK(pm); 1565129198Scognet 1566129198Scognet } 1567129198Scognet 1568137664Scognet if (maskbits & PVF_WRITE) 1569225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1570239934Salc rw_wunlock(&pvh_global_lock); 1571135641Scognet return (count); 1572129198Scognet} 1573129198Scognet 1574129198Scognet/* 1575129198Scognet * main pv_entry manipulation functions: 1576129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1577129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1578129198Scognet * 1579129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1580240166Salc * pmap_remove_pv expects the caller to lock the pvh before calling 1581129198Scognet */ 1582129198Scognet 1583129198Scognet/* 1584240442Salc * pmap_enter_pv: enter a mapping onto a vm_page's PV list 1585129198Scognet * 1586240166Salc * => caller should hold the proper lock on pvh_global_lock 1587129198Scognet * => caller should have pmap locked 1588240442Salc * => we will (someday) gain the lock on the vm_page's PV list 1589129198Scognet * => caller should adjust ptp's wire_count before calling 1590129198Scognet * => caller should not adjust pmap's wire_count 1591129198Scognet */ 1592129198Scognetstatic void 1593129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1594129198Scognet vm_offset_t va, u_int flags) 1595129198Scognet{ 1596194459Sthompsa 1597239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1598240442Salc PMAP_ASSERT_LOCKED(pm); 1599240166Salc if (pg->md.pv_kva != 0) { 1600240442Salc pve->pv_pmap = kernel_pmap; 1601194459Sthompsa pve->pv_va = pg->md.pv_kva; 1602194459Sthompsa pve->pv_flags = PVF_WRITE | PVF_UNMAN; 1603240442Salc if (pm != kernel_pmap) 1604240442Salc PMAP_LOCK(kernel_pmap); 1605240442Salc TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1606240442Salc TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist); 1607240442Salc if (pm != kernel_pmap) 1608240442Salc PMAP_UNLOCK(kernel_pmap); 1609194459Sthompsa pg->md.pv_kva = 0; 1610194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 1611240166Salc panic("pmap_kenter_pv: no pv entries"); 1612194459Sthompsa } 1613129198Scognet pve->pv_pmap = pm; 1614129198Scognet pve->pv_va = va; 1615129198Scognet pve->pv_flags = flags; 1616129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1617144760Scognet TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1618129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1619129198Scognet if (pve->pv_flags & PVF_WIRED) 1620129198Scognet ++pm->pm_stats.wired_count; 1621225418Skib vm_page_aflag_set(pg, PGA_REFERENCED); 1622129198Scognet} 1623129198Scognet 1624129198Scognet/* 1625129198Scognet * 1626129198Scognet * pmap_find_pv: Find a pv entry 1627129198Scognet * 1628129198Scognet * => caller should hold lock on vm_page 1629129198Scognet */ 1630129198Scognetstatic PMAP_INLINE struct pv_entry * 1631129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1632129198Scognet{ 1633129198Scognet struct pv_entry *pv; 1634129198Scognet 1635239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1636129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1637129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1638129198Scognet break; 1639129198Scognet return (pv); 1640129198Scognet} 1641129198Scognet 1642129198Scognet/* 1643129198Scognet * vector_page_setprot: 1644129198Scognet * 1645129198Scognet * Manipulate the protection of the vector page. 1646129198Scognet */ 1647129198Scognetvoid 1648129198Scognetvector_page_setprot(int prot) 1649129198Scognet{ 1650129198Scognet struct l2_bucket *l2b; 1651129198Scognet pt_entry_t *ptep; 1652129198Scognet 1653129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1654129198Scognet 1655129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1656129198Scognet 1657129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1658129198Scognet PTE_SYNC(ptep); 1659129198Scognet cpu_tlb_flushD_SE(vector_page); 1660129198Scognet cpu_cpwait(); 1661129198Scognet} 1662129198Scognet 1663129198Scognet/* 1664129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1665129198Scognet * 1666129198Scognet * => caller should hold proper lock on pmap_main_lock 1667129198Scognet * => pmap should be locked 1668129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1669129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1670129198Scognet * => caller should NOT adjust pmap's wire_count 1671129198Scognet * => we return the removed pve 1672129198Scognet */ 1673135641Scognet 1674135641Scognetstatic void 1675135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1676135641Scognet{ 1677135641Scognet 1678194459Sthompsa struct pv_entry *pv; 1679239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1680159352Salc PMAP_ASSERT_LOCKED(pm); 1681135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1682144760Scognet TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1683135641Scognet if (pve->pv_flags & PVF_WIRED) 1684135641Scognet --pm->pm_stats.wired_count; 1685144760Scognet if (pg->md.pvh_attrs & PVF_MOD) 1686144760Scognet vm_page_dirty(pg); 1687175840Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1688175840Scognet pg->md.pvh_attrs &= ~PVF_REF; 1689175840Scognet else 1690225418Skib vm_page_aflag_set(pg, PGA_REFERENCED); 1691175840Scognet if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) || 1692175840Scognet (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC))) 1693175840Scognet pmap_fix_cache(pg, pm, 0); 1694175840Scognet else if (pve->pv_flags & PVF_WRITE) { 1695175840Scognet TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list) 1696175840Scognet if (pve->pv_flags & PVF_WRITE) 1697175840Scognet break; 1698175840Scognet if (!pve) { 1699175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1700225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1701175840Scognet } 1702146647Scognet } 1703194459Sthompsa pv = TAILQ_FIRST(&pg->md.pv_list); 1704194459Sthompsa if (pv != NULL && (pv->pv_flags & PVF_UNMAN) && 1705194459Sthompsa TAILQ_NEXT(pv, pv_list) == NULL) { 1706205425Scognet pm = kernel_pmap; 1707194459Sthompsa pg->md.pv_kva = pv->pv_va; 1708194459Sthompsa /* a recursive pmap_nuke_pv */ 1709194459Sthompsa TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list); 1710194459Sthompsa TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist); 1711194459Sthompsa if (pv->pv_flags & PVF_WIRED) 1712194459Sthompsa --pm->pm_stats.wired_count; 1713194459Sthompsa pg->md.pvh_attrs &= ~PVF_REF; 1714194459Sthompsa pg->md.pvh_attrs &= ~PVF_MOD; 1715225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1716194459Sthompsa pmap_free_pv_entry(pv); 1717194459Sthompsa } 1718135641Scognet} 1719135641Scognet 1720129198Scognetstatic struct pv_entry * 1721129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1722129198Scognet{ 1723135641Scognet struct pv_entry *pve; 1724129198Scognet 1725239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1726135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1727129198Scognet 1728129198Scognet while (pve) { 1729129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1730135641Scognet pmap_nuke_pv(pg, pm, pve); 1731129198Scognet break; 1732129198Scognet } 1733129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1734129198Scognet } 1735129198Scognet 1736194459Sthompsa if (pve == NULL && pg->md.pv_kva == va) 1737194459Sthompsa pg->md.pv_kva = 0; 1738194459Sthompsa 1739129198Scognet return(pve); /* return removed pve */ 1740129198Scognet} 1741129198Scognet/* 1742129198Scognet * 1743129198Scognet * pmap_modify_pv: Update pv flags 1744129198Scognet * 1745129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1746129198Scognet * => caller should NOT adjust pmap's wire_count 1747129198Scognet * => we return the old flags 1748236991Simp * 1749129198Scognet * Modify a physical-virtual mapping in the pv table 1750129198Scognet */ 1751129198Scognetstatic u_int 1752129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1753129198Scognet u_int clr_mask, u_int set_mask) 1754129198Scognet{ 1755129198Scognet struct pv_entry *npv; 1756129198Scognet u_int flags, oflags; 1757129198Scognet 1758159352Salc PMAP_ASSERT_LOCKED(pm); 1759239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1760129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1761129198Scognet return (0); 1762129198Scognet 1763129198Scognet /* 1764129198Scognet * There is at least one VA mapping this page. 1765129198Scognet */ 1766129198Scognet 1767129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1768129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1769129198Scognet 1770129198Scognet oflags = npv->pv_flags; 1771129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1772129198Scognet 1773129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1774129198Scognet if (flags & PVF_WIRED) 1775129198Scognet ++pm->pm_stats.wired_count; 1776129198Scognet else 1777129198Scognet --pm->pm_stats.wired_count; 1778129198Scognet } 1779129198Scognet 1780175840Scognet if ((flags ^ oflags) & PVF_WRITE) 1781175840Scognet pmap_fix_cache(pg, pm, 0); 1782129198Scognet 1783129198Scognet return (oflags); 1784129198Scognet} 1785129198Scognet 1786129198Scognet/* Function to set the debug level of the pmap code */ 1787129198Scognet#ifdef PMAP_DEBUG 1788129198Scognetvoid 1789129198Scognetpmap_debug(int level) 1790129198Scognet{ 1791129198Scognet pmap_debug_level = level; 1792129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1793129198Scognet} 1794129198Scognet#endif /* PMAP_DEBUG */ 1795129198Scognet 1796129198Scognetvoid 1797129198Scognetpmap_pinit0(struct pmap *pmap) 1798129198Scognet{ 1799129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1800129198Scognet 1801135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1802159325Salc bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1803159325Salc PMAP_LOCK_INIT(pmap); 1804129198Scognet} 1805129198Scognet 1806147217Salc/* 1807147217Salc * Initialize a vm_page's machine-dependent fields. 1808147217Salc */ 1809147217Salcvoid 1810147217Salcpmap_page_init(vm_page_t m) 1811147217Salc{ 1812129198Scognet 1813147217Salc TAILQ_INIT(&m->md.pv_list); 1814244414Scognet m->md.pv_memattr = VM_MEMATTR_DEFAULT; 1815147217Salc} 1816147217Salc 1817129198Scognet/* 1818129198Scognet * Initialize the pmap module. 1819129198Scognet * Called by vm_init, to initialize any structures that the pmap 1820129198Scognet * system needs to map virtual memory. 1821129198Scognet */ 1822129198Scognetvoid 1823129198Scognetpmap_init(void) 1824129198Scognet{ 1825152128Scognet int shpgperproc = PMAP_SHPGPERPROC; 1826129198Scognet 1827197770Sstas PDEBUG(1, printf("pmap_init: phys_start = %08x\n", PHYSADDR)); 1828147114Scognet 1829240803Salc l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1830240803Salc NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1831240803Salc l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL, 1832240803Salc NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1833240803Salc 1834129198Scognet /* 1835240803Salc * Initialize the PV entry allocator. 1836129198Scognet */ 1837236991Simp pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1838129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1839240803Salc TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1840240803Salc pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1841247360Sattilio uma_zone_reserve_kva(pvzone, pv_entry_max); 1842240803Salc pv_entry_high_water = 9 * (pv_entry_max / 10); 1843240803Salc 1844129198Scognet /* 1845129198Scognet * Now it is safe to enable pv_table recording. 1846129198Scognet */ 1847129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1848129198Scognet} 1849129198Scognet 1850129198Scognetint 1851129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1852129198Scognet{ 1853129198Scognet struct l2_dtable *l2; 1854129198Scognet struct l2_bucket *l2b; 1855129198Scognet pd_entry_t *pl1pd, l1pd; 1856129198Scognet pt_entry_t *ptep, pte; 1857129198Scognet vm_paddr_t pa; 1858129198Scognet u_int l1idx; 1859129198Scognet int rv = 0; 1860129198Scognet 1861129198Scognet l1idx = L1_IDX(va); 1862239934Salc rw_wlock(&pvh_global_lock); 1863159384Salc PMAP_LOCK(pm); 1864129198Scognet 1865129198Scognet /* 1866129198Scognet * If there is no l2_dtable for this address, then the process 1867129198Scognet * has no business accessing it. 1868129198Scognet * 1869129198Scognet * Note: This will catch userland processes trying to access 1870129198Scognet * kernel addresses. 1871129198Scognet */ 1872129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1873129198Scognet if (l2 == NULL) 1874129198Scognet goto out; 1875129198Scognet 1876129198Scognet /* 1877129198Scognet * Likewise if there is no L2 descriptor table 1878129198Scognet */ 1879129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1880129198Scognet if (l2b->l2b_kva == NULL) 1881129198Scognet goto out; 1882129198Scognet 1883129198Scognet /* 1884129198Scognet * Check the PTE itself. 1885129198Scognet */ 1886129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1887129198Scognet pte = *ptep; 1888129198Scognet if (pte == 0) 1889129198Scognet goto out; 1890129198Scognet 1891129198Scognet /* 1892129198Scognet * Catch a userland access to the vector page mapped at 0x0 1893129198Scognet */ 1894129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 1895129198Scognet goto out; 1896157027Scognet if (va == vector_page) 1897157027Scognet goto out; 1898129198Scognet 1899129198Scognet pa = l2pte_pa(pte); 1900129198Scognet 1901129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 1902129198Scognet /* 1903129198Scognet * This looks like a good candidate for "page modified" 1904129198Scognet * emulation... 1905129198Scognet */ 1906129198Scognet struct pv_entry *pv; 1907129198Scognet struct vm_page *pg; 1908129198Scognet 1909129198Scognet /* Extract the physical address of the page */ 1910129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 1911129198Scognet goto out; 1912129198Scognet } 1913129198Scognet /* Get the current flags for this page. */ 1914129198Scognet 1915129198Scognet pv = pmap_find_pv(pg, pm, va); 1916129198Scognet if (pv == NULL) { 1917129198Scognet goto out; 1918129198Scognet } 1919129198Scognet 1920129198Scognet /* 1921129198Scognet * Do the flags say this page is writable? If not then it 1922129198Scognet * is a genuine write fault. If yes then the write fault is 1923129198Scognet * our fault as we did not reflect the write access in the 1924129198Scognet * PTE. Now we know a write has occurred we can correct this 1925129198Scognet * and also set the modified bit 1926129198Scognet */ 1927129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 1928129198Scognet goto out; 1929129198Scognet } 1930129198Scognet 1931157970Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 1932157970Scognet vm_page_dirty(pg); 1933129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 1934129198Scognet 1935236991Simp /* 1936129198Scognet * Re-enable write permissions for the page. No need to call 1937175840Scognet * pmap_fix_cache(), since this is just a 1938129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 1939129198Scognet * changing. We've already set the cacheable bits based on 1940129198Scognet * the assumption that we can write to this page. 1941129198Scognet */ 1942147114Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 1943129198Scognet PTE_SYNC(ptep); 1944129198Scognet rv = 1; 1945129198Scognet } else 1946129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 1947129198Scognet /* 1948129198Scognet * This looks like a good candidate for "page referenced" 1949129198Scognet * emulation. 1950129198Scognet */ 1951129198Scognet struct pv_entry *pv; 1952129198Scognet struct vm_page *pg; 1953129198Scognet 1954129198Scognet /* Extract the physical address of the page */ 1955159384Salc if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 1956129198Scognet goto out; 1957129198Scognet /* Get the current flags for this page. */ 1958129198Scognet 1959129198Scognet pv = pmap_find_pv(pg, pm, va); 1960159384Salc if (pv == NULL) 1961129198Scognet goto out; 1962129198Scognet 1963129198Scognet pg->md.pvh_attrs |= PVF_REF; 1964129198Scognet pv->pv_flags |= PVF_REF; 1965129198Scognet 1966129198Scognet 1967129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 1968129198Scognet PTE_SYNC(ptep); 1969129198Scognet rv = 1; 1970129198Scognet } 1971129198Scognet 1972129198Scognet /* 1973129198Scognet * We know there is a valid mapping here, so simply 1974129198Scognet * fix up the L1 if necessary. 1975129198Scognet */ 1976129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1977129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 1978129198Scognet if (*pl1pd != l1pd) { 1979129198Scognet *pl1pd = l1pd; 1980129198Scognet PTE_SYNC(pl1pd); 1981129198Scognet rv = 1; 1982129198Scognet } 1983129198Scognet 1984129198Scognet#ifdef CPU_SA110 1985129198Scognet /* 1986129198Scognet * There are bugs in the rev K SA110. This is a check for one 1987129198Scognet * of them. 1988129198Scognet */ 1989129198Scognet if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 1990129198Scognet curcpu()->ci_arm_cpurev < 3) { 1991129198Scognet /* Always current pmap */ 1992129198Scognet if (l2pte_valid(pte)) { 1993129198Scognet extern int kernel_debug; 1994129198Scognet if (kernel_debug & 1) { 1995129198Scognet struct proc *p = curlwp->l_proc; 1996129198Scognet printf("prefetch_abort: page is already " 1997129198Scognet "mapped - pte=%p *pte=%08x\n", ptep, pte); 1998129198Scognet printf("prefetch_abort: pc=%08lx proc=%p " 1999129198Scognet "process=%s\n", va, p, p->p_comm); 2000129198Scognet printf("prefetch_abort: far=%08x fs=%x\n", 2001129198Scognet cpu_faultaddress(), cpu_faultstatus()); 2002129198Scognet } 2003129198Scognet#ifdef DDB 2004129198Scognet if (kernel_debug & 2) 2005129198Scognet Debugger(); 2006129198Scognet#endif 2007129198Scognet rv = 1; 2008129198Scognet } 2009129198Scognet } 2010129198Scognet#endif /* CPU_SA110 */ 2011129198Scognet 2012129198Scognet#ifdef DEBUG 2013129198Scognet /* 2014129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 2015129198Scognet * stale TLB entry for the faulting address. This happens when two or 2016129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 2017129198Scognet * a context switch between such processes, we can take domain faults 2018129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 2019129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2020129198Scognet * example. 2021129198Scognet * 2022129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 2023129198Scognet * entry for a recently entered mapping. In this case, the TLB is 2024129198Scognet * flushed for the new mapping, but there may still be TLB entries for 2025129198Scognet * other mappings belonging to other processes in the 1MB range 2026129198Scognet * covered by the L1 entry. 2027129198Scognet * 2028129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 2029129198Scognet * value, so the fault must be due to a stale TLB entry. 2030129198Scognet * 2031129198Scognet * Since we always need to flush the TLB anyway in the case where we 2032129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2033129198Scognet * stale TLB entries dynamically. 2034129198Scognet * 2035129198Scognet * However, the above condition can ONLY happen if the current L1 is 2036129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 2037129198Scognet * that other parts of the pmap are not doing their job WRT managing 2038129198Scognet * the TLB. 2039129198Scognet */ 2040129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2041129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2042225988Smarcel pm, (u_long)va, ftype); 2043129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2044129198Scognet l2, l2b, ptep, pl1pd); 2045129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2046129198Scognet pte, l1pd, last_fault_code); 2047129198Scognet#ifdef DDB 2048129198Scognet Debugger(); 2049129198Scognet#endif 2050129198Scognet } 2051129198Scognet#endif 2052129198Scognet 2053129198Scognet cpu_tlb_flushID_SE(va); 2054129198Scognet cpu_cpwait(); 2055129198Scognet 2056129198Scognet rv = 1; 2057129198Scognet 2058129198Scognetout: 2059239934Salc rw_wunlock(&pvh_global_lock); 2060159384Salc PMAP_UNLOCK(pm); 2061129198Scognet return (rv); 2062129198Scognet} 2063129198Scognet 2064129198Scognetvoid 2065152128Scognetpmap_postinit(void) 2066152128Scognet{ 2067129198Scognet struct l2_bucket *l2b; 2068129198Scognet struct l1_ttable *l1; 2069129198Scognet pd_entry_t *pl1pt; 2070129198Scognet pt_entry_t *ptep, pte; 2071129198Scognet vm_offset_t va, eva; 2072129198Scognet u_int loop, needed; 2073129198Scognet 2074129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2075129198Scognet needed -= 1; 2076129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2077129198Scognet 2078129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 2079129198Scognet /* Allocate a L1 page table */ 2080132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2081132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 2082129198Scognet 2083129198Scognet if (va == 0) 2084129198Scognet panic("Cannot allocate L1 KVM"); 2085129198Scognet 2086129198Scognet eva = va + L1_TABLE_SIZE; 2087129198Scognet pl1pt = (pd_entry_t *)va; 2088129198Scognet 2089135641Scognet while (va < eva) { 2090129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2091129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2092129198Scognet pte = *ptep; 2093129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2094129198Scognet *ptep = pte; 2095129198Scognet PTE_SYNC(ptep); 2096129198Scognet cpu_tlb_flushD_SE(va); 2097129198Scognet 2098129198Scognet va += PAGE_SIZE; 2099129198Scognet } 2100129198Scognet pmap_init_l1(l1, pl1pt); 2101129198Scognet } 2102129198Scognet 2103129198Scognet 2104129198Scognet#ifdef DEBUG 2105129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2106129198Scognet needed); 2107129198Scognet#endif 2108129198Scognet} 2109129198Scognet 2110129198Scognet/* 2111129198Scognet * This is used to stuff certain critical values into the PCB where they 2112129198Scognet * can be accessed quickly from cpu_switch() et al. 2113129198Scognet */ 2114129198Scognetvoid 2115129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2116129198Scognet{ 2117129198Scognet struct l2_bucket *l2b; 2118129198Scognet 2119129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2120129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2121129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2122129198Scognet 2123129198Scognet if (vector_page < KERNBASE) { 2124129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2125129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2126129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2127145071Scognet L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2128129198Scognet } else 2129129198Scognet pcb->pcb_pl1vec = NULL; 2130129198Scognet} 2131129198Scognet 2132129198Scognetvoid 2133129198Scognetpmap_activate(struct thread *td) 2134129198Scognet{ 2135129198Scognet pmap_t pm; 2136129198Scognet struct pcb *pcb; 2137129198Scognet 2138135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2139129198Scognet pcb = td->td_pcb; 2140129198Scognet 2141129198Scognet critical_enter(); 2142129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2143129198Scognet 2144129198Scognet if (td == curthread) { 2145129198Scognet u_int cur_dacr, cur_ttb; 2146129198Scognet 2147129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2148129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2149129198Scognet 2150129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2151129198Scognet 2152129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2153129198Scognet cur_dacr == pcb->pcb_dacr) { 2154129198Scognet /* 2155129198Scognet * No need to switch address spaces. 2156129198Scognet */ 2157129198Scognet critical_exit(); 2158129198Scognet return; 2159129198Scognet } 2160129198Scognet 2161129198Scognet 2162129198Scognet /* 2163129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2164129198Scognet * to 'vector_page' in the incoming L1 table before switching 2165129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2166129198Scognet * domain faults!) will jump into hyperspace. 2167129198Scognet */ 2168129198Scognet if (pcb->pcb_pl1vec) { 2169129198Scognet 2170129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2171129198Scognet /* 2172129198Scognet * Don't need to PTE_SYNC() at this point since 2173129198Scognet * cpu_setttb() is about to flush both the cache 2174129198Scognet * and the TLB. 2175129198Scognet */ 2176129198Scognet } 2177129198Scognet 2178129198Scognet cpu_domains(pcb->pcb_dacr); 2179129198Scognet cpu_setttb(pcb->pcb_pagedir); 2180129198Scognet } 2181129198Scognet critical_exit(); 2182129198Scognet} 2183129198Scognet 2184129198Scognetstatic int 2185129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2186129198Scognet{ 2187129198Scognet pd_entry_t *pdep, pde; 2188129198Scognet pt_entry_t *ptep, pte; 2189129198Scognet vm_offset_t pa; 2190129198Scognet int rv = 0; 2191129198Scognet 2192129198Scognet /* 2193129198Scognet * Make sure the descriptor itself has the correct cache mode 2194129198Scognet */ 2195129198Scognet pdep = &kl1[L1_IDX(va)]; 2196129198Scognet pde = *pdep; 2197129198Scognet 2198129198Scognet if (l1pte_section_p(pde)) { 2199129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2200129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2201129198Scognet pte_l1_s_cache_mode_pt; 2202129198Scognet PTE_SYNC(pdep); 2203129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2204129198Scognet sizeof(*pdep)); 2205183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)pdep, 2206183838Sraj sizeof(*pdep)); 2207129198Scognet rv = 1; 2208129198Scognet } 2209129198Scognet } else { 2210129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2211129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2212129198Scognet if (ptep == NULL) 2213129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2214129198Scognet 2215129198Scognet ptep = &ptep[l2pte_index(va)]; 2216129198Scognet pte = *ptep; 2217129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2218129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2219129198Scognet pte_l2_s_cache_mode_pt; 2220129198Scognet PTE_SYNC(ptep); 2221129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2222129198Scognet sizeof(*ptep)); 2223183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)ptep, 2224183838Sraj sizeof(*ptep)); 2225129198Scognet rv = 1; 2226129198Scognet } 2227129198Scognet } 2228129198Scognet 2229129198Scognet return (rv); 2230129198Scognet} 2231129198Scognet 2232129198Scognetstatic void 2233236991Simppmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2234129198Scognet pt_entry_t **ptep) 2235129198Scognet{ 2236129198Scognet vm_offset_t va = *availp; 2237129198Scognet struct l2_bucket *l2b; 2238129198Scognet 2239129198Scognet if (ptep) { 2240129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2241129198Scognet if (l2b == NULL) 2242129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2243129198Scognet 2244129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2245129198Scognet } 2246129198Scognet 2247129198Scognet *vap = va; 2248129198Scognet *availp = va + (PAGE_SIZE * pages); 2249129198Scognet} 2250129198Scognet 2251129198Scognet/* 2252129198Scognet * Bootstrap the system enough to run with virtual memory. 2253129198Scognet * 2254129198Scognet * On the arm this is called after mapping has already been enabled 2255129198Scognet * and just syncs the pmap module with what has already been done. 2256129198Scognet * [We can't call it easily with mapping off since the kernel is not 2257129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2258129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2259129198Scognet * (physical) address starting relative to 0] 2260129198Scognet */ 2261129198Scognet#define PMAP_STATIC_L2_SIZE 16 2262147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2263147114Scognetextern struct mtx smallalloc_mtx; 2264147114Scognet#endif 2265147114Scognet 2266129198Scognetvoid 2267247046Salcpmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt) 2268129198Scognet{ 2269129198Scognet static struct l1_ttable static_l1; 2270129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2271129198Scognet struct l1_ttable *l1 = &static_l1; 2272129198Scognet struct l2_dtable *l2; 2273129198Scognet struct l2_bucket *l2b; 2274129198Scognet pd_entry_t pde; 2275129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2276129198Scognet pt_entry_t *ptep; 2277129198Scognet vm_paddr_t pa; 2278129198Scognet vm_offset_t va; 2279135641Scognet vm_size_t size; 2280129198Scognet int l1idx, l2idx, l2next = 0; 2281129198Scognet 2282197770Sstas PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n", 2283247046Salc firstaddr, vm_max_kernel_address)); 2284129198Scognet 2285129198Scognet virtual_avail = firstaddr; 2286129198Scognet kernel_pmap->pm_l1 = l1; 2287150865Scognet kernel_l1pa = l1pt->pv_pa; 2288143192Scognet 2289143192Scognet /* 2290129198Scognet * Scan the L1 translation table created by initarm() and create 2291129198Scognet * the required metadata for all valid mappings found in it. 2292129198Scognet */ 2293129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2294129198Scognet pde = kernel_l1pt[l1idx]; 2295129198Scognet 2296129198Scognet /* 2297129198Scognet * We're only interested in Coarse mappings. 2298129198Scognet * pmap_extract() can deal with section mappings without 2299129198Scognet * recourse to checking L2 metadata. 2300129198Scognet */ 2301129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2302129198Scognet continue; 2303129198Scognet 2304129198Scognet /* 2305129198Scognet * Lookup the KVA of this L2 descriptor table 2306129198Scognet */ 2307129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2308129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2309129198Scognet 2310129198Scognet if (ptep == NULL) { 2311129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2312129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2313129198Scognet } 2314129198Scognet 2315129198Scognet /* 2316129198Scognet * Fetch the associated L2 metadata structure. 2317129198Scognet * Allocate a new one if necessary. 2318129198Scognet */ 2319129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2320129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2321129198Scognet panic("pmap_bootstrap: out of static L2s"); 2322236991Simp kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2323129198Scognet &static_l2[l2next++]; 2324129198Scognet } 2325129198Scognet 2326129198Scognet /* 2327129198Scognet * One more L1 slot tracked... 2328129198Scognet */ 2329129198Scognet l2->l2_occupancy++; 2330129198Scognet 2331129198Scognet /* 2332129198Scognet * Fill in the details of the L2 descriptor in the 2333129198Scognet * appropriate bucket. 2334129198Scognet */ 2335129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2336129198Scognet l2b->l2b_kva = ptep; 2337129198Scognet l2b->l2b_phys = pa; 2338129198Scognet l2b->l2b_l1idx = l1idx; 2339129198Scognet 2340129198Scognet /* 2341129198Scognet * Establish an initial occupancy count for this descriptor 2342129198Scognet */ 2343129198Scognet for (l2idx = 0; 2344129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2345129198Scognet l2idx++) { 2346129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2347129198Scognet l2b->l2b_occupancy++; 2348129198Scognet } 2349129198Scognet } 2350129198Scognet 2351129198Scognet /* 2352129198Scognet * Make sure the descriptor itself has the correct cache mode. 2353129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2354129198Scognet * should consider this a clue to fix up their initarm() 2355129198Scognet * function. :) 2356129198Scognet */ 2357129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2358129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2359129198Scognet "L2 pte @ %p\n", ptep); 2360129198Scognet } 2361129198Scognet } 2362129198Scognet 2363129198Scognet 2364129198Scognet /* 2365129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2366129198Scognet * a page table. Bitch if it is not correctly set. 2367129198Scognet */ 2368129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2369129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2370129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2371129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2372129198Scognet "primary L1 @ 0x%x\n", va); 2373129198Scognet } 2374129198Scognet 2375129198Scognet cpu_dcache_wbinv_all(); 2376183838Sraj cpu_l2cache_wbinv_all(); 2377129198Scognet cpu_tlb_flushID(); 2378129198Scognet cpu_cpwait(); 2379129198Scognet 2380159325Salc PMAP_LOCK_INIT(kernel_pmap); 2381222813Sattilio CPU_FILL(&kernel_pmap->pm_active); 2382129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2383144760Scognet TAILQ_INIT(&kernel_pmap->pm_pvlist); 2384239934Salc 2385239934Salc /* 2386239934Salc * Initialize the global pv list lock. 2387239934Salc */ 2388239934Salc rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE); 2389129198Scognet 2390129198Scognet /* 2391129198Scognet * Reserve some special page table entries/VA space for temporary 2392129198Scognet * mapping of pages. 2393129198Scognet */ 2394129198Scognet#define SYSMAP(c, p, v, n) \ 2395129198Scognet v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2396236991Simp 2397129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2398129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2399129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2400129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2401247046Salc size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) / 2402247046Salc L1_S_SIZE; 2403135641Scognet pmap_alloc_specials(&virtual_avail, 2404135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2405135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2406135641Scognet 2407135641Scognet size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2408135641Scognet pmap_alloc_specials(&virtual_avail, 2409135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2410135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2411135641Scognet 2412137362Scognet pmap_alloc_specials(&virtual_avail, 2413137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2414184728Sraj pmap_alloc_specials(&virtual_avail, 2415184728Sraj MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL); 2416135641Scognet SLIST_INIT(&l1_list); 2417129198Scognet TAILQ_INIT(&l1_lru_list); 2418129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2419129198Scognet pmap_init_l1(l1, kernel_l1pt); 2420129198Scognet cpu_dcache_wbinv_all(); 2421183838Sraj cpu_l2cache_wbinv_all(); 2422129198Scognet 2423129198Scognet virtual_avail = round_page(virtual_avail); 2424247046Salc virtual_end = vm_max_kernel_address; 2425135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2426247046Salc arm_nocache_startaddr = vm_max_kernel_address; 2427159088Scognet mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 2428156191Scognet 2429147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2430147114Scognet mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF); 2431161105Scognet arm_init_smallalloc(); 2432147114Scognet#endif 2433161105Scognet pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); 2434129198Scognet} 2435129198Scognet 2436129198Scognet/*************************************************** 2437129198Scognet * Pmap allocation/deallocation routines. 2438129198Scognet ***************************************************/ 2439129198Scognet 2440129198Scognet/* 2441129198Scognet * Release any resources held by the given physical map. 2442129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2443129198Scognet * Should only be called if the map contains no valid mappings. 2444129198Scognet */ 2445129198Scognetvoid 2446129198Scognetpmap_release(pmap_t pmap) 2447129198Scognet{ 2448135641Scognet struct pcb *pcb; 2449135641Scognet 2450135641Scognet pmap_idcache_wbinv_all(pmap); 2451183838Sraj cpu_l2cache_wbinv_all(); 2452135641Scognet pmap_tlb_flushID(pmap); 2453135641Scognet cpu_cpwait(); 2454135641Scognet if (vector_page < KERNBASE) { 2455135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2456135641Scognet pcb = thread0.td_pcb; 2457135641Scognet if (pmap_is_current(pmap)) { 2458135641Scognet /* 2459135641Scognet * Frob the L1 entry corresponding to the vector 2460135641Scognet * page so that it contains the kernel pmap's domain 2461135641Scognet * number. This will ensure pmap_remove() does not 2462135641Scognet * pull the current vector page out from under us. 2463135641Scognet */ 2464135641Scognet critical_enter(); 2465135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2466135641Scognet cpu_domains(pcb->pcb_dacr); 2467135641Scognet cpu_setttb(pcb->pcb_pagedir); 2468135641Scognet critical_exit(); 2469135641Scognet } 2470135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2471135641Scognet /* 2472135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2473135641Scognet * since this process has no remaining mappings of its own. 2474135641Scognet */ 2475135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2476135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2477135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2478135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2479135641Scognet 2480135641Scognet } 2481129198Scognet pmap_free_l1(pmap); 2482135641Scognet 2483129198Scognet dprintf("pmap_release()\n"); 2484129198Scognet} 2485129198Scognet 2486129198Scognet 2487135641Scognet 2488129198Scognet/* 2489135641Scognet * Helper function for pmap_grow_l2_bucket() 2490135641Scognet */ 2491135641Scognetstatic __inline int 2492135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2493135641Scognet{ 2494135641Scognet struct l2_bucket *l2b; 2495135641Scognet pt_entry_t *ptep; 2496135641Scognet vm_paddr_t pa; 2497135641Scognet struct vm_page *pg; 2498135641Scognet 2499150865Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2500135641Scognet if (pg == NULL) 2501135641Scognet return (1); 2502135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2503135641Scognet 2504135641Scognet if (pap) 2505135641Scognet *pap = pa; 2506135641Scognet 2507135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2508135641Scognet 2509135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2510135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2511135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2512135641Scognet PTE_SYNC(ptep); 2513135641Scognet return (0); 2514135641Scognet} 2515135641Scognet 2516135641Scognet/* 2517135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2518135641Scognet * used by pmap_growkernel(). 2519135641Scognet */ 2520135641Scognetstatic __inline struct l2_bucket * 2521135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2522135641Scognet{ 2523135641Scognet struct l2_dtable *l2; 2524135641Scognet struct l2_bucket *l2b; 2525135641Scognet struct l1_ttable *l1; 2526135641Scognet pd_entry_t *pl1pd; 2527135641Scognet u_short l1idx; 2528135641Scognet vm_offset_t nva; 2529135641Scognet 2530135641Scognet l1idx = L1_IDX(va); 2531135641Scognet 2532135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2533135641Scognet /* 2534135641Scognet * No mapping at this address, as there is 2535135641Scognet * no entry in the L1 table. 2536135641Scognet * Need to allocate a new l2_dtable. 2537135641Scognet */ 2538135641Scognet nva = pmap_kernel_l2dtable_kva; 2539135641Scognet if ((nva & PAGE_MASK) == 0) { 2540135641Scognet /* 2541135641Scognet * Need to allocate a backing page 2542135641Scognet */ 2543135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2544135641Scognet return (NULL); 2545135641Scognet } 2546135641Scognet 2547135641Scognet l2 = (struct l2_dtable *)nva; 2548135641Scognet nva += sizeof(struct l2_dtable); 2549135641Scognet 2550236991Simp if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2551135641Scognet PAGE_MASK)) { 2552135641Scognet /* 2553135641Scognet * The new l2_dtable straddles a page boundary. 2554135641Scognet * Map in another page to cover it. 2555135641Scognet */ 2556135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2557135641Scognet return (NULL); 2558135641Scognet } 2559135641Scognet 2560135641Scognet pmap_kernel_l2dtable_kva = nva; 2561135641Scognet 2562135641Scognet /* 2563135641Scognet * Link it into the parent pmap 2564135641Scognet */ 2565135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2566150865Scognet memset(l2, 0, sizeof(*l2)); 2567135641Scognet } 2568135641Scognet 2569135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2570135641Scognet 2571135641Scognet /* 2572135641Scognet * Fetch pointer to the L2 page table associated with the address. 2573135641Scognet */ 2574135641Scognet if (l2b->l2b_kva == NULL) { 2575135641Scognet pt_entry_t *ptep; 2576135641Scognet 2577135641Scognet /* 2578135641Scognet * No L2 page table has been allocated. Chances are, this 2579135641Scognet * is because we just allocated the l2_dtable, above. 2580135641Scognet */ 2581135641Scognet nva = pmap_kernel_l2ptp_kva; 2582135641Scognet ptep = (pt_entry_t *)nva; 2583135641Scognet if ((nva & PAGE_MASK) == 0) { 2584135641Scognet /* 2585135641Scognet * Need to allocate a backing page 2586135641Scognet */ 2587135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2588135641Scognet &pmap_kernel_l2ptp_phys)) 2589135641Scognet return (NULL); 2590135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2591135641Scognet } 2592150865Scognet memset(ptep, 0, L2_TABLE_SIZE_REAL); 2593135641Scognet l2->l2_occupancy++; 2594135641Scognet l2b->l2b_kva = ptep; 2595135641Scognet l2b->l2b_l1idx = l1idx; 2596135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2597135641Scognet 2598135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2599135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2600135641Scognet } 2601135641Scognet 2602135641Scognet /* Distribute new L1 entry to all other L1s */ 2603135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2604145071Scognet pl1pd = &l1->l1_kva[L1_IDX(va)]; 2605135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2606135641Scognet L1_C_PROTO; 2607135641Scognet PTE_SYNC(pl1pd); 2608135641Scognet } 2609135641Scognet 2610135641Scognet return (l2b); 2611135641Scognet} 2612135641Scognet 2613135641Scognet 2614135641Scognet/* 2615129198Scognet * grow the number of kernel page table entries, if needed 2616129198Scognet */ 2617129198Scognetvoid 2618129198Scognetpmap_growkernel(vm_offset_t addr) 2619129198Scognet{ 2620135641Scognet pmap_t kpm = pmap_kernel(); 2621129198Scognet 2622135641Scognet if (addr <= pmap_curmaxkvaddr) 2623135641Scognet return; /* we are OK */ 2624135641Scognet 2625135641Scognet /* 2626135641Scognet * whoops! we need to add kernel PTPs 2627135641Scognet */ 2628135641Scognet 2629135641Scognet /* Map 1MB at a time */ 2630135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2631135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2632135641Scognet 2633135641Scognet /* 2634135641Scognet * flush out the cache, expensive but growkernel will happen so 2635135641Scognet * rarely 2636135641Scognet */ 2637135641Scognet cpu_dcache_wbinv_all(); 2638183838Sraj cpu_l2cache_wbinv_all(); 2639135641Scognet cpu_tlb_flushD(); 2640135641Scognet cpu_cpwait(); 2641135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2642129198Scognet} 2643129198Scognet 2644129198Scognet 2645129198Scognet/* 2646129198Scognet * Remove all pages from specified address space 2647129198Scognet * this aids process exit speeds. Also, this code 2648129198Scognet * is special cased for current process only, but 2649129198Scognet * can have the more generic (and slightly slower) 2650129198Scognet * mode enabled. This is much faster than pmap_remove 2651129198Scognet * in the case of running down an entire address space. 2652129198Scognet */ 2653129198Scognetvoid 2654157443Speterpmap_remove_pages(pmap_t pmap) 2655129198Scognet{ 2656144760Scognet struct pv_entry *pv, *npv; 2657144760Scognet struct l2_bucket *l2b = NULL; 2658144760Scognet vm_page_t m; 2659144760Scognet pt_entry_t *pt; 2660144760Scognet 2661239934Salc rw_wlock(&pvh_global_lock); 2662159352Salc PMAP_LOCK(pmap); 2663175840Scognet cpu_idcache_wbinv_all(); 2664183838Sraj cpu_l2cache_wbinv_all(); 2665144760Scognet for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2666194459Sthompsa if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) { 2667194459Sthompsa /* Cannot remove wired or unmanaged pages now. */ 2668144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2669144760Scognet continue; 2670144760Scognet } 2671144760Scognet pmap->pm_stats.resident_count--; 2672144760Scognet l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2673144760Scognet KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2674144760Scognet pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2675144760Scognet m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2676164079Scognet#ifdef ARM_USE_SMALL_ALLOC 2677164079Scognet KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2678164079Scognet#else 2679164079Scognet KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2680164079Scognet#endif 2681144760Scognet *pt = 0; 2682144760Scognet PTE_SYNC(pt); 2683144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2684144760Scognet pmap_nuke_pv(m, pmap, pv); 2685150865Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 2686225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 2687144760Scognet pmap_free_pv_entry(pv); 2688164874Scognet pmap_free_l2_bucket(pmap, l2b, 1); 2689144760Scognet } 2690239934Salc rw_wunlock(&pvh_global_lock); 2691135641Scognet cpu_tlb_flushID(); 2692135641Scognet cpu_cpwait(); 2693159352Salc PMAP_UNLOCK(pmap); 2694129198Scognet} 2695129198Scognet 2696129198Scognet 2697129198Scognet/*************************************************** 2698129198Scognet * Low level mapping routines..... 2699129198Scognet ***************************************************/ 2700129198Scognet 2701171620Scognet#ifdef ARM_HAVE_SUPERSECTIONS 2702170582Scognet/* Map a super section into the KVA. */ 2703170582Scognet 2704170582Scognetvoid 2705170582Scognetpmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags) 2706170582Scognet{ 2707171620Scognet pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) | 2708171620Scognet (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL, 2709170582Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2710170582Scognet struct l1_ttable *l1; 2711171620Scognet vm_offset_t va0, va_end; 2712170582Scognet 2713170582Scognet KASSERT(((va | pa) & L1_SUP_OFFSET) == 0, 2714171620Scognet ("Not a valid super section mapping")); 2715170582Scognet if (flags & SECTION_CACHE) 2716170582Scognet pd |= pte_l1_s_cache_mode; 2717170582Scognet else if (flags & SECTION_PT) 2718170582Scognet pd |= pte_l1_s_cache_mode_pt; 2719171620Scognet va0 = va & L1_SUP_FRAME; 2720170582Scognet va_end = va + L1_SUP_SIZE; 2721170582Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2722171620Scognet va = va0; 2723170582Scognet for (; va < va_end; va += L1_S_SIZE) { 2724170582Scognet l1->l1_kva[L1_IDX(va)] = pd; 2725170582Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2726170582Scognet } 2727170582Scognet } 2728170582Scognet} 2729171620Scognet#endif 2730170582Scognet 2731147114Scognet/* Map a section into the KVA. */ 2732147114Scognet 2733147114Scognetvoid 2734147114Scognetpmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2735147114Scognet{ 2736147114Scognet pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2737147114Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2738147114Scognet struct l1_ttable *l1; 2739147114Scognet 2740147114Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2741147114Scognet ("Not a valid section mapping")); 2742147114Scognet if (flags & SECTION_CACHE) 2743147114Scognet pd |= pte_l1_s_cache_mode; 2744147114Scognet else if (flags & SECTION_PT) 2745147114Scognet pd |= pte_l1_s_cache_mode_pt; 2746147114Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2747147114Scognet l1->l1_kva[L1_IDX(va)] = pd; 2748147114Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2749147114Scognet } 2750147114Scognet} 2751147114Scognet 2752129198Scognet/* 2753184728Sraj * Make a temporary mapping for a physical address. This is only intended 2754184728Sraj * to be used for panic dumps. 2755184728Sraj */ 2756184728Srajvoid * 2757184728Srajpmap_kenter_temp(vm_paddr_t pa, int i) 2758184728Sraj{ 2759184728Sraj vm_offset_t va; 2760184728Sraj 2761184728Sraj va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 2762184728Sraj pmap_kenter(va, pa); 2763184728Sraj return ((void *)crashdumpmap); 2764184728Sraj} 2765184728Sraj 2766184728Sraj/* 2767129198Scognet * add a wired page to the kva 2768129198Scognet * note that in order for the mapping to take effect -- you 2769129198Scognet * should do a invltlb after doing the pmap_kenter... 2770129198Scognet */ 2771135641Scognetstatic PMAP_INLINE void 2772135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2773129198Scognet{ 2774129198Scognet struct l2_bucket *l2b; 2775129198Scognet pt_entry_t *pte; 2776129198Scognet pt_entry_t opte; 2777194459Sthompsa struct pv_entry *pve; 2778194459Sthompsa vm_page_t m; 2779194459Sthompsa 2780129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2781129198Scognet (uint32_t) va, (uint32_t) pa)); 2782129198Scognet 2783129198Scognet 2784129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2785135641Scognet if (l2b == NULL) 2786135641Scognet l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2787129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2788129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2789129198Scognet opte = *pte; 2790129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2791129198Scognet (uint32_t) pte, opte, *pte)); 2792129198Scognet if (l2pte_valid(opte)) { 2793194459Sthompsa pmap_kremove(va); 2794135641Scognet } else { 2795129198Scognet if (opte == 0) 2796129198Scognet l2b->l2b_occupancy++; 2797135641Scognet } 2798236991Simp *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2799135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2800135641Scognet if (flags & KENTER_CACHE) 2801135641Scognet *pte |= pte_l2_s_cache_mode; 2802142570Scognet if (flags & KENTER_USER) 2803142570Scognet *pte |= L2_S_PROT_U; 2804129198Scognet PTE_SYNC(pte); 2805194459Sthompsa 2806240166Salc /* 2807240166Salc * A kernel mapping may not be the page's only mapping, so create a PV 2808240166Salc * entry to ensure proper caching. 2809240166Salc * 2810240166Salc * The existence test for the pvzone is used to delay the recording of 2811240166Salc * kernel mappings until the VM system is fully initialized. 2812240166Salc * 2813240166Salc * This expects the physical memory to have a vm_page_array entry. 2814240166Salc */ 2815240166Salc if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) { 2816239934Salc rw_wlock(&pvh_global_lock); 2817240166Salc if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) { 2818194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 2819194459Sthompsa panic("pmap_kenter_internal: no pv entries"); 2820194459Sthompsa PMAP_LOCK(pmap_kernel()); 2821194459Sthompsa pmap_enter_pv(m, pve, pmap_kernel(), va, 2822198341Smarcel PVF_WRITE | PVF_UNMAN); 2823194459Sthompsa pmap_fix_cache(m, pmap_kernel(), va); 2824194459Sthompsa PMAP_UNLOCK(pmap_kernel()); 2825194459Sthompsa } else { 2826194459Sthompsa m->md.pv_kva = va; 2827194459Sthompsa } 2828239934Salc rw_wunlock(&pvh_global_lock); 2829194459Sthompsa } 2830135641Scognet} 2831129198Scognet 2832135641Scognetvoid 2833135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2834135641Scognet{ 2835135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2836129198Scognet} 2837129198Scognet 2838142570Scognetvoid 2839156191Scognetpmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2840156191Scognet{ 2841156191Scognet 2842156191Scognet pmap_kenter_internal(va, pa, 0); 2843156191Scognet} 2844156191Scognet 2845156191Scognetvoid 2846142570Scognetpmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2847142570Scognet{ 2848143192Scognet 2849142570Scognet pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2850143192Scognet /* 2851143192Scognet * Call pmap_fault_fixup now, to make sure we'll have no exception 2852143192Scognet * at the first use of the new address, or bad things will happen, 2853143192Scognet * as we use one of these addresses in the exception handlers. 2854143192Scognet */ 2855143192Scognet pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2856142570Scognet} 2857129198Scognet 2858240983Salcvm_paddr_t 2859240983Salcpmap_kextract(vm_offset_t va) 2860240983Salc{ 2861240983Salc 2862240983Salc return (pmap_extract_locked(kernel_pmap, va)); 2863240983Salc} 2864240983Salc 2865129198Scognet/* 2866194908Scognet * remove a page from the kernel pagetables 2867129198Scognet */ 2868169763Scognetvoid 2869129198Scognetpmap_kremove(vm_offset_t va) 2870129198Scognet{ 2871135641Scognet struct l2_bucket *l2b; 2872135641Scognet pt_entry_t *pte, opte; 2873194459Sthompsa struct pv_entry *pve; 2874194459Sthompsa vm_page_t m; 2875194459Sthompsa vm_offset_t pa; 2876135641Scognet 2877135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2878145071Scognet if (!l2b) 2879145071Scognet return; 2880135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2881135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2882135641Scognet opte = *pte; 2883135641Scognet if (l2pte_valid(opte)) { 2884194459Sthompsa /* pa = vtophs(va) taken from pmap_extract() */ 2885194459Sthompsa switch (opte & L2_TYPE_MASK) { 2886194459Sthompsa case L2_TYPE_L: 2887194459Sthompsa pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET); 2888194459Sthompsa break; 2889194459Sthompsa default: 2890194459Sthompsa pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET); 2891194459Sthompsa break; 2892194459Sthompsa } 2893194459Sthompsa /* note: should never have to remove an allocation 2894194459Sthompsa * before the pvzone is initialized. 2895194459Sthompsa */ 2896239934Salc rw_wlock(&pvh_global_lock); 2897194459Sthompsa PMAP_LOCK(pmap_kernel()); 2898194459Sthompsa if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) && 2899194459Sthompsa (pve = pmap_remove_pv(m, pmap_kernel(), va))) 2900236991Simp pmap_free_pv_entry(pve); 2901194459Sthompsa PMAP_UNLOCK(pmap_kernel()); 2902239934Salc rw_wunlock(&pvh_global_lock); 2903195779Sraj va = va & ~PAGE_MASK; 2904135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2905183838Sraj cpu_l2cache_wbinv_range(va, PAGE_SIZE); 2906135641Scognet cpu_tlb_flushD_SE(va); 2907135641Scognet cpu_cpwait(); 2908144760Scognet *pte = 0; 2909135641Scognet } 2910129198Scognet} 2911129198Scognet 2912129198Scognet 2913129198Scognet/* 2914129198Scognet * Used to map a range of physical addresses into kernel 2915129198Scognet * virtual address space. 2916129198Scognet * 2917129198Scognet * The value passed in '*virt' is a suggested virtual address for 2918129198Scognet * the mapping. Architectures which can support a direct-mapped 2919129198Scognet * physical to virtual region can return the appropriate address 2920129198Scognet * within that region, leaving '*virt' unchanged. Other 2921129198Scognet * architectures should map the pages starting at '*virt' and 2922129198Scognet * update '*virt' with the first usable address after the mapped 2923129198Scognet * region. 2924129198Scognet */ 2925129198Scognetvm_offset_t 2926129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2927129198Scognet{ 2928161105Scognet#ifdef ARM_USE_SMALL_ALLOC 2929161105Scognet return (arm_ptovirt(start)); 2930161105Scognet#else 2931129198Scognet vm_offset_t sva = *virt; 2932129198Scognet vm_offset_t va = sva; 2933129198Scognet 2934129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2935129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2936129198Scognet prot)); 2937236991Simp 2938129198Scognet while (start < end) { 2939129198Scognet pmap_kenter(va, start); 2940129198Scognet va += PAGE_SIZE; 2941129198Scognet start += PAGE_SIZE; 2942129198Scognet } 2943129198Scognet *virt = va; 2944129198Scognet return (sva); 2945161105Scognet#endif 2946129198Scognet} 2947129198Scognet 2948143724Scognetstatic void 2949150865Scognetpmap_wb_page(vm_page_t m) 2950143724Scognet{ 2951143724Scognet struct pv_entry *pv; 2952129198Scognet 2953143724Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2954150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2955144760Scognet (pv->pv_flags & PVF_WRITE) == 0); 2956143724Scognet} 2957143724Scognet 2958150865Scognetstatic void 2959150865Scognetpmap_inv_page(vm_page_t m) 2960150865Scognet{ 2961150865Scognet struct pv_entry *pv; 2962150865Scognet 2963150865Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2964150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2965150865Scognet} 2966129198Scognet/* 2967129198Scognet * Add a list of wired pages to the kva 2968129198Scognet * this routine is only used for temporary 2969129198Scognet * kernel mappings that do not need to have 2970129198Scognet * page modification or references recorded. 2971129198Scognet * Note that old mappings are simply written 2972129198Scognet * over. The page *must* be wired. 2973129198Scognet */ 2974129198Scognetvoid 2975129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2976129198Scognet{ 2977129198Scognet int i; 2978129198Scognet 2979129198Scognet for (i = 0; i < count; i++) { 2980150865Scognet pmap_wb_page(m[i]); 2981236991Simp pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 2982135641Scognet KENTER_CACHE); 2983129198Scognet va += PAGE_SIZE; 2984129198Scognet } 2985129198Scognet} 2986129198Scognet 2987129198Scognet 2988129198Scognet/* 2989129198Scognet * this routine jerks page mappings from the 2990129198Scognet * kernel -- it is meant only for temporary mappings. 2991129198Scognet */ 2992129198Scognetvoid 2993129198Scognetpmap_qremove(vm_offset_t va, int count) 2994129198Scognet{ 2995146596Scognet vm_paddr_t pa; 2996129198Scognet int i; 2997129198Scognet 2998129198Scognet for (i = 0; i < count; i++) { 2999146596Scognet pa = vtophys(va); 3000146596Scognet if (pa) { 3001150865Scognet pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 3002146596Scognet pmap_kremove(va); 3003146596Scognet } 3004129198Scognet va += PAGE_SIZE; 3005129198Scognet } 3006129198Scognet} 3007129198Scognet 3008129198Scognet 3009129198Scognet/* 3010129198Scognet * pmap_object_init_pt preloads the ptes for a given object 3011129198Scognet * into the specified pmap. This eliminates the blast of soft 3012129198Scognet * faults on process startup and immediately after an mmap. 3013129198Scognet */ 3014129198Scognetvoid 3015129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3016129198Scognet vm_pindex_t pindex, vm_size_t size) 3017129198Scognet{ 3018157156Scognet 3019248084Sattilio VM_OBJECT_ASSERT_WLOCKED(object); 3020195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3021157156Scognet ("pmap_object_init_pt: non-device object")); 3022129198Scognet} 3023129198Scognet 3024129198Scognet 3025129198Scognet/* 3026129198Scognet * pmap_is_prefaultable: 3027129198Scognet * 3028129198Scognet * Return whether or not the specified virtual address is elgible 3029129198Scognet * for prefault. 3030129198Scognet */ 3031129198Scognetboolean_t 3032129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3033129198Scognet{ 3034135641Scognet pd_entry_t *pde; 3035129198Scognet pt_entry_t *pte; 3036129198Scognet 3037135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 3038135641Scognet return (FALSE); 3039159073Scognet KASSERT(pte != NULL, ("Valid mapping but no pte ?")); 3040135641Scognet if (*pte == 0) 3041135641Scognet return (TRUE); 3042135641Scognet return (FALSE); 3043129198Scognet} 3044129198Scognet 3045129198Scognet/* 3046129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3047129198Scognet * Returns TRUE if the mapping exists, else FALSE. 3048129198Scognet * 3049129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 3050129198Scognet * It is not safe to take any pmap locks here, since we could be right 3051129198Scognet * in the middle of debugging the pmap anyway... 3052129198Scognet * 3053129198Scognet * It is possible for this routine to return FALSE even though a valid 3054129198Scognet * mapping does exist. This is because we don't lock, so the metadata 3055129198Scognet * state may be inconsistent. 3056129198Scognet * 3057129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3058129198Scognet * a "section" mapping. 3059129198Scognet */ 3060129198Scognetboolean_t 3061129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3062129198Scognet{ 3063129198Scognet struct l2_dtable *l2; 3064129198Scognet pd_entry_t *pl1pd, l1pd; 3065129198Scognet pt_entry_t *ptep; 3066129198Scognet u_short l1idx; 3067129198Scognet 3068129198Scognet if (pm->pm_l1 == NULL) 3069129198Scognet return (FALSE); 3070129198Scognet 3071129198Scognet l1idx = L1_IDX(va); 3072129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3073129198Scognet l1pd = *pl1pd; 3074129198Scognet 3075129198Scognet if (l1pte_section_p(l1pd)) { 3076129198Scognet *ptp = NULL; 3077129198Scognet return (TRUE); 3078129198Scognet } 3079129198Scognet 3080129198Scognet if (pm->pm_l2 == NULL) 3081129198Scognet return (FALSE); 3082129198Scognet 3083129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3084129198Scognet 3085129198Scognet if (l2 == NULL || 3086129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3087129198Scognet return (FALSE); 3088129198Scognet } 3089129198Scognet 3090129198Scognet *ptp = &ptep[l2pte_index(va)]; 3091129198Scognet return (TRUE); 3092129198Scognet} 3093129198Scognet 3094129198Scognet/* 3095129198Scognet * Routine: pmap_remove_all 3096129198Scognet * Function: 3097129198Scognet * Removes this physical page from 3098129198Scognet * all physical maps in which it resides. 3099129198Scognet * Reflects back modify bits to the pager. 3100129198Scognet * 3101129198Scognet * Notes: 3102129198Scognet * Original versions of this routine were very 3103129198Scognet * inefficient because they iteratively called 3104129198Scognet * pmap_remove (slow...) 3105129198Scognet */ 3106129198Scognetvoid 3107129198Scognetpmap_remove_all(vm_page_t m) 3108129198Scognet{ 3109129198Scognet pv_entry_t pv; 3110188019Scognet pt_entry_t *ptep; 3111135641Scognet struct l2_bucket *l2b; 3112135641Scognet boolean_t flush = FALSE; 3113135641Scognet pmap_t curpm; 3114135641Scognet int flags = 0; 3115129198Scognet 3116224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3117223677Salc ("pmap_remove_all: page %p is not managed", m)); 3118135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3119135641Scognet return; 3120239934Salc rw_wlock(&pvh_global_lock); 3121175840Scognet pmap_remove_write(m); 3122135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3123129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3124135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3125135641Scognet pv->pv_pmap == pmap_kernel())) 3126135641Scognet flush = TRUE; 3127193712Sraj 3128159352Salc PMAP_LOCK(pv->pv_pmap); 3129193712Sraj /* 3130193712Sraj * Cached contents were written-back in pmap_remove_write(), 3131193712Sraj * but we still have to invalidate the cache entry to make 3132193712Sraj * sure stale data are not retrieved when another page will be 3133193712Sraj * mapped under this virtual address. 3134193712Sraj */ 3135193712Sraj if (pmap_is_current(pv->pv_pmap)) { 3136193712Sraj cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE); 3137203637Sraj if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va)) 3138203637Sraj cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE); 3139193712Sraj } 3140193712Sraj 3141194459Sthompsa if (pv->pv_flags & PVF_UNMAN) { 3142194459Sthompsa /* remove the pv entry, but do not remove the mapping 3143194459Sthompsa * and remember this is a kernel mapped page 3144194459Sthompsa */ 3145194459Sthompsa m->md.pv_kva = pv->pv_va; 3146194459Sthompsa } else { 3147194459Sthompsa /* remove the mapping and pv entry */ 3148194459Sthompsa l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3149194459Sthompsa KASSERT(l2b != NULL, ("No l2 bucket")); 3150194459Sthompsa ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3151194459Sthompsa *ptep = 0; 3152194459Sthompsa PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3153194459Sthompsa pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3154194459Sthompsa pv->pv_pmap->pm_stats.resident_count--; 3155194459Sthompsa flags |= pv->pv_flags; 3156194459Sthompsa } 3157135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3158159352Salc PMAP_UNLOCK(pv->pv_pmap); 3159129198Scognet pmap_free_pv_entry(pv); 3160129198Scognet } 3161129198Scognet 3162135641Scognet if (flush) { 3163135641Scognet if (PV_BEEN_EXECD(flags)) 3164135641Scognet pmap_tlb_flushID(curpm); 3165135641Scognet else 3166135641Scognet pmap_tlb_flushD(curpm); 3167135641Scognet } 3168225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 3169239934Salc rw_wunlock(&pvh_global_lock); 3170129198Scognet} 3171129198Scognet 3172129198Scognet 3173129198Scognet/* 3174129198Scognet * Set the physical protection on the 3175129198Scognet * specified range of this map as requested. 3176129198Scognet */ 3177129198Scognetvoid 3178129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3179129198Scognet{ 3180129198Scognet struct l2_bucket *l2b; 3181129198Scognet pt_entry_t *ptep, pte; 3182129198Scognet vm_offset_t next_bucket; 3183129198Scognet u_int flags; 3184129198Scognet int flush; 3185129198Scognet 3186183838Sraj CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x", 3187183838Sraj pm, sva, eva, prot); 3188183838Sraj 3189129198Scognet if ((prot & VM_PROT_READ) == 0) { 3190129198Scognet pmap_remove(pm, sva, eva); 3191129198Scognet return; 3192129198Scognet } 3193129198Scognet 3194129198Scognet if (prot & VM_PROT_WRITE) { 3195129198Scognet /* 3196129198Scognet * If this is a read->write transition, just ignore it and let 3197135641Scognet * vm_fault() take care of it later. 3198129198Scognet */ 3199129198Scognet return; 3200129198Scognet } 3201129198Scognet 3202239934Salc rw_wlock(&pvh_global_lock); 3203159352Salc PMAP_LOCK(pm); 3204129198Scognet 3205129198Scognet /* 3206129198Scognet * OK, at this point, we know we're doing write-protect operation. 3207129198Scognet * If the pmap is active, write-back the range. 3208129198Scognet */ 3209129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3210129198Scognet 3211129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3212129198Scognet flags = 0; 3213129198Scognet 3214129198Scognet while (sva < eva) { 3215129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3216129198Scognet if (next_bucket > eva) 3217129198Scognet next_bucket = eva; 3218129198Scognet 3219129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3220129198Scognet if (l2b == NULL) { 3221129198Scognet sva = next_bucket; 3222129198Scognet continue; 3223129198Scognet } 3224129198Scognet 3225129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3226129198Scognet 3227129198Scognet while (sva < next_bucket) { 3228129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3229129198Scognet struct vm_page *pg; 3230129198Scognet u_int f; 3231129198Scognet 3232129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3233129198Scognet pte &= ~L2_S_PROT_W; 3234129198Scognet *ptep = pte; 3235129198Scognet PTE_SYNC(ptep); 3236129198Scognet 3237239268Sgonzo if (!(pg->oflags & VPO_UNMANAGED)) { 3238239268Sgonzo f = pmap_modify_pv(pg, pm, sva, 3239239268Sgonzo PVF_WRITE, 0); 3240239268Sgonzo if (f & PVF_WRITE) 3241224049Smarcel vm_page_dirty(pg); 3242129198Scognet } else 3243239268Sgonzo f = 0; 3244129198Scognet 3245129198Scognet if (flush >= 0) { 3246129198Scognet flush++; 3247129198Scognet flags |= f; 3248129198Scognet } else 3249129198Scognet if (PV_BEEN_EXECD(f)) 3250129198Scognet pmap_tlb_flushID_SE(pm, sva); 3251129198Scognet else 3252129198Scognet if (PV_BEEN_REFD(f)) 3253129198Scognet pmap_tlb_flushD_SE(pm, sva); 3254129198Scognet } 3255129198Scognet 3256129198Scognet sva += PAGE_SIZE; 3257129198Scognet ptep++; 3258129198Scognet } 3259129198Scognet } 3260129198Scognet 3261129198Scognet 3262129198Scognet if (flush) { 3263129198Scognet if (PV_BEEN_EXECD(flags)) 3264129198Scognet pmap_tlb_flushID(pm); 3265129198Scognet else 3266129198Scognet if (PV_BEEN_REFD(flags)) 3267129198Scognet pmap_tlb_flushD(pm); 3268129198Scognet } 3269239934Salc rw_wunlock(&pvh_global_lock); 3270129198Scognet 3271159352Salc PMAP_UNLOCK(pm); 3272129198Scognet} 3273129198Scognet 3274129198Scognet 3275129198Scognet/* 3276129198Scognet * Insert the given physical page (p) at 3277129198Scognet * the specified virtual address (v) in the 3278129198Scognet * target physical map with the protection requested. 3279129198Scognet * 3280129198Scognet * If specified, the page will be wired down, meaning 3281129198Scognet * that the related pte can not be reclaimed. 3282129198Scognet * 3283129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3284129198Scognet * or lose information. That is, this routine must actually 3285129198Scognet * insert this page into the given map NOW. 3286129198Scognet */ 3287135641Scognet 3288129198Scognetvoid 3289175067Salcpmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3290175067Salc vm_prot_t prot, boolean_t wired) 3291129198Scognet{ 3292159127Salc 3293239934Salc rw_wlock(&pvh_global_lock); 3294159352Salc PMAP_LOCK(pmap); 3295160260Scognet pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK); 3296239934Salc rw_wunlock(&pvh_global_lock); 3297159352Salc PMAP_UNLOCK(pmap); 3298159127Salc} 3299159127Salc 3300159127Salc/* 3301240803Salc * The pvh global and pmap locks must be held. 3302159127Salc */ 3303159127Salcstatic void 3304159127Salcpmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3305160260Scognet boolean_t wired, int flags) 3306159127Salc{ 3307135641Scognet struct l2_bucket *l2b = NULL; 3308129198Scognet struct vm_page *opg; 3309144760Scognet struct pv_entry *pve = NULL; 3310129198Scognet pt_entry_t *ptep, npte, opte; 3311129198Scognet u_int nflags; 3312129198Scognet u_int oflags; 3313129198Scognet vm_paddr_t pa; 3314129198Scognet 3315159325Salc PMAP_ASSERT_LOCKED(pmap); 3316239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 3317129198Scognet if (va == vector_page) { 3318129198Scognet pa = systempage.pv_pa; 3319129198Scognet m = NULL; 3320208688Salc } else { 3321254138Sattilio KASSERT((m->oflags & VPO_UNMANAGED) != 0 || 3322254138Sattilio vm_page_xbusied(m) || (flags & M_NOWAIT) != 0, 3323208688Salc ("pmap_enter_locked: page %p is not busy", m)); 3324129198Scognet pa = VM_PAGE_TO_PHYS(m); 3325208688Salc } 3326129198Scognet nflags = 0; 3327129198Scognet if (prot & VM_PROT_WRITE) 3328129198Scognet nflags |= PVF_WRITE; 3329129198Scognet if (prot & VM_PROT_EXECUTE) 3330129198Scognet nflags |= PVF_EXEC; 3331129198Scognet if (wired) 3332129198Scognet nflags |= PVF_WIRED; 3333129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3334129198Scognet "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3335236991Simp 3336135641Scognet if (pmap == pmap_kernel()) { 3337129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3338135641Scognet if (l2b == NULL) 3339135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3340160260Scognet } else { 3341160260Scognetdo_l2b_alloc: 3342129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3343160260Scognet if (l2b == NULL) { 3344160260Scognet if (flags & M_WAITOK) { 3345160260Scognet PMAP_UNLOCK(pmap); 3346239934Salc rw_wunlock(&pvh_global_lock); 3347160260Scognet VM_WAIT; 3348239934Salc rw_wlock(&pvh_global_lock); 3349160260Scognet PMAP_LOCK(pmap); 3350160260Scognet goto do_l2b_alloc; 3351160260Scognet } 3352160260Scognet return; 3353160260Scognet } 3354160260Scognet } 3355160260Scognet 3356129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3357236991Simp 3358135641Scognet opte = *ptep; 3359129198Scognet npte = pa; 3360129198Scognet oflags = 0; 3361129198Scognet if (opte) { 3362129198Scognet /* 3363129198Scognet * There is already a mapping at this address. 3364129198Scognet * If the physical address is different, lookup the 3365129198Scognet * vm_page. 3366129198Scognet */ 3367129198Scognet if (l2pte_pa(opte) != pa) 3368129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3369129198Scognet else 3370129198Scognet opg = m; 3371129198Scognet } else 3372129198Scognet opg = NULL; 3373129198Scognet 3374135641Scognet if ((prot & (VM_PROT_ALL)) || 3375135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3376129198Scognet /* 3377135641Scognet * - The access type indicates that we don't need 3378135641Scognet * to do referenced emulation. 3379135641Scognet * OR 3380135641Scognet * - The physical page has already been referenced 3381135641Scognet * so no need to re-do referenced emulation here. 3382129198Scognet */ 3383135641Scognet npte |= L2_S_PROTO; 3384135641Scognet 3385135641Scognet nflags |= PVF_REF; 3386135641Scognet 3387144760Scognet if (m && ((prot & VM_PROT_WRITE) != 0 || 3388144760Scognet (m->md.pvh_attrs & PVF_MOD))) { 3389129198Scognet /* 3390135641Scognet * This is a writable mapping, and the 3391135641Scognet * page's mod state indicates it has 3392135641Scognet * already been modified. Make it 3393135641Scognet * writable from the outset. 3394129198Scognet */ 3395135641Scognet nflags |= PVF_MOD; 3396157970Scognet if (!(m->md.pvh_attrs & PVF_MOD)) 3397144760Scognet vm_page_dirty(m); 3398129198Scognet } 3399144760Scognet if (m && opte) 3400225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 3401135641Scognet } else { 3402135641Scognet /* 3403135641Scognet * Need to do page referenced emulation. 3404135641Scognet */ 3405135641Scognet npte |= L2_TYPE_INV; 3406135641Scognet } 3407135641Scognet 3408164229Salc if (prot & VM_PROT_WRITE) { 3409135641Scognet npte |= L2_S_PROT_W; 3410208846Salc if (m != NULL && 3411224746Skib (m->oflags & VPO_UNMANAGED) == 0) 3412225418Skib vm_page_aflag_set(m, PGA_WRITEABLE); 3413164229Salc } 3414244574Scognet if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 3415244414Scognet npte |= pte_l2_s_cache_mode; 3416135641Scognet if (m && m == opg) { 3417135641Scognet /* 3418135641Scognet * We're changing the attrs of an existing mapping. 3419135641Scognet */ 3420135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3421135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3422135641Scognet PVF_MOD | PVF_REF, nflags); 3423135641Scognet 3424135641Scognet /* 3425135641Scognet * We may need to flush the cache if we're 3426135641Scognet * doing rw-ro... 3427135641Scognet */ 3428135641Scognet if (pmap_is_current(pmap) && 3429135641Scognet (oflags & PVF_NC) == 0 && 3430183838Sraj (opte & L2_S_PROT_W) != 0 && 3431203637Sraj (prot & VM_PROT_WRITE) == 0 && 3432203637Sraj (opte & L2_TYPE_MASK) != L2_TYPE_INV) { 3433135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3434203637Sraj cpu_l2cache_wb_range(va, PAGE_SIZE); 3435183838Sraj } 3436129198Scognet } else { 3437129198Scognet /* 3438135641Scognet * New mapping, or changing the backing page 3439135641Scognet * of an existing mapping. 3440129198Scognet */ 3441129198Scognet if (opg) { 3442129198Scognet /* 3443135641Scognet * Replacing an existing mapping with a new one. 3444135641Scognet * It is part of our managed memory so we 3445135641Scognet * must remove it from the PV list 3446129198Scognet */ 3447194459Sthompsa if ((pve = pmap_remove_pv(opg, pmap, va))) { 3448194459Sthompsa 3449194459Sthompsa /* note for patch: the oflags/invalidation was moved 3450194459Sthompsa * because PG_FICTITIOUS pages could free the pve 3451194459Sthompsa */ 3452194459Sthompsa oflags = pve->pv_flags; 3453135641Scognet /* 3454135641Scognet * If the old mapping was valid (ref/mod 3455135641Scognet * emulation creates 'invalid' mappings 3456135641Scognet * initially) then make sure to frob 3457135641Scognet * the cache. 3458135641Scognet */ 3459194459Sthompsa if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 3460135641Scognet if (PV_BEEN_EXECD(oflags)) { 3461129198Scognet pmap_idcache_wbinv_range(pmap, va, 3462129198Scognet PAGE_SIZE); 3463135641Scognet } else 3464135641Scognet if (PV_BEEN_REFD(oflags)) { 3465135641Scognet pmap_dcache_wb_range(pmap, va, 3466135641Scognet PAGE_SIZE, TRUE, 3467135641Scognet (oflags & PVF_WRITE) == 0); 3468135641Scognet } 3469194459Sthompsa } 3470194459Sthompsa 3471194459Sthompsa /* free/allocate a pv_entry for UNMANAGED pages if 3472194459Sthompsa * this physical page is not/is already mapped. 3473194459Sthompsa */ 3474194459Sthompsa 3475224746Skib if (m && (m->oflags & VPO_UNMANAGED) && 3476194459Sthompsa !m->md.pv_kva && 3477224746Skib TAILQ_EMPTY(&m->md.pv_list)) { 3478194459Sthompsa pmap_free_pv_entry(pve); 3479194459Sthompsa pve = NULL; 3480194459Sthompsa } 3481224746Skib } else if (m && 3482224746Skib (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva || 3483194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3484194459Sthompsa pve = pmap_get_pv_entry(); 3485224746Skib } else if (m && 3486224746Skib (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva || 3487194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3488194459Sthompsa pve = pmap_get_pv_entry(); 3489194459Sthompsa 3490224746Skib if (m) { 3491224746Skib if ((m->oflags & VPO_UNMANAGED)) { 3492194459Sthompsa if (!TAILQ_EMPTY(&m->md.pv_list) || 3493224746Skib m->md.pv_kva) { 3494194459Sthompsa KASSERT(pve != NULL, ("No pv")); 3495194459Sthompsa nflags |= PVF_UNMAN; 3496194459Sthompsa pmap_enter_pv(m, pve, pmap, va, nflags); 3497194459Sthompsa } else 3498194459Sthompsa m->md.pv_kva = va; 3499194459Sthompsa } else { 3500224746Skib KASSERT(va < kmi.clean_sva || 3501224746Skib va >= kmi.clean_eva, 3502224746Skib ("pmap_enter: managed mapping within the clean submap")); 3503224746Skib KASSERT(pve != NULL, ("No pv")); 3504224746Skib pmap_enter_pv(m, pve, pmap, va, nflags); 3505129198Scognet } 3506157970Scognet } 3507129198Scognet } 3508129198Scognet /* 3509129198Scognet * Make sure userland mappings get the right permissions 3510129198Scognet */ 3511129198Scognet if (pmap != pmap_kernel() && va != vector_page) { 3512129198Scognet npte |= L2_S_PROT_U; 3513129198Scognet } 3514129198Scognet 3515129198Scognet /* 3516129198Scognet * Keep the stats up to date 3517129198Scognet */ 3518129198Scognet if (opte == 0) { 3519129198Scognet l2b->l2b_occupancy++; 3520129198Scognet pmap->pm_stats.resident_count++; 3521236991Simp } 3522129198Scognet 3523129198Scognet /* 3524129198Scognet * If this is just a wiring change, the two PTEs will be 3525129198Scognet * identical, so there's no need to update the page table. 3526129198Scognet */ 3527129198Scognet if (npte != opte) { 3528135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3529129198Scognet 3530129198Scognet *ptep = npte; 3531129198Scognet if (is_cached) { 3532129198Scognet /* 3533129198Scognet * We only need to frob the cache/tlb if this pmap 3534129198Scognet * is current 3535129198Scognet */ 3536129198Scognet PTE_SYNC(ptep); 3537236991Simp if (L1_IDX(va) != L1_IDX(vector_page) && 3538129198Scognet l2pte_valid(npte)) { 3539129198Scognet /* 3540129198Scognet * This mapping is likely to be accessed as 3541129198Scognet * soon as we return to userland. Fix up the 3542129198Scognet * L1 entry to avoid taking another 3543129198Scognet * page/domain fault. 3544129198Scognet */ 3545129198Scognet pd_entry_t *pl1pd, l1pd; 3546129198Scognet 3547129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3548129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3549144760Scognet L1_C_PROTO; 3550129198Scognet if (*pl1pd != l1pd) { 3551129198Scognet *pl1pd = l1pd; 3552129198Scognet PTE_SYNC(pl1pd); 3553129198Scognet } 3554129198Scognet } 3555129198Scognet } 3556129198Scognet 3557129198Scognet if (PV_BEEN_EXECD(oflags)) 3558129198Scognet pmap_tlb_flushID_SE(pmap, va); 3559135641Scognet else if (PV_BEEN_REFD(oflags)) 3560129198Scognet pmap_tlb_flushD_SE(pmap, va); 3561129198Scognet 3562129198Scognet 3563157025Scognet if (m) 3564175840Scognet pmap_fix_cache(m, pmap, va); 3565129198Scognet } 3566129198Scognet} 3567129198Scognet 3568129198Scognet/* 3569159303Salc * Maps a sequence of resident pages belonging to the same object. 3570159303Salc * The sequence begins with the given page m_start. This page is 3571159303Salc * mapped at the given virtual address start. Each subsequent page is 3572159303Salc * mapped at a virtual address that is offset from start by the same 3573159303Salc * amount as the page is offset from m_start within the object. The 3574159303Salc * last page in the sequence is the page with the largest offset from 3575159303Salc * m_start that can be mapped at a virtual address less than the given 3576159303Salc * virtual address end. Not every virtual page between start and end 3577159303Salc * is mapped; only those for which a resident page exists with the 3578159303Salc * corresponding offset from m_start are mapped. 3579159303Salc */ 3580159303Salcvoid 3581159303Salcpmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3582159303Salc vm_page_t m_start, vm_prot_t prot) 3583159303Salc{ 3584159303Salc vm_page_t m; 3585159303Salc vm_pindex_t diff, psize; 3586159303Salc 3587250884Sattilio VM_OBJECT_ASSERT_LOCKED(m_start->object); 3588250884Sattilio 3589159303Salc psize = atop(end - start); 3590159303Salc m = m_start; 3591239934Salc rw_wlock(&pvh_global_lock); 3592159325Salc PMAP_LOCK(pmap); 3593159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3594159303Salc pmap_enter_locked(pmap, start + ptoa(diff), m, prot & 3595160260Scognet (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT); 3596159303Salc m = TAILQ_NEXT(m, listq); 3597159303Salc } 3598239934Salc rw_wunlock(&pvh_global_lock); 3599159325Salc PMAP_UNLOCK(pmap); 3600159303Salc} 3601159303Salc 3602159303Salc/* 3603129198Scognet * this code makes some *MAJOR* assumptions: 3604129198Scognet * 1. Current pmap & pmap exists. 3605129198Scognet * 2. Not wired. 3606129198Scognet * 3. Read access. 3607129198Scognet * 4. No page table pages. 3608129198Scognet * but is *MUCH* faster than pmap_enter... 3609129198Scognet */ 3610129198Scognet 3611159627Supsvoid 3612159627Supspmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3613129198Scognet{ 3614138897Salc 3615239934Salc rw_wlock(&pvh_global_lock); 3616159325Salc PMAP_LOCK(pmap); 3617159127Salc pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 3618160260Scognet FALSE, M_NOWAIT); 3619239934Salc rw_wunlock(&pvh_global_lock); 3620159325Salc PMAP_UNLOCK(pmap); 3621129198Scognet} 3622129198Scognet 3623129198Scognet/* 3624129198Scognet * Routine: pmap_change_wiring 3625129198Scognet * Function: Change the wiring attribute for a map/virtual-address 3626129198Scognet * pair. 3627129198Scognet * In/out conditions: 3628129198Scognet * The mapping must already exist in the pmap. 3629129198Scognet */ 3630129198Scognetvoid 3631129198Scognetpmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3632129198Scognet{ 3633129198Scognet struct l2_bucket *l2b; 3634129198Scognet pt_entry_t *ptep, pte; 3635129198Scognet vm_page_t pg; 3636129198Scognet 3637239934Salc rw_wlock(&pvh_global_lock); 3638159325Salc PMAP_LOCK(pmap); 3639129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3640129198Scognet KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3641129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3642129198Scognet pte = *ptep; 3643129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3644236991Simp if (pg) 3645221844Scognet pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired ? PVF_WIRED : 0); 3646239934Salc rw_wunlock(&pvh_global_lock); 3647159325Salc PMAP_UNLOCK(pmap); 3648129198Scognet} 3649129198Scognet 3650129198Scognet 3651129198Scognet/* 3652129198Scognet * Copy the range specified by src_addr/len 3653129198Scognet * from the source map to the range dst_addr/len 3654129198Scognet * in the destination map. 3655129198Scognet * 3656129198Scognet * This routine is only advisory and need not do anything. 3657129198Scognet */ 3658129198Scognetvoid 3659129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3660129198Scognet vm_size_t len, vm_offset_t src_addr) 3661129198Scognet{ 3662129198Scognet} 3663129198Scognet 3664129198Scognet 3665129198Scognet/* 3666129198Scognet * Routine: pmap_extract 3667129198Scognet * Function: 3668129198Scognet * Extract the physical page address associated 3669129198Scognet * with the given map/virtual_address pair. 3670129198Scognet */ 3671131658Salcvm_paddr_t 3672240983Salcpmap_extract(pmap_t pmap, vm_offset_t va) 3673129198Scognet{ 3674240983Salc vm_paddr_t pa; 3675240983Salc 3676240983Salc PMAP_LOCK(pmap); 3677240983Salc pa = pmap_extract_locked(pmap, va); 3678240983Salc PMAP_UNLOCK(pmap); 3679240983Salc return (pa); 3680240983Salc} 3681240983Salc 3682240983Salcstatic vm_paddr_t 3683240983Salcpmap_extract_locked(pmap_t pmap, vm_offset_t va) 3684240983Salc{ 3685129198Scognet struct l2_dtable *l2; 3686159450Salc pd_entry_t l1pd; 3687129198Scognet pt_entry_t *ptep, pte; 3688129198Scognet vm_paddr_t pa; 3689129198Scognet u_int l1idx; 3690240983Salc 3691240983Salc if (pmap != kernel_pmap) 3692240983Salc PMAP_ASSERT_LOCKED(pmap); 3693129198Scognet l1idx = L1_IDX(va); 3694240983Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3695129198Scognet if (l1pte_section_p(l1pd)) { 3696129198Scognet /* 3697240983Salc * These should only happen for the kernel pmap. 3698129198Scognet */ 3699240983Salc KASSERT(pmap == kernel_pmap, ("unexpected section")); 3700171620Scognet /* XXX: what to do about the bits > 32 ? */ 3701236991Simp if (l1pd & L1_S_SUPERSEC) 3702171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3703171620Scognet else 3704171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3705129198Scognet } else { 3706129198Scognet /* 3707129198Scognet * Note that we can't rely on the validity of the L1 3708129198Scognet * descriptor as an indication that a mapping exists. 3709129198Scognet * We have to look it up in the L2 dtable. 3710129198Scognet */ 3711240983Salc l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3712129198Scognet if (l2 == NULL || 3713240983Salc (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) 3714129198Scognet return (0); 3715240983Salc pte = ptep[l2pte_index(va)]; 3716240983Salc if (pte == 0) 3717129198Scognet return (0); 3718129198Scognet switch (pte & L2_TYPE_MASK) { 3719129198Scognet case L2_TYPE_L: 3720129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3721129198Scognet break; 3722129198Scognet default: 3723129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3724129198Scognet break; 3725129198Scognet } 3726129198Scognet } 3727129198Scognet return (pa); 3728129198Scognet} 3729129198Scognet 3730133453Salc/* 3731133453Salc * Atomically extract and hold the physical page with the given 3732133453Salc * pmap and virtual address pair if that mapping permits the given 3733133453Salc * protection. 3734133453Salc * 3735133453Salc */ 3736129198Scognetvm_page_t 3737129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3738129198Scognet{ 3739135641Scognet struct l2_dtable *l2; 3740159378Salc pd_entry_t l1pd; 3741135641Scognet pt_entry_t *ptep, pte; 3742207410Skmacy vm_paddr_t pa, paddr; 3743135641Scognet vm_page_t m = NULL; 3744135641Scognet u_int l1idx; 3745135641Scognet l1idx = L1_IDX(va); 3746207410Skmacy paddr = 0; 3747129198Scognet 3748159325Salc PMAP_LOCK(pmap); 3749207410Skmacyretry: 3750159378Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3751135641Scognet if (l1pte_section_p(l1pd)) { 3752135641Scognet /* 3753135641Scognet * These should only happen for pmap_kernel() 3754135641Scognet */ 3755135641Scognet KASSERT(pmap == pmap_kernel(), ("huh")); 3756171620Scognet /* XXX: what to do about the bits > 32 ? */ 3757236991Simp if (l1pd & L1_S_SUPERSEC) 3758171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3759171620Scognet else 3760171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3761207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3762207410Skmacy goto retry; 3763135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3764135641Scognet m = PHYS_TO_VM_PAGE(pa); 3765135641Scognet vm_page_hold(m); 3766135641Scognet } 3767135641Scognet 3768135641Scognet } else { 3769135641Scognet /* 3770135641Scognet * Note that we can't rely on the validity of the L1 3771135641Scognet * descriptor as an indication that a mapping exists. 3772135641Scognet * We have to look it up in the L2 dtable. 3773135641Scognet */ 3774135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3775135641Scognet 3776135641Scognet if (l2 == NULL || 3777135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3778159325Salc PMAP_UNLOCK(pmap); 3779135641Scognet return (NULL); 3780135641Scognet } 3781135641Scognet 3782135641Scognet ptep = &ptep[l2pte_index(va)]; 3783135641Scognet pte = *ptep; 3784135641Scognet 3785150865Scognet if (pte == 0) { 3786159325Salc PMAP_UNLOCK(pmap); 3787135641Scognet return (NULL); 3788150865Scognet } 3789135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3790135641Scognet switch (pte & L2_TYPE_MASK) { 3791135641Scognet case L2_TYPE_L: 3792135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3793135641Scognet break; 3794135641Scognet 3795135641Scognet default: 3796135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3797135641Scognet break; 3798135641Scognet } 3799207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3800207410Skmacy goto retry; 3801135641Scognet m = PHYS_TO_VM_PAGE(pa); 3802135641Scognet vm_page_hold(m); 3803135641Scognet } 3804129198Scognet } 3805135641Scognet 3806159325Salc PMAP_UNLOCK(pmap); 3807207410Skmacy PA_UNLOCK_COND(paddr); 3808129198Scognet return (m); 3809129198Scognet} 3810129198Scognet 3811129198Scognet/* 3812129198Scognet * Initialize a preallocated and zeroed pmap structure, 3813129198Scognet * such as one in a vmspace structure. 3814129198Scognet */ 3815129198Scognet 3816173361Skibint 3817129198Scognetpmap_pinit(pmap_t pmap) 3818129198Scognet{ 3819129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3820129198Scognet 3821129198Scognet pmap_alloc_l1(pmap); 3822129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3823129198Scognet 3824222813Sattilio CPU_ZERO(&pmap->pm_active); 3825129198Scognet 3826144760Scognet TAILQ_INIT(&pmap->pm_pvlist); 3827129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3828129198Scognet pmap->pm_stats.resident_count = 1; 3829129198Scognet if (vector_page < KERNBASE) { 3830175840Scognet pmap_enter(pmap, vector_page, 3831175397Scognet VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa), 3832129198Scognet VM_PROT_READ, 1); 3833236991Simp } 3834173361Skib return (1); 3835129198Scognet} 3836129198Scognet 3837129198Scognet 3838129198Scognet/*************************************************** 3839129198Scognet * page management routines. 3840129198Scognet ***************************************************/ 3841129198Scognet 3842129198Scognet 3843135641Scognetstatic void 3844129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3845129198Scognet{ 3846129198Scognet pv_entry_count--; 3847129198Scognet uma_zfree(pvzone, pv); 3848129198Scognet} 3849129198Scognet 3850129198Scognet 3851129198Scognet/* 3852129198Scognet * get a new pv_entry, allocating a block from the system 3853129198Scognet * when needed. 3854129198Scognet * the memory allocation is performed bypassing the malloc code 3855129198Scognet * because of the possibility of allocations at interrupt time. 3856129198Scognet */ 3857129198Scognetstatic pv_entry_t 3858129198Scognetpmap_get_pv_entry(void) 3859129198Scognet{ 3860129198Scognet pv_entry_t ret_value; 3861129198Scognet 3862129198Scognet pv_entry_count++; 3863159500Salc if (pv_entry_count > pv_entry_high_water) 3864159500Salc pagedaemon_wakeup(); 3865129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3866129198Scognet return ret_value; 3867129198Scognet} 3868129198Scognet 3869129198Scognet/* 3870129198Scognet * Remove the given range of addresses from the specified map. 3871129198Scognet * 3872129198Scognet * It is assumed that the start and end are properly 3873129198Scognet * rounded to the page size. 3874129198Scognet */ 3875175840Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3876129198Scognetvoid 3877129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3878129198Scognet{ 3879129198Scognet struct l2_bucket *l2b; 3880129198Scognet vm_offset_t next_bucket; 3881129198Scognet pt_entry_t *ptep; 3882175840Scognet u_int total; 3883129198Scognet u_int mappings, is_exec, is_refd; 3884135641Scognet int flushall = 0; 3885129198Scognet 3886129198Scognet 3887129198Scognet /* 3888129198Scognet * we lock in the pmap => pv_head direction 3889129198Scognet */ 3890129198Scognet 3891239934Salc rw_wlock(&pvh_global_lock); 3892159352Salc PMAP_LOCK(pm); 3893129198Scognet total = 0; 3894129198Scognet while (sva < eva) { 3895129198Scognet /* 3896129198Scognet * Do one L2 bucket's worth at a time. 3897129198Scognet */ 3898129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3899129198Scognet if (next_bucket > eva) 3900129198Scognet next_bucket = eva; 3901129198Scognet 3902129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3903129198Scognet if (l2b == NULL) { 3904129198Scognet sva = next_bucket; 3905129198Scognet continue; 3906129198Scognet } 3907129198Scognet 3908129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3909129198Scognet mappings = 0; 3910129198Scognet 3911129198Scognet while (sva < next_bucket) { 3912129198Scognet struct vm_page *pg; 3913129198Scognet pt_entry_t pte; 3914129198Scognet vm_paddr_t pa; 3915129198Scognet 3916129198Scognet pte = *ptep; 3917129198Scognet 3918129198Scognet if (pte == 0) { 3919129198Scognet /* 3920129198Scognet * Nothing here, move along 3921129198Scognet */ 3922129198Scognet sva += PAGE_SIZE; 3923129198Scognet ptep++; 3924129198Scognet continue; 3925129198Scognet } 3926129198Scognet 3927129198Scognet pm->pm_stats.resident_count--; 3928129198Scognet pa = l2pte_pa(pte); 3929129198Scognet is_exec = 0; 3930129198Scognet is_refd = 1; 3931129198Scognet 3932129198Scognet /* 3933129198Scognet * Update flags. In a number of circumstances, 3934129198Scognet * we could cluster a lot of these and do a 3935129198Scognet * number of sequential pages in one go. 3936129198Scognet */ 3937129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3938129198Scognet struct pv_entry *pve; 3939159474Salc 3940129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3941135641Scognet if (pve) { 3942159474Salc is_exec = PV_BEEN_EXECD(pve->pv_flags); 3943159474Salc is_refd = PV_BEEN_REFD(pve->pv_flags); 3944129198Scognet pmap_free_pv_entry(pve); 3945129198Scognet } 3946129198Scognet } 3947129198Scognet 3948175840Scognet if (l2pte_valid(pte) && pmap_is_current(pm)) { 3949175840Scognet if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3950175840Scognet total++; 3951175840Scognet if (is_exec) { 3952175840Scognet cpu_idcache_wbinv_range(sva, 3953183838Sraj PAGE_SIZE); 3954183838Sraj cpu_l2cache_wbinv_range(sva, 3955183838Sraj PAGE_SIZE); 3956175840Scognet cpu_tlb_flushID_SE(sva); 3957175840Scognet } else if (is_refd) { 3958175840Scognet cpu_dcache_wbinv_range(sva, 3959183838Sraj PAGE_SIZE); 3960183838Sraj cpu_l2cache_wbinv_range(sva, 3961183838Sraj PAGE_SIZE); 3962175840Scognet cpu_tlb_flushD_SE(sva); 3963175840Scognet } 3964175840Scognet } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3965175840Scognet /* flushall will also only get set for 3966175840Scognet * for a current pmap 3967175840Scognet */ 3968175840Scognet cpu_idcache_wbinv_all(); 3969183838Sraj cpu_l2cache_wbinv_all(); 3970175840Scognet flushall = 1; 3971175840Scognet total++; 3972129198Scognet } 3973129198Scognet } 3974175840Scognet *ptep = 0; 3975175840Scognet PTE_SYNC(ptep); 3976129198Scognet 3977129198Scognet sva += PAGE_SIZE; 3978129198Scognet ptep++; 3979129198Scognet mappings++; 3980129198Scognet } 3981129198Scognet 3982129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 3983129198Scognet } 3984129198Scognet 3985239934Salc rw_wunlock(&pvh_global_lock); 3986135641Scognet if (flushall) 3987135641Scognet cpu_tlb_flushID(); 3988159352Salc PMAP_UNLOCK(pm); 3989129198Scognet} 3990129198Scognet 3991129198Scognet/* 3992129198Scognet * pmap_zero_page() 3993236991Simp * 3994129198Scognet * Zero a given physical page by mapping it at a page hook point. 3995129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 3996129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 3997129198Scognet * _any_ bulk data very slow. 3998129198Scognet */ 3999164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3) 4000129198Scognetvoid 4001129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 4002129198Scognet{ 4003161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4004161105Scognet char *dstpg; 4005161105Scognet#endif 4006161105Scognet 4007172300Scognet if (_arm_bzero && size >= _min_bzero_size && 4008150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4009150865Scognet return; 4010129198Scognet 4011161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4012161105Scognet dstpg = (char *)arm_ptovirt(phys); 4013161105Scognet if (off || size != PAGE_SIZE) { 4014161105Scognet bzero(dstpg + off, size); 4015161105Scognet cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); 4016183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size); 4017161105Scognet } else { 4018161105Scognet bzero_page((vm_offset_t)dstpg); 4019161105Scognet cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4020183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4021161105Scognet } 4022161105Scognet#else 4023150865Scognet 4024159088Scognet mtx_lock(&cmtx); 4025129198Scognet /* 4026183836Sraj * Hook in the page, zero it, invalidate the TLB as needed. 4027183836Sraj * 4028183836Sraj * Note the temporary zero-page mapping must be a non-cached page in 4029184730Sraj * order to work without corruption when write-allocate is enabled. 4030129198Scognet */ 4031183836Sraj *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 4032228530Sraj PTE_SYNC(cdst_pte); 4033129198Scognet cpu_tlb_flushD_SE(cdstp); 4034129198Scognet cpu_cpwait(); 4035183836Sraj if (off || size != PAGE_SIZE) 4036129198Scognet bzero((void *)(cdstp + off), size); 4037183836Sraj else 4038129198Scognet bzero_page(cdstp); 4039183836Sraj 4040159088Scognet mtx_unlock(&cmtx); 4041161105Scognet#endif 4042129198Scognet} 4043129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4044129198Scognet 4045129198Scognet#if ARM_MMU_XSCALE == 1 4046129198Scognetvoid 4047129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 4048129198Scognet{ 4049172713Scognet#ifdef ARM_USE_SMALL_ALLOC 4050172713Scognet char *dstpg; 4051172713Scognet#endif 4052172713Scognet 4053172300Scognet if (_arm_bzero && size >= _min_bzero_size && 4054150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4055150865Scognet return; 4056172713Scognet#ifdef ARM_USE_SMALL_ALLOC 4057172713Scognet dstpg = (char *)arm_ptovirt(phys); 4058172713Scognet if (off || size != PAGE_SIZE) { 4059172713Scognet bzero(dstpg + off, size); 4060172713Scognet cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); 4061172713Scognet } else { 4062172713Scognet bzero_page((vm_offset_t)dstpg); 4063172713Scognet cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4064172713Scognet } 4065172713Scognet#else 4066159088Scognet mtx_lock(&cmtx); 4067129198Scognet /* 4068129198Scognet * Hook in the page, zero it, and purge the cache for that 4069129198Scognet * zeroed page. Invalidate the TLB as needed. 4070129198Scognet */ 4071129198Scognet *cdst_pte = L2_S_PROTO | phys | 4072129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4073129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4074129198Scognet PTE_SYNC(cdst_pte); 4075129198Scognet cpu_tlb_flushD_SE(cdstp); 4076129198Scognet cpu_cpwait(); 4077135641Scognet if (off || size != PAGE_SIZE) 4078129198Scognet bzero((void *)(cdstp + off), size); 4079129198Scognet else 4080129198Scognet bzero_page(cdstp); 4081159088Scognet mtx_unlock(&cmtx); 4082129198Scognet xscale_cache_clean_minidata(); 4083172713Scognet#endif 4084129198Scognet} 4085129198Scognet 4086129198Scognet/* 4087129198Scognet * Change the PTEs for the specified kernel mappings such that they 4088129198Scognet * will use the mini data cache instead of the main data cache. 4089129198Scognet */ 4090129198Scognetvoid 4091135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 4092129198Scognet{ 4093129198Scognet struct l2_bucket *l2b; 4094129198Scognet pt_entry_t *ptep, *sptep, pte; 4095129198Scognet vm_offset_t next_bucket, eva; 4096129198Scognet 4097164778Scognet#if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3) 4098129198Scognet if (xscale_use_minidata == 0) 4099129198Scognet return; 4100129198Scognet#endif 4101129198Scognet 4102135641Scognet eva = va + size; 4103129198Scognet 4104129198Scognet while (va < eva) { 4105129198Scognet next_bucket = L2_NEXT_BUCKET(va); 4106129198Scognet if (next_bucket > eva) 4107129198Scognet next_bucket = eva; 4108129198Scognet 4109129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4110129198Scognet 4111129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4112129198Scognet 4113129198Scognet while (va < next_bucket) { 4114129198Scognet pte = *ptep; 4115129198Scognet if (!l2pte_minidata(pte)) { 4116129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 4117129198Scognet cpu_tlb_flushD_SE(va); 4118129198Scognet *ptep = pte & ~L2_B; 4119129198Scognet } 4120129198Scognet ptep++; 4121129198Scognet va += PAGE_SIZE; 4122129198Scognet } 4123129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4124129198Scognet } 4125129198Scognet cpu_cpwait(); 4126129198Scognet} 4127129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4128129198Scognet 4129129198Scognet/* 4130236991Simp * pmap_zero_page zeros the specified hardware page by mapping 4131129198Scognet * the page into KVM and using bzero to clear its contents. 4132129198Scognet */ 4133129198Scognetvoid 4134129198Scognetpmap_zero_page(vm_page_t m) 4135129198Scognet{ 4136135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4137129198Scognet} 4138129198Scognet 4139129198Scognet 4140129198Scognet/* 4141236991Simp * pmap_zero_page_area zeros the specified hardware page by mapping 4142129198Scognet * the page into KVM and using bzero to clear its contents. 4143129198Scognet * 4144129198Scognet * off and size may not cover an area beyond a single hardware page. 4145129198Scognet */ 4146129198Scognetvoid 4147129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 4148129198Scognet{ 4149129198Scognet 4150129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4151129198Scognet} 4152129198Scognet 4153129198Scognet 4154129198Scognet/* 4155236991Simp * pmap_zero_page_idle zeros the specified hardware page by mapping 4156129198Scognet * the page into KVM and using bzero to clear its contents. This 4157129198Scognet * is intended to be called from the vm_pagezero process only and 4158129198Scognet * outside of Giant. 4159129198Scognet */ 4160129198Scognetvoid 4161129198Scognetpmap_zero_page_idle(vm_page_t m) 4162129198Scognet{ 4163129198Scognet 4164129198Scognet pmap_zero_page(m); 4165129198Scognet} 4166129198Scognet 4167150865Scognet#if 0 4168129198Scognet/* 4169129198Scognet * pmap_clean_page() 4170129198Scognet * 4171129198Scognet * This is a local function used to work out the best strategy to clean 4172197770Sstas * a single page referenced by its entry in the PV table. It should be used by 4173129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4174129198Scognet * 4175129198Scognet * Its policy is effectively: 4176129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4177129198Scognet * o If there is one mapping, we clean just that page. 4178129198Scognet * o If there are multiple mappings, we clean the entire cache. 4179129198Scognet * 4180129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4181129198Scognet * clean the entire cache, or 1 if it did. 4182129198Scognet * 4183129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4184129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4185129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4186129198Scognet * it will just result in not the most efficient clean for the page. 4187197770Sstas * 4188197770Sstas * We don't yet use this function but may want to. 4189129198Scognet */ 4190129198Scognetstatic int 4191129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4192129198Scognet{ 4193129198Scognet pmap_t pm, pm_to_clean = NULL; 4194129198Scognet struct pv_entry *npv; 4195129198Scognet u_int cache_needs_cleaning = 0; 4196129198Scognet u_int flags = 0; 4197129198Scognet vm_offset_t page_to_clean = 0; 4198129198Scognet 4199129198Scognet if (pv == NULL) { 4200129198Scognet /* nothing mapped in so nothing to flush */ 4201129198Scognet return (0); 4202129198Scognet } 4203129198Scognet 4204129198Scognet /* 4205129198Scognet * Since we flush the cache each time we change to a different 4206129198Scognet * user vmspace, we only need to flush the page if it is in the 4207129198Scognet * current pmap. 4208129198Scognet */ 4209135641Scognet if (curthread) 4210135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4211129198Scognet else 4212129198Scognet pm = pmap_kernel(); 4213129198Scognet 4214129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4215129198Scognet if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4216129198Scognet flags |= npv->pv_flags; 4217129198Scognet /* 4218236991Simp * The page is mapped non-cacheable in 4219129198Scognet * this map. No need to flush the cache. 4220129198Scognet */ 4221129198Scognet if (npv->pv_flags & PVF_NC) { 4222129198Scognet#ifdef DIAGNOSTIC 4223129198Scognet if (cache_needs_cleaning) 4224129198Scognet panic("pmap_clean_page: " 4225129198Scognet "cache inconsistency"); 4226129198Scognet#endif 4227129198Scognet break; 4228129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4229129198Scognet continue; 4230129198Scognet if (cache_needs_cleaning) { 4231129198Scognet page_to_clean = 0; 4232129198Scognet break; 4233129198Scognet } else { 4234129198Scognet page_to_clean = npv->pv_va; 4235129198Scognet pm_to_clean = npv->pv_pmap; 4236129198Scognet } 4237129198Scognet cache_needs_cleaning = 1; 4238129198Scognet } 4239129198Scognet } 4240129198Scognet if (page_to_clean) { 4241129198Scognet if (PV_BEEN_EXECD(flags)) 4242129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4243129198Scognet PAGE_SIZE); 4244129198Scognet else 4245129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4246129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4247129198Scognet } else if (cache_needs_cleaning) { 4248129198Scognet if (PV_BEEN_EXECD(flags)) 4249129198Scognet pmap_idcache_wbinv_all(pm); 4250129198Scognet else 4251129198Scognet pmap_dcache_wbinv_all(pm); 4252129198Scognet return (1); 4253129198Scognet } 4254129198Scognet return (0); 4255129198Scognet} 4256150865Scognet#endif 4257129198Scognet 4258129198Scognet/* 4259129198Scognet * pmap_copy_page copies the specified (machine independent) 4260129198Scognet * page by mapping the page into virtual memory and using 4261129198Scognet * bcopy to copy the page, one machine dependent page at a 4262129198Scognet * time. 4263129198Scognet */ 4264129198Scognet 4265129198Scognet/* 4266129198Scognet * pmap_copy_page() 4267129198Scognet * 4268129198Scognet * Copy one physical page into another, by mapping the pages into 4269129198Scognet * hook points. The same comment regarding cachability as in 4270129198Scognet * pmap_zero_page also applies here. 4271129198Scognet */ 4272164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3) 4273129198Scognetvoid 4274129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4275129198Scognet{ 4276151596Scognet#if 0 4277129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4278151596Scognet#endif 4279129198Scognet 4280129198Scognet /* 4281129198Scognet * Clean the source page. Hold the source page's lock for 4282129198Scognet * the duration of the copy so that no other mappings can 4283129198Scognet * be created while we have a potentially aliased mapping. 4284129198Scognet */ 4285129198Scognet#if 0 4286150865Scognet /* 4287150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4288150865Scognet * pmap_copy_page(). 4289150865Scognet */ 4290129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4291150865Scognet#endif 4292129198Scognet /* 4293129198Scognet * Map the pages into the page hook points, copy them, and purge 4294129198Scognet * the cache for the appropriate page. Invalidate the TLB 4295129198Scognet * as required. 4296129198Scognet */ 4297159088Scognet mtx_lock(&cmtx); 4298129198Scognet *csrc_pte = L2_S_PROTO | src | 4299129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4300129198Scognet PTE_SYNC(csrc_pte); 4301129198Scognet *cdst_pte = L2_S_PROTO | dst | 4302129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4303129198Scognet PTE_SYNC(cdst_pte); 4304129198Scognet cpu_tlb_flushD_SE(csrcp); 4305129198Scognet cpu_tlb_flushD_SE(cdstp); 4306129198Scognet cpu_cpwait(); 4307129198Scognet bcopy_page(csrcp, cdstp); 4308159088Scognet mtx_unlock(&cmtx); 4309129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4310129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4311183838Sraj cpu_l2cache_inv_range(csrcp, PAGE_SIZE); 4312183838Sraj cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE); 4313129198Scognet} 4314248280Skib 4315248280Skibvoid 4316248280Skibpmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs, 4317248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt) 4318248280Skib{ 4319248280Skib 4320248280Skib mtx_lock(&cmtx); 4321248280Skib *csrc_pte = L2_S_PROTO | a_phys | 4322248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4323248280Skib PTE_SYNC(csrc_pte); 4324248280Skib *cdst_pte = L2_S_PROTO | b_phys | 4325248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4326248280Skib PTE_SYNC(cdst_pte); 4327248280Skib cpu_tlb_flushD_SE(csrcp); 4328248280Skib cpu_tlb_flushD_SE(cdstp); 4329248280Skib cpu_cpwait(); 4330248280Skib bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt); 4331248280Skib mtx_unlock(&cmtx); 4332248280Skib cpu_dcache_inv_range(csrcp + a_offs, cnt); 4333248280Skib cpu_dcache_wbinv_range(cdstp + b_offs, cnt); 4334248280Skib cpu_l2cache_inv_range(csrcp + a_offs, cnt); 4335248280Skib cpu_l2cache_wbinv_range(cdstp + b_offs, cnt); 4336248280Skib} 4337129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4338129198Scognet 4339129198Scognet#if ARM_MMU_XSCALE == 1 4340129198Scognetvoid 4341129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4342129198Scognet{ 4343150865Scognet#if 0 4344150865Scognet /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4345129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4346150865Scognet#endif 4347129198Scognet 4348129198Scognet /* 4349129198Scognet * Clean the source page. Hold the source page's lock for 4350129198Scognet * the duration of the copy so that no other mappings can 4351129198Scognet * be created while we have a potentially aliased mapping. 4352129198Scognet */ 4353150865Scognet#if 0 4354150865Scognet /* 4355150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4356150865Scognet * pmap_copy_page(). 4357150865Scognet */ 4358130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4359150865Scognet#endif 4360129198Scognet /* 4361129198Scognet * Map the pages into the page hook points, copy them, and purge 4362129198Scognet * the cache for the appropriate page. Invalidate the TLB 4363129198Scognet * as required. 4364129198Scognet */ 4365159088Scognet mtx_lock(&cmtx); 4366129198Scognet *csrc_pte = L2_S_PROTO | src | 4367129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4368129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4369129198Scognet PTE_SYNC(csrc_pte); 4370129198Scognet *cdst_pte = L2_S_PROTO | dst | 4371129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4372129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4373129198Scognet PTE_SYNC(cdst_pte); 4374129198Scognet cpu_tlb_flushD_SE(csrcp); 4375129198Scognet cpu_tlb_flushD_SE(cdstp); 4376129198Scognet cpu_cpwait(); 4377129198Scognet bcopy_page(csrcp, cdstp); 4378159088Scognet mtx_unlock(&cmtx); 4379129198Scognet xscale_cache_clean_minidata(); 4380129198Scognet} 4381248280Skib 4382248280Skibvoid 4383248280Skibpmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs, 4384248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt) 4385248280Skib{ 4386248280Skib 4387248280Skib mtx_lock(&cmtx); 4388248280Skib *csrc_pte = L2_S_PROTO | a_phys | 4389248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4390248280Skib L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4391248280Skib PTE_SYNC(csrc_pte); 4392248280Skib *cdst_pte = L2_S_PROTO | b_phys | 4393248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4394248280Skib L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4395248280Skib PTE_SYNC(cdst_pte); 4396248280Skib cpu_tlb_flushD_SE(csrcp); 4397248280Skib cpu_tlb_flushD_SE(cdstp); 4398248280Skib cpu_cpwait(); 4399248280Skib bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt); 4400248280Skib mtx_unlock(&cmtx); 4401248280Skib xscale_cache_clean_minidata(); 4402248280Skib} 4403129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4404129198Scognet 4405129198Scognetvoid 4406129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4407129198Scognet{ 4408161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4409161105Scognet vm_offset_t srcpg, dstpg; 4410161105Scognet#endif 4411161105Scognet 4412146596Scognet cpu_dcache_wbinv_all(); 4413183838Sraj cpu_l2cache_wbinv_all(); 4414172300Scognet if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size && 4415236991Simp _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4416150865Scognet (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4417150865Scognet return; 4418161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4419161105Scognet srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src)); 4420161105Scognet dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst)); 4421161105Scognet bcopy_page(srcpg, dstpg); 4422161105Scognet cpu_dcache_wbinv_range(dstpg, PAGE_SIZE); 4423183838Sraj cpu_l2cache_wbinv_range(dstpg, PAGE_SIZE); 4424161105Scognet#else 4425129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4426161105Scognet#endif 4427129198Scognet} 4428129198Scognet 4429248508Skibint unmapped_buf_allowed = 1; 4430248508Skib 4431248280Skibvoid 4432248280Skibpmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4433248280Skib vm_offset_t b_offset, int xfersize) 4434248280Skib{ 4435248280Skib vm_page_t a_pg, b_pg; 4436248280Skib vm_offset_t a_pg_offset, b_pg_offset; 4437248280Skib int cnt; 4438248280Skib#ifdef ARM_USE_SMALL_ALLOC 4439248280Skib vm_offset_t a_va, b_va; 4440248280Skib#endif 4441129198Scognet 4442248280Skib cpu_dcache_wbinv_all(); 4443248280Skib cpu_l2cache_wbinv_all(); 4444248280Skib while (xfersize > 0) { 4445248280Skib a_pg = ma[a_offset >> PAGE_SHIFT]; 4446248280Skib a_pg_offset = a_offset & PAGE_MASK; 4447248280Skib cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4448248280Skib b_pg = mb[b_offset >> PAGE_SHIFT]; 4449248280Skib b_pg_offset = b_offset & PAGE_MASK; 4450248280Skib cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4451248280Skib#ifdef ARM_USE_SMALL_ALLOC 4452248280Skib a_va = arm_ptovirt(VM_PAGE_TO_PHYS(a_pg)) + a_pg_offset; 4453248280Skib b_va = arm_ptovirt(VM_PAGE_TO_PHYS(b_pg)) + b_pg_offset; 4454248280Skib bcopy((char *)a_va, (char *)b_va, cnt); 4455248280Skib cpu_dcache_wbinv_range(b_va, cnt); 4456248280Skib cpu_l2cache_wbinv_range(b_va, cnt); 4457248280Skib#else 4458248280Skib pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset, 4459248280Skib VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt); 4460248280Skib#endif 4461248280Skib xfersize -= cnt; 4462248280Skib a_offset += cnt; 4463248280Skib b_offset += cnt; 4464248280Skib } 4465248280Skib} 4466129198Scognet 4467129198Scognet/* 4468129198Scognet * this routine returns true if a physical page resides 4469129198Scognet * in the given pmap. 4470129198Scognet */ 4471129198Scognetboolean_t 4472129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4473129198Scognet{ 4474129198Scognet pv_entry_t pv; 4475129198Scognet int loops = 0; 4476208990Salc boolean_t rv; 4477129198Scognet 4478224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4479208990Salc ("pmap_page_exists_quick: page %p is not managed", m)); 4480208990Salc rv = FALSE; 4481239934Salc rw_wlock(&pvh_global_lock); 4482208990Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4483129198Scognet if (pv->pv_pmap == pmap) { 4484208990Salc rv = TRUE; 4485208990Salc break; 4486129198Scognet } 4487129198Scognet loops++; 4488129198Scognet if (loops >= 16) 4489129198Scognet break; 4490129198Scognet } 4491239934Salc rw_wunlock(&pvh_global_lock); 4492208990Salc return (rv); 4493129198Scognet} 4494129198Scognet 4495173708Salc/* 4496173708Salc * pmap_page_wired_mappings: 4497173708Salc * 4498173708Salc * Return the number of managed mappings to the given physical page 4499173708Salc * that are wired. 4500173708Salc */ 4501173708Salcint 4502173708Salcpmap_page_wired_mappings(vm_page_t m) 4503173708Salc{ 4504173708Salc pv_entry_t pv; 4505173708Salc int count; 4506129198Scognet 4507173708Salc count = 0; 4508224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 4509173708Salc return (count); 4510239934Salc rw_wlock(&pvh_global_lock); 4511173708Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 4512173708Salc if ((pv->pv_flags & PVF_WIRED) != 0) 4513173708Salc count++; 4514239934Salc rw_wunlock(&pvh_global_lock); 4515173708Salc return (count); 4516173708Salc} 4517173708Salc 4518129198Scognet/* 4519255028Salc * This function is advisory. 4520255028Salc */ 4521255028Salcvoid 4522255028Salcpmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4523255028Salc{ 4524255028Salc} 4525255028Salc 4526255028Salc/* 4527129198Scognet * pmap_ts_referenced: 4528129198Scognet * 4529129198Scognet * Return the count of reference bits for a page, clearing all of them. 4530129198Scognet */ 4531129198Scognetint 4532129198Scognetpmap_ts_referenced(vm_page_t m) 4533129198Scognet{ 4534164778Scognet 4535224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4536208990Salc ("pmap_ts_referenced: page %p is not managed", m)); 4537135641Scognet return (pmap_clearbit(m, PVF_REF)); 4538129198Scognet} 4539129198Scognet 4540129198Scognet 4541129198Scognetboolean_t 4542129198Scognetpmap_is_modified(vm_page_t m) 4543129198Scognet{ 4544135641Scognet 4545224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4546208504Salc ("pmap_is_modified: page %p is not managed", m)); 4547135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4548135641Scognet return (TRUE); 4549129198Scognet 4550129198Scognet return(FALSE); 4551129198Scognet} 4552129198Scognet 4553129198Scognet 4554129198Scognet/* 4555129198Scognet * Clear the modify bits on the specified physical page. 4556129198Scognet */ 4557129198Scognetvoid 4558129198Scognetpmap_clear_modify(vm_page_t m) 4559129198Scognet{ 4560129198Scognet 4561224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4562208504Salc ("pmap_clear_modify: page %p is not managed", m)); 4563248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 4564254138Sattilio KASSERT(!vm_page_xbusied(m), 4565254138Sattilio ("pmap_clear_modify: page %p is exclusive busied", m)); 4566208504Salc 4567208504Salc /* 4568225418Skib * If the page is not PGA_WRITEABLE, then no mappings can be modified. 4569208504Salc * If the object containing the page is locked and the page is not 4570254138Sattilio * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4571208504Salc */ 4572225418Skib if ((m->aflags & PGA_WRITEABLE) == 0) 4573208504Salc return; 4574129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4575129198Scognet pmap_clearbit(m, PVF_MOD); 4576129198Scognet} 4577129198Scognet 4578129198Scognet 4579129198Scognet/* 4580207155Salc * pmap_is_referenced: 4581207155Salc * 4582207155Salc * Return whether or not the specified physical page was referenced 4583207155Salc * in any physical maps. 4584207155Salc */ 4585207155Salcboolean_t 4586207155Salcpmap_is_referenced(vm_page_t m) 4587207155Salc{ 4588207155Salc 4589224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4590208574Salc ("pmap_is_referenced: page %p is not managed", m)); 4591208574Salc return ((m->md.pvh_attrs & PVF_REF) != 0); 4592207155Salc} 4593207155Salc 4594129198Scognet 4595129198Scognet/* 4596160537Salc * Clear the write and modified bits in each of the given page's mappings. 4597160537Salc */ 4598160537Salcvoid 4599160889Salcpmap_remove_write(vm_page_t m) 4600160537Salc{ 4601160537Salc 4602224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4603208175Salc ("pmap_remove_write: page %p is not managed", m)); 4604208175Salc 4605208175Salc /* 4606254138Sattilio * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4607254138Sattilio * set by another thread while the object is locked. Thus, 4608254138Sattilio * if PGA_WRITEABLE is clear, no page table entries need updating. 4609208175Salc */ 4610248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 4611254138Sattilio if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0) 4612160537Salc pmap_clearbit(m, PVF_WRITE); 4613160537Salc} 4614160537Salc 4615160537Salc 4616160537Salc/* 4617129198Scognet * perform the pmap work for mincore 4618129198Scognet */ 4619129198Scognetint 4620208504Salcpmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4621129198Scognet{ 4622235717Simp struct l2_bucket *l2b; 4623235717Simp pt_entry_t *ptep, pte; 4624235717Simp vm_paddr_t pa; 4625235717Simp vm_page_t m; 4626235717Simp int val; 4627235717Simp boolean_t managed; 4628235717Simp 4629235717Simp PMAP_LOCK(pmap); 4630235717Simpretry: 4631235717Simp l2b = pmap_get_l2_bucket(pmap, addr); 4632235717Simp if (l2b == NULL) { 4633235717Simp val = 0; 4634235717Simp goto out; 4635235717Simp } 4636235717Simp ptep = &l2b->l2b_kva[l2pte_index(addr)]; 4637235717Simp pte = *ptep; 4638235717Simp if (!l2pte_valid(pte)) { 4639235717Simp val = 0; 4640235717Simp goto out; 4641235717Simp } 4642235717Simp val = MINCORE_INCORE; 4643235717Simp if (pte & L2_S_PROT_W) 4644235717Simp val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4645235717Simp managed = false; 4646235717Simp pa = l2pte_pa(pte); 4647235717Simp m = PHYS_TO_VM_PAGE(pa); 4648235717Simp if (m != NULL && !(m->oflags & VPO_UNMANAGED)) 4649235717Simp managed = true; 4650235717Simp if (managed) { 4651235717Simp /* 4652241044Salc * The ARM pmap tries to maintain a per-mapping 4653235717Simp * reference bit. The trouble is that it's kept in 4654235717Simp * the PV entry, not the PTE, so it's costly to access 4655241044Salc * here. You would need to acquire the pvh global 4656235717Simp * lock, call pmap_find_pv(), and introduce a custom 4657235717Simp * version of vm_page_pa_tryrelock() that releases and 4658241044Salc * reacquires the pvh global lock. In the end, I 4659235717Simp * doubt it's worthwhile. This may falsely report 4660235717Simp * the given address as referenced. 4661235717Simp */ 4662235717Simp if ((m->md.pvh_attrs & PVF_REF) != 0) 4663235717Simp val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4664235717Simp } 4665235717Simp if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4666235717Simp (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 4667235717Simp /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4668235717Simp if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4669235717Simp goto retry; 4670235717Simp } else 4671235717Simpout: 4672235717Simp PA_UNLOCK_COND(*locked_pa); 4673235717Simp PMAP_UNLOCK(pmap); 4674235717Simp return (val); 4675129198Scognet} 4676129198Scognet 4677129198Scognet 4678198341Smarcelvoid 4679198341Smarcelpmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4680198341Smarcel{ 4681198341Smarcel} 4682198341Smarcel 4683198341Smarcel 4684178893Salc/* 4685178893Salc * Increase the starting virtual address of the given mapping if a 4686178893Salc * different alignment might result in more superpage mappings. 4687178893Salc */ 4688178893Salcvoid 4689178893Salcpmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4690178893Salc vm_offset_t *addr, vm_size_t size) 4691178893Salc{ 4692178893Salc} 4693129198Scognet 4694178893Salc 4695129198Scognet/* 4696129198Scognet * Map a set of physical memory pages into the kernel virtual 4697129198Scognet * address space. Return a pointer to where it is mapped. This 4698129198Scognet * routine is intended to be used for mapping device memory, 4699129198Scognet * NOT real memory. 4700129198Scognet */ 4701129198Scognetvoid * 4702129198Scognetpmap_mapdev(vm_offset_t pa, vm_size_t size) 4703129198Scognet{ 4704129198Scognet vm_offset_t va, tmpva, offset; 4705129198Scognet 4706129198Scognet offset = pa & PAGE_MASK; 4707135641Scognet size = roundup(size, PAGE_SIZE); 4708129198Scognet 4709129198Scognet GIANT_REQUIRED; 4710129198Scognet 4711254025Sjeff va = kva_alloc(size); 4712129198Scognet if (!va) 4713129198Scognet panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4714129198Scognet for (tmpva = va; size > 0;) { 4715135641Scognet pmap_kenter_internal(tmpva, pa, 0); 4716129198Scognet size -= PAGE_SIZE; 4717129198Scognet tmpva += PAGE_SIZE; 4718129198Scognet pa += PAGE_SIZE; 4719129198Scognet } 4720129198Scognet 4721159068Sbenno return ((void *)(va + offset)); 4722129198Scognet} 4723129198Scognet 4724129198Scognet#define BOOTSTRAP_DEBUG 4725129198Scognet 4726129198Scognet/* 4727129198Scognet * pmap_map_section: 4728129198Scognet * 4729129198Scognet * Create a single section mapping. 4730129198Scognet */ 4731129198Scognetvoid 4732129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4733129198Scognet int prot, int cache) 4734129198Scognet{ 4735129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4736129198Scognet pd_entry_t fl; 4737129198Scognet 4738129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4739129198Scognet 4740129198Scognet switch (cache) { 4741129198Scognet case PTE_NOCACHE: 4742129198Scognet default: 4743129198Scognet fl = 0; 4744129198Scognet break; 4745129198Scognet 4746129198Scognet case PTE_CACHE: 4747129198Scognet fl = pte_l1_s_cache_mode; 4748129198Scognet break; 4749129198Scognet 4750129198Scognet case PTE_PAGETABLE: 4751129198Scognet fl = pte_l1_s_cache_mode_pt; 4752129198Scognet break; 4753129198Scognet } 4754129198Scognet 4755129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4756129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4757129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4758129198Scognet 4759129198Scognet} 4760129198Scognet 4761129198Scognet/* 4762129198Scognet * pmap_link_l2pt: 4763129198Scognet * 4764164079Scognet * Link the L2 page table specified by l2pv.pv_pa into the L1 4765129198Scognet * page table at the slot for "va". 4766129198Scognet */ 4767129198Scognetvoid 4768129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4769129198Scognet{ 4770129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4771129198Scognet u_int slot = va >> L1_S_SHIFT; 4772129198Scognet 4773129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4774129198Scognet 4775236991Simp#ifdef VERBOSE_INIT_ARM 4776164079Scognet printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va); 4777164079Scognet#endif 4778164079Scognet 4779129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4780164079Scognet 4781129198Scognet PTE_SYNC(&pde[slot]); 4782129198Scognet 4783129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4784129198Scognet 4785129198Scognet 4786129198Scognet} 4787129198Scognet 4788129198Scognet/* 4789129198Scognet * pmap_map_entry 4790129198Scognet * 4791129198Scognet * Create a single page mapping. 4792129198Scognet */ 4793129198Scognetvoid 4794129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4795129198Scognet int cache) 4796129198Scognet{ 4797129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4798129198Scognet pt_entry_t fl; 4799129198Scognet pt_entry_t *pte; 4800129198Scognet 4801129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4802129198Scognet 4803129198Scognet switch (cache) { 4804129198Scognet case PTE_NOCACHE: 4805129198Scognet default: 4806129198Scognet fl = 0; 4807129198Scognet break; 4808129198Scognet 4809129198Scognet case PTE_CACHE: 4810129198Scognet fl = pte_l2_s_cache_mode; 4811129198Scognet break; 4812129198Scognet 4813129198Scognet case PTE_PAGETABLE: 4814129198Scognet fl = pte_l2_s_cache_mode_pt; 4815129198Scognet break; 4816129198Scognet } 4817129198Scognet 4818129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4819129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4820129198Scognet 4821129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4822129198Scognet 4823129198Scognet if (pte == NULL) 4824129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4825129198Scognet 4826129198Scognet pte[l2pte_index(va)] = 4827129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4828129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4829129198Scognet} 4830129198Scognet 4831129198Scognet/* 4832129198Scognet * pmap_map_chunk: 4833129198Scognet * 4834129198Scognet * Map a chunk of memory using the most efficient mappings 4835129198Scognet * possible (section. large page, small page) into the 4836129198Scognet * provided L1 and L2 tables at the specified virtual address. 4837129198Scognet */ 4838129198Scognetvm_size_t 4839129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4840129198Scognet vm_size_t size, int prot, int cache) 4841129198Scognet{ 4842129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4843129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4844236991Simp vm_size_t resid; 4845129198Scognet int i; 4846129198Scognet 4847129198Scognet resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4848129198Scognet 4849129198Scognet if (l1pt == 0) 4850129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4851129198Scognet 4852236991Simp#ifdef VERBOSE_INIT_ARM 4853159322Scognet printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 4854129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4855129198Scognet#endif 4856129198Scognet 4857129198Scognet switch (cache) { 4858129198Scognet case PTE_NOCACHE: 4859129198Scognet default: 4860129198Scognet f1 = 0; 4861129198Scognet f2l = 0; 4862129198Scognet f2s = 0; 4863129198Scognet break; 4864129198Scognet 4865129198Scognet case PTE_CACHE: 4866129198Scognet f1 = pte_l1_s_cache_mode; 4867129198Scognet f2l = pte_l2_l_cache_mode; 4868129198Scognet f2s = pte_l2_s_cache_mode; 4869129198Scognet break; 4870129198Scognet 4871129198Scognet case PTE_PAGETABLE: 4872129198Scognet f1 = pte_l1_s_cache_mode_pt; 4873129198Scognet f2l = pte_l2_l_cache_mode_pt; 4874129198Scognet f2s = pte_l2_s_cache_mode_pt; 4875129198Scognet break; 4876129198Scognet } 4877129198Scognet 4878129198Scognet size = resid; 4879129198Scognet 4880129198Scognet while (resid > 0) { 4881129198Scognet /* See if we can use a section mapping. */ 4882129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4883129198Scognet#ifdef VERBOSE_INIT_ARM 4884129198Scognet printf("S"); 4885129198Scognet#endif 4886129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4887129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4888129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4889129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4890129198Scognet va += L1_S_SIZE; 4891129198Scognet pa += L1_S_SIZE; 4892129198Scognet resid -= L1_S_SIZE; 4893129198Scognet continue; 4894129198Scognet } 4895129198Scognet 4896129198Scognet /* 4897129198Scognet * Ok, we're going to use an L2 table. Make sure 4898129198Scognet * one is actually in the corresponding L1 slot 4899129198Scognet * for the current VA. 4900129198Scognet */ 4901129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4902129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4903129198Scognet 4904129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4905129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4906129198Scognet if (pte == NULL) 4907129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4908129198Scognet "0x%08x", va); 4909129198Scognet /* See if we can use a L2 large page mapping. */ 4910129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4911129198Scognet#ifdef VERBOSE_INIT_ARM 4912129198Scognet printf("L"); 4913129198Scognet#endif 4914129198Scognet for (i = 0; i < 16; i++) { 4915129198Scognet pte[l2pte_index(va) + i] = 4916129198Scognet L2_L_PROTO | pa | 4917129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4918129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4919129198Scognet } 4920129198Scognet va += L2_L_SIZE; 4921129198Scognet pa += L2_L_SIZE; 4922129198Scognet resid -= L2_L_SIZE; 4923129198Scognet continue; 4924129198Scognet } 4925129198Scognet 4926129198Scognet /* Use a small page mapping. */ 4927129198Scognet#ifdef VERBOSE_INIT_ARM 4928129198Scognet printf("P"); 4929129198Scognet#endif 4930129198Scognet pte[l2pte_index(va)] = 4931129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4932129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4933129198Scognet va += PAGE_SIZE; 4934129198Scognet pa += PAGE_SIZE; 4935129198Scognet resid -= PAGE_SIZE; 4936129198Scognet } 4937129198Scognet#ifdef VERBOSE_INIT_ARM 4938129198Scognet printf("\n"); 4939129198Scognet#endif 4940129198Scognet return (size); 4941129198Scognet 4942129198Scognet} 4943129198Scognet 4944135641Scognet/********************** Static device map routines ***************************/ 4945135641Scognet 4946135641Scognetstatic const struct pmap_devmap *pmap_devmap_table; 4947135641Scognet 4948135641Scognet/* 4949135641Scognet * Register the devmap table. This is provided in case early console 4950135641Scognet * initialization needs to register mappings created by bootstrap code 4951135641Scognet * before pmap_devmap_bootstrap() is called. 4952135641Scognet */ 4953135641Scognetvoid 4954135641Scognetpmap_devmap_register(const struct pmap_devmap *table) 4955135641Scognet{ 4956135641Scognet 4957135641Scognet pmap_devmap_table = table; 4958135641Scognet} 4959135641Scognet 4960135641Scognet/* 4961135641Scognet * Map all of the static regions in the devmap table, and remember 4962135641Scognet * the devmap table so other parts of the kernel can look up entries 4963135641Scognet * later. 4964135641Scognet */ 4965135641Scognetvoid 4966135641Scognetpmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4967135641Scognet{ 4968135641Scognet int i; 4969135641Scognet 4970135641Scognet pmap_devmap_table = table; 4971135641Scognet 4972135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4973135641Scognet#ifdef VERBOSE_INIT_ARM 4974159322Scognet printf("devmap: %08x -> %08x @ %08x\n", 4975135641Scognet pmap_devmap_table[i].pd_pa, 4976135641Scognet pmap_devmap_table[i].pd_pa + 4977135641Scognet pmap_devmap_table[i].pd_size - 1, 4978135641Scognet pmap_devmap_table[i].pd_va); 4979135641Scognet#endif 4980135641Scognet pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4981135641Scognet pmap_devmap_table[i].pd_pa, 4982135641Scognet pmap_devmap_table[i].pd_size, 4983135641Scognet pmap_devmap_table[i].pd_prot, 4984135641Scognet pmap_devmap_table[i].pd_cache); 4985135641Scognet } 4986135641Scognet} 4987135641Scognet 4988135641Scognetconst struct pmap_devmap * 4989135641Scognetpmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4990135641Scognet{ 4991135641Scognet int i; 4992135641Scognet 4993135641Scognet if (pmap_devmap_table == NULL) 4994135641Scognet return (NULL); 4995135641Scognet 4996135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4997135641Scognet if (pa >= pmap_devmap_table[i].pd_pa && 4998135641Scognet pa + size <= pmap_devmap_table[i].pd_pa + 4999135641Scognet pmap_devmap_table[i].pd_size) 5000135641Scognet return (&pmap_devmap_table[i]); 5001135641Scognet } 5002135641Scognet 5003135641Scognet return (NULL); 5004135641Scognet} 5005135641Scognet 5006135641Scognetconst struct pmap_devmap * 5007135641Scognetpmap_devmap_find_va(vm_offset_t va, vm_size_t size) 5008135641Scognet{ 5009135641Scognet int i; 5010135641Scognet 5011135641Scognet if (pmap_devmap_table == NULL) 5012135641Scognet return (NULL); 5013135641Scognet 5014135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5015135641Scognet if (va >= pmap_devmap_table[i].pd_va && 5016135641Scognet va + size <= pmap_devmap_table[i].pd_va + 5017135641Scognet pmap_devmap_table[i].pd_size) 5018135641Scognet return (&pmap_devmap_table[i]); 5019135641Scognet } 5020135641Scognet 5021135641Scognet return (NULL); 5022135641Scognet} 5023135641Scognet 5024244414Scognetvoid 5025244414Scognetpmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 5026244414Scognet{ 5027244414Scognet /* 5028244414Scognet * Remember the memattr in a field that gets used to set the appropriate 5029244414Scognet * bits in the PTEs as mappings are established. 5030244414Scognet */ 5031244414Scognet m->md.pv_memattr = ma; 5032244414Scognet 5033244414Scognet /* 5034244414Scognet * It appears that this function can only be called before any mappings 5035244414Scognet * for the page are established on ARM. If this ever changes, this code 5036244414Scognet * will need to walk the pv_list and make each of the existing mappings 5037244414Scognet * uncacheable, being careful to sync caches and PTEs (and maybe 5038244414Scognet * invalidate TLB?) for any current mapping it modifies. 5039244414Scognet */ 5040244414Scognet if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL) 5041244414Scognet panic("Can't change memattr on page with existing mappings"); 5042244414Scognet} 5043244414Scognet 5044244414Scognet 5045